Gate driver circuit and memory device including the same

Abstract

A memory device includes a memory cell having an access transistor and a variable resistance element; a word line connected to a gate of the access transistor; and a gate driver circuit configured to provide a word line voltage to the word line in a read operation or a write operation, receive a first power supply voltage from the power terminal during the read operation, and provide a second power supply voltage to the word line by attenuating the first power supply voltage to the second power supply voltage lower than the first power supply voltage, and during the write operation, receiving a third power supply voltage higher than the first power supply voltage from the power terminal, and providing the third power supply voltage to the word line without attenuating the third power supply voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0086092 filed in the Korean Intellectual Property Office on July 3, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a memory device including a gate driver circuit. Background Art

[0004] For example, semiconductor memory can be classified as volatile memory or non-volatile memory. Generally, when compared with non-volatile memory, volatile memory (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)) can exhibit faster read and / or write speeds. However, when the power applied to the volatile memory is disconnected, the data stored in the volatile memory may disappear. In contrast, non-volatile memory can retain data even when the power is disconnected.

[0005] Magnetoresistive random access memory (MRAM) may include a magnetic tunnel junction (MTJ). The magnetization direction of the MTJ may change according to the direction of the current applied to the MTJ. The resistance value of the MTJ may change according to the magnetization direction of the MTJ. MRAM may use these MTJ characteristics to store or read data.

[0006] The MRAM can perform a read operation by comparing with a reference resistor Rref having an intermediate size between the resistance distribution R0 of data 0 and the resistance distribution R1 of data 1. However, the resistance distribution of the MRAM may vary due to the influence of a resistance component and / or a capacitor component of an MTJ or word line, etc. The rise time of the word line may vary according to the number of memory cells connected to the word line. As the number of memory cells increases, the operation speed may slow down during a read or write operation due to a resistance or capacitor component of the MTJ or word line. Summary of the invention

[0007] Example embodiments of the present disclosure provide a gate driver capable of reducing a rising time of a word line voltage even if the rising time of the word line voltage increases due to an increase in the number of memory cells connected to one word line.

[0008] Example embodiments of the present disclosure provide a memory device that can reduce a reduction in operation speed due to a resistance or capacitor component of a word line or a memory cell.

[0009] According to one aspect of the present disclosure, a memory device includes: a memory cell having an access transistor and a variable resistance element; a word line connected to a gate of the access transistor; and a gate driver circuit configured to: provide a word line voltage to the word line in a read operation or a write operation, during a read operation, receive a first power supply voltage from a power terminal and provide a second power supply voltage to the word line by attenuating the first power supply voltage to a second power supply voltage lower than the first power supply voltage, and during a write operation, receive a third power supply voltage higher than the first power supply voltage from the power terminal and provide the third power supply voltage to the word line without attenuating the third power supply voltage.

[0010] According to one aspect of the present disclosure, a memory device includes: a memory cell array including word lines and a plurality of memory cells connected to the word lines; a column decoder connected to the plurality of memory cells through a plurality of source lines and a plurality of bit lines and configured to select the plurality of memory cells through the column lines; and a gate driver circuit configured to: provide a word line voltage to the word line in a read operation or a write operation, during a read operation, receive a first power supply voltage from a power terminal and provide a second power supply voltage to the word line by attenuating the first power supply voltage to a second power supply voltage lower than the first power supply voltage, and during a write operation, receive a third power supply voltage higher than the first power supply voltage from the power terminal and provide the third power supply voltage to the word line without attenuating the third power supply voltage.

[0011] According to one aspect of the present disclosure, a gate driver circuit of a memory device includes: a driver control circuit configured to generate a word line enable signal, a write enable signal, and a gate control signal; a first PMOS transistor connected between a power terminal and a first node and configured to operate in response to the word line enable signal; a second PMOS transistor connected between the first node and a second node connected to the word line and configured to operate in response to the write enable signal; a first NMOS transistor connected between the first node and the second node and configured to operate in response to the gate control signal; and a second NMOS transistor connected between the second node and a ground terminal and configured to operate in response to the word line enable signal. During a read operation, the gate driver circuit receives a first power supply voltage from the power terminal and provides a second power supply voltage to the word line by attenuating the first power supply voltage to a second power supply voltage lower than the first power supply voltage. During a write operation, the gate driver circuit receives a third power supply voltage higher than the first power supply voltage from the power terminal and provides the third power supply voltage to the word line without attenuating the third power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating a storage device according to an example embodiment of the present disclosure.

[0014] Figure 2 It shows Figure 1 A block diagram of an example embodiment of a memory device is shown.

[0015] Figure 3 It shows Figure 1 Diagram of a memory cell array.

[0016] Figures 4 to 6 Is used to describe Figure 3 FIG. 1 is a diagram of a first storage unit.

[0017] Figure 7 is shown with Figure 3 The circuit diagram of the memory cell array connected to the word line driver and column line driver is shown.

[0018] Figure 8 is shown when the word line enable signal is applied to Figure 7 FIG. 5 is a graph showing the voltage level of the first word line WL1 when the first word line driver is activated.

[0019] Fig. 9 is a block diagram illustrating a memory device including a gate driver circuit according to an example embodiment of the present disclosure.

[0020] Fig.10 and Fig.11 It shows Fig. 9 A circuit diagram of an example embodiment of a gate driver circuit is shown.

[0021] Fig.12 and Fig.13 It shows Fig.10 A circuit diagram of an example embodiment of an operating method of a first word line driver is shown.

[0022] Fig.14 It shows that Fig.12 FIG. 4 is a graph of the voltage level of a word line during a read operation of a word line driver. DETAILED DESCRIPTION

[0023] Exemplary embodiments of the present disclosure will be described below in detail and clearly to such an extent that those having ordinary skill in the art can easily realize the inventive concept.

[0024] Figure 11 is a block diagram showing a storage device according to an example embodiment of the present disclosure. The storage device 1000 may be a flash memory device based on flash memory. For example, the storage device 1000 may be implemented as a solid state drive (SSD), a universal flash memory (UFS), a memory card, etc.

[0025] refer to Figure 1 , the storage device 1000 may include a storage device 1100 and a storage controller 1200. The storage device 1100 may receive an input / output signal IO from the storage controller 1200 through an input / output line, receive a control signal CTRL through a control line, and receive external power PWR through a power line. The storage device 1000 may store data in the storage device 1100 under the control of the storage controller 1200.

[0026] The memory device 1100 may include a memory cell array MCA and a peripheral circuit 1115. The memory cell array MCA may include a plurality of memory blocks. Each memory block may have a vertical 3D structure. Each memory block may include a plurality of memory cells. Multi-bit data may be stored in each memory cell.

[0027] In terms of design layout structure, the memory cell array MCA may be located (eg, disposed) beside or above the peripheral circuit 1115. The structure in which the memory cell array MCA is located above the peripheral circuit 1115 may be referred to as a cell-on-periphery (COP) structure.

[0028] In example embodiments, the memory cell array MCA may be manufactured as a chip separate from the peripheral circuit 1115. An upper chip including the memory cell array MCA and a lower chip including the peripheral circuit 1115 may be connected to each other by a bonding method. This structure may be referred to as a chip-to-chip (C2C) structure.

[0029] The peripheral circuit 1115 may include an analog circuit and / or a digital circuit for storing data in the memory cell array MCA or reading data stored in the memory cell array MCA. The peripheral circuit 1115 may receive external power PWR through a power line and generate various levels of internal power.

[0030] The peripheral circuit 1115 may receive a command, an address, and / or data from the memory controller 1200 through an input / output line. The peripheral circuit 1115 may store data in the memory cell array MCA according to the control signal CTRL. The peripheral circuit 1115 may read the data stored in the memory cell array MCA and provide the read data to the memory controller 1200.

[0031] The peripheral circuit 1115 may include a gate driver circuit 2000. The gate driver circuit 2000 may be connected to the memory cell array 1110 via a plurality of word lines. The gate driver circuit 2000 may provide a word line voltage to a selected word line during a read or write operation. As the number of memory cells connected to one word line increases, the time for the word line voltage to reach a desired target voltage during a read or write operation may be delayed due to increased word line resistance and capacitance.

[0032] In a read operation, the gate driver circuit 2000 may receive a power supply voltage from a power terminal and provide a voltage lower than the power supply voltage to a word line through threshold voltage attenuation. In a write operation, the gate driver circuit 2000 may provide a voltage input from a power terminal to a word line without attenuating the threshold voltage. The memory device 1000 according to an example embodiment of the present disclosure may reduce the delay time of the word line voltage by using the gate driver circuit 2000.

[0033] Figure 2 It shows Figure 1 A block diagram of an example embodiment of a memory device is shown. Figure 1 The memory device 1000 may be a resistive memory device based on a resistive memory. For example, the memory device 1100 may be an MRAM, a resistive random access memory (ReRAM), or a phase change random access memory (PRAM).

[0034] refer to Figure 1 and Figure 2 , the memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115. The peripheral circuit 1115 may include a column decoder 1130, an input / output circuit 1140, a control logic 1160, and a gate driver circuit 2000.

[0035] The memory cell array 1110 may include a plurality of memory blocks. Each memory block may be composed of a plurality of memory cells. Each memory cell may store multi-bit data. Each memory block may be connected to a plurality of word lines (WL1, WL2, ..., WLm).

[0036] The column decoder 1130 may be connected to the memory cell array 1110 through a source line (SL) and / or a bit line (BL). The column decoder 1130 may select a source line SL or a bit line BL in response to a column line signal (CL1 to CLn) provided from the gate driver circuit 2000. The column decoder 1130 may select a source line (SL) or a bit line (BL) using a plurality of NMOS transistors (not shown).

[0037] The input / output circuit 1140 may be internally connected to the column decoder 1130 through data lines, and externally connected to the memory controller through input / output lines IO1 to IOn (refer to Figure 1 , 1200). The input / output circuit 1140 may receive programming data from the memory controller 1200 during a write operation (ie, a program operation). In addition, the input / output circuit 1140 may provide the memory controller 1200 with data read from the memory cell array 1110 during a read operation.

[0038] The input / output circuit 1140 may include a sense amplifier 1141 and a write driver 1142. The input / output circuit 1140 may receive or output data through an input / output terminal. The number of input / output terminals may vary depending on the type of the storage device 1000. The input / output circuit 1140 may provide data to the write driver 1142 in response to a control signal, or output data provided from the sense amplifier 1141 to the outside.

[0039] The sense amplifier 1141 can read the data stored in the selected memory cell by sensing the difference between the voltage of the source line SL and the reference voltage Vref during the read operation. The reference voltage Vref can be provided by a reference voltage generator circuit (not shown). The sense amplifier 1141 can operate in response to a control signal provided from the control logic 1160.

[0040] The write driver 1142 may receive a control signal from the control logic 1160 and provide a programming current I_PGM to the data line. The programming current I_PGM may be used to program the selected memory cell to one of multiple states. During the MLC programming operation, the write driver 1142 may provide the programming current I_PGM one or more times according to the multiple states of the selected memory cell.

[0041] Control logic 1160 may control read and / or write operations of memory device 1100 using a command CMD, an address ADDR, and a control signal CTRL provided from a memory controller. Address ADDR may include a row address for selecting a memory block or a word line, and a column address for selecting a memory cell.

[0042] The gate driver circuit 2000 may be connected to the memory cell array 1110 through a plurality of word lines (WL1 to WLm). The gate driver circuit 2000 may provide a word line voltage to a selected word line during a read or write operation. The gate driver circuit 2000 may receive internal power from the control logic 1160 and generate a word line voltage for reading or writing data.

[0043] The gate driver circuit 2000 may include a driver control circuit 2100, a word line driver 2200, and a column line driver 2300. The driver control circuit 2100 may provide a control signal to the word line driver 2200 and / or the column line driver 2300 during a read or write operation. The word line driver 2200 and the column line driver 2300 may receive a control signal from the driver control circuit 2100 and perform a read or write operation.

[0044] The gate driver circuit 2000 may receive a power supply voltage from the power terminal during a read operation and provide a voltage lower than the power supply voltage to the word line through threshold voltage attenuation. The gate driver circuit 2000 may provide the power supply voltage input from the power terminal to the word line without attenuating the threshold voltage during a write operation. The memory device 1100 according to an example embodiment of the present disclosure may reduce the delay time of the word line voltage by using the gate driver circuit 2000.

[0045] Figure 3 It shows Figure 1 Diagram of a memory cell array. Figures 4 to 6 Is used to describe Figure 3 Figure 1.1 shows the first memory cell. Figures 3 to 6 The memory cell array MCA may include a plurality of memory cells, each of which may be an MRAM cell, and the plurality of memory cells may be connected to word lines WL1 to WLm, bit lines BL1 to BLz, and source lines SL1 to SLz.

[0046] For example, the first memory cell MC1 may include an access transistor TR and a variable resistance element MTJ (e.g., a magnetic tunnel junction). The first terminal of the access transistor TR may be connected to the first source line SL1, the second terminal of the access transistor TR may be connected to the first terminal of the variable resistance element MTJ, and the gate of the access transistor TR may be connected to the first word line WL1. The second terminal of the variable resistance element MTJ may be connected to the first bit line BL1.

[0047] Data can be stored in each of the plurality of memory cells by adjusting the resistance value of the variable resistance element MTJ of each memory cell. Figure 4 and Figure 6 As shown, the variable resistance element MTJ may include a free layer FRL, a barrier layer BRL, and a fixed layer FXL. The barrier layer BRL may be interposed between the free layer FRL and the fixed layer FXL, the free layer FRL may be connected to the first bit line BL1, and the fixed layer FXL may be connected to the second terminal of the access transistor TR.

[0048] The magnetization direction of the fixed layer FXL can be fixed to a specific direction, and the magnetization direction of the free layer FRL can be changed according to specific conditions (eg, the direction of the write current). According to some embodiments, the variable resistance element MTJ may further include an antiferromagnetic layer for fixing the magnetization direction of the fixed layer FXL.

[0049] The free layer FRL may include a material having a variable magnetization direction, or may be formed of a material having a variable magnetization direction. The magnetization direction of the free layer FRL may be changed by an electric / magnetic factor provided from the outside and / or inside of the memory cell. The free layer FRL may include a ferromagnetic material containing at least one of cobalt (Co), iron (Fe) and nickel (Ni), or may be formed of a ferromagnetic material containing at least one of cobalt (Co), iron (Fe) and nickel (Ni). For example, the free layer FRL may include at least one selected from the following: FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO and Y3Fe5O12. However, the present disclosure is not limited to these examples.

[0050] The thickness of the barrier layer BRL may be less than the spin diffusion distance. The barrier layer BRL may include a non-magnetic material, or may be formed by a non-magnetic material. For example, the barrier layer BRL may include at least one selected from the following groups or may be formed by at least one selected from the following groups: oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn) and magnesium boron (MgB), and nitrides of titanium (Ti) and vanadium (V). However, the present disclosure is not limited to these examples.

[0051] The fixed layer FXL may have a magnetization direction pinned by the antiferromagnetic layer. The fixed layer FXL may include a ferromagnetic material, or may be formed of a ferromagnetic material. For example, the fixed layer FXL may include at least one selected from the group consisting of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12. According to some embodiments, the antiferromagnetic layer may include an antiferromagnetic material. For example, the antiferromagnetic layer may include at least one selected from the group consisting of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr. However, the present disclosure is not limited to these examples.

[0052] like Figure 4 As shown, the magnetization direction of the free layer FRL can be changed according to the direction of the write current WC1 or WC2 flowing through the variable resistance element MTJ. Figure 4 As shown in the first write current WC1, when the current flows in the direction from the first source line SL1 to the first bit line BL1, the magnetization direction of the free layer FRL may be opposite to the magnetization direction of the fixed layer FXL, which corresponds to the antiparallel state of the variable resistance element MTJ. Figure 4 As shown by the second write current WC2 , when the current flows in the direction from the first bit line BL1 to the first source line SL1 , the magnetization direction of the free layer FRL may be the same as the magnetization direction of the fixed layer FXL, which corresponds to a parallel state of the variable resistance element MTJ.

[0053] See below for a more detailed description Figure 5 , when the variable resistance element MTJ is in an anti-parallel state, the variable resistance element MTJ may have an anti-parallel resistance value R1 greater than the reference resistance Rref. When the variable resistance element MTJ is in a parallel state, the variable resistance element MTJ may have a parallel resistance value R0 less than the reference resistance Rref. That is, data may be stored in the first memory cell MC1 according to the resistance value of the variable resistance element MTJ, and the data stored in the first memory cell MC1 may be read by determining the resistance value of the variable resistance element MTJ. For example, the data stored in the variable resistance element MTJ may be represented by the resistance value of the variable resistance element MTJ relative to the reference resistance Rref.

[0054] When the variable resistance element MTJ is in a semi-balanced state (ie, an anti-parallel state), the variable resistance element MTJ may have a semi-balanced resistance R1 (ie, an anti-parallel resistance value), as shown in FIG. Figure 5 When the variable resistance element MTJ is in a balanced state (ie, a parallel state), the variable resistance element MTJ may have a balanced resistance R0 (ie, a parallel resistance value). The memory device 1100 may distinguish data 0 or data 1 using the size of the resistance value.

[0055] The memory device 1100 can perform a read operation by comparing with a reference resistance Rref having an intermediate level between data 0 and data 1. The reference resistance Rref can be changed externally when the memory device 1100 is manufactured without using a fixed value. The reference resistance can be determined by a test operation. Data can be stored in the first memory cell MC1 according to the resistance value of the variable resistance element MTJ. Data stored in the first memory cell MC1 can be read by reading the resistance value of the variable resistance element MTJ.

[0056] refer to Figure 6, the access transistor TR may include a body substrate 111, a gate electrode 112, and junctions 113 and 114. The junction 113 may be formed at the body substrate 111 and may be connected to the first source line SL1. The junction 114 may be formed at the body substrate 111 and may be connected to the first bit line BL1 through the MTJ element. The gate electrode 112 may be formed on the body substrate 111 between the junctions 113 and 114 and may be connected to the first word line WL1.

[0057] Figure 7 is shown with Figure 3 The circuit diagram of the memory cell array connected to the word line driver and column line driver is shown. Figure 7 , the word line driver and the column line driver can each be configured as an inverter.

[0058] The memory cell array 1110 may include a first memory cell MC1. The first memory cell MC1 may include an access transistor TR and a variable resistance element MTJ. The access transistor TR may be connected between a first source line SL1 and the variable resistance element MTJ. A gate of the access transistor TR may be connected to a first word line WL1. The variable resistance element MTJ may be connected between the access transistor TR and a first bit line BL1.

[0059] The column decoder 1130 may include a source line transistor TS and a bit line transistor TB. The source line transistor TS may be connected between the first source line SL1 and the input / output circuit 1140. The gate of the source line transistor TS may be connected to the first column line CL1. The bit line transistor TB may be connected between the first bit line BL1 and the input / output circuit 1140. The gate of the bit line transistor TB may be connected to the first column line CL1.

[0060] The first word line driver WLD1 may be configured as an inverter including a PMOS transistor P11 and an NMOS transistor N11. The PMOS transistor P11 and the NMOS transistor N11 may be configured as high voltage transistors that withstand high voltage. The PMOS transistor P11 may be connected between a power terminal and the first word line WL1. The NMOS transistor N11 may be connected between the first word line WL1 and a ground terminal. A word line enable signal WL_EN may be applied to a gate of the NMOS transistor N11 and a gate of the PMOS transistor P11. According to a voltage level of the word line enable signal WL_EN, one of the NMOS transistor N11 and the PMOS transistor P11 is turned on. For example, in response to a word line enable signal WL_EN having a high voltage level, the NMOS transistor N11 is turned on, and in response to a word line enable signal WL_EN having a low voltage level, the PMOS transistor P11 is turned on. The design and fabrication of the high voltage NMOS transistor N11 or PMOS transistor P11 involves considerations such as optimizing channel doping, gate oxide thickness, and device geometry to ensure reliable operation under high voltage conditions while maintaining good performance characteristics (e.g., low on-resistance and fast switching speed).

[0061] The first column line driver CLD1 may be configured as an inverter including a PMOS transistor P12 and an NMOS transistor N12. The PMOS transistor P12 and the NMOS transistor N12 may be configured as high voltage transistors that withstand high voltage. The PMOS transistor P12 may be connected between a power terminal and the first column line CL1. The NMOS transistor N12 may be connected between the first column line CL1 and a ground terminal. A column line enable signal CL_EN may be applied to the gates of the NMOS transistor N12 and the PMOS transistor P12. Depending on the voltage level of the column line enable signal CL_EN, one of the NMOS transistor N12 and the PMOS transistor P12 is turned on. For example, in response to a column line enable signal CL_EN having a high voltage level, the NMOS transistor N12 is turned on, and in response to a column line enable signal CL_EN having a low voltage level, the PMOS transistor P12 is turned on. The design and fabrication of the high voltage NMOS transistor N12 or PMOS transistor P12 involves considerations such as optimizing channel doping, gate oxide thickness, and device geometry to ensure reliable operation under high voltage conditions while maintaining good performance characteristics (e.g., low on-resistance and fast switching speed).

[0062] Figure 8 is shown when the word line enable signal is applied to Figure 7 FIG. 1 is a graph showing a voltage level of the first word line WL1 when the first word line driver is in operation. When the column line enable signal CL_EN is applied to Figure 7When the first column line driver CLD1 is shown, the first column line CL1 may have the same or similar voltage level as the first word line.

[0063] In the period T0 to T1, the voltage level of the word line enable signal WL_EN may be the power supply voltage Vdd. In an embodiment, the power supply voltage Vdd may be applied to the memory device, which corresponds to Figure 1 When the word line enable signal WL_EN is the power supply voltage Vdd, the PMOS transistor P11 is turned off and the NMOS transistor N11 is turned on. Therefore, the voltage level of the first word line WL1 may be a ground voltage or 0V.

[0064] In the period T1 to T2 , the voltage level of the word line enable signal WL_EN may transition from the power supply voltage Vdd to 0 V. When the word line enable signal WL_EN transitions to 0 V, the PMOS transistor P11 may be turned on, and the NMOS transistor N11 may be turned off.

[0065] In the period T1 to T3, the voltage level of the first word line WL1 may rise from 0V to the power supply voltage Vdd. If the transition time of the word line enable signal WL_EN is T2-T1, the rise time of the first word line WL1 may be T3-T1. The rise time of the first word line WL1 may vary according to the number of memory cells connected to the first word line WL1. As the number of memory cells connected to the first word line WL1 increases, the delay time (tRC) due to the resistance and capacitance of the first word line WL1 may increase.

[0066] There may be several ways to reduce the delay time (tRC). For example, by increasing the size of the PMOS transistor P11 and the NMOS transistor N11 in the first word line driver WLD1, the delay time (tRC) may be reduced. In some embodiments, the delay time (tRC) may be reduced by changing the internal configuration of the first word line driver WLD1, or by changing the level of the power supply voltage applied to the power terminal. Example embodiments for changing the internal configuration of the word line driver, or changing the level of the power supply voltage, will be described in detail below.

[0067] Fig. 9 is a block diagram showing a memory device including a gate driver circuit according to an example embodiment of the present disclosure. Fig. 9 , the memory device 1100 may include a memory cell array 1110 , a column decoder 1130 , an input / output circuit 1140 , and a gate driver circuit 2000 .

[0068] The memory cell array 1110 may include a first memory cell MC1. The first memory cell MC1 may include an access transistor TR and a variable resistance element MTJ. The access transistor TR may be connected between a first source line SL1 and the variable resistance element MTJ. A gate of the access transistor TR may be connected to a first word line WL1. The variable resistance element MTJ may be connected between the access transistor TR and a first bit line BL1.

[0069] The column decoder 1130 may include a source line transistor TS and a bit line transistor TB. The source line transistor TS may be connected between the first source line SL1 and the input / output circuit 1140. The gate of the source line transistor TS may be connected to the first column line CL1. The bit line transistor TB may be connected between the first bit line BL1 and the input / output circuit 1140. The gate of the bit line transistor TB may be connected to the first column line CL1.

[0070] The gate driver circuit 2000 may include a driver control circuit 2100, a word line driver 2200, and a column line driver 2300. The driver control circuit 2100 may provide control signals (e.g., write enable signals, word line enable signals, and column line enable signals) to the word line driver 2200 and / or the column line driver 2300 during a read or write operation.

[0071] The driver control circuit 2100 may include a VGWL generator 2110, a WT_EN generator 2120, a WL_EN generator 2130, and a CL_EN generator 2140. The VGWL generator 2110 may generate a gate control voltage VGWL. The gate control voltage VGWL may be provided to the word line driver 2200 and / or the column line driver 2300. The WT_EN generator 2120 may generate a write enable signal WT_EN. The write enable signal WT_EN may be provided to the word line driver 2200 and / or the column line driver 2300.

[0072] The WL_EN generator 2130 may generate a word line enable signal WL_EN. The word line enable signal WL_EN may be provided to the word line driver 2200 . The CL_EN generator 2140 may generate a column line enable signal CL_EN. The column line enable signal CL_EN may be provided to the column line driver 2300 .

[0073] The word line driver 2200 may receive a gate control voltage VGWL, a write enable signal WT_EN, and a word line enable signal WL_EN from the driver control circuit 2100, and may perform a read or write operation. The word line driver 2200 may include a first word line driver (WLD1, 2210). The first word line driver 2210 may be connected to a first word line WL1. The first word line driver 2210 may provide a word line voltage to the first word line WL1 during a read or write operation.

[0074] The column line driver 2300 may receive a gate control voltage VGWL, a write enable signal WT_EN, and a column line enable signal CL_EN from the driver control circuit 2100, and may perform a read or write operation. The column line driver 2300 may include a first column line driver (CLD1, 2310). The first column line driver 2310 may be connected to a first column line CL1. The first column line driver 2310 may control the on or off operation of the source line transistor TS and / or the bit line transistor TB.

[0075] Fig.10 and Fig.11 It shows Fig. 9 A circuit diagram of an example embodiment of a gate driver circuit is shown. Fig.10 and Fig.11 , the gate driver circuit 2000 may include a VGWL generator 2110 , a WT_EN generator 2120 , a WL_EN generator 2130 , a CL_EN generator 2140 , a first word line driver 2210 , and a first column line driver 2310 .

[0076] refer to Fig.10 , the VGWL generator 2110 may provide a gate control voltage VGWL to the first word line driver 2210. The VGWL generator 2110 may include a current generator 2111, a voltage generator 2112, a comparator (COM, 2113) and an NMOS transistor N21. The VGWL generator 2110 may receive a power supply voltage Vddio through a power terminal. Figure 2 The control logic 1160 shown is used to input the power supply voltage Vddio. The power supply voltage Vddio can be higher than the power supply voltage Vdd. For example, the power supply voltage Vddio can be about 1.8V, and the power supply voltage Vdd can be about 1V.

[0077] The current generator 2111 may be connected between a power terminal supplying a power supply voltage Vddio and a first node N1. The current generator 2111 may receive the power supply voltage Vddio from the power terminal and generate a current Ig. The voltage generator 2112 may be connected between a second node N2 and a ground terminal. The voltage generator 2112 may generate a voltage Vg.

[0078] The comparator (COM, 2113) may have a (-) input terminal, a (+) input terminal, and an output terminal. The (-) input terminal of the comparator 2113 may be connected to the first node N1. And the (+) input terminal may be connected to the third node N3. The output terminal of the comparator 2113 may be connected to the third node N3. The comparator 2113 may compare the voltage levels of the first node N1 and the third node N3, and generate a gate control voltage VGWL according to the comparison result. For example, when the voltage level of the third node N3 is higher than the voltage level of the first node N1, the comparator 2113 may output a high-level gate control voltage VGWL.

[0079] The NMOS transistor N21 may be connected between the first node N1 and the second node N2. The gate of the NMOS transistor N21 may be connected to the first node N1. The NMOS transistor N21 may be a high voltage transistor that withstands high voltage. The NMOS transistor N21 may have a diode structure in which the drain and the gate are connected. The drain and the gate of the NMOS transistor N21 may be connected to the (-) input terminal of the comparator 2113.

[0080] The first word line driver 2210 may selectively receive a word line voltage VWL or a power supply voltage Vddio from a power terminal. Figure 2 The control logic 1160 shown receives the word line voltage VWL or the power supply voltage Vddio. The word line voltage VWL can be higher than the power supply voltage Vddio. For example, VWL can be about 2V, and the power supply voltage Vddio can be about 1.8V.

[0081] The first word line driver 2210 may include a PMOS transistor (P21, P22) and an NMOS transistor (N22, N23). The PMOS transistor (P21, P22) and the NMOS transistor (N22, N23) may be a high voltage transistor that withstands a high voltage. For example, the first word line driver 2210 may include a PMOS transistor P21, an NMOS transistor N22, and an inverter structured PMOS transistor P22 and an NMOS transistor N23.

[0082] The PMOS transistor P21 may be connected between the power terminal and the fourth node N4. The PMOS transistor P21 may receive the word line voltage VWL or the power supply voltage Vddio in response to the switch signal SW provided from the control logic 1160. The gate of the PMOS transistor P21 may be connected to the fifth node N5. The PMOS transistor P21 may receive the word line enable signal WL_EN through the WL_EN generator 2130. The PMOS transistor P22 may be connected between the fourth node N4 and the sixth node N6. The PMOS transistor P22 may receive the write enable signal WT_EN through the WT_EN generator 2120.

[0083] The NMOS transistor N22 may be connected between the fourth node N4 and the sixth node N6. The gate control voltage VGWL may be provided to the gate of the NMOS transistor N22. The NMOS transistor N22 may perform an on or off operation according to the gate control voltage VGWL. If the difference between the gate voltage and the source voltage of the NMOS transistor N22 is higher than the threshold voltage, the NMOS transistor N22 may be turned on. If the threshold voltage of the NMOS transistor N22 is about 0.4V, when the voltage difference between VGWL and the sixth node N6 is higher than 0.4V, the NMOS transistor N22 may be turned on.

[0084] The NMOS transistor N23 may be connected between the sixth node N6 and the ground terminal. The gate of the NMOS transistor N23 may be connected to the fifth node N5. The word line enable signal WL_EN may be provided to the gate of the NMOS transistor N23. The drain of the NMOS transistor N23 may be connected to the first word line WL1.

[0085] refer to Fig.11 , the VGWL generator 2110 can provide a gate control voltage VGWL to the first column line driver 2310. The VGWL generator 2110 can also provide a gate control voltage VGWL to the first column line driver 2310. Fig.10 The first word line driver 2210 shown provides a gate control voltage VGWL. According to example embodiments, a VGWL generator for providing the gate control voltage VGWL to the first word line driver 2210 and a VGWL generator for providing the gate control voltage VGWL to the first column line driver 2310 may be provided separately.

[0086] The first column line driver 2310 may selectively receive a word line voltage VWL or a power supply voltage Vddio from a power terminal. The first column line driver 2310 may include a PMOS transistor (P31 and P32) and an NMOS transistor (N31 and N32). The PMOS transistor (P31, P32) and the NMOS transistor (N31, N32) may be a high voltage transistor that withstands a high voltage. For example, the first column line driver 2310 may include a PMOS transistor P31, an NMOS transistor N31, and a PMOS transistor P32 and an NMOS transistor N32 of an inverter structure.

[0087] The PMOS transistor P31 may be connected between the power terminal and the fourth node N4. The gate of the PMOS transistor P31 may be connected to the fifth node N5. The PMOS transistor P31 may receive the column line enable signal CL_EN through the CL_EN generator 2140. The PMOS transistor P32 may be connected between the fourth node N4 and the sixth node N6. The PMOS transistor P32 may receive the write enable signal WT_EN through the WT_EN generator 2120.

[0088] The NMOS transistor N31 may be connected between the fourth node N4 and the sixth node N6. The gate control voltage VGWL may be provided to the gate of the NMOS transistor N31. If the difference between the gate voltage and the source voltage of the NMOS transistor N31 is higher than the threshold voltage, the NMOS transistor N31 may be turned on. The NMOS transistor N32 may be connected between the sixth node N6 and the ground terminal. The NMOS transistor N32 may be controlled according to the column line enable signal CL_EN. The drain of the NMOS transistor N32 may be connected to the first column line CL1.

[0089] Fig.12 and Fig.13 It shows Fig.10 A circuit diagram of an example embodiment of an operating method of a first word line driver is shown. Fig.12 shows the bias conditions and current flow during a read operation of the first word line driver 2210, and Fig.13 The bias conditions and current flow during a write operation are shown.

[0090] refer to Fig.12 , the first word line driver 2210 may receive a power supply voltage Vddio from the power terminal during a read operation. The PMOS transistor P21 may receive a low level (L) word line enable signal WL_EN. The PMOS transistor P21 may be turned on and may form a current path between the power terminal and the fourth node N4. The PMOS transistor P22 may receive a high level (H) write enable signal WT_EN. The PMOS transistor P22 may be turned off.

[0091] The NMOS transistor N22 may receive a high level (H) gate control voltage VGWL. The NMOS transistor N22 may be turned on and may form a current path between the fourth node N4 and the sixth node N6. The NMOS transistor N23 may receive a low level (L) word line enable signal WL_EN. The NMOS transistor N23 may be turned off.

[0092] The first word line driver 2210 may use a power supply voltage Vddio (e.g., 1.8V) higher than the power supply voltage Vdd (e.g., 1.0V) during a read operation. The first word line driver 2210 may attenuate the power supply voltage Vddio in the NMOS transistor N22 and provide the power supply voltage Vdd to the first word line WL1. The first word line driver 2210 may provide a gate control voltage VGWL to the gate of the NMOS transistor N22 to attenuate the power supply voltage Vddio in the NMOS transistor N22. For example, VGWL having a voltage level of the sum of the power supply voltage Vdd and Vth may be 1.4V. Here, Vth (e.g., 0.4V) is the threshold voltage of the NMOS transistor N22.

[0093] Threshold voltage decay may occur at the NMOS transistor N22 in the first word line driver 2210. However, since the first word line driver 2210 uses the power supply voltage Vddio instead of the power supply voltage Vdd as the power supply voltage during the read operation, a higher drain-source voltage than before may be applied to the NMOS transistor N22, and thus the first word line driver 2210 may reduce the rise time of the first word line voltage during the read operation. For example, increasing the supply voltage of the NMOS transistor N22 may increase the charging speed of the capacitive load of the first word line WL1, thereby reducing the rise time.

[0094] As the number of memory cells connected to the first word line WL1 increases, the delay time (tRC) due to the resistance and capacitance of the first word line WL1 may increase. The first word line driver 2210 may receive a power supply voltage Vddio higher than the power supply voltage Vdd during a read operation, and may reduce the delay time (tRC) by applying a gate control voltage VGWL to the NMOS transistor N22.

[0095] refer to Fig.13, the first word line driver 2210 may receive a word line voltage VWL from the power terminal during a write operation. The PMOS transistor P21 may receive a low level (L) word line enable signal WL_EN. The PMOS transistor P21 may be turned on and may form a current path between the power terminal and the fourth node N4. The PMOS transistor P22 may receive a low level (L) write enable signal WT_EN. The PMOS transistor P22 may be turned on and may form a current path between the fourth node N4 and the sixth node N6.

[0096] The NMOS transistor N22 may receive a high level (H) gate control voltage VGWL. And the NMOS transistor N23 may receive a low level (L) word line enable signal WL_EN. The NMOS transistor N23 may be turned off.

[0097] The first word line driver 2210 may use a word line voltage (VWL, for example, 2V) during a write operation. And the first word line driver 2210 may provide the word line voltage VWL to the first word line WL1 through the PMOS transistors (P21 and P22). Since the first word line driver 2210 uses the current path of the PMOS transistors (P21 and P22), threshold voltage decay does not occur. The first word line driver 2210 may provide the word line voltage VWL to the first word line WL1.

[0098] Fig.14 It shows that Fig.12 FIG. 1 is a graph of the voltage level of a word line during a read operation of a word line driver. Fig.14 In the figure, curve (A) shows the Figure 7 and Figure 8 The word line voltage level during the read operation of the word line driver of the inverter structure shown in FIG. Fig.12 The word line voltage levels during a read operation of the word line driver are shown.

[0099] In the period T0 to T1, the voltage level of the word line enable signal WL_EN may be the power supply voltage Vddio. When the word line enable signal WL_EN is the power supply voltage Vddio, the PMOS transistor P21 is turned off and the NMOS transistor N23 is turned on. Therefore, the voltage level of the first word line WL1 may be the ground voltage or 0V.

[0100] In the period T1 to T2 , the voltage level of the word line enable signal WL_EN may transition from the power supply voltage Vddio to 0 V. When the word line enable signal WL_EN transitions to 0 V, the PMOS transistor P21 is turned on, and the NMOS transistor N23 is turned off.

[0101] In the period T1 to T3a, the voltage level of the first word line WL1 may rise from 0V to the power supply voltage Vdd. At this time, the voltage level of the first word line WL1 may rise to the power supply voltage Vdd by attenuation of the threshold voltage of the NMOS transistor N22. If the transition time of the word line enable signal WL_EN is T2-T1, the rising time of the first word line WL1 may be T3a-T1.

[0102] As the number of memory cells connected to the first word line WL1 increases, the delay time (tRC) due to the resistance component and the capacitor component may increase. The first word line driver 2210 may use a power supply voltage Vddio higher than the power supply voltage Vdd during a read operation. The first word line driver 2210 may reduce the delay time from tRC1 to tRC2 (reduced by time T3-T3a).

[0103] According to the present disclosure, the reduction in operation speed due to the resistance or capacitor components of the word line or memory cell can be reduced. Even if the rise time of the word line voltage increases due to the increase in the number of memory cells connected to one word line, the gate driver circuit can reduce the rise time of the word line voltage.

[0104] Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: A memory cell having an access transistor and a variable resistance element; a word line connected to the gate of the access transistor; as well as The gate driver circuit is configured as: providing a word line voltage to the word line in a read operation or a write operation, During the read operation, receiving a first power supply voltage from a power terminal and providing the second power supply voltage to the word line by attenuating the first power supply voltage to a second power supply voltage lower than the first power supply voltage, and During the write operation, a third power supply voltage higher than the first power supply voltage is received from the power terminal, and the third power supply voltage is provided to the word line without attenuating the third power supply voltage.

2. The memory device according to claim 1, in, The gate driver circuit includes an N-type metal oxide semiconductor (NMOS) transistor configured to provide the second power supply voltage by attenuating the first power supply voltage by a threshold voltage of the NMOS transistor during the read operation, and The gate driver circuit further includes a P-type metal oxide semiconductor (PMOS) transistor, and the PMOS transistor is configured to provide the third power supply voltage without attenuating the third power supply voltage during the write operation.

3. The memory device according to claim 2, in, Each of the NMOS transistor and the PMOS transistor is a high-voltage transistor that operates at a voltage higher than a power supply voltage supplied to the memory device.

4. The memory device according to claim 1, in, The gate driver circuit comprises: a word line driver circuit configured to: receive the first power supply voltage and the third power supply voltage, and selectively provide one of the second power supply voltage and the third power supply voltage to the word line; and The driver control circuit is configured to control the word line driver circuit.

5. The memory device according to claim 4, in, The word line driver circuit comprises: a first PMOS transistor connected between the power terminal and the first node and having a gate electrode receiving a word line enable signal; a second PMOS transistor connected between the first node and a second node connected to the word line and having a gate electrode receiving a write enable signal; a first NMOS transistor connected between the first node and the second node and having a gate electrode receiving a gate control signal; and a second NMOS transistor connected between the second node and a ground terminal and having a gate electrode receiving the word line enable signal, and Wherein, the driver control circuit is configured to: provide the word line enable signal, the write enable signal and the gate control signal.

6. The memory device according to claim 5, in, Each of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor is a high voltage transistor that operates at a voltage higher than a power supply voltage supplied to the memory device.

7. The memory device according to claim 5, in, The driver control circuit is configured to control the word line driver circuit to provide the second power supply voltage to the word line through the first PMOS transistor and the first NMOS transistor during the read operation.

8. The memory device according to claim 5, in, The driver control circuit is configured to control the word line driver circuit to provide the third power supply voltage to the word line through the first PMOS transistor and the second PMOS transistor during the write operation.

9. The memory device according to claim 5, in, A voltage level of the gate control signal corresponds to a sum of the second power supply voltage and a threshold voltage of the first NMOS transistor.

10. The memory device according to claim 1, in, The memory cell is a magnetoresistive random access memory (MRAM) memory cell.

11. A storage device comprising: A memory cell array comprising a word line and a plurality of memory cells connected to the word line; a column decoder connected to the plurality of memory cells through a plurality of source lines and a plurality of bit lines and configured to select the plurality of memory cells through the column lines; as well as The gate driver circuit is configured as: providing a word line voltage to the word line in a read operation or a write operation, During the read operation, receiving a first power supply voltage from a power terminal and providing the second power supply voltage to the word line by attenuating the first power supply voltage to a second power supply voltage lower than the first power supply voltage, and During the write operation, a third power supply voltage higher than the first power supply voltage is received from the power terminal, and the third power supply voltage is provided to the word line without attenuating the third power supply voltage.

12. The memory device according to claim 11, in, The gate driver circuit includes an NMOS transistor configured to provide the second power supply voltage by attenuating the first power supply voltage by a threshold voltage of the NMOS transistor during the read operation, and The gate driver circuit further includes a PMOS transistor, and the PMOS transistor is configured to provide the third power supply voltage without attenuating the third power supply voltage during the write operation.

13. The memory device according to claim 11, in, The gate driver circuit comprises: a word line driver circuit configured to: receive the first power supply voltage and the third power supply voltage, and selectively provide one of the second power supply voltage and the third power supply voltage to the word line; a column line driver circuit configured to: receive the first power supply voltage and the third power supply voltage, and selectively provide one of the second power supply voltage and the third power supply voltage to the column line; and The driver control circuit is configured to control the word line driver circuit and the column line driver circuit.

14. The memory device according to claim 13, in, The word line driver circuit comprises: a first PMOS transistor connected between the power terminal and the first node and having a gate electrode receiving a word line enable signal; a second PMOS transistor connected between the first node and a second node connected to the word line and having a gate electrode receiving a write enable signal; a first NMOS transistor connected between the first node and the second node and having a gate electrode receiving a gate control signal; and a second NMOS transistor connected between the second node and a ground terminal and having a gate electrode receiving the word line enable signal, and Wherein, the driver control circuit is configured to: provide the word line enable signal, the write enable signal and the gate control signal.

15. The memory device according to claim 14, in, The driver control circuit is configured to control the word line driver circuit to provide the second power supply voltage to the word line through the first PMOS transistor and the first NMOS transistor during the read operation.

16. The memory device according to claim 14, in, The driver control circuit is configured to control the word line driver circuit to provide the third power supply voltage to the word line through the first PMOS transistor and the second PMOS transistor during the write operation.

17. The memory device according to claim 13, in, The column line driver circuit comprises: a first PMOS transistor connected between the power supply terminal and the first node and having a gate electrode receiving a column line enable signal; a second PMOS transistor connected between the first node and a second node connected to the column line and having a gate electrode receiving a write enable signal; a first NMOS transistor connected between the first node and the second node and having a gate electrode receiving a gate control signal; and a second NMOS transistor connected between the second node and a ground terminal and having a gate electrode receiving the column line enable signal, and Wherein, the driver control circuit is configured to: provide the column line enable signal, the write enable signal and the gate control signal.

18. The memory device according to claim 17, in, The driver control circuit is configured to control the column line driver circuit to provide the second power supply voltage to the column line through the first PMOS transistor and the first NMOS transistor during the read operation.

19. The memory device according to claim 17, in, The driver control circuit is configured to control the column line driver circuit to provide the third power supply voltage to the column line through the first PMOS transistor and the second PMOS transistor during the write operation.

20. A gate driver circuit for a memory device, comprising: A driver control circuit configured to generate a word line enable signal, a write enable signal, and a gate control signal; a first PMOS transistor connected between the power terminal and the first node and configured to operate in response to the word line enable signal; a second PMOS transistor connected between the first node and a second node connected to the word line and configured to operate in response to the write enable signal; a first NMOS transistor connected between the first node and the second node and configured to operate in response to the gate control signal; as well as a second NMOS transistor connected between the second node and a ground terminal and configured to operate in response to the word line enable signal, wherein, during a read operation, the gate driver circuit receives a first power supply voltage from the power terminal and provides the second power supply voltage to the word line by attenuating the first power supply voltage to a second power supply voltage lower than the first power supply voltage, and Wherein, during a write operation, the gate driver circuit receives a third power supply voltage higher than the first power supply voltage from the power terminal and provides the third power supply voltage to the word line without attenuating the third power supply voltage.

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