Memory device using multiple pillar memory cells for matrix vector multiplication

Abstract

The invention relates to a memory device using multiple pillar memory cells for matrix vector multiplication. Systems, methods, and apparatus related to memory devices that use multi-strut memory cells to perform multiplications and other operations are described. In one method, a memory cell array has memory cells to perform matrix vector multiplication based on summing output currents from the memory cells. The memory cells are arranged in pillars of serially connected memory cells. Each memory cell uses at least one transistor from two or more different pillars. Bit lines overlying the pillars are formed. The bit lines are electrically connected to the pillars and accumulate output currents from the pillars when the matrix vector multiplication is performed.

Description

[0001] Related Applications

[0002] This application claims priority to Provisional U.S. Patent Application No. 63 / 511,806, filed on July 3, 2023, the entire disclosure of which is hereby incorporated by reference herein. Technical Field

[0003] At least some embodiments disclosed herein relate generally to memory devices and more particularly, but not limited to, memory devices that use multi-pillar memory cells to perform multiplication and other operations. Background Art

[0004] Limited memory bandwidth is a significant problem in machine learning systems. For example, DRAM devices used in current systems store the large number of weights and activations used in deep neural networks (DNNs).

[0005] In one example, a deep learning machine (e.g., those supporting processing for convolutional neural networks (CNNs)) performs processing to determine a large number of calculations per second. For example, input / output data, deep learning network training parameters, and intermediate results are constantly extracted from and stored in one or more memory devices (e.g., DRAM). When large storage density (e.g., storage density greater than 100MB) is involved, DRAM-type memory is generally used due to its cost advantage. In one example of a deep learning hardware system, a computing unit (e.g., a system on a chip (SOC), FPGA, CPU, or GPU) is attached to (several) memory devices (e.g., DRAM devices).

[0006] Existing computer architectures use processor chips dedicated to serial processing and DRAM optimized for high-density memory. The interface between these two devices is a major bottleneck, introducing latency and bandwidth limitations and adding considerable power consumption overhead. On-chip memory is area expensive and it is not possible to add large amounts of memory to the CPU and GPU processors currently used to train and deploy DNNs.

[0007] Memory in a neural network is used to store input data, weight parameters, and activations as the inputs propagate through the network. During training, activations from the forward path must be retained until they can be used to calculate error gradients in the reverse path. As an example, a network may have 26 million weight parameters and calculate 16 million activations in the forward path. If 32-bit floating point values ​​are used to store each weight and activation, this corresponds to a total storage requirement of 168MB.

[0008] GPUs and other machines require significant memory for the weights and activations of neural networks. GPUs cannot directly perform the small convolutions used in deep neural networks efficiently, so they require significant activation or weight storage. Finally, memory is also needed to store input data, temporary values, and program instructions. For example, a high-performance GPU may require more than 7GB of local DRAM.

[0009] It is not possible to keep large amounts of storage data on a GPU processor. In many cases, a high-performance GPU processor may have only 1KB of memory associated with each of the processor cores that can be read fast enough to saturate the floating point data path. Therefore, at each layer of the DNN, the GPU needs to save the state to external DRAM, load the next layer of the network, and then reload the data. As a result, the off-chip memory interface suffers from the burden of constantly reloading weights and saving and retrieving activations. This significantly reduces training time and increases power consumption.

[0010] In one example, image and other sensors are used and generate large amounts of data. In some applications, it is inefficient to transfer certain types of data from the sensors to a general purpose microprocessor (e.g., a central processing unit (CPU)) for processing. For example, it is inefficient to transfer image data from an image sensor to a microprocessor for image segmentation, object recognition, feature extraction, etc.

[0011] Some image processing may include intensive computations involving multiplication of columns or matrices of elements for accumulation. Some specialized circuits have been developed to accelerate multiplication and accumulation operations. For example, a multiplier-accumulator (MAC unit) may be implemented using a set of parallel computational logic circuits to achieve higher computational performance than a general-purpose microprocessor. Summary of the invention

[0012] According to one aspect of the present application, a device is provided. The device includes: a selection transistor; at least one first pillar of transistors; at least one second pillar of transistors, wherein each of a plurality of memory cells includes a corresponding first transistor from the first pillar and a corresponding second transistor from the second pillar; and a bit line overlying the first and second pillars, wherein each of the first and second pillars is electrically connected to the bit line through the selection transistor.

[0013] According to another aspect of the present application, a method is provided. The method includes: forming a logic circuit system on a semiconductor substrate; forming a memory cell array above the semiconductor substrate; forming a conductive layer above the array; and patterning the conductive layer to provide bit lines, the bit lines including a first bit line for accessing a first memory cell; wherein the logic circuit system is configured to use the first bit line to accumulate an output current from the first memory cell.

[0014] According to another aspect of the present application, a device is provided. The device includes: a host interface configured to communicate with a host; and a memory cell array including memory cells configured to store weights received from the host and access lines configured to access the memory cells, wherein the array includes rows of pillars, and each memory cell of the array includes corresponding transistors from at least two corresponding pillars located in adjacent rows of the pillars. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which reference characters indicate similar elements.

[0016] Figure 1 An integrated circuit device having a sensor, a memory cell array, and circuitry to perform inference computations according to one embodiment is shown.

[0017] Figure 2 A computation is shown that multiplies a column of weight bits by a column of input bits to provide an accumulated result, according to one embodiment.

[0018] Figure 3 A method of calculation in an integrated circuit device based on summing output currents from memory cells according to one embodiment is presented.

[0019] Figure 4 An analog weight-fixed architecture for matrix-vector multiplication (MVM) is presented according to one embodiment.

[0020] Figure 5 An analog weight fixing method using a select gate drain (SGD) cell architecture according to one embodiment is presented.

[0021] Figure 6 An example arrangement of memory cells for a tile of a NAND flash memory array is shown according to one embodiment.

[0022] Figure 7 Sensing circuitry coupled to bit lines used to access NAND flash memory cells is shown according to one embodiment.

[0023] Figure 8 A string of memory cells connected to a common bit line segment is shown according to one embodiment.

[0024] Fig. 9 Example target currents on an IV curve for a memory cell are shown, with each target current corresponding to a different weight value.

[0025] Fig.10 Bit lines used to access multi-pillar memory cells of a memory array are shown according to one embodiment.

[0026] Fig.11 A top view of the bit lines used to access a single pillar memory cell is shown.

[0027] Fig.12 A top view of bit lines used to access multi-pillar memory cells is shown according to one embodiment.

[0028] Fig.13 An architecture with resistive random access memory (RRAM) or NOR memory cells arranged in a parallel configuration for performing multiplication is shown according to one embodiment.

[0029] Fig.14 A method for forming a memory device having multi-pillar memory cells for use in performing multiplication is shown according to one embodiment. DETAILED DESCRIPTION

[0030] The following disclosure describes various embodiments of memory devices that use multi-pillar memory cells to perform multiplication and other operations. Each memory cell provides an output current depending on its previous programming and the input of the memory cell during read inference. In one embodiment, the memory device applies bias to access lines (e.g., word lines and / or bit lines) when performing multiplication and / or other operations using a three-dimensional NAND flash memory cell array. The memory device may, for example, store data used by a host device (e.g., a computing device of an autonomous vehicle, or another computing device that accesses data stored in the memory device). In one example, the memory device is a solid-state drive installed in an electric vehicle.

[0031] There may be a combination of various mechanisms that may cause the magnitude of the output current from a memory cell to vary so that it is above or below the desired initial target threshold voltage or current that the memory cell has been programmed to. For example, since the MVM or other operation is the sum of the output currents from selected memory cells, any cell / array mechanism that results in deviation from the expected target current value for that cell may result in an error.

[0032] One problem that can cause this error is the IR voltage drop (or simply IR drop) along the access line caused by the output current flow in the memory array. This problem can be particularly severe for the current in the bit lines used to accumulate the output current from the memory cell strings during MVM. For example, the bit lines (BL) accumulate current for the MVM function of the memory device. The voltage on each bit line varies due to the IR drop. The IR drop can vary depending on the bit line resistance, the range of weights used to program the memory cells (e.g., the range of target output currents), and / or the weights and input distribution (e.g., input pattern) during the inference read. The IR drop lowers the target voltage across each string, which introduces errors in the MVM function.

[0033] The IR drop may vary, for example, depending on the memory cell location within the array tile and / or the current in the array. The current varies depending on both the input to the multiplication and the weight pattern of the memory cell. In one example, one factor that affects the IR drop is the location of the memory cell relative to one or more voltage drivers. The bit lines and pillars have a certain resistance, so the IR drop seen by the cell increases as the cell is located farther away from the driver(s).

[0034] To combat this IR drop, various embodiments described below reduce the effective resistance of the bit line. By reducing the effective IR drop along the bit line, the window budget can be improved and / or the errors in the MVM can be reduced. This window budget is sometimes expressed as an acceptable amount of error. For example, the degree of tolerable error also depends on the AI ​​model used.

[0035] In one example, the bit lines are formed using the top metal of the NAND memory cell array. The output currents from the memory cells are accumulated by the bit lines for multiplication. Sometimes, the accumulated current can be significant if, for example, numerous strings along the bit lines conduct high currents due to the programmed states and / or valid inputs of the memory cells. This can cause a large IR drop and produce errors in the multiplication result.

[0036] In one embodiment, a memory cell array uses multi-pillar memory cells to reduce IR drop when performing calculations for layers of a neural network. For example, these calculations include matrix-vector multiplications (MVM) for each layer of the neural network. The weights of the neural network are stored in the memory cell array and multiplications using the weights are performed in the memory cell array itself based on the output current from the memory cells in the array. The output current is digitized and used by the controller to support MVM.

[0037] In addition to the above, improved power efficiency is particularly desirable for use of neural networks on mobile devices and automobiles. Storing the weights of the neural network in a memory device and performing multiplications in the memory device avoids or reduces the need to move the weights to a central processing unit or other processing device. This reduces the power consumption required to move data to and from memory, and also reduces the memory bandwidth issues described herein.

[0038] More generally, neural networks are one of the most popular classes of machine learning algorithms (e.g., modeled after our understanding of how the brain works). For example, a network has a large number of neurons that independently perform fairly simple calculations but together can learn complex and nonlinear functions. For example, a neuron calculation is basically a number of input values ​​multiplied by a neuron weight (which represents the importance of each input to the calculation) and the results are summed. The weights are learned during network training. Each result is then passed through a nonlinear activation function to allow the neuron to learn complex relationships.

[0039] In terms of computational burden, multiplying all input values ​​by the neuron weights of all neurons in the network is the most demanding use of processing power. For example, depending on the network design, this multiplication may account for 90% or more of the computational requirements. When scaling to a full layer of a neural network, the calculation is vectorized and becomes a matrix-vector multiplication problem. The calculation is sometimes also called a dot product or sum of products (SOP) calculation.

[0040] Deep learning technology is an example implementation of neural networks and plays an important role in a variety of applications such as image classification, object detection, speech recognition, natural language processing, recommendation systems, automatic generation and robotics, etc. Many domain-specific deep learning accelerators (DLAs) such as GPUs, TPUs, and embedded NPUs have been introduced to provide the required efficient implementation of deep neural networks (DNNs) from the cloud to the edge. However, due to the frequent data back and forth movement between the computing unit and the memory in deep learning, limited memory bandwidth remains a key challenge, especially for energy-constrained systems and applications such as edge AI.

[0041] Conventional Von-Neumann computer architectures have been developed with processor chips dedicated to serial processing and DRAM optimized for high-density memory. The interface between these two devices is a major bottleneck that introduces latency and bandwidth limitations and adds considerable power consumption overhead. As the demand for higher accuracy and higher speed in AI applications continues to grow, larger DNN models are developed and implemented using a large number of weights and activations. The resulting bottlenecks in memory bandwidth and power consumption for data movement between chips are significant technical issues.

[0042] As time goes by, the complexity of neural networks continues to grow exponentially, which means that much more computation is required. This makes the performance of traditional computing architectures inadequate. For example, MVM operations require specially built computing blocks to meet the performance requirements (GPUs, digital accelerators). Moreover, neuron weights must be fetched from memory, which both causes performance bottlenecks and is energy inefficient, as mentioned above.

[0043] In some cases, the precision of the computations can be reduced to address these issues. For example, the choice of neural network training type can achieve approximately equivalent neural network accuracy with significantly lower precision. The lower precision can improve the performance and / or energy efficiency of the neural network implementation. Moreover, using lower precision can support storing weights in memory and performing multiplications in memory, as described herein.

[0044] For example, when using lower precision weight and input representations (e.g., using fewer bits for each weight or input), the key aspect to consider is the final answer, such as the classification of an image. In many cases, if the neural network model is properly structured (e.g., the manner or method used to train the network), the accuracy of obtaining the correct final answer can be maintained almost the same (e.g., only reduced by 2 to 5%) even when using lower precision. For example, analog multiplication in the memory itself may even be preferable because of the ability to achieve similar accuracy as in traditional methods but with this lower precision.

[0045] The neural network design itself usually dictates the size of the MVM operation at each layer of the network. Each layer may have a different number of features and neurons. In one embodiment, the MVM calculation will be performed in a portion of a NAND flash or other memory array. This portion is represented as a tile in the array.

[0046] In one embodiment, a memory device has memory cells configured in an array, wherein each memory cell is programmed, for example, to allow a certain amount of current to pass when a voltage is applied within a predetermined voltage region to represent a first logic state (e.g., a first value stored in the memory cell), or to allow a negligible amount of current to pass to represent a second logic state (e.g., a second value stored in the memory cell).

[0047] The memory device performs calculations based on applying voltages digitally in the form of whether to apply input voltages to produce currents for summing on a line (e.g., a bit line of a memory array). The total current on the line will be a multiple of the amount of current allowed for cells programmed with a first value. In one example, an analog-to-digital converter is used to convert the current to a digital result of the sum of the bitwise multiplications.

[0048] As mentioned above, the memory cell stores the weights used in the multiplication. The weights are set at a target threshold voltage (VT) to sink a specific amount of current (e.g., a target current magnitude corresponding to the value of the stored weight). The accuracy of this current needs to be maintained to obtain the proper summed value or result from the multiplication. Therefore, the accuracy of the MVM calculation depends on the stable output current from the memory cell. It is expected that the output current value is consistent across many different conditions experienced during operation of the memory device. This output current consistency can be improved by using multi-pillar memory cells to reduce the IR drop.

[0049] To address the above-mentioned IR drop, power efficiency and / or other technical issues, the memory device integrates memory and processing. In one example, the memory and inference computing processing are integrated into the same integrated circuit device. In some embodiments, the memory device is an integrated circuit device having an image or other sensor, a memory cell array, and one or more circuits for using the memory cell array to perform inference computing on data from the sensor. In some embodiments, the memory device includes or is used with various types of sensors (e.g., LIDAR, radar, sound).

[0050] Existing methods of matrix-vector multiplication use digital logic gates. Compared to the various embodiments described below, digital logic implementations are more complex, consume more silicon area and dissipate more power. These embodiments effectively reduce the multiplication of memory access functions that can be parallelized in an array. The accumulation function is implemented by wires connecting these memory elements, which can also be parallelized in an array. By combining these two features in an array, matrix-vector multiplication can be performed more efficiently than methods using digital logic gates.

[0051] In order to solve the technical problem of maintaining the desired target output current during multiplication or other operations, the memory device reduces the IR drop in the bit line by using multi-pillar memory cells. Using this method, the error characteristics of MVM or other operations can be improved.

[0052] In one embodiment, a NAND flash memory device is formed on a semiconductor substrate. A memory array having multi-pillar memory cells extends vertically above the semiconductor substrate, and the memory array includes at least one first pillar of transistors (e.g., a first row of pillars) and at least one second pillar of transistors (e.g., a second row of pillars extending parallel to the first row). Each memory cell includes a respective first transistor from the first pillar and a respective second transistor from the second pillar.

[0053] The bit line is formed in a metal or other conductive layer overlying the first and second pillars. The bit line is electrically connected to the first and second pillars. The bit line accumulates the output currents of the memory cells from the first and second pillars when performing multiplication (eg, MVM).

[0054] In one embodiment, a NAND analog weight fixture is used to perform the multiplication. A word line voltage is applied to the gates of the multi-pillar memory cells that form one or more synapses of the neural network. In one embodiment, an integrated circuit (IC) device (e.g., Figure 1 The IC device 101 includes a host interface configured to communicate with a host. The IC device includes a memory cell array having memory cells for storing weights of a neural network. Access lines (e.g., word lines, bit lines) are used to access the memory cells. The IC device also includes logic circuitry for receiving weights of the neural network from the host via the host interface. The logic circuitry programs a portion of the memory cells of the memory cell array to store the weights.

[0055] In one embodiment, the image sensor is configured with analog capabilities to support inference computations, such as computations of artificial neural networks, by using matrix-vector multiplication. The image sensor may be implemented as an integrated circuit device having an image sensor chip and a memory chip. The memory chip may have a 3D memory array configured to support multiplication and accumulation operations. The integrated circuit device includes one or more logic circuits configured to process images from the image sensor chip and operate memory cells in the memory chip to perform multiplication and accumulation operations.

[0056] The memory chip may have multiple layers of memory cells. Each memory cell may be programmed to store a bit of a binary representation of an integer weight. Each input line may have a voltage applied to it according to the bit of the integer. Columns of memory cells may be used to store bits of a weight matrix; and a set of input lines may be used to control a voltage driver to apply a read voltage to a row of memory cells according to the bits of an input vector.

[0057] In one embodiment, the threshold voltage or state of a memory cell used for a multiply and accumulate operation can be programmed so that the current through the memory cell subjected to a predetermined read voltage is either a predetermined amount representing a value of one stored in the memory cell or is negligible representing a value of zero stored in the memory cell. When the predetermined read voltage is not applied, the current through the memory cell is negligible regardless of the value stored in the memory cell. As a result of the configuration, the current through the memory cell corresponds to the result of a 1-bit weight as stored in the memory cell multiplied by a 1-bit input, the result corresponding to the presence or absence of the predetermined read voltage driven by a voltage driver controlled by the 1-bit input.

[0058] The output currents of the memory cells representing the results of the columns of 1-bit weights stored in the memory cells multiplied by the columns of 1-bit inputs are connected to a common line for summing. The summed current in the common line is a multiple of a predetermined amount; and the multiple can be digitized and determined using an analog-to-digital converter or other digitizer. Such results of 1-bit to 1-bit multiplication and accumulation can be performed for different significant bits of the weights and different significant bits of the inputs. The results of different significant bits can be shifted (e.g., shifted to the left) to apply the weights of the corresponding significant bits for summing to obtain the results of the multiplication and accumulation of multi-bit weights and multi-bit inputs.

[0059] Using the ability to perform multiplication and accumulation operations implemented via the memory cell array, the logic circuit can be configured to perform inference calculations, such as those of artificial neural networks.

[0060] Various embodiments of memory devices that perform multiplication using the logic states of memory cells are described below. The memory cells in the array may generally be of various types. Examples include NAND or NOR flash memory cells and phase change memory (PCM) cells. In one example, the PCM cells are chalcogenide memory cells. In one example, a floating gate or charge trap memory device in a NAND or NOR memory configuration is used.

[0061] In various embodiments using chalcogenide memory cells, multiplication and other processing are performed by operating the chalcogenide memory cells in the subthreshold region. This is to avoid thresholding or mutation of any memory cell, which would normally prevent proper multiplication (e.g., due to large undesirable output currents associated with the mutation).

[0062] The summation of the results represented by the output currents from the memory cells can be implemented by connecting the currents to a common line (e.g., a bit line or a source SRC line). The summation of the results can be digitized to provide a digital output. In one example, an analog-to-digital converter is used to measure the sum as a multiple of a predetermined current amount and provide a digital output.

[0063] In one embodiment, the memory device implements unsigned 1-bit to multi-bit multiplication. The multi-bit weight can be implemented via multiple memory cells. Each of the memory cells is configured to store one of the bits of the multi-bit weight, as just described above. The voltage represented by the 1-bit input can be applied individually to the multiple memory cells to obtain the result of the unsigned 1-bit to 1-bit multiplication as described above.

[0064] Each memory cell has a position corresponding to its stored bit in the binary representation of the multi-bit weight. Its digitized output (e.g., the sum of the output currents from the memory cells originating on a common bit line) can be shifted left according to its position in the binary representation to obtain a shifted result. For example, the digitized output of the memory cell storing the least significant bit of the multi-bit weight is shifted by 0 bits; the digitized output of the memory cell storing the second least significant bit of the multi-bit weight is shifted by 1 bit; the digitized output of the memory cell storing the third least significant bit of the multi-bit weight is shifted by 2 bits; etc. The shifted results can be summed to obtain the result of a 1-bit input multiplied by the multi-bit weight stored in multiple memory cells.

[0065] Figure 1 An integrated circuit device 101 is shown having one or more sensors 111, a memory cell array 113, and circuitry to perform inference calculations according to one embodiment. Figure 1 In FIG. 1 , integrated circuit device 101 has integrated circuit die 109 with logic circuits 121 and 123 , integrated circuit die 103 with sensor 111 (eg, image sensing pixel array), and integrated circuit die 105 with memory cell array 113 .

[0066] In one example, integrated circuit die 109 with logic circuits 121 and 123 is a logic chip; integrated circuit die 103 with sensor 111 is a sensor chip; and integrated circuit die 105 with memory cell array 113 is a memory chip.

[0067] exist Figure 1 In the embodiment, the integrated circuit die 105 having the memory cell array 113 further includes a voltage driver 115 and a current digitizer 117. The memory cell array 113 is connected so that the current generated by the memory cells in response to the voltage applied by the voltage driver 115 is summed for the columns of memory cells in the array 113 (e.g., as Figure 2 and the summed current is digitized to produce the sum of the bitwise multiplication. The inference logic circuit 123 can be configured to instruct the voltage driver 115 to apply a read voltage according to the column of the input, and perform shifting and summing to produce a column of weights or a matrix multiplied by the column of the input and the accumulated result.

[0068] In one embodiment, sensing circuitry 150 is coupled to the memory cells in tiles 141, 142. Sensing circuitry 150 is used to sense one or more characteristics of the memory cells. In one embodiment, sensing circuitry 150 includes circuitry to precharge the bit lines of tiles 141, 142. Sensing circuitry 150 is configured to receive signals from controller 124 and / or read register 160 to configure sensing operations. In one embodiment, sensing circuitry 150 includes an ADC or other digitizer to convert the sum of output currents from the memory cells accumulated on access lines (e.g., accumulated on bit lines) to provide a digital result (e.g., accumulated result).

[0069] The inference logic circuit 123 may be further configured to perform inference calculations (e.g., calculations of an artificial neural network) based on the weights stored in the memory cell array 113 and the inputs derived from the data generated by the sensor 111. Optionally, the inference logic circuit 123 may include a programmable processor that can execute a set of instructions to control the inference calculations. Alternatively, the inference calculations are configured for a specific artificial neural network having certain aspects that can be adjusted via the weights stored in the memory cell array 113. Optionally, the inference logic circuit 123 is implemented via the core of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a programmable microprocessor.

[0070] In one embodiment, the inference logic circuit 123 includes a controller 124. In one example, the controller 124 manages communications with the host system via the interface 125. In one example, the controller 124 performs signed or unsigned multiplication using the memory cell array 113. In one embodiment, the controller 124 selects whether to perform a signed or unsigned multiplication based on the data type to be used as an input to the multiplication. In one example, the controller 124 selects a signed multiplication in response to determining that the input to the multiplication is signed.

[0071] exist Figure 1 , the integrated circuit die 105 having the memory cell array 113 has a bottom surface 133; and the integrated circuit die 109 having the inference logic circuit 123 has a portion of the top surface 134. The two surfaces 133 and 134 can be connected via bonding (e.g., using hybrid bonding) to provide a portion of the interconnect 107 between the metal portions on the surfaces 133 and 134.

[0072] Similarly, the integrated circuit die 103 with the sensor 111 has a bottom surface 131, and the integrated circuit die 109 with the inference logic circuit 123 has another portion of its top surface 132. The two surfaces 131 and 132 may be connected via bonding (e.g., using hybrid bonding) to provide a portion of the interconnect 107 between metal portions on the surfaces 131 and 132.

[0073] The image sensing pixel array of sensor 111 may include photosensitive elements configured to generate signals in response to the intensity of light received in the element. For example, image sensing pixels implemented using complementary metal oxide semiconductor (CMOS) technology or charge coupled device (CCD) technology may be used.

[0074] In some implementations, image processing logic 121 is configured to pre-process images from the image sensing pixel array to provide processed images as input to inference calculations controlled by inference logic 123. Optionally, image processing logic 121 may also use multiplication and accumulation functions provided via memory cell array 113.

[0075] In some implementations, interconnect 107 includes wires for writing image data from the image sensing pixel array to a portion of memory cell array 113 for further processing by image processing logic circuitry 121 or inference logic circuitry 123 or for retrieval via interface 125. Inference logic circuitry 123 may buffer results of inference calculations in a portion of memory cell array 113.

[0076] The interface 125 of the integrated circuit device 101 may be configured to support the memory access protocol or the storage access protocol or any combination thereof. Thus, an external device (eg, a processor, a central processing unit) may send commands to the interface 125 to access the storage capacity provided by the memory cell array 113 .

[0077] For example, the interface 125 may be configured to support connections and communication protocols on a computer bus, such as a Peripheral Component Interconnect Express (PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Universal Serial Bus (USB) bus, a Compute Express link, etc. In some embodiments, the interface 125 may be configured to include an interface for a solid state drive (SSD), such as a ball grid array (BGA) SSD. In some embodiments, the interface 125 may be configured to include an interface for a memory module, such as a double data rate (DDR) memory module, a dual in-line memory module, etc. The interface 125 may be configured to support communication protocols, such as protocols according to the Non-Volatile Memory Express (NVMe), the Non-Volatile Memory Host Controller Interface Specification (NVMHCIS), etc.

[0078] From the perspective of a device communicating with the interface 125, the integrated circuit device 101 may appear as a memory subsystem. Through the interface 125, an external device (e.g., a processor, a central processing unit) may access the storage capacity of the memory cell array 113. For example, the external device may store and update weight matrices and instructions for the inference logic circuit 123, retrieve images generated by the image sensing pixel array of the sensor 111 and processed by the image processing logic circuit 121, and retrieve results of inference calculations controlled by the inference logic circuit 123.

[0079] Integrated circuit die 105 includes a local controller 161 having registers 160. Local controller 161 may perform at least a portion of the control functions handled by controller 124. Registers 160 may be set by controller 124 and / or a host to configure memory cell programming adjustments.

[0080] Integrated circuit die 109 includes memory 170 having registers 174. In one embodiment, configuration data from a host is received via interface 125. In one example, the configuration data is data used to set registers 174 and / or 160 to configure adjustments for programming of memory cells based on a context of the memory cells of IC device 101. In one example, this context includes a temperature determined using temperature circuitry 163. In one example, temperature circuitry 163 provides the temperature of the memory cells in memory cell array 113. In one example, temperature circuitry 163 is embedded within memory cell array 113.

[0081] In one example, the context used to adjust cell programming includes current measured by the sensing circuitry 150. In one example, one or more string currents are measured for the pillars of a NAND flash memory cell.

[0082] In one example, the context used to coordinate cell programming includes the time that has elapsed since the memory cell was last programmed. One or more timers 172 are used to monitor this time for the memory cells in the memory cell array 113.

[0083] In one example, the context used to adjust cell programming includes data regarding the values ​​of weights stored in memory cells of the memory cell array 113. In one example, this data indicates the number of memory cells that are in an erased state.

[0084] In one example, the context used to adjust cell programming includes data obtained from one or more sensors 111. Sensors 111 may include temperature sensors.

[0085] In one example, IC device 101 performs processing for a neural network, including MVM calculations mapped to tiles 141 , 142 .

[0086] exist Figure 1 In the embodiment of the present invention, the interface 125 is positioned at, for example, the bottom side of the integrated circuit device 101, while the image sensor chip is positioned at the top side of the integrated circuit device 101 to receive incident light to generate an image.

[0087] Controllable Figure 1 The voltage driver 115 in the array 113 is used to apply a voltage to program the threshold voltage of the memory cells in the array 113. The data stored in the memory cell can be represented by the level of the programmed threshold voltage of the memory cell.

[0088] In one example, the interface 125 may be operable for the host system to write data into the memory cell array 113 and read data from the memory cell array 113. For example, the host system may send commands to the interface 125 to write a weight matrix of the artificial neural network into the memory cell array 113 and read the output of the artificial neural network, raw data from the sensor 111, or processed image data from the image processing logic circuit 121, or any combination thereof.

[0089] The reasoning logic circuit 123 and / or the controller 161 may be programmable and include a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA), or any combination thereof. Instructions for implementing the calculations of the artificial neural network may also be written into the memory cell array 113 via the interface 125 for execution by the reasoning logic circuit 123.

[0090] Figure 2 A calculation is shown in which a column of weight bits is multiplied by a column of input bits to provide an accumulated result according to one embodiment. Figure 2 , 227 (eg, in the memory cell array 113 of the integrated circuit device 101) may be programmed to have threshold voltages at levels representing a weight of storing one bit per memory cell.

[0091] In one embodiment, at least a portion of the memory cell is implemented as e.g. Fig.10 A multi-pillar memory cell is shown in FIG.

[0092] , 223 (eg, in voltage driver 115 of integrated circuit device 101 ) are configured to apply voltages 205 , 215 , . . . , 225 to memory cells 207 , 217 , . . . , 227 according to their received input bits 201 , 211 , . . . , 221 , respectively.

[0093] For example, when the input bit 201 has a value of one, the voltage driver 203 applies a predetermined read voltage as the voltage 205, causing the memory cell 207 to output a predetermined amount of current as its output current 209 to represent a stored weight of one when the memory cell 207 has a threshold voltage programmed at a lower level (which is lower than the predetermined read voltage), or to output a negligible amount of current as its output current 209 to represent a stored weight of zero when the memory cell 207 has a threshold voltage programmed at a higher level (which is higher than the predetermined read voltage).

[0094] However, when the input bit 201 has a value of zero, the voltage driver 203 applies a voltage (e.g., zero) lower than the threshold voltage of the lower level as the voltage 205 (e.g., does not apply the predetermined read voltage), thereby causing the memory cell 207 to output a negligible amount of current as its output current 209, regardless of the weight stored in the memory cell 207. Therefore, the output current 209, which is a multiple of the predetermined amount of current, represents the result of multiplying the weight bit stored in the memory cell 207 by the input bit 201.

[0095] Similarly, current 219 passing through memory cell 217 as a multiple of a predetermined current amount represents the result of multiplying the weight bits stored in memory cell 217 by input bit 211; and current 229 passing through memory cell 227 as a multiple of a predetermined current amount represents the result of multiplying the weight bits stored in memory cell 227 by input bit 221.

[0096] The output currents 209, 219, ..., 229 of the memory cells 207, 217, ..., 227 are connected to a common line 241 (e.g., a bit line or source line in the tile 141) for summing. In one example, the common line 241 is a bit line. When summing the output currents, a constant voltage (e.g., ground or -1V) is maintained on the bit line.

[0097] The digitizer 233 of the analog-to-digital converter 245 compares the summed current 231 with a unit current 232 equal to a predetermined current amount to determine a digital result 237 of multiplying the columns of weight bits stored in the memory cells 207, 217, ..., 227, respectively, by the columns of input bits 201, 211, ..., 221, respectively, and the sum of the multiplication results.

[0098] The sum of the negligible amounts of current from the memory cells connected to line 241 is smaller than the unit current 232 (e.g., the predetermined amount of current). Therefore, the presence of the negligible amounts of current from the memory cells does not change the result 237 and is negligible in the operation of the analog-to-digital converter 245.

[0099] exist Figure 2, voltages 205, 215, ..., 225 applied to memory cells 207, 217, ..., 227 represent digitized input bits 201, 211, ..., 221; memory cells 207, 217, ..., 227 are programmed to store digitized weight bits; and currents 209, 219, ..., 229 represent digitized results.

[0100] The result 237 is an integer not greater than the count of memory cells 207, 217, ..., 227 connected to line 241. The digitized form of the output currents 209, 219, ..., 229 can improve the accuracy and reliability of calculations performed using the memory cells 207, 217, ..., 227.

[0101] In general, the weights involved in the multiplication and accumulation operations may be more than one bit. Memory cells may be used to store different significant bits of the weights (e.g., Fig.13 ) to perform multiplication and accumulation operations. Figure 2 The circuit illustrated in can be viewed as a multiplier-accumulator unit configured to operate on columns of 1-bit weights and columns of 1-bit inputs. Multiple such circuits can be connected in parallel to implement a multiplier-accumulator unit to operate on columns of multi-bit weights and columns of 1-bit inputs.

[0102] Figure 2 The circuits described in can also be used to read data stored in memory cells 207, 217, ..., 227. For example, the sensing circuit system 150 can be used to sense the current associated with the memory cell. For example, in order to read the data or weight stored in the memory cell 207, the input bit 211, ..., 221 can be set to zero to cause the memory cell 217, ..., 227 to output a negligible amount of current to the line 241 (e.g., as a bit line). The input bit 201 is set to one to cause the voltage driver 203 to apply a predetermined read voltage. Therefore, the result 237 from the digitizer 233 provides the data or weight stored in the memory cell 207. Similarly, the data or weight stored in the memory cell 217 can be read by applying one as the input bit 211 and applying zero as the remaining input bits in the column; and the data or weight stored in the memory cell 227 can be read by applying one as the input bit 221 and applying zero as the other input bits in the column.

[0103] Generally speaking, Figure 2The circuits illustrated in can be used to select any of the memory cells 207, 217, ..., 227 for reading or writing. A voltage driver (e.g., 203) can apply a programming voltage pulse (e.g., one or more pulses or other waveforms, as appropriate for the memory cell type) to adjust the threshold voltage of the corresponding memory cell (e.g., 207) to erase data, store data or weight, etc.

[0104] In general, the inputs involved in multiplication and accumulation operations can be more than 1 bit. For example, columns of input bits can be applied one column at a time to weights stored in a memory cell array to obtain the result of multiplying the column of weights by the column of inputs and accumulating the results.

[0105] Figure 2 The multiplier-accumulator unit described in Figure 1 The integrated circuit device 101 is implemented in the embodiment of the present invention.

[0106] In one implementation, a memory chip (e.g., integrated circuit die 105) includes circuits of voltage drivers, digitizers, shifters, and adders to perform multiplication and accumulation operations. The memory chip may further include circuits configured to control the operations of the drivers, digitizers, shifters, and adders to perform operations such as Figure 2 The control logic of the operations in .

[0107] The inference logic circuit 123 may be configured to use the computing power of the memory chip (e.g., the integrated circuit die 105) to perform inference calculations of an application, such as inference calculations of an artificial neural network. The inference results may be stored in a portion of the memory cell array 113 for retrieval by an external device via the interface 125 of the integrated circuit device 101.

[0108] Optionally, the voltage drivers, digitizers, shifters, adders, and at least a portion of the control logic may be configured in the integrated circuit die 109 of the logic chip.

[0109] Memory cells (e.g., memory cells of array 113) may include volatile memory, nonvolatile memory, or both. Examples of nonvolatile memory include flash memory, memory cells formed based on NAND logic gates, NOR logic gates, phase change memory (PCM), magnetic memory (MRAM), resistive random access memory, cross-point storage, and memory devices. Cross-point memory devices may use transistor-free memory elements, each of which has memory cells and selectors stacked together in columns. The columns of memory elements are connected via two layers of wires extending in a vertical direction, wherein the wires of one layer extend in one direction in a layer located above the columns of memory elements, and the wires of the other layer extend in another direction in a layer located below the columns of memory elements. Each memory element may be individually selected at the intersection of a wire on each of the two layers. Cross-point memory devices are fast and nonvolatile and may be used as a unified memory pool for processing and storage. Further examples of non-volatile memory include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM) memory, etc. Examples of volatile memory include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0110] Integrated circuit die 105 and integrated circuit die 109 may include circuits to address memory cells in memory cell array 113, such as row decoders and column decoders to convert physical addresses into control signals to select a portion of memory cells for reading and writing. Thus, an external device may send commands to interface 125 to write weights into memory cell array 113 and read results from memory cell array 113.

[0111] In some implementations, image processing logic circuit 121 may also send commands to interface 125 to write an image into memory cell array 113 for processing.

[0112] Figure 3 A method for calculation in an integrated circuit device based on summing output currents from memory cells according to one embodiment is presented. For example, Figure 3 The method can be used Figure 2 , 4 or 13 multiplication and accumulation techniques in Figure 1 is executed in the integrated circuit device 101.

[0113] Figure 3The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 3 The method is at least partially performed by one or more processing devices (e.g., Figure 1 The controller 124 of the reasoning logic circuit 123 or the local controller 161 of the integrated circuit die 105 is executed.

[0114] Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0115] At block 301, a memory cell (or a group of memory cells storing bits of a signed weight, such as a group of 4 cells) is programmed to a target weight for performing a multiplication. In one example, the memory cells of the memory cell array 113 are programmed. In one example, the memory cells 207, 206, 208 are programmed to store weights of different bit significance. The weights correspond to multi-bit weights (e.g., Fig.13 In one example, the memory cell is Fig.10 A multi-pillar memory cell.

[0116] At block 303, a voltage is applied to the memory cell. The voltage represents an input bit to be multiplied by the weight stored by the memory cell. In one example, a voltage driver applies the input voltage 205, 215, 225.

[0117] At block 305, the output currents from the memory cells resulting from the applied voltages are summed. In one example, using Figure 2 Line 241 in collects and sums the output currents.

[0118] At block 307, a digital result based on the summed output current is provided. In one example, the summed output current is used to generate Figure 2 The result is X 237.

[0119] In one embodiment, the apparatus further includes an interface (eg, 125) operable for a host system to write data into and read data from the memory cell array.

[0120] In one embodiment, the memory cell includes a first and a second memory cell; the corresponding weight stored by the first memory cell is the most significant bit (MSB) of the multi-bit weight; and the corresponding weight stored by the second memory cell is the least significant bit (LSB) of the multi-bit weight.

[0121] In one embodiment, the digitizer is configured in an analog-to-digital converter.

[0122] Figure 4 An analog weight fixed architecture for matrix vector multiplication (MVM) is shown according to one embodiment. Because the computational burden when executing a neural network is primarily on the MVM operation, an analog weight fixed architecture focused on the MVM operation is used. Other computations / logic required can typically be implemented in the digital and / or analog space as they have relatively little impact on performance and energy efficiency.

[0123] In a weight-fixed architecture, computations are performed where the weights are stored (e.g., in a NAND flash memory device where the weights are stored). This eliminates or reduces the performance bottleneck and power inefficiency of moving weights out of memory for computation. MVM computations are performed in the analog domain. This often results in some computational errors that are not present in the digital domain.

[0124] The weights are stored in a memory cell 405 (e.g., a memory cell) within a memory device (e.g., 101). The input is sent to an electrode 408 of the memory cell, resulting in a multiplication of the input and the weight (based on the conductance of the memory cell storing the weight) (e.g., weight g12 multiplied by input Vin1). Digital-to-analog converters (DACs) 402, 404 convert the digital input into a magnitude of an analog voltage used to drive an electrode 408 (e.g., an access line, such as a select gate drain line).

[0125] The result is summed to another electrode (e.g., 406) within the memory array (e.g., Figure 2 41) and detected by ADCs 420, 422. For example, integrators 410, 412 accumulate currents I1, I2 from memory cell 405 determined by the conductance of the cell and provide the accumulated current as input to the ADCs 420, 422.

[0126] Figure 5 An example architecture that can be used to perform MVM on weights stored within memory cells of a three-dimensional (3D) NAND flash memory device according to one embodiment is shown. The memory cells extend vertically upward from a semiconductor substrate (not shown). The memory cells are arranged as vertical pillars of cells (sometimes referred to as strings). The cells in each pillar / string are connected in series. A bypass voltage (e.g., Vpass) is applied to the gates of unselected memory cells during multiplication.

[0127] The threshold voltage (VT) of the memory cell is set (programmed) based on the expected weight. When the cell is read using the word line voltage, the cell will sink some current that varies according to the weight stored within the cell (based on the cell IV characteristic). The VT of the memory cell is adjusted during programming (e.g., as described above) based on the context of the memory cell as determined by the controller (e.g., 124 and / or 161).

[0128] The inputs multiplied by the weights can be introduced to the pillars in various ways. For example, the inputs are applied as gate voltages of another cell with a fixed threshold (VT). For example, the select gates are used as digital inputs (e.g., by applying a digital time-sliced ​​pulse stream). For example, the inputs are applied on the bit lines.

[0129] In one example, the summing of the multiplication results is done by summing the currents at the bit lines. In one example, the summing of the multiplication results is done by summing the currents at the sources. This approach requires unique source routing that is not part of the traditional 3D NAND architecture.

[0130] More specifically, Figure 5 An analog weight fixing method using a select gate drain (SGD) cell architecture according to one embodiment is shown. For example, each weight (e.g., unsigned or signed bit) is stored in a cell or a group of cells (e.g., 510, 512), where a word line (WL) voltage (e.g., W00, W01, W10, W11) is applied to each selected cell. The input is applied to the select gate drain (SGD) lines 502, 504 (e.g., as a digital time-sliced ​​pulse stream). Select transistors 530, 532 connect each pillar to the bit lines 506, 508. The output currents are summed on the bit lines 506, 508. A bypass voltage is applied to the unselected cells 520, 522 during multiplication.

[0131] Various memory cell implementations can be used to perform signed multiplication (e.g., using Figure 6 In one embodiment, signed multiplication is performed in a so-called four-quadrant system, where each of the inputs and weights to be multiplied can have a positive or negative sign. For example, some neural network models use matrix-vector multiplication, where the weights of the model are signed. In one example, resistive random access memory (RRAM) cells are used. In one example, NAND or NOR flash memory cells are used.

[0132] In one embodiment, matrix-vector multiplication is performed using stored weights. The input signal is multiplied by the weights to provide a result. In one example, the weights are determined by training a neural network model. The model uses both positive and negative values ​​for the weights. In one example, the weights are stored in Figure 1 In a memory cell of the memory cell array 113 of . In one example, the model is trained using image data, and the trained model provides inference results based on input from the image sensor.

[0133] In one instance, the Figure 1 The interface 125 determines the result in response to a request from the host system. In one example, the signed input used to generate the result is based on the signed input of Figure 1 The data collected by the sensor 111.

[0134] In one example, the input line provides a voltage to a group of memory cells. The group has four memory cells. In one example, the input line can be a word line, a bit line, or a select gate line (SL or SGD), depending on the type of memory cells and the specific group configuration (e.g., memory cells arranged in series for NAND flash memory versus memory cells arranged in parallel for RRAM or NOR).

[0135] In one embodiment, an image is provided as an input to a neural network. The neural network includes convolutional layers. Each layer is of a different size. For example, each layer has a different number of features and neurons. The neural network provides a result. In one example, the result is a classification of an object represented by the image.

[0136] When performing calculations, matrix-vector multiplication operations are mapped to tiles in a memory cell array (e.g., 113). For example, such mapping involves identifying portions of the memory cell array to be used during calculations for a particular layer. Such mapping typically changes as calculations progress from one layer to another.

[0137] In one example, the image is data obtained from an array of image sensing pixels of sensor 111. In one example, the weights of the neural network have been programmed into the memory cells of tiles 141, 142.

[0138] Figure 6 An example arrangement of memory cells of a tile of a NAND flash memory array according to one embodiment is shown. The NAND flash memory array is an example of memory cell array 113. The tiles are examples of tiles 141, 142. The memory cells are arranged in vertical strings 610 (e.g., extending over a semiconductor substrate (not shown)).

[0139] The illustrated tile has a size of, for example, 512 features and 512 neurons. The tile has 1,024 bit lines and 1,024 select gate drain (SGD) lines because the tile is configured to store signed weights for each of the 512 neurons. For example, group 602 includes four selected memory cells (indicated by W+, W-) that store bits (e.g., LSB bits or MSB bits) of the signed weights.

[0140] The input for the multiplication is provided on a select gate line 604. The select gate line is used to turn on or off a select transistor (e.g., 605) depending on the value of the input. For example, each bit position of the input feature vector (X0, X1, X2, etc.) is stretched in series. Each Xn is the same bit position for each of the 512 features. The output current from the selected memory cell is accumulated on a bit line (e.g., 606).

[0141] In one embodiment, the memory device includes tiles organized into an array of memory cells, such as 113. In one example, the array includes about 1,500 NAND tiles. The tiles are populated (programmed) with the weights of the neurons to be used. The specific weights valid for a given MVM calculation will vary.

[0142] Each tile includes neurons and features. In one example, each of the neurons corresponds to a bit line or source line used to accumulate the output current of the memory cell. In one example, each of the features corresponds to a select gate drain line used to provide one or more input bits for multiplication of the weight stored in the memory cell.

[0143] In preparation for the matrix-vector multiplication operation, the controller causes voltage biases to be applied to the various access lines of the tile. These access lines may include bit lines or source lines and / or select gate drain lines. These access lines may further include word lines and / or other lines of the memory cell array. In one embodiment, the bias applied to one or more of the aforementioned access lines varies based on the context determined for the memory cell and / or memory cell array. The bias adjustment may be different for each type of access line and / or individual access lines.

[0144] In one embodiment, the bit lines are electrically shorted (e.g., by Fig.10 12) so that each memory cell can use transistors from two or more pillars. For example, the bit lines can be shorted so that the unit line pair can operate as a single logical bit line for a multi-pillar memory cell.

[0145] In one embodiment, the bit lines are precharged and used during the multiplication operation. In one embodiment, each bit line is connected to an analog-to-digital converter (ADC). Each ADC will be charged and used during the multiplication operation. In one embodiment, the bit lines are precharged using adjustments based on the context of the memory cell array (e.g., as described above).

[0146] Figure 7 Sense circuitry (e.g., using a sense amplifier or other sense circuit) coupled to a bit line 704 used to access a NAND flash memory cell is shown according to one embodiment. The sense circuitry may include an ADC. The memory cells are located in a string 702. Select gate drain and source transistors 706, 708 are used to control access to the string 702. Select gate transistor 706 is coupled to bit line 704.

[0147] The sensing circuitry includes a current source 718 used to precharge the bit line 704 in preparation for sensing the current (eg, accumulated output current) and / or state of a selected memory cell in the string 702. The sensing circuitry is connected to the bit line 704 through a transistor 710.

[0148] During sensing, node 712 is charged, which corresponds to capacitance 714 (eg, parasitic capacitance of the sensing circuitry). Bit line 704 is also charged.

[0149] In one embodiment, the memory device uses an array of memory cells organized into groups of memory cells. In one example, resistive random access memory (RRAM) cells are used. In one example, NAND or NOR flash memory cells are used.

[0150] Each group can be programmed to store a multi-bit signed weight. After being programmed, a voltage driver (adjusting the voltage based on the context in which the memory cell is used) applies a voltage to the memory cells in each group. The voltage represents the multi-bit signed input to be multiplied by the multi-bit signed weight.

[0151] One or more common lines are coupled to each group. The lines receive one or more output currents from the memory cells in each group (eg, similar to that discussed above for groups of two or four cells, for example). Each common line accumulates the currents to sum the output currents from the group.

[0152] In one example, the line(s) are bit lines that extend vertically above the semiconductor substrate. As an example, 512 groups of memory cells are coupled to the line(s). Input is provided using 512 pairs of select lines (e.g., SL+, SL-), with one pair used for each group. The output current from each of the 512 groups is collected on the line(s), and then one or more total current magnitudes are digitized to provide first and second digital values.

[0153] In one example, the memory device includes one or more digitizers. The digitizer(s) provide a signed result based on summing the output current from each of the 512 sets on the first and second common lines (eg, as described above).

[0154] A first digital value (e.g., an integer) representing the current on the first common line is determined as a multiple of a predetermined current (e.g., as described above) representing 1. A second digital value representing the current on the second common line is determined as a multiple of the predetermined current. The first and second digital values ​​are, for example, outputs from digitizer(s).

[0155] In one embodiment, a memory device includes a memory cell array having groups of NAND flash memory cells (eg, using Figure 6 An array of digitizers is provided. Each group is programmable to store a multi-bit signed weight. A voltage driver applies a voltage to each group. The voltage corresponds to a multi-bit signed input that is multiplied by a multi-bit signed weight for each group. Two common lines are coupled to each group. Each common line sums a corresponding output current from each group. A digitizer on each common line provides a signed result based on the sum of the output currents from the group. Each signed result corresponds to a bit significance of the input and a bit significance of the weight, for example as described above. The signed results are added together taking into account the corresponding bit significance to provide a first and a second digital value representing a signed accumulation result from a multi-bit to multi-bit multiplication.

[0156] In one embodiment, a signed input is applied to a group of memory cells on two conductors (e.g., two select lines), each conductor carrying a signal. Whether the input is positive or negative depends on where the magnitude of the signal is provided. In other words, the sign depends on which conductor carries the signal. The other conductor carries a signal of a constant value (e.g., a constant voltage corresponding to zero).

[0157] Each signed input applied to the group is considered to have a positive magnitude. One of the two wires is always biased to zero (more generally to a constant signal). The other wire carries the magnitude of the input pattern.

[0158] In one embodiment, a multi-bit input is represented as a serial or time-sliced ​​input provided on two wires. For example, an input pattern is a number of bits (e.g., 1101011) for which a corresponding voltage is applied serially to the wires, one bit per time slice. In one example, the input bits are applied serially one at a time.

[0159] In one embodiment, the contribution of the output current from each of the memory cells to the common line varies corresponding to the MSB, MID, or LSB significance of the bit stored by the memory cell (e.g., for the 3 bits stored in the group of 3 memory cells described above). The contribution of the highest significance (e.g., 100 nA) is twice the MID significance (e.g., 50 nA). The contribution of the MID significance is twice the LSB significance (e.g., 25 nA).

[0160] When the output current contribution takes into account the bit significance, then no left shift is required when adding the signed results (e.g., the first, second, third, and fourth signed results) to obtain the signed accumulation result. Alternatively, the signed results can be added directly without left shift.

[0161] In one embodiment, a memory device performs an analog summation of 1-bit result currents with different bit significance implemented via different bias voltage levels. A memory cell (e.g., an RRAM cell or a NAND flash memory cell) can be programmed to have a current that increases exponentially (e.g., increases by a power of 2) for different bias voltage levels.

[0162] In one embodiment, a memory cell may be programmed to have a threshold with a current that increases exponentially for higher bias / applied voltages. A first voltage may be applied to the memory cell to allow a predetermined amount of current (indicated as 1X) to pass to represent a bit value of 1 for the least significant bit.

[0163] To represent a bit value of 1 for the second least significant bit, a second voltage may be applied to the memory cell to allow twice (indicated as 2X) the predetermined amount of current to pass, which is equal to the predetermined amount of current multiplied by the bit significance of the second least significant bit.

[0164] When the bit value is 1, the memory cell may similarly be biased to have a higher current amount equal to a predetermined current amount multiplied by the bit significance of the bit.

[0165] When different voltages are applied to memory cells that each represent a bit in a number so that the respective bit significance of each cell is built into the output current as described above, the results of multiplications involving the memory cells can be summed by connecting them to lines without having to individually convert the currents for the bits for summation.

[0166] For example, a 3-bit resolution weight can be implemented using three memory cells. Each memory cell stores 1 bit of the 3-bit weight. Each memory cell is biased at a separate voltage level so that if it is programmed in a state representing 1, the current through the cell is the base unit multiplied by the bit significance of the cell. For example, the current through the cell storing the least significant bit (LSB) is 25nA of the base unit, the current through the cell storing the middle bit (MID) is 2 times (2x) of the base unit (50nA), and the current through the cell storing the most significant bit (MSB) is 4 times (4x) of the base unit (100nA).

[0167] In one embodiment, a solid state drive (SSD) or other storage device uses a memory cell array having memory cells. In one example, resistive random access memory (RRAM) cells are used. In one example, NAND or NOR flash memory cells are used.

[0168] In one embodiment, each memory cell can be programmed to store one bit of a multi-bit weight. After being programmed, a voltage driver applies different voltages to bias the memory cell for performing multiplication. The input to be multiplied by the multi-bit weight can be represented by a corresponding input pattern applied to a select gate coupled to a select transistor of the memory cell (e.g., as described above), or by varying different voltages between a fixed voltage state representing an input bit 1 and a zero state representing an input bit 0.

[0169] One or more common lines are coupled to the memory cells. The lines receive one or more output currents from the memory cells (eg, as described above). Each common line (eg, a bit line) is used to accumulate the currents to sum the output currents.

[0170] In one embodiment, three memory cells store a three-bit value representing a stored weight. One bit is used for the MSB, one bit is used for a bit of medium significance (sometimes indicated herein as "MID"), and one bit is used for the LSB. This provides a multi-bit representation of the stored weight.

[0171] In one example, when programming memory cells, programming for individual cells is adjusted due to predicted IR drop, etc. For example, the controller shifts each cell threshold voltage during programming so that the initial current during programming is at a higher level. It should be noted that during placement (programming), the current level is typically lower because individual cells are calibrated for programming. Therefore, the drain voltage tends to be closer to the driver output voltage (and IR drop is minimized or greatly reduced). In contrast, during inference, for example, many pillars may be selected, so the bit line current may be relatively high, which causes a large IR drop.

[0172] Figure 8Strings of memory cells are shown connected to a common bit line segment 802 according to one embodiment. For example, strings 808, 810 are connected to bit line segment 802. Each string contains memory cells connected in series to select transistors 818, 819. An input pattern 820 for a multiplication operation is applied to the gates of select transistors 818, 819.

[0173] Voltage driver 804 applies a voltage to bit line segment 802 using bit line strap 806. In one embodiment, bit line strap 806 is connected to other bit line segments (not shown). In one example, voltage driver 804 includes an analog-to-digital (ADC) converter. In one example, voltage driver 804 applies a voltage of 0.3V to bit line strap 806.

[0174] The weights are stored in the memory cells of each string. For example, the memory cells 814, 816 are programmed to store the weights by programming to an adjusted threshold voltage or an adjusted target current. For example, during a multiplication operation, the cell current (e.g., Fig. 9 's I_String) flows through each of the memory cells 814, 816.

[0175] During a multiplication operation, current from one or more of the strings flows through the bit line segment 802 (e.g., when output currents are accumulated from multiple strings). This causes a voltage drop due to the parasitic resistance 812 of various portions of the bit line segment 802. The voltage drop has a greater magnitude as the distance of the bit line segment 802 through which the current flows increases. For example, strings closer to the voltage driver 804 have drain voltages 824 that are closer in magnitude to the voltage applied by the voltage driver 804. Strings farther from the voltage driver 804 have drain voltages 822 that exhibit a more significant voltage drop (e.g., significantly less than the 0.3V applied by the voltage driver 804) than strings closer to the voltage driver 804.

[0176] Fig. 9 An example target current on an IV curve 902 of a memory cell is shown, where each target current corresponds to a different weight value. The illustrated graph plots the string current I_String versus VGS-VT, which is the gate voltage VGS applied to a selected memory cell minus the threshold voltage VT of the cell. Curve 902 corresponds to a drain voltage VDS applied to the memory cell.

[0177] Each of several weight values ​​Weight0 to Weight7 corresponds to a magnitude of an output current from the memory cell during multiplication (e.g., see points 904, 906, 908 on IV curve 902). For example, Weight7 corresponds to an output current of 105 nA. It is desirable that these output currents be stable during multiplication so that the results from the multiplication are accurate. In one example, these weights provide initial weight targets that can be provided by the host when programming the memory cells to support multiplication for a given layer of the neural network.

[0178] Fig.10 A bit line used to access a multi-pillar memory cell of a memory array is shown according to one embodiment. The bit line includes two bit line segments 1002, 1004 that are electrically connected. For example, the bit line segments 1002, 1004 are electrically shorted together using conductive shunts 1050, 1052.

[0179] In one embodiment, shunts 1050, 1052 are formed as part of the same conductive layer used to form bit line segments 1002, 1004. In one example, the conductive layer is a top metal layer of a NAND flash memory array.

[0180] In various embodiments, the shunt may be located at various different locations along the bit line. The size of the shunt may vary. In one example, the shunt may be a portion of a conductive layer that extends over 50% of the length of the bit line.

[0181] By electrically shorting the bit line segments 1002, 1004, the bit line effectively operates as a single logical bit line used to access memory cells of a memory cell array (e.g., 113) storing weights of a neural network. Each memory cell stores a single weight. Each memory cell includes at least one transistor from each of two or more rows of pillars underlying the bit line.

[0182] For example, transistor 1030 from pillar 1006 and transistor 1040 from pillar 1008 together provide a single memory cell storing a single weight. This single memory cell provides a total output current accumulated on the bit line. The total output current corresponds to the stored weight. The total output current includes two component currents. The first current is provided by transistor 1030, and the second current is provided by transistor 1040.

[0183] Pillars 1006, 1008 are electrically connected to the bit lines through select gate transistors 1032, 1042. The same input pattern used for multiplication is provided to the gates of select transistors 1032, 1042. When performing multiplication, a memory cell is selected by applying a bias voltage to the gates of transistors 1030, 1040 using a common word line (not shown).

[0184] In this manner, other memory cells configured using transistors from two or more pillars provide output current contributions to the bit line. The output current is accumulated from multiple pillars and the total accumulated current is sensed by the sensing circuit system 1020. For example, the total accumulated current corresponds to the digital result from a matrix-vector multiplication of the input pattern multiplied by the weights stored in the multi-pillar memory cell.

[0185] In one example, each multi-pillar memory cell uses transistors from at least two adjacent pillars. In one example, each multi-pillar memory cell uses transistors from at least three or more pillars.

[0186] In one embodiment, the bit lines are formed as rows overlying pillars. For example, a first row of pillars includes pillars 1006 and 1010. A second row of pillars includes pillars 1008 and 1012. A multi-pillar memory cell electrically connected to the bit lines uses at least one transistor from each of two different rows of pillars. In one example, the rows of pillars are adjacent to each other in the memory array.

[0187] In one embodiment, the distance between the bit line segments 1002, 1004 used in the layout for manufacturing the integrated circuit is consistent for some or all bit line segments. For example, a constant pitch in the mask of the photolithography process used to form the bit lines is used to layout the bit lines.

[0188] In one example, the constant pitch corresponds to the pitch of the bit lines used to lay out a single-pillar memory cell. In one example, the single-pillar memory cell corresponds to Figure 8 814, 816 are shown in. In this single pillar memory cell approach, a single bit line segment 802 overlies a single row of pillars.

[0189] In some cases, the thickness of a single bit line segment 802 is narrow enough to make the resistance higher than desired, resulting in increased IR drop. In one embodiment, to reduce this IR drop, the bit line segments 1002, 1004 are drawn as a single connecting metal layer in the layout mask (e.g., see Fig.12 ). This reduces the resistance of the effective bit line in the circuit path to the multi-pillar memory cell and therefore reduces the IR drop.

[0190] In one embodiment, a memory device may be formed using both single-pillar memory cells and multi-pillar memory cells. For example, a layout mask may define a portion of a metal layer to provide a bit line segment connected to a single-pillar memory cell. A different portion of the layout mask may define a bit line segment that is electrically shorted for use with a multi-pillar memory cell.

[0191] In one embodiment, the shunts 1050, 1052 may be formed from a different conductive layer than the conductive layer used to form the bit line segments. For example, the conductive layer (not shown) forming the shunts may be higher or lower than the height of the conductive layer forming the bit line segments. Vias or other interconnects (not shown) may be used to electrically connect the two conductive layers (shunts and bit lines) as needed to perform electrical shorting of the bit line segments.

[0192] In one embodiment, the two transistors forming the multi-pillar memory cell have the same applied input signal, and / or they have the same level selection control (e.g., using a common word line). This is a bit like increasing the size of each memory cell. The two transistors act as a single memory cell storing the weight.

[0193] As an example, if the target output current for a given weight is 200 nanoamps (nA), then the use of two transistors reduces the current through each cell to about 100 nanoamps. This reduces the load on each leg. Thus, for example, when two legs are used in parallel, the target output current can be safely increased to, for example, 300 nanoamps.

[0194] In one embodiment, a memory device or memory array may use a dual bit line configuration with multi-pillar memory cells in a first portion of the device or array and a single bit line configuration with single pillar memory cells in a second portion of the device or array, depending on the foreseen current demand for multiplication. For example, a controller may choose to use the first or second portion depending on the expected current demand (e.g., for a given layer of a neural network) based on known information about weights, AI models, etc.

[0195] In one embodiment, the controller operation when using two bit line segments shorted together is substantially the same as the bit line usage.The two transistors in each memory cell are programmed and read together as a single cell.

[0196] In one embodiment, the multi-pillar memory cell method can be applied to store weights for more significant bits, which typically have higher currents. The unit line method with a single-pillar memory cell can be used for the least significant bit, which typically has lower currents. These two methods can be used in different parts of a memory array or device.

[0197] Fig.11 A top view of a bit line used to access a single pillar memory cell is shown. Each bit line segment 1102, 1104, 1106, 1108 operates as a single logical bit line used to access a memory cell in a row of pillars underlying the memory cell. For example, bit line segment 1102 accesses memory cells in pillars 1110, 1112. In one example, the top view of the bit line segment is from a top-down perspective, such as from a top-down perspective. Figure 8 The bit line segment 802.

[0198] In one example, each bit line segment has a constant layout pitch, such as described above. In some cases, the width of the bit line segment is narrower than desired, which may result in an undesirably increased IR drop.

[0199] Fig.12 A top view of a bit line for accessing a multi-pillar memory cell according to one embodiment is shown. In one example, the top view is a top view of Fig.10 A view of the bit lines.

[0200] In one embodiment, bit line segments 1102, 1104 are drawn in the layout mask so as to provide a single valid bit line 1202. Similarly, bit line segments 1106, 1108 are drawn to provide a single valid bit line 1204. In one example, valid bit line 1202 corresponds to Fig.10 The electrically shorted bit line segments 1002, 1004.

[0201] The bit line 1202 overlies pillars 1210, 1212, 1214. In one example, these pillars are arranged in adjacent rows of the memory array. Increasing the width of each active bit line 1202, 1204 reduces the resistance so that the IR drop is reduced.

[0202] The bit lines 1202, 1204 are illustrated as being formed by combining adjacent bit line segment pairs (e.g., 1102, 1104). However, in other embodiments, another three adjacent bit line segments may be combined to provide a single valid bit line. For example, all bit line segments 1102, 1104, 1106, 1108 may be combined to provide a single logical bit line. In this case, each multi-pillar memory cell may use transistors from each of the different rows of pillars underlying different bit line segments. In one example, each bit line 1202, 1204 is connected to the sensing circuitry (e.g., 1020).

[0203] In one example, there is a vertical connection from each bit line to a driver located in the underlying semiconductor substrate.Support circuitry may be located below the memory array on the semiconductor substrate.

[0204] In some cases, shunting the bit lines together as described herein can allow more levels to be added in the vertical direction. This is because the current through any given pillar can be lower than in the unit line approach. The shunting approach can also allow existing NAND manufacturing methods to be used, but with additional levels added, because the shunting reduces the load on any given pillar / cell.

[0205] Fig.13An architecture with resistive random access memory (RRAM) or NOR memory cells arranged in a parallel configuration for performing multiplication (e.g., MVM) according to one embodiment is shown. For example, memory cells 1330, 1331, 1332 of memory cell array 1302 store bits of respective significance for a multi-bit weight (indicated as Weight1). A simple 3-bit weight is illustrated, but a larger number of bits may be stored for each weight. When performing multiplication, each of memory cells 1330, 1331, 1332 may be accessed in parallel. In one example, memory cell array 1302 includes a plurality of memory cells 1330, 1331, 1332, each of which may be accessed in parallel. Figure 6 Memory cells arranged as described in .

[0206] Each memory cell provides an output current corresponding to the validity of the bit stored by the memory cell.Memory cells 1330, 1331, 1332 are connected to a common line 1310 for accumulating the output currents.In one example, line 1310 is a bit line.

[0207] Different voltages V1, V2, V3 are applied to memory cells 1330, 1331, 1332 using word lines 1320, 1321, 1322. The voltages are selected so that the output current varies by a power of 2 based on the bit significance, such as described above.

[0208] In one embodiment, input signal I1 is applied to the gate of select transistor 1340. Select transistor 1340 is coupled to common line 1310. The output of select transistor 1340 provides the sum of output currents. In one embodiment, when the input signal is applied to the gate of select transistor 1340, different voltages V1, V2, V3 are maintained at a constant voltage level.

[0209] In an alternative embodiment, similar to the above description, by varying different voltages V1, V2, V3 between a fixed voltage and a zero voltage, an input pattern for multiplying Weight1 may be applied to word lines 1320, 1321, 1322 to represent input bits 1 or 0, respectively.

[0210] The memory cell array 1302 is formed over a semiconductor substrate 1304. In one embodiment, the memory cell array 1302 and the semiconductor substrate 1304 are on different chips or wafers (eg, joined by bonding) before being assembled.

[0211] Similarly, as described above for Weight1, multi-bit weights Weight2 and Weight3 can be stored in other memory cells of the memory cell array 1302, and the output currents are accumulated on common lines 1311, 1312, as illustrated. These other memory cells can be accessed using word lines 1320, 1321, 1322. Common lines 1311, 1312 are coupled to select transistors 1341, 1342, which each provide the sum of the output currents as output. Input patterns I2, I3 can be applied to the gates of the select transistors. Additional weights can be stored in the memory cell array 1302.

[0212] The output currents from the common lines 1310, 1311, 1312 are accumulated by accumulation circuitry 1350. In one embodiment, accumulation circuitry 1350 is formed in semiconductor substrate 1304 (eg, at the top surface).

[0213] In one embodiment, voltage driver 1306 and bias circuitry 1305 are formed in semiconductor substrate 1304. Logic circuitry (not shown) formed in semiconductor substrate 1304 is used to implement controller 1303. Controller 1303 controls voltage driver 1306 and bias circuitry 1305.

[0214] In one embodiment, voltage driver 1306 provides different voltages V1, V2, and V3. Each voltage is adjusted based on the context of the memory cell array as determined by a controller (eg, 124, 161). Bias circuitry 1305 applies inputs I1, I2, I3.

[0215] Fig.14 A method for forming a memory device having multi-pillar memory cells for use in performing multiplication is presented according to one embodiment. For example, Fig.14 The method can be found in Figure 1 The integrated circuit device 101 is executed in the integrated circuit device 101 (for example, as described above in various embodiments).

[0216] Fig.14 The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Fig.14 The method is at least partially performed by one or more processing devices (e.g., Figure 1 Controller 124 and / or 161) is used to execute.

[0217] Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0218] At block 1401 , logic circuitry is formed on a semiconductor substrate. In one example, the logic circuitry is inference logic circuit 123 .

[0219] At block 1403 , a memory cell array is formed over a semiconductor substrate. The memory cell array uses multi-pillar memory cells. In one example, the memory cell array is array 113 .

[0220] At block 1405, a conductive layer is formed over the memory cell. In one example, the conductive layer is a metal layer used to form bit lines in a NAND flash memory array.

[0221] At block 1407, the conductive layer is patterned to provide bit lines (eg, see Fig.12 ). The bit lines are electrically connected to the memory cells for accumulating output currents from the memory cells. In one example, the bit lines accumulate output currents from transistors connected in series. In one example, the transistors are configured in pillars 1006, 1008, 1010, 1012.

[0222] In one example, the output currents from the memory cells are summed using the bit line segments 1002, 1004 to store the Fig.10 The weights in the multi-pillar memory cell are multiplied by one or more input patterns. In one example, the accumulation circuitry accumulates the output currents on the bit lines and generates a digital result corresponding to the sum of the output currents.

[0223] In one embodiment, a memory device includes: a semiconductor substrate; a memory array (e.g., 113) having memory cells, the memory array extending vertically above the semiconductor substrate, and the memory array including at least one first pillar (e.g., 1006, 1010) of transistors (e.g., a first row of pillars) and at least one second pillar (e.g., 1008, 1012) of transistors (e.g., a second row of pillars extending parallel to the first row), wherein each memory cell includes a corresponding first transistor from the first pillar and a corresponding second transistor from the second pillar; a bit line (e.g., bit line segments 1002, 1004 are electrically shorted to provide an effective single bit line) overlying the first and second pillars, wherein the bit line is electrically connected to the first and second pillars, and the bit line is configured to accumulate output currents from the first and second pillars when performing multiplication (e.g., MVM).

[0224] In one embodiment, each transistor is a NAND flash transistor.

[0225] In one embodiment, the device further includes a word line configured to select a first memory cell, wherein the word line is connected to the gates of the respective first and second transistors of the first memory cell, and wherein the bit line is configured to accumulate an output current from the first memory cell (e.g., the output current is provided by substantially equal current from each of the first and second transistors).

[0226] In one embodiment, each of the first and second pillars is electrically connected to the bit line (e.g., the first and second parallel rows of pillars are connected to the same common bit line) through a select transistor (e.g., 1032, 1042). At least one input pattern for the multiplication is applied to the gate of the select transistor.

[0227] In one embodiment, the apparatus further comprises an accumulator to accumulate the output currents from the multiplication and provide a digital result of the multiplication.

[0228] In one embodiment, each memory cell (eg, memory cells using transistors 1030, 1040) is configured to store a weight used in the multiplication when the memory cell has been selected.

[0229] In one embodiment, each memory cell is programmed to store the weight and the first and second transistors of the memory cell are programmed in parallel.

[0230] In one embodiment, the first and second transistors of each memory cell are programmed to store respective weights such that the sum of the output currents from the first and second transistors during the multiplication corresponds to a target current for the respective weight (e.g., each of the first and second transistors is configured to provide half of the target current).

[0231] In one embodiment, a method includes: forming a logic circuit system on a semiconductor substrate; forming a memory cell array above the semiconductor substrate, the memory cell array including pillars, wherein each pillar has a transistor connected in series, each pillar extends vertically above the semiconductor substrate, and each of a plurality of first memory cells includes a corresponding first transistor of the first pillar and a corresponding second transistor of the second pillar; forming a conductive layer above the pillars; and patterning the conductive layer to provide bit lines (e.g., 1202, 1204) electrically connected to the pillars (e.g., 1210, 1214), wherein the bit lines include a first bit line for accessing the first memory cell.

[0232] The logic circuitry is configured to: program the first memory cell to store a first weight of a neural network; and after programming the first memory cell, perform a multiplication based on accumulating output currents from the first memory cell using the first bit line.

[0233] In one embodiment, the first memory cell is coupled to the first bit line through a select transistor, and performing the multiplication includes applying at least one input pattern to a gate of the select transistor.

[0234] In one embodiment, the method further includes: applying a bias voltage to the first bit line during the multiplication and using at least one voltage driver; and determining an accumulated result from the multiplication by measuring the sum of the output currents using a sensing circuit system coupled to the first bit line.

[0235] In one embodiment, the first bit line includes first and second bit line segments (eg, 1002, 1004) electrically connected to configure the first bit line to operate as a single logical bit line.

[0236] In one embodiment, the method further includes forming at least one shunt (eg, 1050, 1052), wherein the first and second bit line segments are electrically connected through the shunt.

[0237] In one embodiment, the conductive layer is a first conductive layer, and the shunt is formed using a second conductive layer (eg, a metal layer) located at a vertical height that is higher or lower than a vertical height of the first conductive layer relative to the semiconductor substrate.

[0238] In one embodiment, the first pillars are arranged in a first row; the second pillars are arranged in a second row; and the first bit line is formed to overlie the first and second rows.

[0239] In one embodiment, the method further includes forming a voltage driver on the semiconductor substrate, and forming a vertical interconnect (eg, via) to connect the voltage driver to the bit line.

[0240] In one embodiment, an apparatus includes a host interface configured to communicate with a host, a memory cell array including memory cells configured to store weights and access lines configured to access the memory cells.

[0241] The array includes rows of pillars. Each pillar has transistors electrically connected in series, and each memory cell of the array includes respective transistors from at least two respective pillars located in adjacent rows of the pillars (e.g., a memory cell includes transistors from each of four adjacent pillars).

[0242] The array also includes logic circuitry configured to: receive a first weight of a neural network from the host via the host interface; program a first memory cell to store the first weight; and perform multiplication of the first weight by a first input by summing output currents from the first memory cell.

[0243] In one embodiment, the memory cell is a resistive random access memory (RRAM) cell, a phase change memory (PCM) cell, a NOR flash memory cell, or a NAND flash memory cell.

[0244] In one embodiment, the access line is a bit line overlying the pillar.

[0245] In one embodiment, the apparatus further includes sensing circuitry coupled to the bit line and configured to measure an output current from the memory cell.

[0246] Integrated circuit device 101 (e.g., Figure 1) can be configured as a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0247] Integrated circuit device 101 (e.g., Figure 1 The image sensor (in the embodiment of the present invention) can be installed in a computing system as a memory subsystem with embedded image sensors and inference computing capabilities. Such a computing system can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a part of a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device including a memory and a processing device.

[0248] Generally speaking, a computing system may include a memory system coupled to one or more memory subsystems (e.g., Figure 1 In one example, the host system is coupled to a memory subsystem.

[0249] As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0250] For example, the host system may include a processor chipset (e.g., a processing device) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, the host system uses a memory subsystem to write data to the memory subsystem and read data from the memory subsystem.

[0251] The host system may be coupled to the memory subsystem via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS) interface, a double data rate (DDR) memory bus interface, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM slot interface supporting double data rate (DDR)), an open NAND flash interface (ONFI), a double data rate (DDR) interface, a low power double data rate (LPDDR) interface, a compute express link (CXL) interface, or any other interface. The physical host interface may be used to transfer data between the host system and the memory subsystem. When the memory subsystem is coupled to the host system through a PCIe interface, the host system may further utilize an NVM express (NVMe) interface to access components (e.g., memory devices). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem and the host system. In general, a host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, or a combination of communication connections.

[0252] The processing device of the host system may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some examples, the controller may be referred to as a memory controller, a memory management unit, or an initiator. In one example, the controller controls communications on a bus coupled between the host system and the memory subsystem. Generally speaking, the controller may send commands or requests for desired access to the memory device to the memory subsystem. The controller may further include an interface circuit system for communicating with the memory subsystem. The interface circuit system may convert responses received from the memory subsystem into information for the host system.

[0253] The controller of the host system can communicate with the controller of the memory subsystem to perform operations such as reading data, writing data, or erasing data at the memory device and other such operations. In some examples, the controller is integrated into the same package of the processing device. In other examples, the controller is separated from the package of the processing device. The controller or processing device may include hardware, such as one or more integrated circuits (ICs), discrete components, buffer memory or cache memory, or a combination thereof. The controller or processing device may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0254] A memory device may include any combination of non-volatile memory components of different types and volatile memory components. A volatile memory device may be, but is not limited to, a random access memory (RAM) such as a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM).

[0255] Some examples of non-volatile memory components include NAND (or NOT AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0256] Each of the memory devices may include one or more arrays of memory cells. One type of memory cell (e.g., a single level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices may include one or more arrays of memory cells (e.g., SLC, MLC, TLC, QLC, PLC, or any combination thereof). In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell, or any combination thereof. The memory cells of a memory device may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0257] Although non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device may be based on any other type of non-volatile memory such as read-only memory (ROM), phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0258] A memory subsystem controller (or simply referred to as a controller) can communicate with a memory device to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device (e.g., in response to commands dispatched by the controller on a command bus). The controller may include hardware, such as one or more integrated circuits (ICs), discrete components, or buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0259] The controller may include a processing device (processor) configured to execute instructions stored in a local memory. In the illustrated example, the local memory of the controller includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem, including handling communications between the memory subsystem and the host system.

[0260] In some embodiments, the local memory may include memory registers that store memory pointers, fetched data, etc. The local memory may also include a read-only memory (ROM) for storing microcode. Although the example memory subsystem includes a controller, in another embodiment of the present disclosure, the memory subsystem does not include a controller, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0261] In general, the controller may receive commands or operations from the host system and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device. The controller may be responsible for other operations associated with the memory device, such as wear leveling operations, obsolete item collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses). The controller may further include a host interface circuit system for communicating with the host system via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device, and convert responses associated with the memory device into information for the host system.

[0262] The memory subsystem may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from a controller and decode the addresses to access a memory device.

[0263] In some embodiments, a memory device includes a local media controller that operates in conjunction with a memory subsystem controller to perform operations on one or more memory cells of the memory device. An external controller (e.g., a memory subsystem controller) can manage the memory device externally (e.g., perform media management operations on the memory device). In some embodiments, the memory device is a managed memory device, which is a raw memory device combined with a local media controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0264] The controller or memory device may include a storage manager configured to implement the storage functions discussed above. In some embodiments, the controller in the memory subsystem includes at least a portion of the storage manager. In other embodiments or combinations, the controller or processing device in the host system includes at least a portion of the storage manager. For example, the controller or processing device may include logic circuitry that implements the storage manager. For example, the controller or processing device (processor) of the host system may be configured to execute instructions stored in the memory for performing the operations of the storage manager described herein. In some embodiments, the storage manager is implemented in an integrated circuit chip disposed in the memory subsystem. In other embodiments, the storage manager may be part of the firmware of the memory subsystem, the operating system of the host system, a device driver or application, or any combination thereof.

[0265] In one embodiment, an example machine of a computer system is executable, and a set of instructions for causing the machine to perform any one or more of the methods discussed herein is stored in the machine. In some embodiments, the computer system may correspond to a host system that includes, is coupled to, or utilizes a memory subsystem or can be used to perform the operations described above. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet, or any combination thereof. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0266] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, a network attached storage facility, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0267] An example computer system includes a processing device, a main memory (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static random access memory (SRAM), etc.), and a data storage system, which communicate with each other via a bus (which may include multiple buses).

[0268] The processing device may be one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or a processor implementing a combination of instruction sets. The processing device may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device is configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include a network interface device for communicating over a network.

[0269] The data storage system may include a machine-readable medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The instructions may also reside completely or at least partially within the main memory and the processing device during execution by the computer system, the main memory and the processing device also constituting machine-readable storage media. The machine-readable medium, data storage system, or main memory may correspond to a memory subsystem.

[0270] In one embodiment, the instructions include instructions to implement functionality corresponding to the operations described above. Although the machine-readable medium is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0271] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Mainly for common purposes, it sometimes proves convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0272] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0273] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0274] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0275] In one embodiment, the memory device includes a voltage driver (e.g., Figure 2 203, 213, 223) and / or other components. The controller is instructed by firmware or other software. The software may be stored as instructions on a machine-readable medium, which may be used to program the controller. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0276] In this description, various functions and operations may be described as being performed or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that the meaning of such statements is that the functions are caused by one or more controllers or processors (such as microprocessors) executing computer instructions. Alternatively or in combination, the functions and operations may be implemented using dedicated circuit systems (such as using application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs)) with or without software instructions. Embodiments may be implemented using hardwired circuit systems without software instructions or in combination with software instructions. Therefore, the technology is neither limited to any specific combination of hardware circuit systems and software, nor to any specific source of instructions executed by the data processing system.

[0277] Unless specifically stated otherwise, disjunctive language such as the phrase "at least one of X, Y, or Z" should be understood in the context as generally used to present items, terms, etc., to mean either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require the presence of at least one of X, at least one of Y, or at least one of Z, respectively.

[0278] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A device comprising: Select transistors; at least one first leg of the transistor; at least one second pillar of transistors, wherein each of a plurality of memory cells comprises a respective first transistor from the first pillar and a respective second transistor from the second pillar; and A bit line overlies the first and second pillars, wherein each of the first and second pillars is electrically connected to the bit line through the select transistor.

2. The device of claim 1 , further comprising a word line configured to select a first memory cell, wherein the word line is connected to gates of the respective first and second transistors of the first memory cell, and wherein the bit line is configured to accumulate output current from the first memory cell.

3. The apparatus of claim 1, wherein at least one input pattern for multiplication is applied to the gate of the select transistor, the apparatus further comprising an accumulator to accumulate memory cell output currents and provide a digital result of the multiplication.

4. The device of claim 1, wherein the first and second transistors of each memory cell are programmed in parallel to store a respective weight used in multiplication when the memory cell has been selected.

5. A method comprising: forming a logic circuit system on a semiconductor substrate; forming a memory cell array over the semiconductor substrate; forming a conductive layer over the array; and patterning the conductive layer to provide bit lines, the bit lines including a first bit line for accessing a first memory cell; Wherein the logic circuitry is configured to accumulate output current from the first memory cell using the first bit line.

6. The method according to claim 5, further comprising: applying a bias voltage to the first bit line during multiplication and using at least one voltage driver; and An accumulated result from the multiplication is determined by measuring the sum of the output currents using sensing circuitry coupled to the first bit line.

7. The method according to claim 5, wherein: The first bit line includes first and second bit line segments electrically connected by at least one shunt to configure the first bit line to operate as a single logical bit line; The conductive layer is a first conductive layer; and The shunt is formed using a second conductive layer located at a height higher or lower than a height of the first conductive layer relative to the semiconductor substrate.

8. A device comprising: a host interface configured to communicate with a host; and A memory cell array comprising memory cells configured to store weights received from the host and access lines configured to access the memory cells, wherein the array comprises rows of pillars and each memory cell of the array comprises respective transistors from at least two respective pillars located in adjacent rows of the pillars.

9. The apparatus of claim 8, further comprising logic circuitry configured to: receiving, via the host interface, first weights of a neural network from the host; programming a first memory cell to store the first weight; and Multiplying the first weight by a first input is performed by summing output currents from the first memory cells.

10. The apparatus of claim 8, wherein the access line is a bit line overlying the pillar, the apparatus further comprising sensing circuitry coupled to the bit line and configured to measure an output current from the memory cell.

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