A redundant circuit, a redundant address access circuit, and an access method

Abstract

The present invention provides a redundant circuit, a redundant address access circuit and an access method. The redundant circuit includes a fuse enable generation module and an address fuse module; the fuse enable generation module generates a fuse enable signal based on the input address and inputs it to the address fuse module, and the address fuse module includes multiple units; the fuse enable generation module is configured to: when the input address does not belong to the characteristic address, the fuse enable signals are all valid signals; when the input address belongs to the characteristic address, the fuse enable signal input to a specific unit is an invalid signal, and the fuse enable signals input to the remaining units are valid signals. By designing the fuse enable generation module in this application, it is possible to avoid incorrect matching without a fuse enable signal without the need to load a fuse enable signal from the outside. Compared with the prior art, not only the loading module of the fuse enable signal is omitted, but also the time for fuse loading during startup can be reduced, and the workload of burning fuses in the test project can be reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a redundant circuit, a redundant address access circuit, and an access method. Background Art

[0002] The configuration of a DRAM (Dynamic Random Access Memory) storage array is: an array structure including multiple word lines and bit lines arranged along the rows and columns of the storage array, and storage capacitors configured one by one at the intersection nodes of the word lines and bit lines. With the continuous reduction of the DRAM manufacturing process and the continuous increase of the storage capacity, there are defective units in mass-produced DRAM chips. To enable the DRAM to be used normally, redundant units are included in the chip design. The redundant units are used to repair the defective units to achieve the purpose of mass-producing qualified DRAMs.

[0003] There may be incorrect redundant addresses during the access process of a DRAM chip. For example, Figure 1 and 2 As shown, the chip test engineer tests the chip. Taking bit line redundancy as an example, assuming that the chip is well fabricated and there is no bit line failure during the test, the fuse setting will not be modified. At this time, the fuse will have a default fuse address. When the chip is powered on, the default fuse address will be loaded as the fuse address 2. During the write / read operation, the column address may exactly match the fuse address 2, resulting in an incorrect redundant address, while in fact, the column address has not failed. To avoid the above situation, it is usually necessary to control by externally loading a fuse enable signal. The process is as shown in Figure 3 As shown. If there is no failed bit line during the test, the fuse is placed at the corresponding value by modifying the enable signal fuse setting to make the fuse enable signal 1 invalid. During the power-on process of the chip, this fuse enable signal 1 is loaded into the redundant circuit, and this value is called the fuse enable signal 2. Even if the column address matches the fuse address 2 and the fuse enable signal 2 is invalid, no incorrect redundant address will occur, thus avoiding the above situation. However, this method not only requires a dedicated module for generating and loading the fuse enable signal 1, but also increases the fuse loading time during startup and the workload of burning the fuse in the test project.

[0004] Therefore, this application proposes a redundant circuit, a redundant address access circuit, and an access method, which can reduce the number of DRAM fuses. Without externally loading a fuse enable signal, it can also avoid the incorrect matching situation without a fuse enable signal, playing a role in reducing the number of fuses, reducing the fuse loading time during startup, and reducing the workload of burning the fuse in the test project.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] The purpose of the present invention is to provide a redundant circuit, a redundant address access circuit and an access method.

[0007] To solve the above problems, in the first aspect, the following provides a redundant circuit, including a fuse enable generation module and an address fuse module;

[0008] The fuse enable generation module generates a fuse enable signal based on the input address and inputs it to the address fuse module. The address fuse module includes multiple units;

[0009] The fuse enable generation module is configured to: when the input address does not belong to the characteristic address, the fuse enable signals are all valid signals; when the input address belongs to the characteristic address, the fuse enable signal input to the specific unit is an invalid signal, and the fuse enable signals input to the remaining units are valid signals.

[0010] By designing the fuse enable generation module in the present application, it is possible to avoid incorrect matching without a fuse enable signal without the need to load a fuse enable signal from the outside. Compared with the prior art, it not only eliminates the fuse enable signal loading module, but also reduces the fuse loading time during startup and the workload of burning fuses in the test project.

[0011] The address fuse module includes multiple address fuse loading and address comparison units; the address fuse loading and address comparison unit is configured to: load the fuse address and store it in the unit, compare the input address with the stored fuse address; if the addresses match and the fuse enable signal is a valid signal, the address fuse loading and address comparison unit generates the flag signal representing the valid signal and the corresponding redundant address; if they do not match or the fuse enable signal is an invalid signal, the address fuse loading and address comparison unit generates the flag signal representing the invalid signal and an invalid redundant address. By comparing the input address with each fuse address stored in the unit to confirm whether they match, and then comprehensively judging whether it is a redundant address in combination with the fuse enable signal, that is, only when it both matches the fuse address and the fuse enable signal is valid, it is determined as a redundant address to prevent incorrect matching.

[0012] The number of the address fuse loading and address comparison units is the same as the number of the redundant addresses; the fuse enable generation module can generate multiple independent fuse enable signals and input them into each of the address fuse loading and address comparison units respectively. This ensures that each redundant address can be judged, avoiding errors.

[0013] The first level represents that the fuse enable signal is a valid signal, and the second level represents that the fuse enable signal is an invalid signal; the first level represents that the flag signal is a valid signal, and the second level represents that the flag signal is an invalid signal; the first level and the second level are respectively one of the high level and the low level. By using high and low levels to represent valid and invalid respectively, that is, it is okay to set the first level and the second level to low or high. For example, an invalid signal is represented by a low level and a valid signal is represented by a high level, or vice versa.

[0014] In a second aspect, the present invention further provides a redundant address access circuit, including the redundant circuit, a selector, and a normal and redundant decoding circuit described in the first aspect;

[0015] The selector selects and outputs the input address or the redundant address to the normal and redundant decoding circuit based on the input address, the redundant address, and the flag signal;

[0016] The normal and redundant decoding circuit decodes the received address and outputs the corresponding word line address or bit line address.

[0017] After adopting the redundant circuit of the present invention, the structure of the redundant address access circuit is greatly simplified, and the fuse loading time during startup can be effectively reduced.

[0018] It further includes an address latch circuit; the address latch circuit is used to receive the input address and output the latched address after latching, and the latched address is respectively input into the redundant circuit and the selector. The input address is latched, and when an activation operation is performed, the input address is maintained unchanged, and the address information that is not the activation of the current bank is filtered out.

[0019] It further includes a pre-decoding circuit; the pre-decoding circuit is arranged between the address latch circuit and the selector, and the pre-decoding circuit is used to pre-decode the input latched address and then input it into the selector. By performing pre-decoding through the pre-decoding circuit, the addressable range can be divided first, and the target word line / bit line can be located faster, improving the overall working efficiency.

[0020] In a third aspect, the present invention further provides a redundant address access method, which is carried out by using a redundant address access circuit described in the second aspect, and includes the following steps:

[0021] Load the input address and the fuse address to the redundancy circuit respectively to generate a flag signal and a redundant address;

[0022] Based on the flag signal, select and output the input address or the redundant address through the selector;

[0023] Transmit the address output by the selector to the normal and redundant decoding circuit to decode and obtain the corresponding word line address or bit line address.

[0024] The method includes the following steps: when there is no failed cell, set the default fuse address corresponding to each redundant address to a characteristic address respectively; load the input address to the redundancy circuit, load the characteristic address as the fuse address and store it in one of the cells respectively, and generate a flag signal and a redundant address based on the fuse enable signal, the input address and the fuse address.

[0025] When there is a failed cell, record the failed address, modify the default fuse address corresponding to the redundant address to the failed address, and set the default fuse addresses corresponding to the remaining redundant addresses to a characteristic address respectively; when the failed address does not belong to the characteristic address, load the input address to the redundancy circuit, load the failed address and / or the characteristic address as the fuse address and store it in one of the cells respectively, and generate a flag signal and a redundant address based on the fuse enable signal, the input address and the fuse address; when the failed address belongs to the characteristic address, load the input address to the redundancy circuit, load the failed address and / or the characteristic address as the fuse address and store it in one of the cells respectively, wherein, load the failed address to the cell whose received fuse enable signal is valid, and generate a flag signal and a redundant address based on the fuse enable signal, the input address and the fuse address.

[0026] Compared with the prior art, the beneficial effects of the present invention mainly include the following: by designing a fuse enable generation module, the present application can avoid incorrect matching without a fuse enable signal without loading a fuse enable signal from the outside. Compared with the prior art, not only the loading module of the fuse enable signal is omitted, but also the fuse loading time during startup can be reduced, and the workload of burning fuses in the test project can be reduced. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is a schematic diagram of the access process of the word line / bit line redundant unit.

[0029] Figure 2 It is a schematic diagram of the redundant circuit structure in the prior art.

[0030] Figure 3 It is a schematic diagram of the overall structure of the redundant circuit in the prior art.

[0031] Figure 4 It is a schematic diagram of the access process of the word line / bit line redundant unit provided in this embodiment.

[0032] Figure 5 It is a schematic diagram of the redundant circuit structure provided in this embodiment.

[0033] Figure 6 It is the circuit design of the fuse enable module provided in this embodiment. Detailed implementation manners

[0034] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the accompanying drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or rear, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0035] The following will elaborate on each embodiment of the present application in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are proposed for the convenience of readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0036] To better understand the working principle of the present invention, the general working process of accessing redundant units in a DRAM chip and the composition of related circuits are exemplarily described below, but the present invention is not limited in any form.

[0037] Such as Figure 1As shown, the word line / bit line redundant access circuit mainly includes an address latch circuit, a pre-decoding circuit, a redundant circuit, a selector, and a normal and redundant decoding circuit. When operating on a DRAM chip (ACT), the input address is latched by the address latch circuit and the latched address is output; based on the input latched address, the redundant circuit compares the latched address with the blown address stored in the redundant circuit to determine whether it is a redundant word line / bit line, and generates a corresponding flag signal and a redundant address; the flag signal and the redundant address are input into the selector, the flag signal controls the selector to select between the normal address and the redundant address, and finally the word line / bit line address is decoded through the normal and redundant decoding circuit; the flag signal is generated after each comparison, and the flag signal has two states, 0 or 1, where 0 can represent a redundant address and 1 can represent a non-redundant address. For example, taking the low level (the first level) as 0 and the high level (the second level) as 1, the first level indicates that the flag signal is a valid signal, and the second level indicates that the flag signal is an invalid signal, or vice versa.

[0038] In the above process, the redundant circuit is the key to realizing the access process. It can be understood that the above example is only a common structure in the prior art. In other solutions, the address latch circuit may not be provided, which is not limited here; in Figure 1 the said structure, there is also a pre-decoding circuit, which is respectively connected to the address latch circuit and the selector. In the example case, the latched input address enters the pre-decoding circuit and the redundant circuit at the same time. In other solutions, the pre-decoding circuit may not be provided, which is not limited here.

[0039] The schematic diagram of the redundant circuit in the prior art is as Figure 2 shown. The redundant circuit mainly includes an enable fuse loading module, an address fuse loading module, and an address comparison module. As Figure 1 shown, the signals input into the redundant circuit include a power-on signal, a latched address, a fuse address 1, and a fuse enable signal 1; as Figure 2 shown, the power-on signal is respectively input into the enable fuse loading module and the address fuse loading module, the latched address is directly input into the address comparison module, the fuse address 1 is input into the address fuse loading module, and the fuse enable signal 1 is input into the enable fuse loading module.

[0040] Specifically, referring to Figure 2, the figure shows the process of fuse address loading and address comparison. It can be understood that in order to ensure the normal use of the DRAM chip, after the chip design stage is completed, the chip test engineer will test the chip. If a word line / bit line failure is found, the address will be recorded, and the fuse will be set to the corresponding value by modifying the fuse setting (that is, the fuse is given the recorded failure address), and this value is called the fuse address 1; during the process of powering on the chip (that is, a power-on signal will be generated), this fuse address 1 is loaded into the redundant circuit (that is, the input address fuse loading module) and latched to obtain a new value, and this value is called the fuse address 2; when operating on the chip, the Figure 1 process shown is to compare the latched address with the fuse address 2 to obtain the corresponding flag signal and redundant address.

[0041] However, the above process may generate incorrect redundant addresses. For easier understanding, the bit line redundancy is taken as an example for illustration. Assume that the chip is well fabricated and there is no bit line failure during the test, then the fuse setting will not be modified. At this time, although the fuse will not be given a failure address, it itself will have a default fuse address, and the default fuse address at this point is the input fuse address 1 (here the default fuse address and the above fuse address 1 are the values of the same point, but when the fuse setting is not modified, there will be a default fuse address, and when the fuse setting is modified, the default fuse address will be modified to the recorded failure address), then when the chip is powered on later, the default fuse address (that is, the fuse address 1 in the figure) will be loaded into the address fuse loading circuit to generate the fuse address 2; later, during the write / read operation, the latched address (in the case of bit line redundancy, the latched address is the column address) may happen to match the fuse address 2, thus generating an incorrect redundant address, while in fact this latched address has not failed.

[0042] To avoid the occurrence of the above incorrect matching situation, it is necessary to add a fuse enable signal for control. In the prior art, the generation of the fuse enable signal requires a dedicated circuit module to be set up. If there is no failed bit line during the test, the fuse is set to the corresponding value by modifying the enable signal fuse setting, thereby obtaining the fuse enable signal 1, and this fuse enable signal 1 represents invalid; during the process of powering on the chip, this fuse enable signal 1 is loaded into the enable fuse loading module of the redundant circuit and outputs a new value, and this value is called the fuse enable signal 2, and the fuse enable signal 2 also represents invalid, and the fuse enable signal 2 is input into the address comparison circuit.

[0043] The overall structural schematic diagram of the redundant circuit is as Figure 3 shown. As described above, the redundant circuit mainly includes an enable fuse loading module, an address fuse loading module, and an address comparison module. In this Figure 3In [the figure], the address fuse loading module and the address comparison module are shown combined together, namely the shown address fuse loading and address comparison module. Refer to Figure 3 , taking DDR4 as an example, assume that its bit lines have 4 groups of redundant addresses, namely SYS0, SYS1, SYS2, and SYS3 respectively. After the input latch address and fuse address 1 (where fuse address 1 is not shown in the figure) are input, the 4 groups of input fuse addresses 1 are respectively loaded into 4 groups of address fuse loading and address comparison units to obtain the corresponding fuse address 2, and then the latch address is compared with the 4 groups of fuse addresses 2 respectively. When comparing the latch address (column address) with the fuse address 2, an additional judgment of the fuse enable signal 2 is introduced. During this process, even if the latch address and the fuse address 2 match, due to the invalidity of the fuse enable signal 2, no incorrect redundant address will occur, thus avoiding the above situation. Only when the latch address and the fuse address 2 match and the fuse enable signal 2 is also valid, the redundant circuit will generate the corresponding flag signal and redundant address and input them into the selector.

[0044] Embodiment 1

[0045] As described above, although the prior art can avoid generating incorrect redundant addresses, it is necessary to load the fuse enable signal 1 from the outside (that is, a corresponding generation module for the fuse enable signal 1 is required, and each redundant address requires a corresponding generation module). Taking DDR4 as an example, assume that its bit lines have 4 groups of redundant addresses, the column address has 7 bits, that is, the bit fuse address is 7 bits, the fuse enable signal is 1 bit, and the column fuse is divided into 24 modules, then the number of its fuses is 4*(7 + 1)*24 = 768; similarly, assume that the word lines have 64 groups of redundant addresses, the row address has 14 bits, that is, the row fuse address has 14 bits, and the fuse enable signal is 1 bit, then the number of its fuses is 64*(14 + 1)=960. Among them, the total number of fuses used to generate the fuse enable signal 1 is (4*1*24)+64*1 = 160. Therefore, the present application wants to provide a new technical solution that can avoid the above situation of incorrect matching without a fuse enable signal without loading the fuse enable signal 1 from an external circuit module, thereby greatly reducing the number of fuses used. Taking the above as an example, it can not only reduce 160 groups of fuse enable signal generation modules, but also reduce the fuse loading time during startup and the workload of burning fuses in the test project.

[0046] The present application provides a redundant circuit, a redundant address access circuit, and an access method, and its word line / bit line redundant access circuit structure is as Figure 4 shown, and the redundant circuit structure therein is as Figure 5 shown.

[0047] Refer to Figure 4 and Figure 5 .Figure 4 The word line / bit line redundant access circuit provided for this application. A redundant address access circuit mainly includes an address latch circuit, a pre-decoding circuit, a redundant circuit, a selector, and a normal and redundant decoding circuit. Among them, the address latch circuit and the pre-decoding circuit are not necessarily required to be provided.

[0048] As Figure 5 shown, a redundant circuit is provided. In this redundant circuit structure, it mainly includes a fuse enable generation module and an address fuse module.

[0049] Among them, the address fuse module is as described above. It includes multiple units, and each unit stores a fuse address respectively. The address fuse module generates a flag signal and a redundant address based on the fuse enable signal, the input address, and the fuse address. Specifically, the address fuse module includes multiple groups of corresponding address fuse loading units and address comparison units, and the address fuse loading and address comparison units therein are the same as those in the prior art.

[0050] This application specially designs a fuse enable generation module. This module circuit is used to generate the MFSYST<3:0> signal (MFSYST<3:0> is an independent four-bit signal, and each bit signal has two states, 0 or 1. In this embodiment, 0 represents an invalid signal, and 1 represents an effective signal. The specific representation method can also refer to the flag signal). The role of this signal is similar to that of the fuse enable signal 2 in the prior art. However, in the prior art, it is necessary to first load the fuse enable signal 1 from an external circuit module to obtain the fuse enable signal 2, while in this patent, it is directly generated inside the circuit without external loading.

[0051] It can be understood that a certain number of redundant cells are provided in the chip to replace possible word line / bit line failures. Each redundant cell has a default fuse address. To facilitate understanding the working principle of the redundant circuit provided in this application, the bit line is taken as an example. Assume that the bit line has 4 groups of redundant addresses (named redundant address SYS0, redundant address SYS1, redundant address SYS2, and redundant address SYS3 respectively), and the column address has 7 bits, that is, the length of the bit fuse address is 7 bits. First, the default fuse addresses corresponding to the 4 groups of bit line redundant addresses are set to different values respectively. In this embodiment, this value is called the characteristic address. That is, the 4 groups of characteristic addresses at this time are: characteristic address SYS0: 0000000, characteristic address SYS1: 0000001, characteristic address SYS2: 1000000, characteristic address SYS3: 1000001. It can be understood that the characteristic address is a pre-determined address by itself, the number of characteristic addresses should be the same as the number of redundant addresses, and the length of the redundant address should be the same as the length of the fuse address. In other embodiments, each characteristic address can also be set to other values, which is not limited thereto, but when set to other values, the logic structure of the corresponding circuit needs to be adjusted adaptively to make the corresponding characteristic address meet the conditions.

[0052] It can be understood that because the bit line has 4 groups of redundant addresses, 4 address fuse loading and address comparison units also need to be set in the corresponding address fuse module, that is, as Figure 5 shown, the address fuse loading and address comparison unit SYS0, the address fuse loading and address comparison unit SYS1, the address fuse loading and address comparison unit SYS2, and the address fuse loading and address comparison unit SYS3.

[0053] Figure 5 The shown fuse enable generation module is configured as follows: when the input address (i.e., the latched address) is different from all of the characteristic addresses SYS0 - SYS3 (i.e., not any one of 0000000, 0000001, 1000000, and 1000001), all 4-bit fuse enable signals generated by the fuse enable generation module represent valid signals; when the input address (i.e., the latched address) is the same as a certain characteristic address (i.e., one of 0000000, 0000001, 1000000, and 1000001), among the 4-bit fuse enable signals MFSYST<3:0> generated by the fuse enable generation module, 3-bit fuse enable signals represent valid, and 1-bit fuse enable signal represents invalid, and the invalid fuse enable signal will be input to a specific unit. In this application, the specific unit is the unit in which the stored fuse address is the same as the input address. There are many ways to implement the fuse enable signal MFSYST<3:0>. In this application, a logic structure is proposed, such as Figure 6 shown.

[0054] Specifically, if a bit line failure is detected during testing, record the failure address. Subsequently, modify the fuse to the recorded failure address by changing the fuse setting. At this time, there are two cases: First, if the failure address is different from all four sets of characteristic addresses, modify one of the characteristic addresses to the recorded failure address by changing the fuse setting. This value is the fuse address 1. After latching in the subsequent circuit, the fuse address 2 for comparison is obtained. During access, if the latched address is different from the failure address, then the latched address and the fuse address 2 cannot match. Regardless of whether the MFSYST<3:0> signal is valid, the finally output flag signal indicates that it is not a redundant address, and the decoded result will be a normal bit line. If the latched address is the same as the failure address, at this time, all four MFSYST<3:0> signals generated by the break enable generation module are valid (because the latched address is different from all four sets of characteristic addresses at this time). The finally output flag signal indicates that it is a redundant address, and the decoded result will be a redundant bit line. Second, if the failure address is the same as one of the four sets of characteristic addresses, also modify the characteristic address to the recorded failure address by changing the fuse setting. This value is the fuse address 1. After latching in the subsequent circuit, the fuse address 2 for comparison is obtained. However, it should be noted that the fuse address 1 to be loaded should be reasonably selected for the address fuse loading and address comparison unit here. For example, when the failure address is 0000000, modify the characteristic address to the recorded failure address by changing the fuse setting. Here, the fuse address 1 cannot be loaded into the address fuse loading and address comparison unit SYS0, but into the other address fuse loading and address comparison units. During access, if the latched address is different from the failure address, then the latched address and the fuse address 2 cannot match. Regardless of whether the MFSYST<3:0> signal is valid, the finally output flag signal indicates that it is not a redundant address, and the decoded result will be a normal bit line. If the latched address is the same as the failure address, among the four MFSYST<3:0> signals generated by the break enable generation module at this time, the one input to the address fuse loading and address comparison unit SYS0 is invalid, while the other three are valid. Because the fuse address 2 is located in the unit representing valid, the finally output flag signal indicates that it is a redundant address, and the decoded result will be a redundant bit line, achieving repair.

[0055] If no failed cells are found during testing, the fuse settings will not be modified, and the fuse will not be assigned a failure address. That is, the final loaded fuse address 1 is the characteristic address. For the first set of bit-line redundant addresses SYS0, its characteristic address is 0000000, that is, the first set of fuse address 1 is 0000000. After this fuse address 1 is input into the address fuse loading unit, it will output the corresponding first set of fuse address 2, and its value is still 0000000. That is, the value of the fuse address 2 loaded in the first address fuse loading and address comparison unit SYS0 at this time is 0000000; similarly, the value of the fuse address 2 loaded in the second address fuse loading and address comparison unit SYS1 is 0000001; the value of the fuse address 2 loaded in the third address fuse loading and address comparison unit SYS2 is 1000000; the value of the fuse address 2 loaded in the fourth address fuse loading and address comparison corresponding to SYS3 is 1000001.

[0056] As described above, we know that the reason for the generation of incorrect redundant addresses is that the value of the fuse address 2 loaded into the corresponding unit and the value of the input latched address just match. That is to say, only when the value of the latched address input into the address fuse loading and address comparison unit is the same as the value of the fuse address 2 stored in this unit, will this incorrect redundant address match occur. Therefore, there are only 4 column addresses that may cause incorrect matches, which are 0000000, 0000001, 1000000, and 1000001 respectively.

[0057] Reference Figure 4 and Figure 5 , when the value of the first column address 0000000 is input, it will be latched and output the corresponding latched address through the address latching circuit, and the value of this latched address is still 0000000; the generated latched address will be input into Figure 5 the fuse enable generation module and the address fuse module at the same time.

[0058] The latched address input into the address fuse module will be compared with the fuse address 2 in each unit respectively. It can be understood that the result of the address comparison is that only the address fuse loading and address comparison unit SYS0 matches, while the other three units do not match.

[0059] The latch address of the input fuse enable generation module generates the MFSYST<3:0> signal and inputs it into the four groups of address fuse loading and address comparison units SYS0 - SYS3 respectively. As mentioned before, the function of the fuse enable generation module is: when the input address (i.e., the latch address) is the same as a certain feature address, among the 4-bit MFSYST<3:0> signals generated by the fuse enable generation module, 3 bits represent valid and 1 bit represents invalid, and the signal representing invalid will be input into the address fuse loading and address comparison unit with the same value as the latch address. That is, at this time, MFSYST<0> in the output MFSYST<3:0> = 0. Although it matches in the address fuse loading and address comparison unit SYS0, the corresponding signal MFSYST<0> represents invalid, so the finally output flag signal represents that it is not a redundant address. Although the other 3-bit signals represent valid, the two addresses in the other three address fuse loading and address comparison units SYS1 - SYS3 do not match, and finally no redundant address will be generated.

[0060] Similarly, when the value of the input column address is 0000001, only the address fuse loading and address comparison unit SYS1 matches, and MFSYST<1> = 0, and finally no incorrect redundant address will be generated; when the value of the input column address is 1000000, only the address fuse loading and address comparison unit SYS2 matches, and MFSYST<2> = 0, and finally no incorrect redundant address will be generated; when the value of the input column address is 1000001, only the address fuse loading and address comparison unit SYS3 matches, and MFSYST<3> = 0, and finally no incorrect redundant address will be generated.

[0061] The above is only an exemplary description with 4 groups of bit lines. The present application does not limit the specific number of bit lines or word lines, redundant units, the length of each address, etc.

[0062] It can be understood that the number of redundant addresses in the DRAM chip can be determined in advance. According to the different numbers of redundant addresses, the fuse enable generation module and the address fuse module will be correspondingly modified. When there are N groups of redundant addresses, denoted as redundant addresses SYSi(0 ≤ i ≤ N - 1) respectively, then the corresponding address fuse module is also composed of N address fuse loading and address comparison units, denoted as address fuse loading and address comparison units SYSi(0 ≤ i ≤ N - 1) respectively. The fuse enable generation module is used to generate the fuse enable signal MFSYST <n-1:0>, the MFSYST <n-1:0>The signals are N independent signals, which are respectively input into an address fuse loading and address comparison unit.

[0063] First, before designing the fuse enable generation module, some characteristic addresses need to be confirmed first, and then the circuit design of the fuse enable generation module is carried out based on the preset characteristic addresses. Specifically, the default fuse addresses corresponding to each redundant address SYSi are respectively set to different characteristic addresses, denoted as characteristic addresses Mi (0 ≤ i ≤ N - 1); at this time, the fuse enable generation module is configured as follows: when the input address does not belong to the characteristic address (that is, it is different from each characteristic address Mi), all N-bit fuse enable signals generated by the fuse enable generation module represent valid signals; when the input address belongs to the characteristic address (that is, it is the same as a certain characteristic address Mi), among the N-bit fuse enable signals generated by the fuse enable generation module, N - 1 bits represent valid and 1 bit represents invalid, and the signal representing invalid will be input into a specific unit, and the address stored in this specific unit is the same as the input address. And this is easy to achieve because the addresses loaded in each address fuse loading and address comparison unit SYSi are controllable by us. As long as it is confirmed in advance which unit each characteristic address is located in, the circuit of the fuse enable generation module can be correspondingly set so that when the input address belongs to the characteristic address, the fuse enable signal input into the specific unit is an invalid signal, and the fuse enable signals input into the other units are valid signals.

[0064] Some common English nouns or letters used in the present invention for the convenience of clear description are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0065] It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A redundant circuit, characterized in that: It includes a fuse enable generation module and an address fuse module; The fuse enable generation module generates a fuse enable signal based on an input address and inputs the signal into the address fuse module, wherein the address fuse module includes a plurality of units; The fuse enable generation module is configured such that: when the input address does not belong to the characteristic address, the fuse enable signals are all valid signals; when the input address belongs to the characteristic address, the fuse enable signal input to a specific unit is an invalid signal, and the fuse enable signal input to other units is a valid signal; The characteristic addresses are pre-determined addresses, and the number of the characteristic addresses is the same as the number of redundant addresses; The address fuse module includes a plurality of address fuse loading and address comparison units; The address fuse loading and address comparison unit is configured to: load a fuse address and store it in the unit, and compare the input address with the stored fuse address; If the address matches and the fuse enable signal is a valid signal, the address fuse loading and address comparison unit generates a flag signal indicating a valid signal and a corresponding redundant address; If there is no match or the fuse enable signal is an invalid signal, the address fuse loading and address comparison unit generates a flag signal indicating an invalid signal and an invalid redundant address.

2. A redundant circuit according to claim 1, characterized in that: The number of the address fuse loading and address comparison units is the same as the number of the redundant addresses; The fuse enable generation module can generate multiple independent fuse enable signals and input them into each of the address fuse loading and address comparison units respectively.

3. A redundant circuit according to claim 1, characterized in that: The first level indicates that the fuse enable signal is a valid signal, and the second level indicates that the fuse enable signal is an invalid signal; Indicating that the flag signal is a valid signal with a first level, and indicating that the flag signal is an invalid signal with a second level; The first level and the second level are respectively one of a high level and a low level.

4. A redundant address access circuit, characterized in that: comprising a redundant circuit, a selector, and a normal and redundant decoding circuit according to any one of claims 1 to 3; The selector selects to output the input address or the redundant address to the normal and redundant decoding circuit based on the input address, the redundant address and the flag signal; The normal and redundant decoding circuit decodes the received address and outputs the corresponding word line address or bit line address.

5. A redundant address access circuit according to claim 4, characterized in that: Also included is an address latch circuit; The address latch circuit is used to receive the input address and output a latched address after latching, and the latched address is input into the redundancy circuit and the selector respectively.

6. A redundant address access circuit according to claim 5, characterized in that: Also includes a pre-decoding circuit; The pre-decoding circuit is arranged between the address latch circuit and the selector, and is used for pre-decoding the input latch address and then inputting it into the selector.

7. A redundant address access method, characterized in that: The method is performed by using a redundant address access circuit as claimed in any one of claims 4 to 6, comprising the following steps: Loading the input address and the fuse address to the redundant circuit respectively to generate a flag signal and a redundant address; Based on the flag signal, the selector selects and outputs the input address or the redundant address; The address output by the selector is transmitted to the normal and redundant decoding circuit, and decoded to obtain a corresponding word line address or bit line address.

8. A redundant address access method according to claim 7, characterized in that: The steps include: When there is no failed unit, the default fuse address corresponding to each redundant address is set to a characteristic address; The input address is loaded into the redundant circuit, the characteristic address is loaded as a fuse address and is stored in one of the units respectively, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address.

9. A redundant address access method according to claim 7, characterized in that: When a failed unit exists, the failed address is recorded, and the default fuse address corresponding to the redundant address is modified to the failed address, and the default fuse addresses corresponding to the remaining redundant addresses are respectively set as a characteristic address; When the failure address does not belong to the characteristic address, the input address is loaded into the redundant circuit, the failure address and / or the characteristic address are loaded as a fuse address and stored in one of the units respectively, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address; When the failure address belongs to the characteristic address, the input address is loaded into the redundant circuit, and the failure address and / or the characteristic address are loaded as fuse addresses and stored in one of the units respectively, wherein the failure address is loaded into the unit where the received fuse enable signal is a valid signal, and a flag signal and a redundant address are generated based on the fuse enable signal, the input address and the fuse address.

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