Vacuum transistor, manufacturing method thereof and array substrate

Abstract

The invention discloses a vacuum transistor and a manufacturing method thereof, and an array substrate. The vacuum transistor comprises a substrate; the emitting electrode, the collecting electrode and the annular grid electrode are arranged on different layers and are arranged at intervals; the orthographic projection of the annular grid electrode on the substrate surrounds the orthographic projection of the collector on the substrate, and the annular grid electrode and the collector are arranged at intervals; the orthographic projection of the annular grid electrode on the substrate is located in the orthographic projection of the emitting electrode on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of vacuum electronic technology, and in particular to a vacuum transistor and a manufacturing method thereof, and an array substrate. Background Art

[0002] Traditional vacuum electronics have been widely studied and applied as an important technical solution in the field of electronic information. However, due to a series of application limitations such as the large size of vacuum electronic devices, difficulty in vacuum integration, and limited working environment, they have gradually been replaced by solid-state electronic devices based on semiconductor materials.

[0003] However, after decades of development, solid-state semiconductor devices are gradually approaching physical limits, Moore's Law has become invalid, and the manufacturing cost of devices has increased significantly, while the performance has not been improved due to the amplified transmission loss of electrons in semiconductor materials. In response to this problem, traditional vacuum electronics has re-entered the research field. Nano-vacuum electronic transistors (NVETs) with good electron transmission characteristics are regarded as a potential technology direction to replace traditional semiconductor devices.

[0004] When the nano vacuum channel is much smaller than the mean free path of electrons in the transmission medium (such as air, helium or vacuum) (for example, less than 1 / 10 of the mean free path), the electrons are transported ballistically in the channel, and their carrier mobility and carrier transmission speed are greatly improved. In addition, compared with semiconductor materials such as Si, GaAs, and GaN, vacuum has obvious advantages in bandgap width, relative dielectric constant, breakdown voltage, electron mobility, and electron saturation rate (as shown in Table 1). Therefore, many institutions have conducted research on vacuum electronic devices.

[0005] Table 1

[0006]

[0007]

[0008] However, nanoscale vacuum channel transistors (NVCTs) require chip-scale manufacturing equipment to be produced, resulting in high manufacturing costs and low gate control capabilities.

[0009] In view of this, how to improve the control capability of the gate while reducing the manufacturing cost of vacuum channel electron transistors has become a technical problem that needs to be solved urgently. Summary of the invention

[0010] The embodiments of the present invention provide a vacuum transistor and a manufacturing method thereof, and an array substrate, so as to solve the technical problems of high manufacturing cost and low gate control capability in the prior art.

[0011] In a first aspect, in order to solve the above technical problems, an embodiment of the present invention provides a vacuum transistor, comprising:

[0012] substrate substrate;

[0013] An emitter, a collector and a ring-shaped gate, wherein the emitter, the collector and the ring-shaped gate are arranged in different layers and are spaced from each other;

[0014] The orthographic projection of the annular gate on the substrate surrounds the orthographic projection of the collector on the substrate and is arranged at intervals; the orthographic projection of the annular gate on the substrate is located within the orthographic projection of the emitter on the substrate.

[0015] In a possible implementation manner, the vacuum transistor further includes:

[0016] a step structure between the emitter and the collector;

[0017] The orthographic projection of the step structure on the base substrate is located within the orthographic projection of the collector on the base substrate, and the step structure is indented relative to the edge of the collector.

[0018] In a possible implementation manner, the emitter is located on one side of the substrate, and the collector is located on a side of the emitter away from the substrate;

[0019] The orthographic projection of the collector on the substrate is located within the orthographic projection of the emitter on the substrate.

[0020] In a possible implementation manner, the vacuum transistor further includes: an annular structure wrapping the annular gate; the annular structure has an orthographic projection on the substrate surrounding the step structure and is spaced apart from the step structure.

[0021] In a possible implementation manner, the annular gate is located between the layer where the emitter is located and the layer where the collector is located;

[0022] The annular structure and the step structure are arranged on the same layer.

[0023] In a possible implementation manner, the annular gate is located between the layer where the emitter is located and the substrate.

[0024] In a possible implementation manner, the shape of the inner contour of the annular gate is the same as the shape of the outer contour of the collector.

[0025] In a possible implementation manner, the outer contour of the collector is circular.

[0026] In a second aspect, an embodiment of the present invention provides a method for manufacturing a vacuum transistor, comprising:

[0027] Providing a substrate;

[0028] An emitter, a collector and a ring-shaped gate are formed on one side of the base substrate. The emitter, the collector and the ring-shaped gate are arranged in different layers and are spaced apart from each other. The orthographic projection of the ring-shaped gate on the base substrate surrounds the orthographic projection of the collector on the base substrate and is spaced apart. The orthographic projection of the ring-shaped gate on the base substrate is located within the orthographic projection of the emitter on the base substrate.

[0029] In a possible implementation manner, an emitter, a collector and a ring gate are formed on one side of the substrate, including:

[0030] forming the emitter on one side of the substrate;

[0031] A dielectric layer and the annular gate are formed on a side of the emitter away from the substrate; the dielectric layer includes the step structure and the annular structure;

[0032] On a side of the dielectric layer away from the substrate, forming a sacrificial layer covering the dielectric layer, and removing a portion of the sacrificial layer located on the surface of the step structure;

[0033] A collector material layer is formed on a side of the sacrificial layer away from the base substrate, and the collector material layer is etched to obtain the collector; the orthographic projection of the step structure on the base substrate is located within the orthographic projection of the collector on the base substrate;

[0034] The remaining sacrificial layer is removed.

[0035] In a possible implementation manner, a dielectric layer and the annular gate are formed on a side of the emitter away from the substrate, including:

[0036] Forming a first sub-dielectric layer on a side of the emitter away from the substrate;

[0037] Forming the annular gate on a side of the first sub-dielectric layer away from the substrate;

[0038] A second sub-dielectric layer is formed on a side of the annular gate away from the substrate; the dielectric layer includes the first sub-dielectric layer and the second sub-dielectric layer;

[0039] The dielectric layer is etched inside the inner ring of the annular gate to form an annular through hole penetrating the dielectric layer, the portion of the dielectric layer located inside the annular through hole constitutes the step structure, and the portion outside the annular through hole constitutes the annular structure.

[0040] In a third aspect, an embodiment of the present invention provides an array substrate, comprising a plurality of vacuum transistors as described in the first aspect arranged in an array. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A top view of a vacuum transistor provided by an embodiment of the present invention;

[0042] Figure 2 The embodiment of the present invention provides Figure 1 Cross-section along the AA' direction;

[0043] Figure 3 A schematic diagram of the structure of a vacuum transistor provided by an embodiment of the present invention;

[0044] Figure 4 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention;

[0046] Figure 6 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention;

[0047] Figure 7 A top view of another vacuum transistor provided by an embodiment of the present invention;

[0048] Figure 8 A top view of another vacuum transistor provided by an embodiment of the present invention;

[0049] Fig. 9 A schematic diagram of a vacuum detection platform for testing a vacuum transistor sample provided by an embodiment of the present invention;

[0050] Fig.10 A test curve diagram of a vacuum transistor provided by an embodiment of the present invention;

[0051] Fig.11 A test curve diagram of another vacuum transistor provided by an embodiment of the present invention;

[0052] Fig.12 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention;

[0053] Fig.13A flow chart of a method for manufacturing a vacuum transistor provided by an embodiment of the present invention;

[0054] Fig.14 A schematic diagram of forming an emitter, a collector and a ring gate provided by an embodiment of the present invention;

[0055] Fig.15 A schematic diagram of forming a dielectric layer and a ring gate provided by an embodiment of the present invention.

[0056] Reference numerals:

[0057] Substrate substrate 1, emitter 2, collector 3, annular gate 4, step structure 5, first sub-step structure 51, second sub-step structure 52, annular structure 6, first sub-annular structure 61, second sub-annular structure 62, gate insulation layer 7, pad 8, first sub-pad 81, second sub-pad 82, third sub-pad 83, connecting line 9, first sub-connecting line 91, second sub-connecting line 92, third sub-connecting line 93, insulating layer L1, encapsulation layer L2, dielectric layer 5', first sub-dielectric layer 51', second sub-dielectric layer 52', sacrificial layer 6', collector material layer 3'. DETAILED DESCRIPTION

[0058] The embodiments of the present invention provide a vacuum transistor and a manufacturing method thereof, and an array substrate, so as to solve the technical problems of high manufacturing cost and low gate control capability in the prior art.

[0059] It should be understood that the specific structural and functional details disclosed in the embodiments of the present invention are only representative and are for the purpose of describing the exemplary embodiments of the present application. However, the present application can be specifically implemented in many alternative forms and should not be interpreted as being limited to the embodiments described herein.

[0060] In the description of the present application, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof are intended to cover non-exclusive inclusions.

[0061] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0062] The terms used in this application are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0063] The term "and / or" in the embodiments of the present invention is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0064] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and examples. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportions.

[0065] It should be noted that specific details are described in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the definition of the attached claims.

[0066] A vacuum transistor and a manufacturing method thereof, and an array substrate provided by an embodiment of the present invention are described in detail below in conjunction with the accompanying drawings.

[0067] See also Figure 1 A top view of a vacuum transistor provided in an embodiment of the present invention, the vacuum transistor comprising:

[0068] Base substrate 1;

[0069] The emitter 2, the collector 3 and the annular gate 4 are all arranged in different layers and spaced from each other;

[0070] The orthographic projection of the annular gate 4 on the substrate 1 surrounds the orthographic projection of the collector 3 on the substrate 1 and is arranged at intervals; the orthographic projection of the annular gate 4 on the substrate 1 is located within the orthographic projection of the emitter 2 on the substrate 1 .

[0071] The material of the substrate 1 can be a material with high insulation, such as glass, quartz, sapphire, low-resistance silicon, etc. The material of the emitter 2 can be a metal or semiconductor material that is easy to generate field emission electrons, such as tungsten, molybdenum, gold, platinum, graphene, gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), single crystal silicon, low-temperature polysilicon, etc. The ring gate 4 and the collector 3 can be made of metal materials, such as gold, copper, molybdenum, aluminum, etc.

[0072] By setting the material of the emitter 2 to a metal or semiconductor material that is easier to generate field emission electrons, the minimum barrier for the escape of electrons from the emitter 2 will be lowered, making it easier for the electrons in the emitter 2 to escape after voltage is applied to the annular gate 4. The escaped electrons quickly reach the collector 3 through the vacuum channel between the emitter 2 and the collector 3.

[0073] It should be understood that metals that are more likely to produce field emission electrons refer to low work function metals whose work function is less than or equal to a preset work function; semiconductor materials that are more likely to produce field emission electrons refer to semiconductor materials whose work function is greater than or equal to a preset work function.

[0074] In some embodiments, the spacing d between the collector 3 and the annular gate 4 on the orthographic projection of the substrate 1 is greater than or equal to 200 nm, which enables the above spacing to be manufactured using a large-area semiconductor process.

[0075] The thickness of the annular gate 4 is in the range of 100 to 300 nm, and the thickness of the emitter 2 is in the range of 20 to 500 nm.

[0076] Since the emitter 2, collector 3 and annular gate 4 in the vacuum transistor are arranged in different layers and spaced apart from each other, the emitter 2, collector 3 and annular gate 4 in the vacuum transistor can be spaced apart and manufactured in different film layers, so that they can be manufactured using equipment for manufacturing array substrates in a large-area semiconductor process (i.e., a process for manufacturing display panels), without the need to use equipment for wafer-level semiconductor process (i.e., a process for manufacturing chips) as required in the prior art, thereby increasing the manufacturing cost of the vacuum transistor.

[0077] It should be noted that wafer-level semiconductor processes usually have higher equipment precision requirements than large-area semiconductor processes, and the substrate area used in large-area semiconductor processes is smaller than that used in wafer-level semiconductor processes. As a result, the number of vacuum transistors that can be generated at one time using a large-area semiconductor process is much larger than the number of vacuum transistors that can be generated at one time using a wafer process. Therefore, the use of large-area semiconductor processes can further dilute the cost of vacuum transistors.

[0078] Furthermore, since the annular gate 4 in the vacuum transistor is annular, and the orthographic projection of the annular gate 4 on the substrate 1 surrounds the orthographic projection of the collector 3 on the substrate 1 and is arranged at intervals; the orthographic projection of the annular gate 4 on the substrate 1 is located within the orthographic projection of the emitter 2 on the substrate 1, so that the vacuum channel between the emitter 2 and the collector 3 is completely surrounded by the annular gate 4, so that the transmission of electrons in the vacuum channel can be better controlled, thereby improving the ability of the annular gate 4 to control electrons.

[0079] In the embodiment provided by the present invention, by arranging the emitter 2, the collector 3 and the annular gate 4 in the vacuum transistor in different layers and spaced from each other, the vacuum transistor can be manufactured using low-precision process equipment of a large-area semiconductor process, and it is also convenient to integrate the vacuum transistor into the display panel, thereby improving the manufacturing cost and application scope of the vacuum transistor and improving the performance of the display panel; and the annular gate 4 in the vacuum transistor is annular, and the orthographic projection of the annular gate 4 on the substrate 1 surrounds the orthographic projection of the collector 3 on the substrate 1 and is arranged at intervals, and at the same time, the orthographic projection of the annular gate 4 on the substrate 1 is located within the orthographic projection of the emitter 2 on the substrate 1, so that the vacuum channel between the emitter 2 and the collector 3 is completely surrounded by the annular gate 4, so that the transmission of electrons in the vacuum channel can be better controlled, thereby improving the ability of the annular gate 4 to control electrons.

[0080] See also Figure 2 The embodiment of the present invention provides Figure 1 The cross-sectional view along the AA' direction, the vacuum transistor also includes:

[0081] A step structure 5 located between the emitter 2 and the collector 3;

[0082] The orthographic projection of the step structure 5 on the base substrate 1 is located within the orthographic projection of the collector 3 on the base substrate 1 , and the step structure 5 is indented relative to the edge of the collector 3 .

[0083] The step structure 5 is an insulating material, such as at least one of an organic material and an inorganic material, including SiO2, SiNx, polyimide, etc.

[0084] In some embodiments, the height h of the step structure 5 is greater than or equal to 100 nm, which can effectively isolate the emitter 2 and the collector 3 .

[0085] In the embodiment provided by the present invention, by setting a step structure 5 between the emitter 2 and the collector 3, the step structure 5 can be used to isolate the emitter 2 and the collector 3, so that the emitter 2 and the collector 3 are spaced apart and arranged in different film layers, which is convenient for forming the emitter 2 and the collector 3 using equipment of large-area semiconductor process; and by setting the step structure 5 indented relative to the collector 3, a vertical vacuum channel can be formed between the emitter 2 and the collector 3, so that the electrons escaping from the emitter 2 under the action of the annular gate 4 can quickly reach the collector 3 through the vacuum channel.

[0086] Please continue to see Figure 1 and Figure 2 , the emitter 2 is located on one side of the substrate 1, and the collector 3 is located on the side of the emitter 2 away from the substrate 1;

[0087] The orthographic projection of the collector 3 on the substrate 1 is located within the orthographic projection of the emitter 2 on the substrate 1 .

[0088] In the embodiment provided by the present invention, by arranging the emitter 2 and the collector 3 on the same side of the substrate 1, and making the orthographic projection of the collector 3 on the substrate 1 located within the orthographic projection of the emitter 2 on the substrate 1, the area of ​​the emitter 2 can be made greater than or equal to the area of ​​the collector 3, thereby ensuring that the collector 3 can maximize the collection of electrons escaping from the emitter 2 and improve the performance of the vacuum transistor.

[0089] See also Figure 3 A schematic diagram of the structure of a vacuum transistor provided in an embodiment of the present invention, the vacuum transistor further includes: an annular structure 6 wrapping the annular gate 4; the orthographic projection of the annular structure 6 on the substrate 1 surrounds the step structure 5 and is spaced apart from the step structure 5.

[0090] By setting a ring structure 6 that wraps the ring gate 4 in the vacuum transistor, and allowing the positive projection of the ring structure 6 on the substrate 1 to surround the step structure 5 and be spaced apart from the step structure 5, the ring structure 6 can be used to allow the ring gate 4 to be spaced apart from the emitter 2 and the collector 3 in different film layers, so that the vacuum transistor can be manufactured using the existing process equipment for manufacturing display panels, and the ring gate 4 can be protected.

[0091] See also Figure 4 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention, the ring structure 6, comprises:

[0092] The first sub-annular structure 61 is located on a side of the annular gate 4 close to the substrate 1;

[0093] The second sub-annular structure 62 is located at a side of the annular gate 4 away from the substrate 1 , and the second sub-annular structure 62 completely covers the annular gate 4 ; the first sub-annular structure 61 overlaps with the second sub-annular structure 62 .

[0094] The first sub-annular structure 61 and the second sub-annular structure 62 may be made of the same material, such as both being organic material or inorganic material; or they may be made of different materials, such as one being an organic material and the other being an inorganic material.

[0095] By configuring the annular structure 6 to include a first sub-annular structure 61 and a second sub-annular structure 62 located on both sides of the annular gate 4 , and allowing the second sub-annular structure 62 to completely cover the annular gate 4 , it is convenient to wrap the annular gate 4 in the annular structure 6 .

[0096] Please continue to see Figure 3 , the annular gate 4 is located between the layer where the emitter 2 is located and the layer where the collector 3 is located;

[0097] The annular structure 6 and the step structure 5 are arranged at the same level.

[0098] By setting the annular gate 4 between the layer where the emitter 2 is located and the layer where the collector 3 is located, and setting the annular structure 6 and the step structure 5 on the same layer, it is convenient to form the annular structure 6 and the step structure 5 simultaneously using the same process, thereby effectively reducing the manufacturing process and improving production efficiency.

[0099] See also Figure 5 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention, wherein the step structure 5 comprises:

[0100] The first sub-step structure 51 is located at a side of the emitter 2 away from the substrate 1 and is disposed at the same layer as the first sub-ring structure 61;

[0101] The second sub-step structure 52 is located on a side of the first sub-step structure 51 away from the base substrate 1 , and is disposed on the same layer as the second sub-annular step structure 5 .

[0102] When the step structure 5 and the annular structure 6 are arranged on the same layer, by arranging the first sub-step structure 51 and the first sub-annular structure 61 on the same layer, and arranging the second sub-step structure 52 and the second sub-annular structure 62 on the same layer, the film layers of the first sub-step structure 51 and the first sub-annular structure 61 can be formed using the same process, and the film layers of the second sub-step structure 52 and the second sub-annular structure 62 can be formed using the same process, thereby enabling the step structure 5 and the annular structure 6 to be formed simultaneously using the same process.

[0103] See also Figure 6 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention, wherein the annular gate 4 is located between the layer where the emitter 2 is located and the base substrate 1;

[0104] The gate insulating layer 7 is located between the annular gate 4 and the emitter 2 .

[0105] In the embodiment provided by the present invention, by arranging the annular gate 4 between the layer where the emitter 2 is located and the base substrate 1, the distance between the emitter 2 and the collector 3 can be reduced, and the length of the vacuum channel between the emitter 2 and the collector 3 (in the direction perpendicular to the base substrate 1) is reduced, so that the electrons escaping from the emitter 2 can pass through the vacuum channel faster to reach the collector 3; and the ability of the annular gate 4 to control electrons can be further improved.

[0106] like Figure 2-Figure 6 As shown, the inner and outer contours of the annular gate 4 are the same as the outer contour of the collector 3, so that the electric field between the annular gate 4 and the collector 3 is evenly distributed, which is convenient for evenly exciting the electrons escaping from the collector 3 and evenly controlling the escaping electrons to flow to the emitter 2, thereby improving the stability of the vacuum transistor.

[0107] See also Figure 7 A top view of another vacuum transistor provided by an embodiment of the present invention. The outer contour of the collector 3 is circular. The inner and outer contours of the corresponding annular gate 4 are also circular.

[0108] exist Figure 7 The area between the two circular dotted lines is the positive projection position of the annular gate 4 on the substrate 1. Since the annular gate 4 is wrapped by the annular structure 6, Figure 7 Only the position of the annular gate 4 is shown.

[0109] By setting the outer contour of the collector 3 to a circle, it is possible to prevent the appearance of a tip at the edge of the collector 3 and prevent the electrons escaping from the emitter 2 from gathering at the tip, thereby enabling the electrons escaping from the emitter 2 to flow evenly to the collector 3, thereby improving the stability of the vacuum transistor.

[0110] In addition, the outer contour shape of the collector 3 can also be as follows Figure 1 The rectangle shown may also be a square or other polygons, and the adjacent sides of the polygons may be transitioned by arcs. The inner and outer contours of the corresponding annular grid 4 are the same as the outer contour of the collector 3.

[0111] See also Figure 8 A top view of another vacuum transistor provided by an embodiment of the present invention, wherein the vacuum transistor further comprises:

[0112] The pad 8 has no overlap with the emitter 2, and the pad 8 includes: a first sub-pad 81, a second sub-pad 82 and a third sub-pad 83;

[0113] The connection line 9 includes: a first sub-connection line 91 connected between the first sub-pad 81 and the emitter 2; a second sub-connection line 92 connected between the second sub-pad 82 and the collector 3; and a third sub-connection line 93 connected between the third sub-pad 83 and the annular gate 4.

[0114] The first sub-pad 81 and the first sub-connection line 91 can be set in the same layer and material as the emitter 2; the second sub-pad 82 and the second sub-connection line 92 can be set in the same layer and material as the collector 3; the third sub-pad 83 and the third sub-connection line 93 can be set in the same layer and material as the annular gate 4.

[0115] By setting a pad 8 that does not overlap with the emitter 2, and including a first sub-pad 81 electrically connected to the emitter 2, a second sub-pad 82 electrically connected to the collector 3, and a third sub-pad 83 electrically connected to the annular gate 4, these sub-pads 8 can be used to provide external testing or connection.

[0116] See also Fig. 9A schematic diagram of a vacuum detection platform for testing vacuum transistor samples provided in an embodiment of the present invention.

[0117] The vacuum detection station is composed of a vacuum probe station and a semiconductor parameter analyzer. The vacuum transistor sample is placed in a vacuum of 5×10 -14 torr vacuum probe station, and use a gate probe to connect between the ring gate 4 and the gate terminal of the semiconductor parameter analyzer, use a drain probe to connect between the collector 3 and the drain terminal of the semiconductor parameter analyzer, and use a source probe to connect between the emitter 2 and the source of the semiconductor parameter analyzer.

[0118] The semiconductor parameter analyzer provides a gate voltage Vg = 0V, and the source-drain voltage Vsd is scanned from 0-5V to 0-30V respectively. The uA-level tunneling current (Id) can be observed through the semiconductor parameter analyzer. Fig.10 A test curve diagram of a vacuum transistor provided by an embodiment of the present invention.

[0119] When the semiconductor parameter analyzer provides a gate voltage of Vg = 20V and scans the source-drain voltage Vsd from 0-5V to 0-30V, the uA-level tunneling current (Id) can also be observed, but it is significantly larger than the tunneling current when Vg = 0V. Fig.11 Shown is a test curve diagram of another vacuum transistor provided by an embodiment of the present invention.

[0120] pass Fig.10 and Fig.11 It can be seen that the annular gate 4 of the vacuum transistor has a strong control capability over the source-drain (emitter 2 - collector 3) current.

[0121] In addition, a new vacuum transistor can be obtained by connecting the annular gates 4, emitters 2 and collectors 3 of a plurality of vacuum transistors having the above structure in parallel to increase the emission current of the new vacuum transistor.

[0122] See also Fig.12 A schematic diagram of the structure of another vacuum transistor provided by an embodiment of the present invention, wherein the vacuum transistor further comprises:

[0123] The insulating layer L1 is located on the same side of the substrate 1 as the emitter 2, the collector 3 and the annular gate 4; the insulating layer L1 has a through hole penetrating in the thickness direction, and the emitter 2, the collector 3 and the annular gate 4 are located in the through hole;

[0124] The packaging layer L2 is located on a side of the insulating layer L1 away from the base substrate 1 and covers the through hole.

[0125] The substrate 1, the encapsulation layer L2 and the encapsulation layer L3 enclose the area in the through hole to form a closed vacuum cavity, so that the emitter 2, the collector 3 and the annular gate 4 are located in the vacuum cavity.

[0126] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a vacuum transistor, see Fig.13 A flowchart of a method for manufacturing a vacuum transistor provided by an embodiment of the present invention, the manufacturing method comprising:

[0127] S11: providing a substrate;

[0128] S12: On one side of the base substrate, an emitter, a collector and a ring gate are formed. The emitter, the collector and the ring gate are arranged in different layers and are spaced apart from each other. The orthographic projection of the ring gate on the base substrate surrounds the orthographic projection of the collector on the base substrate and is spaced apart. The orthographic projection of the ring gate on the base substrate is located within the orthographic projection of the emitter on the base substrate.

[0129] By forming an emitter, a collector and a ring gate on one side of a substrate, the emitter, the collector and the ring gate are arranged in different layers and are spaced apart from each other, the orthographic projection of the ring gate on the substrate surrounds the orthographic projection of the collector on the substrate and is spaced apart, the orthographic projection of the ring gate on the substrate is located within the orthographic projection of the emitter on the substrate, a large-area semiconductor process can be used to manufacture a vacuum transistor, thereby reducing the manufacturing cost of the vacuum transistor, and setting the ring gate in a ring shape can provide control capabilities of the vacuum transistor.

[0130] See also Fig.14 A schematic diagram of forming an emitter, a collector and a ring gate is provided in an embodiment of the present invention. The emitter, the collector and the ring gate are formed on one side of the substrate, which can be achieved by the following methods:

[0131] S21: forming an emitter 2 on one side of the base substrate 1;

[0132] A layer of emitter material, such as Mo / Cu / Au / graphene, etc., can be deposited on the substrate 1 by sputtering, chemical vapor deposition, etc., and the emitter material is patterned to form a Figure 8 The emitter 2 , the first sub-connection line 91 and the first sub-pad 81 are shown.

[0133] S22: forming a dielectric layer 5' and a ring-shaped gate 4 on a side of the emitter 2 away from the substrate 1; the dielectric layer 5' includes a step structure 5 and a ring structure 6;

[0134] like Fig.15FIG. 1 is a schematic diagram of forming a dielectric layer and a ring gate according to an embodiment of the present invention. The dielectric layer and the ring gate are formed on the side of the emitter away from the substrate, which can be achieved by the following methods:

[0135] S221: forming a first sub-dielectric layer 51 ′ on a side of the emitter 2 away from the substrate 1 ;

[0136] The entire first dielectric layer 5 ′ can be formed on the emitter 2 by chemical vapor deposition.

[0137] S222: forming a ring gate 4 on a side of the first sub-dielectric layer 51 ′ away from the base substrate 1 ;

[0138] The first sub-dielectric layer 51' may be formed by sputtering. Figure 8 As shown in the annular gate 4 , the third sub-connection line 93 and the third sub-pad 83 , the center of the annular gate 4 can roughly coincide with the center of the emitter 2 .

[0139] S223: forming a second sub-dielectric layer 52' ​​on a side of the annular gate 4 away from the substrate 1; the dielectric layer 5' includes a first sub-dielectric layer 51' and a second sub-dielectric layer 52';

[0140] The entire second sub-dielectric layer 52' ​​is prepared by chemical vapor deposition on the first sub-dielectric layer 51' and the annular gate 4. The second sub-dielectric layer 52' ​​and the first sub-dielectric layer 51' together wrap the annular gate 4.

[0141] S224 : etching the dielectric layer 5 ′ inside the inner ring of the annular gate 4 to form an annular through hole penetrating the dielectric layer 5 ′. The portion of the dielectric layer 5 ′ inside the annular through hole constitutes the step structure 5 , and the portion outside the annular through hole constitutes the annular structure 6 .

[0142] The dielectric layer 5' can be dry-etched to form an annular groove, the orthographic projection of the annular groove on the substrate 1 is located inside the annular gate 4 and does not overlap with the annular gate 4. The portion of the dielectric layer 5' after etching in the annular groove is composed of a first sub-step structure 51 (corresponding to the first sub-dielectric layer 51' after etching) and a second sub-step structure 52 (corresponding to the second sub-dielectric layer 52' ​​after etching) to form a step structure 5, and the portion outside the groove is composed of a first sub-annular structure 61 (corresponding to the first sub-dielectric layer 51' after etching) and a second sub-annular structure 62 (corresponding to the second sub-dielectric layer 52' ​​after etching) to form an annular structure 6 that wraps the annular gate 4.

[0143] After forming the first sub-dielectric layer 51' on the side of the emitter 2 away from the substrate 1, forming the annular gate 4 on the side of the first sub-dielectric layer 51' away from the substrate 1, and then forming the second sub-dielectric layer 52' ​​on the side of the annular gate 4 away from the substrate 1; the dielectric layer 5' includes the first sub-dielectric layer 51' and the second sub-dielectric layer 52', and finally etching the dielectric layer 5' in the inner ring of the annular gate 4 to form an annular through hole penetrating the dielectric layer 5', the part of the dielectric layer 5' located in the annular through hole constitutes the step structure 5, and the part located outside the annular through hole constitutes the annular structure 6, so that the step structure 5 and the annular structure 6 can be formed simultaneously through the same process, thereby saving the process and improving the production efficiency.

[0144] S23: forming a sacrificial layer 6' covering the dielectric layer 5' on a side of the dielectric layer 5' away from the substrate 1, and removing a portion of the sacrificial layer 6' located on the surface of the step structure 5;

[0145] Photoresist or SiO2 can be used as the sacrificial layer 6', which is coated on the entire surface to cover the dielectric layer 5'. The sacrificial layer 6' on at least the central area of ​​the step structure 5 is removed by photolithography.

[0146] S24: forming a collector material layer 3' on the side of the sacrificial layer 6' away from the base substrate 1, and etching the collector material layer 3' to obtain the collector 3; the orthographic projection of the step structure 5 on the base substrate 1 is located within the orthographic projection of the collector 3 on the base substrate 1;

[0147] The collector material layer 3', such as Au / Cu, is deposited on the sacrificial layer 6' by sputtering, and the collector material layer 3' is patterned to form the collector 3. The edge of the orthographic projection of the step structure 5 on the substrate 1 is indented relative to the edge of the orthographic projection of the collector 3 on the substrate 1, and the collector 3 and the annular gate 4 do not overlap.

[0148] It is important to understand that Fig.14 and Fig.15 Ideally, the side of the collector 3 facing the emitter 2 is flat, but during the process, the groove caused by the step structure 5 will cause the side of the collector 3 facing the emitter 2 to protrude towards the emitter 2, which reduces the distance between the emitter 2 and the collector 3, allowing electrons escaping from the emitter 2 to quickly reach the collector 3 through a shorter vacuum channel.

[0149] S25: removing the remaining sacrificial layer 6'.

[0150] The photoresist or SiO2 sacrificial layer 6' can be removed by a stripping solution or wet release to form a partially suspended collector 3. The area where the suspended part of the collector 3 overlaps with the emitter 2 is the vacuum channel of the vacuum transistor.

[0151] Based on the same inventive concept, an embodiment of the present invention provides an array substrate, which includes a plurality of vacuum transistors as described above arranged in a row.

[0152] The array substrate can be an array substrate in display panels such as a liquid crystal display panel (LCD), an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, and a micro light emitting diode (MicroLightEmitting Diodes) display panel, and the present invention does not make any specific limitation on this.

[0153] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0154] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A vacuum transistor, characterized in that: include: substrate substrate; An emitter, a collector and a ring-shaped gate, wherein the emitter, the collector and the ring-shaped gate are arranged in different layers and are spaced from each other; The orthographic projection of the annular gate on the substrate surrounds the orthographic projection of the collector on the substrate and is arranged at intervals; the orthographic projection of the annular gate on the substrate is located within the orthographic projection of the emitter on the substrate.

2. The vacuum transistor according to claim 1, characterized in that The vacuum transistor further comprises: a step structure between the emitter and the collector; The orthographic projection of the step structure on the base substrate is located within the orthographic projection of the collector on the base substrate, and the step structure is indented relative to the edge of the collector.

3. The vacuum transistor according to claim 2, characterized in that The emitter is located on one side of the substrate, and the collector is located on a side of the emitter away from the substrate; The orthographic projection of the collector on the substrate is located within the orthographic projection of the emitter on the substrate.

4. The vacuum transistor according to claim 2 or 3, characterized in that: The vacuum transistor further includes: an annular structure wrapping the annular gate; the orthographic projection of the annular structure on the substrate surrounds the step structure and is spaced apart from the step structure.

5. The vacuum transistor according to claim 4, characterized in that The annular gate is located between the layer where the emitter is located and the layer where the collector is located; The annular structure and the step structure are arranged on the same layer.

6. The vacuum transistor according to claim 4, characterized in that The annular gate is located between the layer where the emitter is located and the substrate.

7. The vacuum transistor according to claim 4, characterized in that The shape of the inner contour of the annular gate is the same as the shape of the outer contour of the collector.

8. The vacuum transistor according to claim 7, characterized in that The outer contour of the collector is circular.

9. A method for manufacturing a vacuum transistor, characterized in that: include: Providing a substrate; An emitter, a collector and a ring-shaped gate are formed on one side of the base substrate. The emitter, the collector and the ring-shaped gate are arranged in different layers and are spaced apart from each other. The orthographic projection of the ring-shaped gate on the base substrate surrounds the orthographic projection of the collector on the base substrate and is spaced apart. The orthographic projection of the ring-shaped gate on the base substrate is located within the orthographic projection of the emitter on the base substrate.

10. The manufacturing method according to claim 9, characterized in that: On one side of the substrate, an emitter, a collector and a ring gate are formed, including: forming the emitter on one side of the substrate; A dielectric layer and the annular gate are formed on a side of the emitter away from the substrate; the dielectric layer includes the step structure and the annular structure; On a side of the dielectric layer away from the substrate, a sacrificial layer covering the dielectric layer is formed, and a portion of the sacrificial layer located on a surface of the step structure is removed; A collector material layer is formed on a side of the sacrificial layer away from the base substrate, and the collector material layer is etched to obtain the collector; the orthographic projection of the step structure on the base substrate is located within the orthographic projection of the collector on the base substrate; The remaining sacrificial layer is removed.

11. The method according to claim 10, characterized in that: A dielectric layer and the annular gate are formed on a side of the emitter away from the substrate, including: Forming a first sub-dielectric layer on a side of the emitter away from the substrate; Forming the annular gate on a side of the first sub-dielectric layer away from the substrate; A second sub-dielectric layer is formed on a side of the annular gate away from the substrate; the dielectric layer includes the first sub-dielectric layer and the second sub-dielectric layer; The dielectric layer is etched inside the inner ring of the annular gate to form an annular through hole penetrating the dielectric layer, the portion of the dielectric layer located inside the annular through hole constitutes the step structure, and the portion outside the annular through hole constitutes the annular structure.

12. An array substrate, characterized in that: The invention comprises a plurality of vacuum transistors according to any one of claims 1 to 8 arranged in an array.

Images