An improved fan-out wafer-level packaging process for high-performance W-band applications

Abstract

The present invention relates to the field of semiconductor packaging technology, and specifically to an improved fan-out wafer-level packaging process for high-performance W-band applications, including the following steps: forming a first-side support carrier and laying a double-sided adhesive film thereon to provide support for subsequent chip fixation; forming a cavity between the chip area and the dielectric area, and forming an electroplating area at the required position to prevent the collapse of the air bridge structure; fixing the chip on the support carrier through flip-chip bonding; using a film pressing technique to fix the chip to ensure the stability of the chip in subsequent processes; by forming a cavity between the chip area and the dielectric area, preventing the collapse of the air bridge structure, improving the structural stability, and preventing the deterioration of the intrinsic performance of the transistor; by not attaching a dielectric to the surface of the active area, preventing the deterioration of the intrinsic performance of the transistor, ensuring the stable performance of the device, and improving the electrothermal performance; achieving electrical connection between the upper and lower parts of the package through glass vias technology, and improving the electrothermal performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and specifically to an improved fan-out wafer-level packaging process for high-performance W-band applications. Background Art

[0002] With the development of wireless communication technology, especially the increasing wide application of high-frequency bands (such as the W-band), the demand for high-performance packaging technology is growing. Applications in the W-band (75 - 110 GHz) cover multiple fields such as high-speed wireless communication and millimeter-wave radar, posing higher requirements for packaging technology. Traditional packaging technologies face many challenges in high-frequency applications. Especially in the flip-chip process, there are the following main problems:

[0003] The air-bridge structure is prone to collapse: In the flip-chip process, the air-bridge structure is likely to collapse during processing, affecting the quality and performance of the packaging.

[0004] The dielectric cannot adhere to the surface of the active region: Since the dielectric cannot adhere to the surface of the active region, it may lead to the deterioration of the intrinsic performance of the transistor, affecting the reliability and lifespan of the device.

[0005] The electrothermal performance of the device is poor: In high-frequency applications, the electrothermal performance of the device is poor, and the heat dissipation effect is not ideal, which may lead to excessive temperature rise and affect the working stability and reliability of the device.

[0006] It is difficult to test the yield rate of mass-produced chips: During mass production, the test methods for chip yield rate are not mature enough, resulting in low production efficiency and increased production costs.

[0007] The packaging consistency is poor: The consistency of packaged chips is poor, affecting the quality of the final product and possibly resulting in large performance differences between batches. Summary of the Invention

[0008] (I) Technical Problems to be Solved

[0009] Aiming at the deficiencies of the prior art, the present invention provides an improved fan-out wafer-level packaging process for high-performance W-band applications.

[0010] (II) Technical Solutions

[0011] To achieve the above object, the present invention provides the following technical solutions: An improved fan-out wafer-level packaging process for high-performance W-band applications of the present invention includes the following steps:

[0012] The first step: Form a first-side support carrier and lay a double-sided adhesive film on it to provide support for subsequent chip fixing;

[0013] Step 2: Formation of the cavity and electroplating area. A cavity is formed between the chip area and the dielectric area to prevent the collapse of the air bridge structure, and an electroplating area is formed at the required positions;

[0014] Step 3: Perform flip-chip bonding. The chip is fixed on the support carrier through flip-chip bonding;

[0015] Step 4: Fix the chip with a film. The film technology is used to fix the chip to ensure its stability in subsequent processes;

[0016] Step 5: Open holes in the glass. Holes are opened in the glass interposer area through the Through Glass Via (TGV) technology to achieve electrical connection between the positive and negative sides of the chip, and electrothermal treatment is performed on the back of the chip;

[0017] Step 6: Deposit thin-film metal electroplating. Thin-film metal electroplating is performed at the positions where electroplating is required to prepare for subsequent processes;

[0018] Step 7: Apply glue. An appropriate glue layer is coated to prepare for the next photolithography step;

[0019] Step 8: Photolithography, electroplating, degluing, and etching of the seed layer. The steps of photolithography, electroplating, degluing, and etching of the seed layer for the backside Redistribution Layer (RDL) are completed;

[0020] Step 9: Fix with a film again. The film technology is used again to fix the chip to ensure its stability during the process;

[0021] Step 10: Form the support carrier for the second side of the flip chip to prepare for subsequent processing;

[0022] Step 11: Unlock the first side of the chip, and perform temporary bonding and photolithography opening of the film on the first side;

[0023] Step 12: Electroplate the RDL on the front side of the chip. The Redistribution Layer (RDL) is electroplated on the front side of the chip;

[0024] Step 13: Surface passivation of the front side of the chip. Surface passivation treatment is performed on the front side of the chip to protect the chip and improve its reliability;

[0025] Step 14: Re-form the support carrier for the first side of the chip to complete the circuit design and electrical connection processing of the first side of the chip;

[0026] Step 15: Unlock the second side of the chip and perform laser opening at the ball placement location;

[0027] Step 16: Form pins at the ball placement positions and unlock the first side of the chip to complete the ball placement work of the chip.

[0028] Preferably, it includes a packaged chip G, and the packaged chip G includes a chip A, packaging dielectric layers B, C, D, E, and ball grid array (BGA) pins F. The dielectric layer B wraps the chip A. The dielectric layer C is encapsulated at the bottom of the chip A and the dielectric layer B. The dielectric layer D is encapsulated on the top of the chip A and the dielectric layer B. The dielectric layer E is encapsulated on the top of the dielectric layer D. A re - distribution layer is electroplated between the packaging dielectric layers B, C, D, E, and the BGA pins F are embedded in the dielectric layer C.

[0029] Further preferably, a cavity is provided between the dielectric layer D and the chip A.

[0030] Again preferably, the dielectric layer B is a glass interposer, the dielectric layer C is a second - side support carrier, the dielectric layer D is a first support carrier, and the dielectric layer E is a double - sided adhesive film.

[0031] Preferably, the packaged chip G is in a fan - shaped structure.

[0032] (III) Beneficial effects

[0033] Compared with the prior art, the present invention provides an improved fan - out wafer - level packaging process for high - performance W - band applications, having the following beneficial effects:

[0034] Prevent the collapse of the air - bridge structure: By forming a cavity between the chip area and the dielectric area, the collapse of the air - bridge structure is prevented, improving the structural stability.

[0035] Prevent the deterioration of the transistor's intrinsic performance: By not attaching a dielectric on the surface of the active area, the deterioration of the transistor's intrinsic performance is prevented, ensuring the stable performance of the device.

[0036] Improve the electro - thermal performance: Through the through - glass via (TGV) technology, the electrical connection above and below the package is achieved, improving the electro - thermal performance.

[0037] Improve the chip yield: Through precise process step control, the chip yield is improved.

[0038] Improve the consistency of the packaged chips: Through a standardized process flow, the consistency and reliability of the packaged chips are ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a structural diagram of the improved fan - out wafer - level packaging of the present invention;

[0040] Figure 2 It is a schematic diagram of the first to fourth process steps of the invention;

[0041] Figure 3 It is a schematic diagram of the fifth to eighth process steps of the invention;

[0042] Figure 4Schematic diagrams of the ninth to tenth process steps of the invention;

[0043] Figure 5 Schematic diagrams of the eleventh to fourteenth process steps of the invention;

[0044] Figure 6 Schematic diagrams of the fifteenth to sixteenth process steps of the invention. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] Please refer to Figure 1-6 , an improved fan-out wafer-level packaging process for high-performance W-band applications of the present invention realizes the packaging of high-performance chips through a series of steps, specifically including the following steps:

[0047] The first step is to form a first-side support carrier and lay a double-sided adhesive film thereon: form a first-side support carrier and lay a double-sided adhesive film thereon to provide support for subsequent chip fixing.

[0048] The second step is the formation of cavities and electroplating areas: form cavities between the chip area and the dielectric area to prevent the collapse of the air bridge structure, and form electroplating areas at the required positions.

[0049] The third step is to perform flip-chip bonding: fix the chip on the support carrier by flip-chip bonding.

[0050] The fourth step is to fix the chip with a film: use film pressing technology to fix the chip to ensure the stability of the chip in subsequent processes.

[0051] The fifth step is glass via formation: form vias in the glass interposer area through through-glass via (TGV) technology to achieve electrical connection between the positive and negative sides of the chip, and perform electro-thermal treatment on the back of the chip.

[0052] The sixth step is thin-film metal electroplating: perform thin-film metal electroplating at the positions where electroplating is required to prepare for subsequent processes.

[0053] The seventh step is glue coating: coat an appropriate glue layer to prepare for the next photolithography step.

[0054] The eighth step is photolithography, electroplating, degluing, and etching seeds: complete the photolithography, electroplating, degluing, and etching seeds steps of the backside redistribution layer (RDL).

[0055] Step 9, Film Pressing and Fixing: Fix it again using the film pressing technique to ensure the stability of the chip during the process.

[0056] Step 10, Forming the Support Carrier for the Second Side of the Flip Chip: Form the support carrier for the second side of the flip chip to prepare for subsequent processing.

[0057] Step 11, Unlocking the First Side of the Chip, Performing Temporary Bonding, and Lithography Opening for the Film on the First Side: Unlock the first side of the chip and perform temporary bonding and lithography opening for the film on the first side.

[0058] Step 12, Electroplating RDL on the Front Side of the Chip: Electroplate the redistribution layer (RDL) on the front side of the chip.

[0059] Step 13, Surface Passivation of the Front Side of the Chip: Perform surface passivation on the front side of the chip to protect the chip and improve reliability.

[0060] Step 14, Re - forming the Support Carrier for the First Side of the Chip: Complete the circuit design and electrical connection processing for the first side of the chip.

[0061] Step 15, Unlocking the Second Side of the Chip and Laser Opening at the Ball Mounting Location: Unlock the second side of the chip and perform laser opening at the ball mounting location.

[0062] Step 16, Forming Pins at the Ball Mounting Location and Unlocking the First Side of the Chip: Form pins at the ball mounting location and unlock the first side of the chip to complete the ball mounting work of the chip.

[0063] Working Principles of Each Preferred Technical Solution

[0064] Structure of the Encapsulated Chip G:

[0065] It includes chip A, encapsulation dielectric layers B, C, D, E, and ball mounting pins F.

[0066] Dielectric layer B wraps around chip A.

[0067] Dielectric layer C is encapsulated at the bottom of chip A and dielectric layer B.

[0068] Dielectric layer D is encapsulated on the top of chip A and dielectric layer B.

[0069] Dielectric layer E is encapsulated on the top of dielectric layer D.

[0070] Redistribution layers are electroplated between the encapsulation dielectric layers B, C, D, E.

[0071] Ball mounting pins F are embedded in dielectric layer C.

[0072] Cavity Design:

[0073] There is a cavity between dielectric layer D and chip A to prevent the collapse of the air bridge structure.

[0074] Specific materials of the dielectric layer:

[0075] Dielectric layer B is a glass interposer.

[0076] Dielectric layer C is a second-side support carrier.

[0077] Dielectric layer D is a first support carrier.

[0078] Dielectric layer E is a double-sided adhesive film.

[0079] Shape of the encapsulated chip G:

[0080] The encapsulated chip G has a fan-shaped structure, which is convenient for subsequent encapsulation and connection.

[0081] Comprehensive working principle

[0082] Through the above steps and technical solutions, the encapsulation process of the present invention can effectively solve several intractable problems faced in W-band multi-chip encapsulation:

[0083] Structural stability and reliability

[0084] Cavity design: By forming a cavity between the chip area and the dielectric area, the collapse of the air bridge structure is effectively prevented, thereby improving the stability and reliability of the encapsulation structure.

[0085] Through Glass Via (TGV) technology: Open holes in the glass interposer area through TGV technology to achieve electrical connection between the positive and negative sides of the chip, and perform electro-thermal treatment on the back of the chip, improving the reliability and electro-thermal performance of the overall structure.

[0086] Electrical performance and heat dissipation performance

[0087] Electrical connection: Achieve electrical connection between the positive and negative sides of the chip through TGV technology, ensuring the electrical performance after encapsulation.

[0088] Heat dissipation performance: Through precise electro-thermal treatment, ensure the heat dissipation performance of the back of the chip, improve the heat dissipation effect of the encapsulated chip, and are applicable to high-frequency (DC~110G) applications.

[0089] Process accuracy and yield

[0090] Film pressing and fixing: Through the two-time film pressing and fixing technology, ensure the stability of the chip in the subsequent process, and reduce the defective rate caused by movement.

[0091] Precision electroplating: Through steps such as thin-layer metal electroplating, photolithography, electroplating, degluing, and etching seeds, ensure the precise formation of the Redistribution Layer (RDL), improving the process accuracy.

[0092] Surface passivation: By performing surface passivation on the front side of the chip, the chip is protected and its reliability is improved, reducing the risk of failure caused by environmental factors.

[0093] Functionality and compatibility

[0094] Rewiring layer (RDL): The rewiring layer is electroplated between the encapsulation dielectric layers, improving the electrical connection performance of the package and enhancing the functionality of the packaged chip.

[0095] Ball grid array (BGA) pins: The BGA pins are embedded in dielectric layer C, providing a reliable pin structure for subsequent soldering and connection, and enhancing the compatibility of the packaged chip.

[0096] Production efficiency and consistency

[0097] Standardized process: Through the standardized process flow, the consistency and reliability of the packaged chip are ensured, and the production efficiency is improved.

[0098] Multi-layer support: Dielectric layers B, C, D, and E are glass interposer, second side support carrier, first support carrier, and double-sided adhesive film respectively. The multi-layer support structure ensures the stability and consistency of the chip during the packaging process.

[0099] Application scope

[0100] Suitable for multiple chips: The improved FOWLP process is suitable for double-sided packaging of gallium arsenide, gallium nitride, and silicon-based chips, expanding the application scope.

[0101] Cost-effectiveness

[0102] Simplified process: By optimizing the process steps, unnecessary complex processes are reduced, the production cost is lowered, and the economic efficiency is improved.

[0103] Structure optimization

[0104] Fan-shaped structure: The packaged chip G has a fan-shaped structure, which is convenient for subsequent packaging and connection, improving the flexibility and practicality of the package.

[0105] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An improved fan-out wafer-level packaging process for high-performance W-band applications, characterized in that, It includes the following steps: The first step: form a first-side support carrier and lay a double-sided adhesive film on it to provide support for subsequent chip fixation; The second step: formation of a cavity and an electroplating area, form a cavity between the chip area and the dielectric area to prevent the collapse of the air bridge structure, and form an electroplating area at the required position; The third step: perform flip-chip bonding, fix the chip on the support carrier by flip-chip bonding; The fourth step: fix the chip with a film, use the film pressing technology to fix the chip to ensure its stability in subsequent processes; The fifth step: open holes in the glass, open holes in the glass interposer area through the glass vias (TGV) technology to achieve electrical connection on both the positive and negative sides of the chip, and perform electro-thermal treatment on the back of the chip; The sixth step: perform thin-film metal electroplating, perform thin-film metal electroplating at the positions where electroplating is required to prepare for subsequent processes; The seventh step: apply glue, apply an appropriate glue layer to prepare for the next photolithography; The eighth step: photolithography, electroplating, de-gluing and etching seeds, complete the steps of photolithography, electroplating, de-gluing and etching seeds for the backside redistribution layer (RDL); The ninth step: fix with a film again, use the film pressing technology again to ensure the stability of the chip during the process; The tenth step: form a support carrier for the second side of the flip-chip to prepare for subsequent processing; The eleventh step: release the first side of the chip, and perform temporary bonding and film opening for photolithography on the first side; The twelfth step: electroplate the RDL on the front side of the chip, electroplate the redistribution layer (RDL) on the front side of the chip; The thirteenth step: surface passivation of the front side of the chip, perform surface passivation treatment on the front side of the chip to protect the chip and improve reliability; The fourteenth step: re-form the support carrier for the first side of the chip to complete the circuit design and electrical connection processing on the first side of the chip; The fifteenth step: release the second side of the chip, and perform laser opening at the ball mounting position; The sixteenth step: form pins at the ball mounting position and release the first side of the chip to complete the ball mounting of the chip.

2. The improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 1, characterized in that, It includes a packaged chip G, and the packaged chip G includes a chip A, packaging dielectric layers B, C, D, E, and ball mounting pins F. The dielectric layer B wraps the chip A, the dielectric layer C is encapsulated at the bottom of the chip A and the dielectric layer B, the dielectric layer D is encapsulated on top of the chip A and the dielectric layer B, the dielectric layer E is encapsulated on top of the dielectric layer D. A redistribution layer is electroplated between the packaging dielectric layers B, C, D, E, and the ball mounting pins F are embedded in the dielectric layer C.

3. An improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 2, characterized in that, There is a cavity between the dielectric layer D and the chip A.

4. An improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 3, characterized in that, The dielectric layer B is a glass interposer, the dielectric layer C is a second-side support carrier, the dielectric layer D is a first support carrier, and the dielectric layer E is a double-sided adhesive film.

5. An improved fan-out wafer-level packaging process for high-performance W-band applications according to claim 4, characterized in that, The packaged chip G is in a fan-shaped structure.

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