A semiconductor package structure and a forming method thereof

Abstract

The embodiments of the present disclosure disclose a semiconductor package structure and a forming method thereof. The semiconductor package structure comprises a substrate, a first chip and a second chip. The substrate comprises a first recess, a second recess and a substrate via. The first recess is formed on the front surface of the substrate, the second recess is formed on the back surface of the substrate, and the substrate via is located outside the first recess and the second recess. The first chip is implanted in the first recess, and the second chip is implanted in the second recess. The first chip and the second chip are electrically connected to the corresponding substrate via respectively, and are communicatively interconnected through the substrate via.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] 3D chip packaging technology involves stacking two or more chips vertically within a single packaging structure. This improves many chip performance aspects, such as size, weight, speed, yield, and power consumption. However, there are still areas for optimization in 3D chip packaging technologies, requiring further improvements in product performance and cost reduction. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor packaging structure and a method for forming the same, which can improve product performance and save costs.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides a semiconductor packaging structure, comprising: a substrate, the substrate including a first groove, a second groove, and a substrate via; the first groove being formed on the front side of the substrate, the second groove being formed on the back side of the substrate, and the substrate via located outside the first groove and the second groove; a first chip implanted in the first groove; a second chip implanted in the second groove; the first chip and the second chip being electrically connected to corresponding substrate vias and interconnected through the substrate vias.

[0006] In some embodiments, the semiconductor package structure further includes: a first redistribution layer and a second redistribution layer; the first redistribution layer is located on the front side of the substrate; the first chip is electrically connected to a corresponding substrate via through the first redistribution layer; the second redistribution layer is located on the back side of the substrate; the second chip is electrically connected to a corresponding substrate via through the second redistribution layer.

[0007] In some embodiments, the front side of the first chip faces the same direction as the front side of the substrate and is electrically connected to the first redistribution layer via conductive bumps; the front side of the second chip faces the same direction as the back side of the substrate and is electrically connected to the second redistribution layer via conductive bumps.

[0008] In some embodiments, the thickness between the bottom surface of the first groove and the bottom surface of the second groove is greater than one-quarter of the thickness of the first chip or the second chip, and less than one-third of the thickness of the first chip or the second chip.

[0009] In some embodiments, the projections of the first groove and the second groove in the vertical direction coincide; the projections of the first chip and the second chip in the vertical direction coincide.

[0010] In some embodiments, the first chip is adhered to the bottom surface of the first groove via an adhesive film; the second chip is adhered to the bottom surface of the second groove via an adhesive film.

[0011] In some embodiments, an insulating layer is filled between the inner wall of the first groove and the side wall of the first chip, and between the inner wall of the second groove and the side wall of the second chip.

[0012] In some embodiments, the number of substrates is multiple; the multiple substrates are stacked along the vertical direction; a molding compound is filled between adjacent substrates; and the chips located in different substrates and adjacent to each other are bonded and electrically connected.

[0013] In some embodiments, both the adhesive film and the molding compound comprise: resin and filler; wherein the filler is silicon oxide or aluminum oxide.

[0014] In some embodiments, the filler content of the molding compound is greater than the filler content of the adhesive film; and the filler volume of the molding compound is smaller than the filler volume of the adhesive film.

[0015] This disclosure also provides a method for forming a semiconductor package structure, the method comprising: providing a substrate; etching the front side of the substrate to form a first groove; implanting a first chip into the first groove; forming a substrate via in the substrate; the substrate via penetrating the substrate vertically and located outside the first groove; etching the back side of the substrate to form a second groove; implanting a second chip into the second groove; electrically connecting the first chip and the second chip to corresponding substrate vias; and the first chip and the second chip being interconnected through the substrate vias.

[0016] In some embodiments, electrically connecting the first chip and the second chip to corresponding substrate vias includes: forming a first redistribution layer on the front side of the substrate to electrically connect the first chip to one end of the corresponding substrate via; thinning the back side of the substrate to expose the other end of the substrate via; and forming a second redistribution layer on the back side of the substrate to electrically connect the second chip to the other end of the corresponding substrate via.

[0017] In some embodiments, implanting the first chip into the first groove includes: attaching the first chip to the bottom surface of the first groove using an adhesive film; and filling an insulating layer between the inner wall of the first groove and the sidewall of the first chip.

[0018] In some embodiments, implanting the second chip into the second groove includes: attaching the second chip to the bottom surface of the second groove using an adhesive film; and filling an insulating layer between the inner wall of the second groove and the sidewall of the second chip.

[0019] In some embodiments, after electrically connecting the first chip and the second chip to the corresponding substrate vias, the forming method further includes: performing a dicing process on the substrate; hot-press bonding the substrate to a substrate; wherein the hot-press bonding position is according to the position of the substrate vias; and forming a molding compound surrounding the substrate by an injection molding process.

[0020] In some embodiments, the number of substrates is multiple; thermally bonding the substrates to the substrate includes: thermally bonding the first substrate to the substrate; sequentially stacking the remaining chips on the first substrate, and thermally bonding adjacent substrates.

[0021] Therefore, this disclosure provides a semiconductor packaging structure and its formation method. The semiconductor packaging structure includes a substrate, a first chip, and a second chip. The substrate includes a first groove, a second groove, and a substrate via. The first groove is formed on the front side of the substrate, the second groove is formed on the back side of the substrate, and the substrate via is located outside the first and second grooves. The first chip is embedded in the first groove, and the second chip is embedded in the second groove. The first chip and the second chip are electrically connected to their respective substrate vias and are interconnected through the substrate vias. In this way, the first chip and the second chip achieve vertical communication interconnection (i.e., three-dimensional package interconnection) through the substrate vias, that is, inter-chip communication interconnection is achieved without forming vias through the chip. Thus, on the one hand, it is not necessary to reserve area in the chip for vias and the KOZ (exclusion zone) near the vias, which can reduce the chip size and increase DPW (die count); on the other hand, it can simplify the process and save costs. Attached Figure Description

[0022] Figure 1 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 1 ;

[0023] Figure 2 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 2 ;

[0024] Figure 3 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 3 ;

[0025] Figure 4 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 4 ;

[0026] Figure 5 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 5 ;

[0027] Figure 6 Flowchart of the method for forming a semiconductor package structure provided in the embodiments of this disclosure Figure 1 ;

[0028] Figure 7 Flowchart of the method for forming a semiconductor package structure provided in the embodiments of this disclosure Figure 2 ;

[0029] Figure 8 Flowchart of the method for forming a semiconductor package structure provided in the embodiments of this disclosure Figure 3 ;

[0030] Figure 9 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 1 ;

[0031] Figure 10 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 2 ;

[0032] Figure 11 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 3 ;

[0033] Figure 12 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 4 ;

[0034] Figure 13 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 5 ;

[0035] Figure 14 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 6 ;

[0036] Figure 15 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 7;

[0037] Figure 16 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 8 ;

[0038] Figure 17 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 9 ;

[0039] Figure 18 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 10 . Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0042] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0044] The following is an explanation of some terms used in the embodiments of this disclosure:

[0045] RDL (Re-distributed Layer): A wiring pattern formed on the surface of a chip that rearranges the chip's I / O ports.

[0046] TSV (Through Silicon Via): A structure that uses vertical through-holes for electrical connection.

[0047] KOZ (Keep Out Zone): The region adjacent to a particular semiconductor structure. To avoid interference, no other semiconductor structures can be placed in the KOZ.

[0048] DPW (Die Per Wafer): refers to the number of dies that can be cut from each wafer.

[0049] FO (Fan-out): A packaging method where the solder joints can be set beyond the area of ​​the bare die, providing more I / O solder joints.

[0050] Figure 1 This is a schematic diagram of an optional semiconductor packaging structure provided in an embodiment of this disclosure. Figure 1 This is a sectional view. For example... Figure 1 As shown, the semiconductor packaging structure includes: a substrate 10, a first chip 201, and a second chip 202.

[0051] refer to Figure 1 The substrate 10 includes a first groove 101, a second groove 102, and a substrate via 11. The first groove 101 is formed on the front side of the substrate 10, the second groove 102 is formed on the back side of the substrate 10, and the substrate via 11 is located outside the first groove 101 and the second groove 102. A first chip 201 is implanted in the first groove 101, and a second chip 202 is implanted in the second groove 102. The first chip 201 and the second chip 202 are electrically connected to their respective substrate vias 11 and are interconnected through the substrate vias 11.

[0052] In this embodiment of the disclosure, reference is made to Figure 1 The substrate 10 can be made of a semiconductor material, such as a silicon substrate. Correspondingly, the substrate via 11 can be a TSV. The substrate via 11 can be filled with conductive materials such as copper, tungsten, or polysilicon to communicate and interconnect the first chip 201 and the second chip 202.

[0053] In this embodiment of the disclosure, the semiconductor material used in the substrate 10 can be the same as the semiconductor material used in the chips (i.e., the first chip 201 and the second chip 202). In this way, the stress caused by the difference in CTE (coefficient of thermal expansion) between the various structures can be eliminated, thereby avoiding warpage.

[0054] In this embodiment of the disclosure, reference continues to be made to... Figure 1On the front and back sides of the substrate 10, a first groove 101 and a second groove 102 are etched, respectively. A first chip 201 is implanted in the first groove 101, and a second chip 202 is implanted in the second groove 102. A substrate via 11 is located outside the first groove 101 and the second groove 102; that is, the substrate via 11 is located outside the first chip 201 and the second chip 202, and no via is formed inside the first chip 201 and the second chip 202.

[0055] It should be noted that forming vias within the chip, especially during the packaging process where these vias need to be exposed on the back of the chip, incurs higher costs and increases process complexity. Furthermore, forming vias within the chip requires reserving space within the chip for the vias and the surrounding KOZ (Knock-Up Zone), thus occupying more chip area and hindering the reduction of chip size.

[0056] It is understood that in this embodiment of the present disclosure, the first chip 201 and the second chip 202 achieve vertical communication interconnection (i.e., three-dimensional package interconnection) through the substrate via 11. In this way, inter-chip communication interconnection is achieved without forming vias through the chip; thus, on the one hand, it is not necessary to reserve area in the chip for vias and the KOZ near the vias, which can reduce the chip size and improve DPW; on the other hand, it can simplify the process and save costs.

[0057] Meanwhile, if the TSV structure is manufactured in the first chip 201 and the second chip 202, each chip needs to undergo a TSV exposure process. However, the embodiments of this disclosure only require a TSV exposure process on the back side of the substrate, which reduces the TSV exposure process requirement by 50%, simplifies the process, and can improve product yield.

[0058] In some embodiments of this disclosure, reference is made to Figure 1 The semiconductor package structure further includes a first wiring layer 301 and a second wiring layer 302. The first wiring layer 301 is located on the front side of the substrate 10; the first chip 201 is electrically connected to the corresponding substrate via 11 through the first wiring layer 301. The second wiring layer 302 is located on the back side of the substrate 10; the second chip 202 is electrically connected to the corresponding substrate via 11 through the second wiring layer 302.

[0059] Figure 2 This is a schematic diagram of an optional semiconductor packaging structure provided in an embodiment of this disclosure. Figure 2 This is a top view. Figure 2 The wiring diagram of the first wiring layer 301 is shown in the example.

[0060] refer to Figure 2The first wiring layer 301 electrically connects the ports on the first chip 201 to the corresponding substrate vias 11. The wiring pattern of the second wiring layer 302 can be found in [reference needed]. Figure 2 To understand the wiring diagram of the first wiring layer 301.

[0061] It should be noted that, in Figure 2 In this configuration, the first wiring layer 301 connects each port on the first chip 201 to a substrate via 11 on the same side. However, the wiring pattern of the first wiring layer 301 can be adjusted as needed and is not limited to... Figure 2 The wiring pattern shown, for example, involves a first wiring layer 301 connecting each port on the first chip 201 to a substrate via 11 on the opposite side, without limitation.

[0062] In this embodiment of the disclosure, such as Figure 1 and Figure 3 As shown, the first chip 201 is connected to the substrate via 11 through a first redistribution layer 301, and the second chip 202 is connected to the substrate via 11 through a second redistribution layer 302, thus forming a signal interconnect. Since the first redistribution layer 301 connecting the first chip 201 extends outwards, and the first redistribution layer 302 connecting the second chip 202 extends outwards, the spacing between the substrate vias 11 is increased, thereby reducing signal crosstalk. Simultaneously, because the substrate vias 11 are relatively far from the first chip 201 and the second chip 202, the heat generated by the substrate vias 11 has a smaller impact on the chips.

[0063] Understandably, by using a redistribution layer, each chip is electrically connected to a corresponding via in the substrate to achieve communication interconnection between the chips. This eliminates the need to form vias throughout the chip to achieve inter-chip communication interconnection. Therefore, on the one hand, it eliminates the need to reserve area in the chip for vias and the KOZ area near them, allowing for a reduction in chip size and improved DPW (Distribution Power W). On the other hand, it eliminates the need for the related processes of forming vias in the chip, thus simplifying the process and saving costs.

[0064] At the same time, by using a redistribution layer, the ports on the chip can be rearranged, so the ports on the chip can be designed to be more compact, thereby reducing the size of the chip.

[0065] In some embodiments of this disclosure, reference is made to Figure 1 The front side of the first chip 201 faces the same direction as the front side of the substrate 10, and is electrically connected to the first redistribution layer 301 via conductive bumps 401. The front side of the second chip 202 faces the same direction as the back side of the substrate 10, and is electrically connected to the second redistribution layer 302 via conductive bumps (or pads) 401.

[0066] In this embodiment of the disclosure, such as Figure 1 and Figure 3 As shown, the first groove 101 and the second groove 102 are arranged opposite each other. The first chip 201 is arranged with its front side (circuit layer) facing upward in the first groove 101, and the second chip 202 is arranged with its front side (circuit layer) facing downward in the second groove 102. In this way, the circuit layers on the first chip 201 and the second chip 202 are far apart, thereby reducing signal crosstalk between the first chip 201 and the second chip 202.

[0067] In some embodiments of this disclosure, reference is made to Figure 1 The thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is greater than one-quarter of the thickness of the first chip 201 or the second chip 202, and less than one-third of the thickness of the first chip 201 or the second chip 202.

[0068] In this embodiment, the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is the thickness of the thinnest portion of the material in the middle of the substrate 10. This portion of material adheres to the bottom of both the first chip 201 and the bottom of the second chip 202. Therefore, this portion of material cannot be too thin, as this would pose a risk of collapse; at the same time, this portion of material cannot be too thick, as this would unnecessarily increase the vertical dimension of the substrate 10, thereby increasing the vertical dimension of the entire semiconductor package structure.

[0069] It is understood that, in this embodiment of the present disclosure, the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is set to between one-quarter and one-third of the thickness of the first chip 201 or the second chip 202. This avoids the risk of collapse while ensuring that the semiconductor packaging structure has a small vertical dimension.

[0070] In some embodiments of this disclosure, reference is made to Figure 1 The projections of the first groove 101 and the second groove 102 along the vertical direction coincide. The projections of the first chip 201 and the second chip 202 along the vertical direction coincide. In this way, the area occupied by the first groove 101 and the second groove 102 on the substrate 10 can be minimized, thereby reducing the size of the substrate 10 and thus reducing the size of the entire semiconductor package structure.

[0071] In some embodiments of this disclosure, reference is made to Figure 3 The first chip 201 is bonded to the bottom surface of the first groove via an adhesive film 501. The second chip 202 is bonded to the bottom surface of the second groove via an adhesive film 501.

[0072] In this embodiment, the adhesive film 501 includes resin and filler; the filler may be silicon oxide (SiO) or aluminum oxide (AlO). The adhesive film 501 has a heat insulation function, thus ensuring that the heat generated by the first chip 201 and the second chip 202 does not affect each other, thereby ensuring stable operating conditions of the first chip 201 and the second chip 202.

[0073] In some embodiments of this disclosure, reference is made to Figure 3 An insulating layer 502 is filled between the inner wall of the first groove and the side wall of the first chip 201, and between the inner wall of the second groove and the side wall of the second chip 202. The insulating layer 502 can be made of polyimide (PI).

[0074] It is understandable that filling the sidewalls of the first chip 201 and the second chip 202 with the insulating layer 502 can, on the one hand, prevent short circuits; on the other hand, it can protect the first chip 201 and the second chip 202 from the stress of the substrate 10.

[0075] like Figures 2 to 4 As shown, the first wiring layer 301 is located on the insulating layer 502, meaning that the first wiring layer 301 extends on the insulating layer 502, and its two ends are respectively connected to the first chip 201 and the substrate via 11, thereby realizing signal transmission. Simultaneously, from... Figure 2 As can be seen, the first wiring layer 301 has a large surface area, therefore, it will generate a significant amount of heat. Since the insulating layer 502 has poor thermal conductivity, while the molding compound 503 has good thermal conductivity (greater than that of the insulating layer 502), and the first wiring layer 301 is in direct contact with the molding compound 503, the heat generated by the first wiring layer 301 will dissipate outwards from the molding compound 503, thus reducing the impact of heat on the chip.

[0076] like Figure 4 As shown, in some embodiments, the insulating layer 502 is made of, for example, polyimide, and the encapsulation material 503 is made of, for example, a molding material. Polyimide is formed by combining a resin material with a small amount of filler, while the molding material is formed by combining a resin material with a large amount of filler. Resin materials have good flowability but poor thermal conductivity. Therefore, the encapsulation material 503 has more filler (silicon oxide) than the insulating layer 502, resulting in greater thermal conductivity for the encapsulation material 503. Simultaneously, since the gap between the first chip 201 and the sidewall of the first groove 101 is small, only a few micrometers to tens of micrometers, a smaller filler volume can be added to the resin material to better fix the first chip 201. That is, the filler volume in the insulating layer 502 is smaller than the filler volume in the encapsulation material 503, thereby increasing the flowability of the insulating layer 502 and providing better gap-filling ability.

[0077] In some embodiments, reference Figure 3 The first chip 201 and the second chip 202 can be the same type of chip, such as both being dynamic random access memory (DRAM) or static random access memory (SRAM). In other embodiments, the first chip 201 and the second chip 202 can also be different types of chips; for example, the first chip 201 is a memory chip, and the second chip 202 is a control chip. When the first chip 201 and the second chip 202 are different types of chips, the substrate via 11 can provide the same power signal to both.

[0078] In some embodiments of this disclosure, reference is made to Figure 4 or Figure 5 In a semiconductor packaging structure, there are multiple substrates 10. These substrates 10 are stacked vertically in a Z-direction. Adjacent substrates 10 are filled with a molding compound 503. Chips located within different substrates 10 and adjacent to each other are bonded together and electrically connected.

[0079] It should be noted that, Figure 4 and Figure 5 In the example shown, there are two bases 10. More bases 10 can be stacked on top of this; that is, the number of bases 10 is not limited to two. Their structure and connection relationships can be found in [reference needed]. Figure 4 and Figure 5 Examples.

[0080] In this embodiment of the disclosure, reference is made to Figure 4 Chips 202 and 203 are located in two different substrates and are electrically connected by bonding, with the bonding location situated at the via 11 in the substrate. Simultaneously, chips 201 and 202 are electrically connected through corresponding vias 11, and chips 203 and 204 are also electrically connected through corresponding vias 11. In this way, communication interconnection can be achieved between chips 201, 202, 203, and 204.

[0081] In this embodiment of the disclosure, reference is made to Figure 5 Chips 202 and 203 are located on two different substrates and are electrically connected by bonding, with the bonding location situated at the conductive bump 401. Simultaneously, chips 201 and 202 are electrically connected through corresponding substrate vias 11, and chips 203 and 204 are also electrically connected through corresponding substrate vias 11. Thus, communication interconnection can be achieved between chips 201, 202, 203, and 204. Since chips 202 and 203 are relatively close to the conductive bump 401, therefore, [the following is used]... Figure 5The illustrated structure can shorten interconnection paths, reduce loop resistance, and improve operating efficiency.

[0082] Understandably, multiple substrates 10 are stacked, and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, within each substrate 10, different chips are electrically connected through corresponding substrate vias 11. In this way, three-dimensional packaging of multiple chips is achieved, resulting in high performance with a small package size.

[0083] Meanwhile, the bonding position can be located at the position of the substrate via 11, and the substrate via 11 is located on the outside of the chip (any one of chips 201 to 204). That is, an FO type package is adopted, thus the setting range of bonding solder joints is larger, and more solder joints can be set, which is more advantageous for chip design.

[0084] In some embodiments of this disclosure, reference is made to Figure 4 or Figure 5 Both the adhesive film 501 and the molding compound 503 include resin and filler. The filler may be silicon dioxide or aluminum oxide.

[0085] It should be noted that in the adhesive film 501 and the molding compound 503, the resin is the base material, and the filler is added to the base material in a certain proportion.

[0086] In some embodiments of this disclosure, the filler content of the molding compound 503 is greater than that of the adhesive film 501. A higher filler content in the molding compound 503 results in a lower resin content. Since resin has poor heat dissipation capabilities, the molding compound 503 exhibits superior heat dissipation. This allows for better heat dissipation in the semiconductor packaging structure.

[0087] In some embodiments of this disclosure, the filler volume of the molding compound 503 is smaller than the filler volume of the adhesive film 501. A smaller filler volume results in better material flowability; therefore, the molding compound 503 exhibits superior flowability. This allows the molding compound 503 to fill more effectively, preventing gaps caused by incomplete filling.

[0088] Figure 6 This is an optional process diagram illustrating a method for forming a semiconductor package structure according to an embodiment of this disclosure. For example... Figure 6 As shown, the method for forming a semiconductor package structure includes steps S101 to S107, which will be explained in conjunction with each step.

[0089] It should be noted that, Figures 9 to 18 The structure of a semiconductor package during its formation process is shown, illustrating and clearly demonstrating the steps of the semiconductor package formation method.

[0090] S101, Provides the substrate.

[0091] In this embodiment of the disclosure, reference is made to Figure 9 The substrate 10 can be made of semiconductor materials, such as silicon. The semiconductor material used in the substrate 10 can be the same as the semiconductor material used in the subsequently implanted chip. This can eliminate the stress caused by the difference in CTE between the various structures, thereby avoiding warpage.

[0092] S102, Etch the front side of the substrate to form the first groove.

[0093] In this embodiment of the disclosure, reference is made to Figure 9 and Figure 10 The first groove 101 can be formed by etching on the front side of the substrate 10. The location where the first groove 101 is formed can be the center of the front side of the substrate 10.

[0094] S103. The first chip is implanted into the first groove.

[0095] In this embodiment of the disclosure, reference is made to Figure 10 and Figure 11 After the first groove 101 is formed, the first chip 201 can be implanted into the first groove 101. There may be a gap between the first chip 201 and the sidewall of the first groove 101.

[0096] S104. A substrate through hole is formed in the substrate; the substrate through hole penetrates the substrate vertically and is located outside the first groove.

[0097] In this embodiment of the disclosure, reference is made to Figure 12 and Figure 13 After the first chip 201 is implanted, a via 11 can be formed in the substrate 10. Specifically, an opening 12 can be formed first at the pad of the first chip 201 and at the corresponding position of the via 11, and then the via 11 can be formed. The via 11 can be filled with a conductive material such as copper, tungsten, or polysilicon to interconnect the various chips.

[0098] S105, Etch the back side of the substrate to form a second groove.

[0099] In this embodiment of the disclosure, reference is made to Figure 14 and Figure 15After completing the relevant processes on the front side of the substrate 10, the back side of the substrate 10 can be etched to form a second groove 102. The location where the second groove 102 is formed can be the middle of the back side of the substrate 10, that is, the projections of the first groove 101 and the second groove 102 along the vertical direction Z can coincide with each other. In this way, the area occupied by the first groove 101 and the second groove 102 on the substrate 10 can be minimized, thereby reducing the size of the substrate 10 and thus reducing the size of the entire semiconductor package structure.

[0100] In this embodiment of the disclosure, during the etching process to form the second groove 102, the etching cutoff position can be controlled, thereby controlling the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102. Specifically, the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 can be set to be greater than one-quarter of the thickness of the first chip 201 or the second chip 202, and less than one-third of the thickness of the first chip 201 or the second chip 202. This avoids the risk of collapse while ensuring a small vertical dimension of the semiconductor package structure.

[0101] S106. The second chip is implanted into the second groove.

[0102] In this embodiment of the disclosure, reference is made to Figure 15 and Figure 16 After the second groove 102 is formed, the second chip 202 can be implanted into the second groove 102. Correspondingly, there can be a gap between the second chip 202 and the sidewall of the second groove 102.

[0103] S107. The first chip and the second chip are electrically connected to their respective substrate vias; the first chip and the second chip are interconnected through the substrate vias.

[0104] In this embodiment of the disclosure, reference is made to Figure 16 The first chip 201 and the second chip 202 are electrically connected to corresponding substrate vias 11 and interconnected through the substrate vias 11. In this way, inter-chip communication interconnection is achieved without forming vias through the chip; thus, on the one hand, it is not necessary to reserve area in the chip for vias and the KOZ area near the vias, which can reduce the chip size and improve DPW; on the other hand, it can simplify the process and save costs.

[0105] It should be noted that the first chip 201 and the second chip 202 are chips after packaging and thinning. At this time, the thickness of the first chip 201 and the second chip 202 can be between 50 and 80 micrometers, for example, 60, 65, or 70 micrometers. Therefore, the thickness between the bottom surface of the first groove 101 and the bottom surface of the second groove 102 is relatively small, which can be between 15 and 20 micrometers, for example, 18 micrometers.

[0106] In some embodiments of this disclosure, it is possible to... Figure 7 The shown S201 to S203 are implemented to achieve this. Figure 6 S107, shown below, will be explained in conjunction with each step.

[0107] S201. A first wiring layer is formed on the front side of the substrate to electrically connect the first chip to one end of the corresponding substrate via.

[0108] In this embodiment of the disclosure, reference is made to Figure 13 On the front side of the substrate 10, one end of the substrate via 11 is exposed. A first redistribution layer 301 can then be formed on the front side of the substrate 10 to electrically connect the first chip 201 to the corresponding end of the substrate via 11. The first redistribution layer 301 is electrically connected to the pads of the first chip 201.

[0109] S202. Thin the back side of the substrate to expose the other end of the through hole in the substrate.

[0110] In this embodiment of the disclosure, reference is made to Figure 13 and Figure 14 The back side of the substrate 10 can be thinned until the other end of the substrate through hole 11 is exposed on the back side of the substrate 10.

[0111] S203. A second wiring layer is formed on the back side of the substrate to electrically connect the second chip to the other end of the corresponding substrate via.

[0112] In this embodiment of the disclosure, reference is made to Figure 16 A second wiring layer 302 can be formed on the back side of the substrate 10 to electrically connect the second chip 202 to the other end of the corresponding substrate via 11. The second wiring layer 302 is electrically connected to the pads of the second chip 202.

[0113] Understandably, by using a redistribution layer, each chip is electrically connected to a corresponding via in the substrate to achieve communication interconnection between the chips. This eliminates the need to form vias throughout the chip to achieve inter-chip communication interconnection. Therefore, on the one hand, it eliminates the need to reserve area in the chip for vias and the KOZ area near them, allowing for a reduction in chip size and improved DPW (Distribution Power W). On the other hand, it eliminates the need for the related processes of forming vias in the chip, thus simplifying the process and saving costs.

[0114] At the same time, by using a redistribution layer, the ports on the chip can be rearranged, so the ports on the chip can be designed to be more compact, thereby reducing the size of the chip.

[0115] In some embodiments of this disclosure, it can be implemented via S301 to S302. Figure 6 S103, shown below, will be explained in conjunction with each step.

[0116] S301. The first chip is bonded to the bottom surface of the first groove using an adhesive film.

[0117] In this embodiment of the disclosure, reference is made to Figure 11 During the implantation of the first chip 201, the first chip 201 can be bonded to the bottom surface of the first groove 101 using an adhesive film 501. The adhesive film 501 includes resin and filler; wherein the filler can be silicon oxide (SiO) or aluminum oxide (AlO).

[0118] S302. An insulating layer is filled between the inner wall of the first groove and the side wall of the first chip.

[0119] In this embodiment of the disclosure, reference is made to Figure 11 and Figure 12 During the implantation of the first chip 201, an insulating layer 502 can be filled between the inner wall of the first groove 101 and the side wall of the first chip 201. The material of the insulating layer 502 can be PI.

[0120] In some embodiments of this disclosure, it can be implemented via S303 to S304. Figure 6 S106, shown below, will be explained in conjunction with each step.

[0121] S303. The second chip is attached to the bottom surface of the second groove using an adhesive film.

[0122] In this embodiment of the disclosure, reference is made to Figure 15 and 16 During the implantation of the second chip 202, the second chip 202 can be bonded to the bottom surface of the second groove 102 by means of the adhesive film 501.

[0123] It is understandable that the adhesive film 501 has a heat insulation function, which ensures that the heat generated by the first chip 201 and the second chip 202 will not affect each other, thereby ensuring the stable operation of the first chip 201 and the second chip 202.

[0124] S304. An insulating layer is filled between the inner wall of the second groove and the side wall of the second chip.

[0125] In this embodiment of the disclosure, reference is made to Figure 15 and 16 During the implantation of the second chip 202, an insulating layer 502 can be filled between the inner wall of the second groove 102 and the side wall of the second chip 202.

[0126] It is understandable that filling the sidewalls of the first chip 201 and the second chip 202 with the insulating layer 502 can, on the one hand, prevent short circuits; on the other hand, it can protect the first chip 201 and the second chip 202 from the stress of the substrate 10.

[0127] In some embodiments of this disclosure, in Figure 6 Following S107 shown, the forming method further includes Figure 8 S108 to S110 shown will be explained in conjunction with each step.

[0128] S108. Perform a dicing process on the substrate.

[0129] S109. The substrate and the base plate are thermally bonded; wherein the thermal bonding position is determined according to the position of the through hole in the substrate.

[0130] S110. A molding compound is formed to surround the substrate through injection molding process.

[0131] In this embodiment of the disclosure, reference is made to Figure 17 After the various structures on the substrate 10 are formed, the substrate 10 can be diced to cut it out. Then, the substrate 10 is thermally compressed and bonded to the substrate 60 (TCB), with the TCB position determined according to the location of the through-holes 11 in the substrate. Finally, a molding compound 503 surrounding the substrate 10 can be formed using an injection molding process.

[0132] In this embodiment of the disclosure, reference continues to be made to... Figure 17 Both the adhesive film 501 and the molding compound 503 include resin and filler. The resin is the base material, and the filler is added to the base material in a certain proportion. The filler can be silicon dioxide or aluminum oxide.

[0133] In some embodiments of this disclosure, the filler content of the molding compound 503 is greater than that of the adhesive film 501. A higher filler content in the molding compound 503 results in a lower resin content. Since resin has poor heat dissipation capabilities, the molding compound 503 exhibits superior heat dissipation. This allows for better heat dissipation in the semiconductor packaging structure.

[0134] In some embodiments of this disclosure, the filler volume of the molding compound 503 is smaller than the filler volume of the adhesive film 501. A smaller filler volume results in better material flowability; therefore, the molding compound 503 exhibits superior flowability. This allows the molding compound 503 to fill more effectively, preventing gaps caused by incomplete filling.

[0135] In some embodiments of this disclosure, the number of substrates is multiple, which can be achieved through steps S401 to S402. Figure 8 S109, shown below, will be explained in conjunction with each step.

[0136] S401, The first substrate is thermally bonded to the substrate.

[0137] S402. Stack the remaining chips sequentially on the first substrate and thermally bond the adjacent substrates together.

[0138] In this embodiment of the disclosure, reference is made to Figure 18 The first substrate 10 (i.e., the bottommost substrate 10) can be thermo-bonded to the substrate 60. Then, a second substrate 10 can be stacked on top of the first substrate 10 and thermo-bonded to the first substrate 10, wherein the bonding location can be located at the substrate via 11. In this way, more substrates 10 can be stacked.

[0139] Understandably, multiple substrates 10 are stacked, and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, within each substrate 10, different chips are electrically connected through corresponding substrate vias 11. In this way, three-dimensional packaging of multiple chips is achieved, resulting in high performance with a small package size.

[0140] Meanwhile, the bonding position can be located at the position of the substrate via 11, and the substrate via 11 is located on the outside of the chip (any one of chips 201 to 204). That is, an FO type package is adopted, thus the setting range of bonding solder joints is larger, and more solder joints can be set, which is more advantageous for chip design.

[0141] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0142] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0143] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor package structure, comprising: The semiconductor package structure comprises: a substrate, the substrate comprising a first recess, a second recess and a substrate via; the first recess is formed on the front surface of the substrate, the second recess is formed on the back surface of the substrate, and the substrate via is located outside the first recess and the second recess; a first chip implanted in the first recess; a second chip implanted in the second recess; the first chip and the second chip are respectively electrically connected to the corresponding substrate via and are communicatively interconnected through the substrate via; the semiconductor package structure further comprises a first redistribution layer and a second redistribution layer; the first redistribution layer is located on the front surface of the substrate; the first chip is electrically connected to the corresponding substrate via through the first redistribution layer; the second redistribution layer is located on the back surface of the substrate; the second chip is electrically connected to the corresponding substrate via through the second redistribution layer; the front surface of the first chip is consistent with the front surface of the substrate in the direction of the front surface, and is electrically connected to the first redistribution layer through a conductive bump; the front surface of the second chip is consistent with the back surface of the substrate in the direction of the back surface, and is electrically connected to the second redistribution layer through a conductive bump; the number of the substrate is multiple; a plurality of the substrates are stacked along the vertical direction; the adjacent substrates are filled with a plastic packaging material; the chips located in different substrates and adjacent to each other are electrically connected by bonding; the bonding position is located at the position of the conductive bump; the plastic packaging material is in direct contact with the first redistribution layer and the second redistribution layer; the inner wall of the first recess and the side wall of the first chip, and the inner wall of the second recess and the side wall of the second chip are both filled with an insulating layer; the thermal conductivity of the plastic packaging material is greater than the thermal conductivity of the insulating layer.

2. The semiconductor package structure of claim 1, wherein, The thickness between the bottom surface of the first recess and the bottom surface of the second recess is greater than one fourth of the thickness of the first chip or the second chip, and less than one third of the thickness of the first chip or the second chip.

3. The semiconductor package structure according to claim 1, wherein: the first recess and the second recess are mutually overlapped in the vertical direction projection; the first chip and the second chip are mutually overlapped in the vertical direction projection.

4. The semiconductor package structure according to any one of claims 1 to 3, wherein: the first chip is adhered to the bottom surface of the first recess through an adhesive film; the second chip is adhered to the bottom surface of the second recess through an adhesive film.

5. The semiconductor package structure of claim 4, wherein, The adhesive film and the plastic packaging material both comprise resin and filler; wherein the filler is silicon oxide or aluminum oxide.

6. The semiconductor package structure according to claim 5, wherein: the filler content of the plastic packaging material is greater than the filler content of the adhesive film; the filler volume of the plastic packaging material is less than the filler volume of the adhesive film.

7. The semiconductor package structure of claim 6, wherein, The filler volume of the plastic packaging material is less than the filler volume of the insulating layer.

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