Semiconductor package and semiconductor device including same

Abstract

The invention relates to a semiconductor package and a semiconductor device including the same. The semiconductor package includes a core layer, an integrated stacked capacitor (ISC) on the core layer, one or more stack layers on the core layer in which the ISC is embedded, and one or more metal layers on the core layer.

Description

Technical Field

[0001] The present disclosure relates to methods of embedding integrated stacked capacitors (ISCs) in substrate buildup layers and devices having ISCs embedded in substrate buildup layers. Background Art

[0002] Currently, multilayer ceramic capacitors (MLCCs) are the most produced and used capacitors in electronic devices. Due to capacitor thickness limitations (e.g., >100 μm), substrates can have large ceramic capacitors on the substrate surface or at the substrate core layer. Due to the large thickness of ceramic capacitors, these capacitors are set outside the stacked layers.

[0003] A semiconductor package may be a metal, plastic, glass, or ceramic housing that contains one or more discrete semiconductor devices or integrated circuits. Individual components may be manufactured on a semiconductor wafer (e.g., a silicon wafer) before being cut into dies, tested, and packaged into a semiconductor package. A semiconductor package may have leads or contacts for the devices inside the semiconductor package.

[0004] The information disclosed in this background technology section is known to the inventor or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0005] Embodiments of the present disclosure relate to forming a semiconductor package in which an integrated stacked capacitor (ISC) is embedded in a substrate buildup layer in the semiconductor package. The semiconductor package may be incorporated into a semiconductor device such as an electronic device (e.g., a handheld device, a computer, a tablet, etc.). The ISC may be embedded in the substrate buildup layer during the substrate manufacturing process. The buildup layer may contain both active and passive ISCs for improving dielectric thickness uniformity.

[0006] The ISC may be formed on the core layer with copper wiring. The ISC may be formed on or adjacent to the copper wiring. One or more buildup layers may be formed on the core layer such that the ISC and the copper wiring are embedded in the one or more buildup layers.

[0007] Embodiments of the present disclosure may result in reduced substrate thickness. For example, conventional semiconductor packages with ceramic capacitors require a 500 μm thick core to allow the capacitor to be embedded in the core layer, while embodiments of the present disclosure have a core thickness of approximately 50 μm if the ISC is embedded in the buildup layer.

[0008] Embodiments of the present disclosure provide improved electrical performance for semiconductor packages. For example, because the ISC has a smaller thickness than a ceramic capacitor, the resulting semiconductor package has a high capacitance density, resulting in improved electrical performance. In addition, the semiconductor package can exhibit improved electrical performance because placing the ISC in a buildup layer results in the ISC being closer to the silicon.

[0009] Embodiments of the present disclosure provide improved dielectric thickness uniformity. For example, the thickness of an ISC in a buildup layer can match the thickness of a copper wiring pattern embedded in the same buildup layer, thereby enabling the ISC to be used as a filler (e.g., dummy silicon) in areas of a semiconductor package where copper cannot be formed or placed. Thus, embodiments of the present disclosure improve the mechanical strength of the dielectric thickness uniformity of a semiconductor package.

[0010] According to one or more embodiments, a method of forming a semiconductor package includes forming a core layer. The method also includes forming an integrated stacked capacitor (ISC) on the core layer. The method also includes forming one or more buildup layers on the core layer, wherein the ISC is embedded in the one or more buildup layers. The method also includes forming one or more metal layers on the core layer.

[0011] According to one or more embodiments, a semiconductor package includes a core layer. The semiconductor package also includes an integrated stacked capacitor (ISC) on the core layer. The semiconductor package includes one or more buildup layers on the core layer, wherein the ISC is embedded in the one or more buildup layers. The semiconductor package includes one or more metal layers on the core layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other features, properties, and various advantages of the disclosed subject matter will become more apparent from the following detailed description and the accompanying drawings, in which:

[0013] Figure 1 is a schematic illustration of an example semiconductor package.

[0014] Figure 2 is an illustration of a process of forming a semiconductor package having an integrated stacked capacitor (ISC) embedded in a buildup layer according to an embodiment of the present disclosure.

[0015] Figure 3 is a schematic illustration of a buildup layer having an ISC and a copper wiring pattern embedded therein according to an embodiment of the present disclosure.

[0016] Figure 4 is an illustration of a process of forming a semiconductor package having an ISC embedded in a buildup layer according to an embodiment of the present disclosure.

[0017] Figure 5is a schematic illustration of a buildup layer having an ISC and a copper wiring pattern embedded therein according to an embodiment of the present disclosure.

[0018] Figure 6 is a schematic illustration of a semiconductor package having one or more ISCs embedded in one or more buildup layers according to an embodiment of the present disclosure.

[0019] Figure 7 is a schematic illustration of a semiconductor package having one or more ISCs embedded in one or more layers according to an embodiment of the present disclosure.

[0020] Figure 8 is a schematic illustration of a buildup layer having an ISC and a copper wiring pattern embedded therein, the buildup layer having one or more terminal contacts according to an embodiment of the present disclosure.

[0021] Fig. 9 is a schematic illustration of a stacked layer with active ISCs and non-active ISCs according to an embodiment of the present disclosure.

[0022] Fig.10 is a flow chart of a process for forming a semiconductor package having an ISC embedded in a buildup layer.

[0023] Fig.11 The present invention at least includes Figure 6 or Figure 7 Schematic diagram of an electronic device with a semiconductor package shown in FIG. DETAILED DESCRIPTION

[0024] The following detailed description of example embodiments refers to the accompanying drawings.The same reference numbers in different drawings may identify the same or similar elements.

[0025] The foregoing disclosure provides explanation and description, but is not intended to be exhaustive or to limit implementation to the disclosed precise form. According to the foregoing disclosure, modification and variation are possible, or can be obtained from the practice of implementation. In addition, one or more features or components of an embodiment can be incorporated into another embodiment (or one or more features of another embodiment) or combined with another embodiment (or one or more features of another embodiment). In addition, in the flowchart and description of the operation provided below, it should be understood that one or more operations can be omitted, one or more operations can be added, one or more operations can be performed (at least partially) simultaneously, and the order of one or more operations can be switched.

[0026] It will be apparent that the systems and / or methods described herein may be implemented in various forms of hardware or firmware. The actual dedicated control hardware used to implement these systems and / or methods does not limit the implementation.

[0027] Even though particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below may be directly dependent on only one claim, the disclosure of possible implementations includes the combination of each dependent claim with every other claim in the claim group.

[0028] Unless explicitly described as such, the elements, actions or instructions used herein should not be interpreted as being crucial or necessary. In addition, as used herein, the articles "a" and "an" are intended to include one or more items, and can be used interchangeably with "one or more". In the case of only meaning one item, the term "one" or similar language is used. In addition, as used herein, the terms "has", "have", "having", "include", "including", etc. are intended to be open terms. In addition, unless otherwise explicitly stated, the phrase "based on" is intended to mean "based at least in part". In addition, statements such as "at least one of [A] and [B]" or "at least one of [A] or [B]" should be understood to include only A, only B, or both A and B.

[0029] References throughout the specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in conjunction with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment," "in an embodiment," and similar language may, but do not necessarily, all refer to the same embodiment throughout this specification.

[0030] In addition, the described features, advantages and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. Based on the description herein, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present disclosure may be recognized in certain embodiments.

[0031] In this article, the term "connection" between two structures or elements may refer to the electrical connection between them. For example, the connection between a semiconductor chip, a semiconductor package and / or a semiconductor device may refer to the electrical connection between two or more corresponding elements. The terms "connection" and "connection" may have the same meaning and are used interchangeably in this article. In addition, the term "isolation" between two structures or elements refers to electrical insulation or separation therebetween. For example, wiring patterns isolated from each other may mean that wiring patterns are not electrically connected to each other.

[0032] In the following, reference is made to Figures 1 to 11 Various implementations of the present disclosure have been described.

[0033] Integrated stacked capacitor (ISC) technology is an emerging technology that uses a silicon dynamic random access memory (DRAM) cell cap process to achieve silicon-based capacitors with high capacitance density. ISC technology is in a very early stage. The most common application of ISC technology is to integrate ISCs in silicon manufacturing processes (e.g., building ISCs in logic chips). Another application is to build ISCs on silicon wafers and later singulate (e.g., cut) the wafers into one or more discrete components. However, current manufacturing of semiconductor packaging and electronic devices does not take advantage of the size advantages of ISCs relative to ceramic capacitors.

[0034] Embodiments of the present disclosure relate to forming a semiconductor package in which an integrated stacked capacitor (ISC) is embedded in a substrate stacking layer in the semiconductor package. The substrate stacking layer may be an organic layer. The substrate stacking layer may have a thickness of 15-45 μm. According to one or more embodiments, the ISC may be embedded in the substrate stacking layer during a substrate manufacturing process.

[0035] In one or more examples, the buildup layer can be formed of one or more buildup films. Multilayer buildup films can be used for the purpose of fanning out a small bump pitch from a chip to a much larger bump pitch for solder balls that connect the substrate to a printed circuit board. The buildup layer provides a high interconnect density between the chip and the substrate.

[0036] The buildup layer can be defined by width, thickness, and spacing. In one or more examples, most signal routing can be included in the buildup layer. The buildup layer can be further characterized by dielectric properties, thickness, electrical properties (such as dielectric constant and loss tangent), and thermal expansion properties.

[0037] The buildup layer may contain one or more vias. A via may be formed by drilling through a single dielectric layer at a time. In one or more examples, a via may rise in steps through the buildup layer. In one or more examples, a via may be stacked in a buildup layer.

[0038] The buildup layers may be fabricated on one or both sides of the package core. In some cases, there may be the same number of buildup layers on both sides of the package core. In other cases, the buildup layers formed on either side of the package core may be asymmetric. The stacking may also be asymmetric, with different layer thicknesses on either side of the core. In one or more examples, the core of the semiconductor package may have a plurality of through holes for making electrical connections from one side of the core to the other side of the core. Therefore, the passages in the core may allow one or more buildup layers on the top end of the semiconductor package to be electrically connected to one or more buildup layers on the bottom end of the semiconductor package.

[0039] The stacking layer can be formed of a dielectric material. Each stacking layer can be formed of the same dielectric material. In one or more examples, the stacking layer can be formed of different dielectric materials. For example, the first stacking layer can be formed of a low-k dielectric material, and the second stacking layer can be formed of a high-k dielectric material. Examples of low-k dielectric materials include, but are not limited to, fluorine-doped silicon dioxide, organic silicate glass (OSG), carbon-doped oxide (CDO), porous silicon dioxide, porous organic silicate glass, spin-on organic polymer dielectrics, spin-on silicon-based polymer dielectrics. Examples of high-k dielectric materials include, but are not limited to, hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide.

[0040] In one or more examples, the buildup layer may be formed of at least one dielectric layer and one metal layer. In one or more examples, the dielectric layer and the metal layer may have the same thickness. In one or more examples, the thickness of the dielectric layer may be thicker than the thickness of the metal layer. For example, the thickness of the dielectric layer may be in the range of 50% to 70% of the thickness of the buildup layer, wherein the metal layer may form the remaining thickness of the dielectric layer.

[0041] In an embodiment of the present disclosure, the term “copper layer” may refer to a copper wiring pattern, a copper trace connection or a copper via, or a copper terminal contact.

[0042] Embodiments of the present disclosure may include an ISC. The ISC exhibits a high capacitance density compared to conventional silicon capacitors. The ISC may include at least one stacked capacitor. In one or more examples, the ISC may be a vertical cylindrical array including one or more capacitive paths. The stacked capacitor may include a plurality of planar capacitors arranged in layers on each other, wherein the electrodes of the plurality of planar capacitors are connected in parallel. The stacked capacitor may include, for example, a crown stacked capacitor, a raw silicon stacked capacitor, or any other suitable capacitor known to those of ordinary skill in the art. The ISC may be manufactured by any suitable stacked capacitor formation process known to those of ordinary skill in the art. Figure 1An example semiconductor package 100 is shown. Semiconductor package 100 may include a core layer 102, ceramic capacitors 104, 106, 108, and 110, and a silicon backplane 112. In one or more examples, the silicon backplane may be another integrated circuit or a display. Ceramic capacitor 108 may be attached to the front side of the package as a die side capacitor (DSC) using a surface mount technology (SMT) process. In one or more examples, ceramic capacitor 110 may be attached to the bottom side of the package as a land side capacitor (LSC).

[0043] Ceramic capacitors 104 and 106 may be embedded in core layer 102, which may be a copper clad laminate (CCL) core. Semiconductor package 100 may include one or more buildup layers that are subsequently added after adding core layer 102. The core layer thickness may be in the range of 100 μm to 800 μm, and the thickness of one buildup layer (which may be referred to as a dielectric thickness) may be in the range of 20 μm to 45 μm. Substrate 100 may be a 3-2-3 structure with two core layers and six buildup layers, resulting in a total of eight layers. For example, as Figure 1 As shown in , layer L4 / L5 constitutes core 102, layer L1-L3 constitutes a buildup layer above core layer 102, and layer L6-L8 constitutes a buildup layer below core layer 102. In one or more examples, each of layers L1-L3 and L6-L8 can have the same thickness. In one or more examples, the L4 / L5 layer constituting the core can have a thickness that is twice the thickness of one buildup layer. In one or more examples, the L4 / L5 layer can have a thickness equal to the thickness of the combined buildup layers L1-L3 or the thickness of the combined layers L6-L8.

[0044] In one or more examples, semiconductor package 100 may include copper vias 114A, 114B, 114C, and 114D. Each of the copper vias may be connected to a copper wiring pattern through a buildup layer. For example, copper via 114A may be connected to copper wiring patterns 116A_1-116A_6 through buildup layers L1-L6. In one or more examples, each copper wiring pattern may include a flat portion and a protruding portion that is perpendicular to the flat portion and is inserted into or penetrates the buildup layer. For example, copper wiring pattern 116A_1 may include a protruding portion in layer L1 that connects copper wiring pattern 116A_1 to copper wiring pattern 116A_2.

[0045] Copper via 114B may be connected to copper wiring patterns 116B_1-116B_6 through buildup layers L1-L6. Copper via 114C may be connected to copper wiring patterns 116C_1-116C_6 through buildup layers L1-L6. Copper via 114D may be connected to copper wiring patterns 116D_1-116D_6 through buildup layers L1-L6.

[0046] Ceramic capacitors 104, 106, 108 and 110 can also be connected to some copper wiring patterns through some buildup layers. For example, ceramic capacitor 104 can be connected to the first group of copper wiring patterns 118A, 118B, 118C and 118D and the second group of copper wiring patterns 120A, 120B, 120C and 120D through buildup layers L1-L3. Similarly, ceramic capacitor 106 can be connected to the third group of copper wiring patterns 122A, 122B, 122C and 122D and the fourth group of copper wiring patterns 124A, 124B, 124C and 124D through buildup layers L1-L3. Ceramic capacitor 108 can be connected to copper path 114A through copper wiring patterns 116A_1, 116A_2 and 116A_3. Ceramic capacitor 108 can also be connected to copper path 114B through copper wiring patterns 116B_1, 116B_2 and 116B_3. The ceramic capacitor 110 may be connected to the copper wiring patterns 118E and 118F and the copper wiring patterns 120E and 120F through the buildup layers L7 and L8. The semiconductor package 100 may further include additional copper wiring patterns 124E and 124F for various other connections.

[0047] The dielectric thickness and core layer thickness of the semiconductor package 100 may be specified as follows in Table 1. As shown in Table 1, the core layer 102 may be two layers (eg, L4 and L5).

[0048] Table 1

[0049] layer thickness L1 20-45μm L2 20-45μm L3 20-45μm L4 / L5 100-800μm L6 20-45μm L7 20-45μm L8 20-45μm

[0050] The copper layer thickness of the flat portion of the copper wiring pattern can be specified as one of C1-C3 and C6-C8. The flat portion of the copper wiring pattern can be perpendicular to the protruding portion of the copper wiring pattern. For example, thickness C1 can correspond to the copper layer thickness of the flat portion of copper wiring patterns 116A_1, 116B_1, 116C_1, 116D_1, 118A, 120A, 122A and 124A. Thickness C2 can correspond to the copper layer thickness of the flat portion of copper wiring patterns 116A_2, 116B_2, 116C_2, 116D_2, 118B, 120B, 122B and 124B. Thickness C3 can correspond to the copper layer thickness of the flat portion of copper wiring patterns 116A_3, 116B_3, 116C_3, 116D_3, 118C, 120C, 122C and 124C. Thickness C6 may correspond to the copper layer thickness of the flat portions of copper wiring patterns 116A_4, 116B_4, 116C_4, and 116D_4. Thickness C7 may correspond to the copper layer thickness of the flat portions of copper wiring patterns 116A_5, 116B_5, 116C_5, 116D_5, 118B, 120E, and 124E. Thickness C8 may correspond to the copper layer thickness of the flat portions of copper wiring patterns 116A_6, 116B_6, 116C_6, 116D_6, 118F, 120F, and 124F.

[0051] Thicknesses C4 and C5 may correspond to the thickness of the top planar portion and the bottom planar portion of each of copper vias 114A-114D, respectively. Copper layer thicknesses C1-C8 may be specified in Table 2 as follows.

[0052] Table 2

[0053] layer thickness C1 10-25μm C2 10-25μm C3 10-25μm C4 25-45μm C5 25-45μm C6 10-25μm C7 10-25μm C8 10-25μm

[0054] Currently, ceramic capacitors are embedded in the core layer due to thickness limitations. For example, ceramic capacitors generally have a thickness that is typically greater than 100 μm, and therefore are generally not included in the buildup layer. Embedding ceramic capacitors in the core layer requires additional manufacturing processes and has only a few applications due to manufacturing costs. Although it is possible to perform a process to embed ceramic capacitors in the buildup layer, this type of process requires removing multiple buildup layers to create space for the ceramic capacitor to be embedded, which is very complex and significantly increases manufacturing costs.

[0055] Figure 22 is an illustration of a process 200 of forming a semiconductor package having an ISC embedded in a buildup layer according to an embodiment of the present disclosure. In operation 200A, a core layer 202 may be formed. The core layer 202 may be a CCL layer. In one or more examples, the core layer 202 may be drilled via mechanical drilling to form through-holes, which may be filled with copper to form copper vias 204A, 204B, 204C, and 204D. The copper vias 204A-204D may be connected to the semiconductor package 204A, 204B, 204C, and 204D, respectively. Figure 1 Furthermore, in one or more examples, a copper wiring pattern 206 can be formed on the core layer 202 .

[0056] In operation 200B, one or more ISCs may be formed on the copper wiring pattern 206. For example, Figure 2 As shown in FIG. 2 , ISCs 208A and 208B are formed on the copper wiring pattern 206. Figure 2 As shown in FIG. 2 , the back surface of each of the ISCs 208A and 208B is in direct contact with the top surface of the copper wiring pattern 206. Therefore, an electrical connection can be established between the copper wiring pattern 206 and each of the ISCs 208A and 208B.

[0057] In operation 200C, a buildup layer may be formed on the core layer such that one or more ISCs are embedded in the buildup layer. Figure 2 As shown in FIG. 2 , buildup layer 210 is formed on core layer 202 such that ISC 208A and ISC 208B are embedded in buildup layer 210. Buildup layer 210 may be formed by, for example, a film lamination process.

[0058] Figure 3 yes Figure 2 , which is a schematic illustration of a buildup layer 210 in which an ISC 208A and at least a portion of a copper wiring pattern 206 are embedded in the buildup layer 210. In one or more examples, the thickness of the ISC 208A can be equal to or substantially equal to (e.g., within ±5%) the thickness of the copper wiring pattern 206. For example, Figure 3 As shown in FIG. 1 , each of the ISC 208A and the copper wiring pattern 206 has a thickness of 15 μm. In one or more examples, the thickness of the buildup layer 210 is greater than the combined thickness of the copper wiring pattern 206 and the ISC 208A. Figure 3 As shown in FIG. 2 , the thickness of the buildup layer 210 is 40 μm. As understood by those skilled in the art, the thickness of the ISC 208A and the thickness of the copper wiring pattern 206 may be different from each other.

[0059] In operation 200D, copper wiring patterns 212A and 212B may be formed. The copper wiring patterns 212A and 212B may be formed by, for example, laser drilling to form vias through the buildup layer 210. The vias may be filled with copper to establish electrical connections with the copper vias 204A-204D, the copper wiring patterns 206, and / or the ISCs 208A and 208B.

[0060] Figure 4 is an illustration of a process 400 of forming a semiconductor package having an ISC embedded in a buildup layer according to an embodiment of the present disclosure.

[0061] In operation 400A, core layer 202 may be formed. Core layer 202 may be formed in operation 200A ( Figure 2 ) is the same as or corresponds to the core layer 202 formed in the embodiment of the present invention. The copper vias 204A-204D may be respectively Figure 1 The copper vias 104A-104D in FIG.

[0062] In operation 400B, ISCs such as ISCs 208A and 208B may be formed on core layer 202, which may be respectively connected to Figure 2 ISC 208A and 208B are the same or corresponding. Figure 2 200 in the process, the process 400 forms ISCs 208A and 208B directly on the top surface of the core layer 202 so that the back surfaces of the ISCs 208A and 208B are in direct contact with the top surface of the core layer 202. In operation 400B, a copper wiring pattern including a copper wiring pattern 406 may be formed.

[0063] In operation 400C, a buildup layer may be formed in a manner similar to that described above for operation 200C. For example, Figure 4 The stacking layer 210 in Figure 2 The stacking layer 210 in is the same or corresponding.

[0064] Figure 5 According to the embodiments of the present disclosure Figure 4 , which is a schematic illustration of a buildup layer 210 having an ISC 208B and a copper wiring pattern 406 embedded in the buildup layer 210. In one or more examples, the thickness of the ISC 208B can be equal to or substantially equal to (e.g., within ±5%) the thickness of the copper wiring pattern 406. For example, Figure 5 As shown in FIG. 4 , the thickness of each of the ISC 208B and the copper wiring pattern 406 is 10 μm. In one or more examples, the thickness of the buildup layer 210 is greater than the thickness of each of the copper wiring pattern 406 and the ISC 208B. Figure 5As shown in FIG. 4 , the thickness of the buildup layer 210 is 20 μm. As will be appreciated by those skilled in the art, the thickness of the ISC 208B and the thickness of the copper wiring pattern 406 may be different from each other.

[0065] In operation 400D, copper wiring patterns 212A and 212B may be formed in a manner similar to that described above with respect to operation 200D.

[0066] Figure 6 is a schematic illustration of a semiconductor package 600 having one or more ISCs embedded in one or more buildup layers according to an embodiment of the present disclosure. The semiconductor package 600 may be incorporated into a semiconductor device such as an electronic device (e.g., a handheld device, a computer, a tablet computer, etc.). The semiconductor device may include a printed circuit board (PCB) including the semiconductor package 600 and one or more integrated circuits coupled to the semiconductor package 600.

[0067] Semiconductor package 600 may be a 3-2-3 structure having two core layers 202 and six build-up layers, resulting in a total of eight layers. Figure 6 As shown in , layers L4 and L5 constitute core layer 202, layers L1-L3 constitute buildup layers above core layer 202, and layers L6-L8 constitute buildup layers below core layer 202. Semiconductor package 600 may include silicon backplane 602 as a base structure. Although not indicated by the reference numerals, semiconductor package 600 may also include the same copper vias 114A-114D and copper wiring patterns 116A_1-116A_6, 116B_1-116B_6, 116C_1-116C_6, 116D_1-116D_6, 118A-118F, 120A-120F, 122A-122F, and 124A-124F. A repeated description thereof is omitted here.

[0068] The semiconductor package 600 may include ISCs 208A and 208B embedded in the buildup layer L3 and ISCs 208C and 208D embedded in the buildup layer L8. The ISCs 208A-208D may be formed on a copper wiring pattern and embedded in the buildup layer according to the process 200 ( Figure 2 ) is formed. In addition, Figure 6 As shown in , semiconductor package 600 may include additional ISC 208E and ceramic capacitor 110 formed outside the buildup layer. The dielectric thickness of the layers for semiconductor package 600 may be according to Table 1. The copper layer thickness of the layers for semiconductor package 600 may be according to Table 2.

[0069] According to one or more embodiments, an ISC may be in the form of a vertical cylindrical array including multiple capacitive paths between two or more connection terminals and have a very low profile (e.g., about 2.0×2.0×2.0 μm), while a DSC or LSC (which may be a multilayer ceramic capacitor (MLCC)) has dimensions of hundreds of microns (μm), e.g., about 1.0×0.5×0.35 mm for a 0402 MLCC. An ISC may have a high capacitance density similar to that of an MLCC. For example, an ISC may have a capacitance of hundreds of nF / mm 2 Capacitance value, for example 1100nF / mm 2 .

[0070] The semiconductor package 600 takes advantage of the thickness of the ISC of about 2 μm. In one or more examples, with the silicon backplane 602 as the base structure, the ISC thickness can be between 2 μm and 700 μm. In the case where the thickness of the ISC is less than the dielectric thickness (e.g., the thickness of the buildup layer), the ISC can be advantageously placed at any buildup layer without the need for a complex process to remove the dielectric material. The ISC can also be placed at the surface layer as a DSC component or an LSC component according to SMT processes known to those of ordinary skill in the art. In one or more examples, no additional Capex investment is required. In one or more examples, the ISC thickness can be designed to match the thickness of a copper wiring pattern embedded in the same buildup layer as the ISC. In one or more examples, the ISC can also be modified to have more than two terminals, which improves the circuit design and advantageously reduces the substrate footprint.

[0071] Figure 7 is a schematic illustration of a semiconductor package 700 having one or more ISCs embedded in one or more layers according to an embodiment of the present disclosure. Semiconductor package 700 may be the same or similar to semiconductor package 600, except that ceramic capacitor 110 is replaced by ISC 208F. Therefore, a repeated description thereof is omitted herein. The dielectric thickness of the layers for semiconductor package 700 may be according to Table 1. The copper layer thickness of the layers for semiconductor package 700 may be according to Table 2.

[0072] Figure 8 is a schematic illustration of a stacked layer having an ISC and a copper layer embedded therein, the stacked layer having one or more terminal contacts according to an embodiment of the present disclosure. Figure 8 As shown in FIG. 1 , ISC 208A may be electrically connected to terminal contacts 800A, 800B, and 800C. Terminal contacts 800A-800C may be formed by, for example, laser drilling to form vias in buildup layer 210. The vias may be filled with copper to form terminal contacts 800A-800C. Figure 8 Three terminal contacts are shown in FIG, but as one of ordinary skill in the art understands, the ISC 208A may be electrically connected to more than three terminal contacts. The terminal contacts may be made of copper and may be referred to as copper terminal contacts.

[0073] As will be appreciated by those of ordinary skill in the art, dielectric thickness uniformity is a relevant issue for high end substrates. In this regard, as substrate sizes continue to grow and dielectric layers continue to become thinner, the thickness uniformity issue becomes increasingly challenging. Specifically, there are disadvantages in the mechanism by which dielectric materials melt and flow during the lamination process. As will be appreciated by those of ordinary skill in the art, areas with high copper density (e.g., copper planes) tend to retain more material, while at low copper density areas, dielectric material tends to flow away, resulting in lower dielectric thickness. High copper density (e.g., continuous copper planes) is preferred, but is not possible due to design / electrical requirements. In addition, another issue with copper density non-uniformity is the resulting substrate warpage. In one or more examples, a non-active ISC can be used as a mechanical filler to help increase pseudo copper density, thereby improving dielectric thickness uniformity and helping to mitigate substrate warpage.

[0074] Fig. 9 is a schematic illustration of a stacked layer with active ISCs and non-active ISCs according to an embodiment of the present disclosure. Fig. 9 As shown in FIG. 1 , semiconductor package 900A has a buildup layer 902 having a non-uniform dielectric thickness. Semiconductor package 900B includes a buildup layer 904 having one or more non-active ISCs 906 to achieve dielectric thickness uniformity. In one or more examples, a semiconductor package may include both active ISCs and non-active ISCs to achieve dielectric thickness uniformity. For example, semiconductor package 900C includes a buildup layer 908 having at least one active ISC 910 and at least one non-active ISC 912. Fig. 9 As shown in , semiconductor package 900C includes a uniform dielectric thickness. In one or more examples, a non-active ISC can be placed simultaneously with an active ISC. In one or more examples, the process 200 ( Figure 2 ) or process 400( Figure 4 ) forms a non-active ISC. As will be appreciated by those of ordinary skill in the art, a non-active ISC may be an ISC that is not configured to store or distribute electrical energy.

[0075] Fig.10 1 is a flow chart of a process 1000 for forming a semiconductor package having an ISC embedded in a buildup layer. The process 1000 may be used to form a semiconductor package 600 ( Figure 6 ) or semiconductor package 700( Figure 7 ).

[0076] The process may begin at operation S1002, where a core layer is formed. For example, the core layer may be formed according to operation 200A ( Figure 2 ) or 400A( Figure 4 )form.

[0077] The process may proceed to operation S1004, where an ISC is formed on the core layer. For example, ISCs 208A and 208B may be formed according to operation 200B ( Figure 2 ) or 400B( Figure 4 ) is formed on the core layer 202.

[0078] The process may proceed to operation S1006, where one or more buildup layers are formed on the core layer. For example, buildup layer 210 may be formed according to operation 200C ( Figure 2 ) or 400C( Figure 4 ) is formed on the core layer 202, wherein ISCs 208A and 208B are embedded therein.

[0079] The process may proceed to operation S1008, where one or more metal layers are formed on the core layer. For example, the one or more metal layers may include the one or more metal layers according to operation 200D ( Figure 2 ) copper wiring patterns 212A and 212B formed on the core layer 202. In another example, one or more metal layers may include the copper wiring patterns 212A and 212B formed on the core layer 202 according to operation 400D ( Figure 4 )Copper wiring 406 formed on the core layer 202.

[0080] Fig.11 The present invention at least includes Figure 6 or Figure 7 Schematic diagram of an electronic device with a semiconductor package shown in FIG.

[0081] Reference Fig.11 The electronic device 1100 may include a printed circuit board (PCB) or a motherboard 1110 on which a plurality of semiconductor packages 1111 - 1115 are mounted. The electronic device 1100 may also include a plurality of other components 1120 .

[0082] Semiconductor package 1111 may include a SoC, which may include at least one of a CPU, a GPU, an AI module, a modem, one or more memory units, a power management unit, etc. to control the overall operation of electronic device 1100. Other semiconductor packages 1112-1115 may include memory chips, various other processor chips, communication chips, and interface chips, respectively. The communication chip included in semiconductor package 1114 may be configured to also perform wireless or wired communication functions associated with the SoC. At least one of semiconductor packages 1111-1115 may be composed of Figure 6 or Figure 7 This is achieved by using the semiconductor package shown in .

[0083] Other components 1120 included in the electronic device 100 may include a storage device, a camera module, a speaker, a microphone, a display, a battery, etc. The storage device may be configured to store user data. The storage device may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS) device, etc. The display may be implemented to display data processed by the SoC and / or receive data through a touch screen panel of the display.

[0084] The foregoing is a description of exemplary embodiments and should not be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above-described embodiments without materially departing from the present disclosure.

[0085] Embodiments of the present disclosure provide significant advantageous features, including space savings, performance improvements (e.g., electrical and mechanical properties), manufacturing yield improvements, etc. In one or more examples, embodiments of the present disclosure provide space savings for substrate surface area by embedding ISCs in a buildup layer (compared to ceramic capacitors that can only be placed on the surface as DSC components or LSC components).

[0086] Embodiments of the present disclosure may result in improved electrical performance. For example, ISCs provide better electrical performance (eg, higher capacitance density) than ceramic capacitors on the surface.

[0087] Embodiments of the present disclosure may result in a simplified packaging / assembly process (eg, capacitors are already placed during the substrate manufacturing process), where no additional component placement is required during assembly.

[0088] Embodiments of the present disclosure can produce a semiconductor package or electronic device that is more mechanically robust. For example, embodiments of the present disclosure do not require solder joints, thereby eliminating the risk of cracking of solder joints. ISC to copper trace connections can be formed by normal copper plating processes, thereby eliminating the soldering process used in DSC processes or LSC processes (which also require cleaning or defluxing processes). Therefore, compared to ordinary DSC or LSC using SMT processes involving solder and chemical cleaning, the embedded ISC according to embodiments of the present disclosure is more environmentally friendly.

[0089] Embodiments of the present disclosure can eliminate the risk of contamination due to overflow of flux or bottom fill material. Bottom fill material (e.g., epoxy material) may be required after silicon attachment, and the bottom fill material may overflow to contaminate the DSC components around the silicon chip. Very strict design rules and process control are required to avoid these disadvantages. By using an embedded ISC according to an embodiment of the present disclosure, surface components (e.g., DSC) are no longer required, thereby eliminating the need to use bottom fill.

[0090] Embodiments of the present disclosure may enable electrical testing to be performed at the substrate level, rather than waiting after the die / components are all attached. Conventionally, DSC testing or LSC testing is performed after assembly, with expensive silicon already attached to the semiconductor package. As a result, conventional DSC testing and LSC testing are more expensive than testing performed for embodiments of the present disclosure.

[0091] Embodiments of the present disclosure may enable ISC to be used as a filler to balance copper density.

[0092] Embodiments of the present disclosure may result in a reduced surface area, resulting in advantageous space savings. In addition, multiple ISCs may be placed in the same layer.

[0093] Embodiments of the present disclosure may yield electrical benefits with the ISC closer to the silicon.

[0094] Embodiments of the present disclosure can result in improved yields because embedding ISCs into buildup layers can be performed inside a substrate manufacturing facility, which is cleaner than an assembly plant (e.g., better particle control). As a result, failures caused by foreign matter are reduced, thereby improving product quality and reliability.

[0095] Embodiments of the present disclosure may produce more feasible multi-terminal components with greater compatibility with substrate manufacturing processes (eg, using laser drilling to form connections to the ISC), resulting in more compact designs and advantageous space savings on the substrate.

[0096] Embodiments of the present disclosure may provide a significantly advantageous feature of matching the thickness of an ISC with the thickness of a copper wiring pattern embedded in the same buildup layer as the ISC. As a result, the ISC may be used as a filler (e.g., dummy silicon) in areas of a semiconductor package where it is not possible to form or place copper, thereby improving the mechanical strength of the semiconductor package and also improving dielectric thickness uniformity.

[0097] Embodiments of the present disclosure may result in reduced substrate thickness. For example, conventional semiconductor packages with ceramic capacitors require a 500 μm thick core to allow the capacitor to be embedded in the core layer. In contrast, if the ISC is embedded in the buildup layer, embodiments of the present disclosure have a core thickness of approximately 50 μm.

[0098] Embodiments have been described above, and as shown in the accompanying drawings, embodiments have been shown in the form of blocks (which perform the described function or functions). These blocks can be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc., and can also be implemented or driven by software and / or firmware (configured to perform the functions or operations described herein). The circuit can be embodied in one or more semiconductor chips, for example, or on a substrate support such as a printed circuit board. The circuit included in the block can be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the block and a processor that performs other functions of the block. Each block of the embodiment can be physically divided into two or more interactive and discrete blocks. Similarly, the blocks of the embodiment can be physically combined into more complex blocks.

[0099] Although embodiments of the present disclosure are described with respect to copper, this metal is merely an example. As will be appreciated by those of ordinary skill in the art, embodiments of the present disclosure may replace copper with other suitable materials such as aluminum (Al), tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), molybdenum (Mo), and ruthenium (Ru).

[0100] Although the present disclosure has described several non-limiting embodiments, there are changes, permutations, and various substitute equivalents that fall within the scope of the present disclosure. Therefore, it will be appreciated that those skilled in the art will be able to design many systems and methods that, although not explicitly shown or described herein, embody the principles of the present disclosure and are therefore within the spirit and scope of the present disclosure.

[0101] The above disclosure also covers the following embodiments:

[0102] (1) A method of forming a semiconductor package, comprising: forming a core layer; forming a capacitor on the core layer; forming one or more buildup layers on the core layer, wherein the capacitor is embedded in the one or more buildup layers; and forming one or more metal layers on the core layer.

[0103] (2) A method according to feature (1), wherein forming the one or more metal layers includes: forming at least one metal layer in contact with a surface of the core layer, wherein a capacitor is formed on the at least one metal layer so that the capacitor is in contact with the at least one metal layer.

[0104] (3) The method according to feature (2), wherein forming the one or more buildup layers includes: forming at least one buildup layer covering the ISC and the at least one metal layer after forming the capacitor.

[0105] (4) The method according to feature (3), wherein a thickness of the capacitor is substantially equal to a thickness of the at least one metal layer.

[0106] (5) The method according to feature (4), wherein a thickness of the at least one buildup layer is greater than a thickness of the capacitor.

[0107] (6) The method according to feature (4), wherein a thickness of the at least one buildup layer is greater than a combination of a thickness of the capacitor and a thickness of the at least one metal layer.

[0108] (7) The method according to feature (1), wherein the capacitor is in contact with a surface of the core layer.

[0109] (8) The method according to feature (7), wherein forming the one or more metal layers includes: forming at least one metal layer in contact with a surface of the core layer.

[0110] (9) The method according to feature (8), wherein forming the one or more buildup layers includes: forming at least one buildup layer covering the capacitor and the at least one metal layer.

[0111] (10) A method according to feature (9), wherein the thickness of the capacitor is substantially equal to the thickness of the at least one metal layer, and wherein the thickness of the at least one buildup layer is greater than the thickness of the capacitor.

[0112] (11) A method according to any one of features (1) to (10), wherein forming the one or more metal layers includes: forming N metal contacts on the capacitor, where N is a positive integer greater than or equal to 3.

[0113] (12) A method according to any one of features (1) to (11), wherein forming the one or more stacking layers includes: forming a first stacking layer in contact with the core layer; and forming a second stacking layer on the first stacking layer, wherein the capacitor is formed on the first stacking layer before forming the second stacking layer.

[0114] (13) A method according to any one of features (1) to (12), wherein the capacitor is an active capacitor, wherein the method further comprises: forming a non-active capacitor included in the same stacking layer as the active capacitor from the one or more stacking layers.

[0115] (14) A method according to any one of features (1) to (13), wherein the one or more metal layers include a metal selected from the group consisting of copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), molybdenum (Mo) and ruthenium (Ru).

[0116] (15) A semiconductor package comprising: a core layer; a capacitor on the core layer; one or more buildup layers on the core layer, wherein the capacitor is embedded in the one or more buildup layers; and one or more metal layers on the core layer.

[0117] (16) A semiconductor package according to feature (15), wherein the one or more metal layers include at least one metal layer in contact with a surface of the core layer, wherein a capacitor is formed on the at least one metal layer such that the capacitor is in contact with the metal layer.

[0118] (17) The semiconductor package according to feature (16), wherein the one or more buildup layers include: at least one buildup layer covering the capacitor and the at least one metal layer.

[0119] (18) The semiconductor package according to feature (17), wherein a thickness of the capacitor is substantially equal to a thickness of the at least one metal layer.

[0120] (19) A semiconductor package according to feature (18), wherein a thickness of the at least one buildup layer is greater than a combination of a thickness of the capacitor and a thickness of the at least one metal layer.

[0121] (20) The semiconductor package according to feature (15), wherein the capacitor is in contact with a surface of the core layer.

[0122] (21) The semiconductor package according to feature (1), wherein the capacitor is an integrated stack capacitor (ISC).

[0123] (22) A semiconductor package according to feature (11), wherein the capacitor is an integrated stack capacitor (ISC).

[0124] This application is based on and claims priority from U.S. Provisional Application No. 63 / 524,758 filed in the U.S. Patent and Trademark Office on July 3, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising: Core layer; a capacitor on the core layer; one or more buildup layers on the core layer, wherein the capacitor is embedded in the one or more buildup layers; as well as One or more metal layers on the core layer.

2. The semiconductor package according to claim 1, wherein the one or more metal layers include at least one metal layer in contact with a surface of the core layer, and Wherein the capacitor is in contact with the at least one metal layer. 3 . The semiconductor package of claim 2 , wherein the one or more build-up layers include at least one build-up layer covering the capacitor and the at least one metal layer. 4 . The semiconductor package of claim 2 , wherein a thickness of the capacitor is substantially equal to a thickness of the at least one metal layer. 5 . The semiconductor package of claim 3 , wherein a thickness of the at least one buildup layer is greater than a thickness of the capacitor. 6 . The semiconductor package of claim 4 , wherein a thickness of the at least one buildup layer is greater than a combination of the thickness of the capacitor and the thickness of the at least one metal layer.

7. The semiconductor package according to claim 1, further comprising: N metal contacts provided on the capacitor, Wherein N is a positive integer greater than or equal to 3.

8. The semiconductor package according to claim 1, wherein the one or more build-up layers include a first build-up layer in contact with the core layer and a second build-up layer on the first build-up layer, The capacitor is disposed on the first buildup layer before the second buildup layer is formed.

9. The semiconductor package of claim 1 , wherein the capacitor is an active capacitor, and wherein the semiconductor package further comprises: A non-active capacitor is included in a same buildup layer from the one or more buildup layers as the active capacitor.

10. The semiconductor package of claim 1, wherein the one or more metal layers include a metal selected from the group consisting of copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), molybdenum (Mo), and ruthenium (Ru).

11. A semiconductor package, comprising: Core layer; a capacitor in contact with the surface of the core layer; one or more buildup layers on the core layer, wherein the capacitor is embedded in the one or more buildup layers; as well as One or more metal layers on the core layer. 12 . The semiconductor package of claim 11 , wherein the one or more metal layers include at least one metal layer in contact with the surface of the core layer. 13 . The semiconductor package of claim 12 , wherein the one or more build-up layers include at least one build-up layer covering the capacitor and the at least one metal layer.

14. The semiconductor package of claim 13, wherein a thickness of the capacitor is substantially equal to a thickness of the at least one metal layer, and The thickness of the at least one buildup layer is greater than the thickness of the capacitor.

15. The semiconductor package according to claim 11, further comprising: N metal contacts provided on the capacitor, Wherein N is a positive integer greater than or equal to 3.

16. The semiconductor package according to claim 11, wherein the one or more build-up layers include a first build-up layer in contact with the core layer and a second build-up layer on the first build-up layer, The capacitor is disposed on the first buildup layer before the second buildup layer is formed.

17. The semiconductor package of claim 11, wherein the capacitor is an active capacitor, and wherein the semiconductor package further comprises: A non-active capacitor is included in a same buildup layer from the one or more buildup layers as the active capacitor.

18. The semiconductor package of claim 11, wherein the one or more metal layers include a metal selected from the group consisting of copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), molybdenum (Mo), and ruthenium (Ru).

19. A semiconductor device comprising: Semiconductor packaging, including: Core layer, Capacitors, one or more build-up layers on the core layer, wherein the capacitor is embedded in the one or more build-up layers, and one or more metal layers on the core layer; and One or more integrated circuits (ICs) are coupled to the semiconductor package.

20. The semiconductor device of claim 19, wherein the capacitor is an integrated stack capacitor (ISC).

Images