Signal processing circuit and method, chip and electronic equipment
By using clock domain conversion, sampling and logic processing modules in the cross-clock domain signal processing circuit, the reset signal of the first clock domain is used to synchronize the cross-clock domain signal, the signal error update problem caused by resetting the clock domain module at different times is solved, and the signal error update problem is realized. Accuracy and consistency of signal processing.
Patent Information
- Application Number
- CN202411137980.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-01-03
AI Technical Summary
When two modules across the clock domain perform reset operations, the reset signal is not valid at the same time, resulting in errors in the cross-clock domain signal, which in turn leads to errors in the module function.
A signal processing circuit is designed, including a clock domain conversion module, a sampling module and a logic processing module, and processes the first signal through the reset signal and the clock signal of the first clock domain, outputs the signal for sampling in the second clock domain, and performs the N-level sampling and logic operations ensure that the same reset signal is used to operate cross-clock domain signal processing when resetting modules in different clock domains.
It solves the problem that cross-clock domain signals are prone to error updates when resetting the clock domain module at different times, ensuring the accuracy and consistency of signal processing.
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Figure CN119254196A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular to a signal processing circuit, method, chip and electronic device. Background Art
[0002] When performing a reset operation on two different modules across clock domains, a pulse signal needs to be transmitted across clock domains. The pulse signal is controlled by the reset signals of the two modules for cross-clock domain processing. When the reset signals of the two modules are not valid at the same time, it is easy for the different reset signals in different clock domains to cause errors in the pulse signal across clock domains, thereby causing module function errors. For example, when resetting the first module and the second module across clock domains, one possible situation is that the reset signal of the first module has changed from a valid state to an invalid state, while the reset signal of the second module is still in a valid state. In this way, when the pulse signal is processed across clock domains between the first module and the second module, it is easy for the pulse signal transmitted to the second module to be incorrectly updated due to the failure of the reset signal of the first module, thereby causing module function errors. Summary of the invention
[0003] In view of the above problems, the embodiments of the present application provide a signal processing circuit, method, chip and electronic device to solve the above technical problems.
[0004] In a first aspect, an embodiment of the present application provides a signal processing circuit, including:
[0005] A clock domain conversion module, configured to process a first signal belonging to the first clock domain according to a reset signal of the first clock domain and a clock signal of the first clock domain, and output a second signal for sampling by the second clock domain;
[0006] a sampling module, configured to perform N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and output a third signal and a fourth signal, wherein the third signal is a sampling signal obtained by sampling at the N-1th level, the fourth signal is a sampling signal obtained by sampling at the Nth level, and the third signal and the fourth signal belong to the second clock domain;
[0007] A logic processing module is used to perform a logic operation on the third signal and the fourth signal, and output a fifth signal belonging to the second clock domain.
[0008] In a second aspect, an embodiment of the present application further provides a signal processing method, including:
[0009] Processing a first signal belonging to the first clock domain according to a reset signal of the first clock domain and a clock signal of the first clock domain, and outputting a second signal for sampling by the second clock domain;
[0010] Performing N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and outputting a third signal and a fourth signal, wherein the third signal is a sampling signal obtained by sampling at the N-1th level, the fourth signal is a sampling signal obtained by sampling at the Nth level, and the third signal and the fourth signal belong to the second clock domain;
[0011] A logic operation is performed on the third signal and the fourth signal, and a fifth signal belonging to the second clock domain is output.
[0012] In a third aspect, an embodiment of the present application further provides a chip, comprising a signal processing circuit according to the second aspect above.
[0013] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising the chip of the third aspect mentioned above.
[0014] The signal processing circuit, method, chip and electronic device provided in the embodiment of the present application are as follows: the signal processing circuit processes the first signal belonging to the first clock domain according to the reset signal of the first clock domain and the clock signal of the first clock domain, and outputs the second signal for sampling by the second clock domain; performs N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and outputs the third signal and the fourth signal belonging to the second clock domain; performs logical operation on the third signal and the fourth signal, and outputs the fifth signal belonging to the second clock domain. The embodiment of the present application obtains the second signal, the third signal and the fourth signal respectively according to the reset signal of the first clock domain, so that when two modules in different clock domains are reset, the same reset signal is always used to act on the processing of the cross-clock domain signal, which solves the technical problem that when the modules in different clock domains are reset, the cross-clock domain signal is prone to erroneous update because the reset signals of different clock domains are not valid at the same time.
[0015] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 The cross-clock domain circuit module provided by the embodiment of the present application is shown.
[0018] Figure 2A schematic diagram of the structure of a traditional signal processing circuit is shown.
[0019] Figure 3 An abnormal timing diagram of a conventional signal processing circuit is shown.
[0020] Figure 4 A module schematic diagram of a signal processing circuit provided in an embodiment of the present application is shown.
[0021] Figure 5 A timing diagram of a signal processing circuit provided in an embodiment of the present application is shown.
[0022] Figure 6 A schematic diagram of the structure of a signal processing circuit provided in an embodiment of the present application is shown.
[0023] Figure 7 A flow chart of a signal processing method provided in an embodiment of the present application is shown.
[0024] Figure 8 A schematic diagram of a chip provided in an embodiment of the present application is shown.
[0025] Fig. 9 A schematic diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0026] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0027] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.
[0028] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0029] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.
[0030] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.
[0031] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0032] When performing a reset operation on different modules across clock domains, because the module reset signals of each clock domain are different, and the module reset signals of each clock domain are used to control the processing of the same cross-clock domain signal, it is easy to cause the reset signals of different modules in different clock domains to be not valid at the same time, resulting in erroneous updates of the cross-clock domain signal, thereby causing module function errors. For example, Figure 1 The cross-clock domain circuit module provided by the embodiment of the present application is shown. Figure 1 The cross-clock domain circuit module shown is used as an example to illustrate the problems of traditional cross-clock domain signal processing.
[0033] like Figure 1 As shown, the first module and the second module are two modules across clock domains, wherein signal transmission between the first module and the second module needs to be synchronized through a CDC module (clock domain crossing), and data of the first module and the second module are accessed through an asynchronous FIFO memory (First Input First Output).
[0034] Next, taking the first module as a state machine and the second module as a register as an example, the following describes the possible problems that may occur when the pulse signal generated by the state machine crosses the clock domain when the state machine is reset. Figure 2 shows a schematic diagram of the structure of a conventional signal processing circuit, Figure 3 shows an abnormal timing diagram of a conventional signal processing circuit, such as Figure 1-Figure 3 As shown, assuming that when the first module (state machine) is reset, a pulse signal flag_pos (the pulse signal flag_pos is a cross-clock domain signal) generated by the first module is to be transmitted to the second module (register). Optionally, the pulse signal flag_pos can be a reset flag pulse. Because the first module (clock domain is clk_fsm) is reset, the reset signal rst_fsm_n is pulled high, so the trigger FF1 is valid. Because the second module (clock domain is clk_reg) is reset, the reset signal rst_reg_n is pulled high, so the triggers FF2 to FF4 are valid. The selector selection end receives the pulse signal generated by the first module. The pulse signal flag_pos is selected, and a preset level signal (high level or low level) is output to the trigger FF1. The level signal is widened by the trigger FF1 to output the level signal asyn_tog. The triggers FF2 to FF4 sample the level signal asyn_tog in the clock domain (clk_reg) of the second module, and output the level signal asyn1, the level signal asyn2 and the level signal asyn3 respectively. The XOR logic gate performs an XOR logic operation on the level signal asyn2 and the level signal asyn3 to output the pulse signal flag_pos_syn to the first module. However, if Figure 3 As shown, after the first module (clock domain is clk_fsm) is reset, its reset signal rst_fsm_n is invalid and correspondingly pulled low. Because the reset signal rst_fsm_n is pulled low, the trigger FF1 under the clock domain (clk_fsm) of the first module will fail, that is, the level signal asyn_tog output by the trigger FF1 will generate a falling edge signal, that is, the falling edge signal is not caused by the cross-clock domain signal flag_pos, but the falling edge signal causes the trigger FF2, trigger FF3, and trigger FF4 under the clock domain (clk_reg) of the second module to continue to process the falling edge signal at the output end of the trigger FF1, which ultimately causes the second module to receive two pulse signals flag_pos_syn, namely the normal pulse signal flag_pos_syn caused by the cross-clock domain signal flag_pos, and the abnormal pulse signal flag_pos_syn caused by the failure of the reset signal rst_fsm_n.
[0035] With respect to the above technical problems, relevant technologies have not yet proposed effective solutions.
[0036] The present application embodiment provides a signal processing circuit. Figure 4 A schematic diagram of a module of a signal processing circuit provided in an embodiment of the present application is shown. Figure 4 As shown, the signal processing circuit includes:
[0037] The clock domain conversion module 100 is used to process a first signal belonging to the first clock domain according to a reset signal of the first clock domain and a clock signal of the first clock domain, and output a second signal that can be sampled by the second clock domain.
[0038] The sampling module 200 is used to perform N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and output a third signal and a fourth signal belonging to the second clock domain, wherein the third signal is a sampling signal obtained by the N-1th level sampling, and the fourth signal is a sampling signal obtained by the Nth level sampling.
[0039] The logic processing module 300 is used to perform logic operation on the third signal and the fourth signal, and output a fifth signal belonging to the second clock domain.
[0040] In some embodiments, the signal processing circuit provided by the embodiments of the present application is applied to Figure 1 In the cross-clock domain circuit module shown, specifically, the signal processing circuit provided in the embodiment of the present application is arranged in the CDC module. Next, taking the first module as a state machine and the second module as a register as an example, the principle of the signal processing circuit provided in the embodiment of the present application is explained. Figure 5 1 shows a timing diagram of a signal processing circuit provided in an embodiment of the present application, such as Figure 5 As shown, the clock domain conversion module processes the first signal flag_pos belonging to the first clock domain clk_fsm to convert it into a second signal asyn_tog that can be sampled by the second clock domain, the sampling module performs three-level sampling on the second signal asyn_tog to obtain a primary sampling signal asyn1, a secondary sampling signal asyn2 (i.e., the third signal), and a tertiary sampling signal asyn3 (i.e., the fourth signal) belonging to the second clock domain clk_reg, and the logic processing module performs logic processing on the third signal asyn2 and the fourth signal asyn3 to obtain a fifth signal flag_pos_sys belonging to the second clock domain. In the embodiment of the present application, the reset signal rst_fsm_n of the first clock domain of the first module is always used to obtain the second signal asyn_tog, the third signal asyn2 and the fourth signal asyn3 belonging to the second clock domain of the second module. Therefore, the second signal asyn_tog, the third signal asyn2 and the fourth signal asyn3 are always synchronized with the state of the reset signal rst_fsm_n of the first clock domain. The second signal asyn_tog will not generate redundant falling edge pulses due to the fact that the reset signals of different modules are not valid at the same time, resulting in the second signal asyn_tog, the third signal asyn2 and the fourth signal asyn3 being out of synchronization, thereby causing the second module to receive two fifth signals flag_pos_sys.
[0041] It is understandable that the embodiment of the present application provides a signal processing circuit for processing pulse signals transmitted across clock domains when different modules are reset, that is, in the embodiment of the present application, the first signal is a pulse signal, and the fifth signal is also a pulse signal. Because the pulse signal cannot be sampled, the embodiment of the present application needs to process the pulse signal to obtain a level signal that can be sampled (the level signal includes the second signal, the third signal, the fourth signal, and the signal output by each level of sampling). Take the first module as a state machine and the second module as a register as an example. For example, when the state machine is reset, the state machine needs to synchronize the timeout interrupt pulse generated inside it to the register. At this time, the timeout interrupt pulse generated by the state machine is the first signal, and the fifth signal obtained by processing the timeout interrupt pulse generated by the state machine through the signal processing circuit provided in the embodiment of the present application is the pulse signal received by the register.
[0042] It can be understood that the above embodiment only illustrates the third-level sampling of the second signal generated by the first signal to obtain the fifth signal. In fact, the embodiment of the present application provides a signal processing circuit, and the number of sampling levels is determined based on the frequency difference between the two clock domains and the sampling capacity of each level. That is, technicians in the relevant field can control the number of sampling levels based on circuit cost when designing the circuit.
[0043] It can be understood that the above embodiments are only used to illustrate the signal processing circuit provided by the embodiments of the present application by taking the first module as a state machine and the second module as a register as examples, and it does not mean that the embodiments of the present application can only be applied between the state machine and the register.
[0044] The signal processing circuit provided in the embodiment of the present application always uses the reset signal of the first clock domain to respectively obtain the second signal, the third signal and the fourth signal, so that when the modules in different clock domains are reset, the same reset signal is always used to act on the processing of cross-clock domain signals, thereby solving the technical problem that when the modules in different clock domains are reset, the cross-clock domain signals are prone to erroneous updates because the reset signals of different clock domains do not effectively act on the same cross-clock domain signals at the same time, which leads to the cross-clock domain signals being easily updated.
[0045] In some embodiments, Figure 6 FIG. 4 shows a schematic diagram of the structure of a signal processing circuit provided in an embodiment of the present application. Figure 6 As shown, the clock domain conversion module 100 includes a selection unit 110 and a first trigger unit 120 .
[0046] The selection unit 110 has a selection end for receiving a first signal, two input ends for receiving a preset first level and a second level, and an output end of the selection unit connected to a first trigger unit for selecting and outputting a first level or a second level according to the first signal. Figure 1In the cross-clock domain circuit module shown, the first signal is a pulse signal output by the first module, and the first level and the second level are respectively a high level and a low level.
[0047] It can be understood that the embodiments of the present application do not limit the sources of the first level and the second level, as long as the first level and the second level belong to the same clock domain as the first signal. For example, the first level and the second level can be provided by the first module. For example, the first level and the second level can also be provided by other modules in the same clock domain as the first module.
[0048] The first trigger unit 110, the clock end of the first trigger unit is used to receive the clock signal of the first clock domain, the set end of the first trigger unit is used to receive the reset signal of the first clock domain, the data input end of the first trigger unit is used to receive the first signal, and the data output end of the first trigger unit is connected to the sampling module. Specifically, the first trigger unit 110 is used to perform pulse stretching processing on the first level or the second level output by the selection unit, so as to obtain a second signal that can be sampled by the second clock domain.
[0049] In some embodiments, Figure 6 As shown, the sampling module 200 includes:
[0050] N-level trigger units 210, the clock ends of the N-level trigger units are all used to receive the clock signal of the second clock domain, the set ends of the N-level trigger units are all used to receive the reset signal of the first clock domain, and in the N-level trigger units, the data input end of the latter-level trigger unit is connected to the data output end of the previous-level trigger unit, N≥3. Among them, the data input end of the first-level trigger unit is connected to the synchronization module, the data output end of the N-1-level trigger unit is connected to the logic processing module, and the data output end of the N-level trigger unit is connected to the logic processing module. Optionally, after the first-level sampling of the second signal, there may be a metastable problem due to crossing the clock domain, so the second signal should also be sampled at least twice and three times, so that the sampling results of the two-level sampling and the sampling results of the three-level sampling can be logically operated. Among them, the sampling level of the second signal should be determined according to the frequency difference between the two clock domains and the sampling capacity of each level, so in the embodiment of the present application, the sampling level should be no less than three levels.
[0051] In the embodiment of the present application, multi-stage sampling of the second signal is achieved by cascading multiple trigger units.
[0052] In some embodiments, Figure 6 As shown, the logic processing module 300 includes:
[0053] XOR logic unit 310, the input end of the XOR logic unit is connected to the sampling module, and is used to receive the third signal and the fourth signal, and the output end is used to output the fifth signal. Optionally, the XOR logic unit is used to perform a logical XOR operation on the third signal and the fourth signal to generate the fifth signal. Optionally, the embodiment of the present application is applied to Figure 1 In the cross-clock domain circuit module shown, the fifth signal is the pulse signal to be received by the second module, that is, the pulse signal output by the first module is processed by the clock domain synchronization module, the sampling module and the logic processing module and transmitted to the second module.
[0054] In some embodiments, Figure 6 As shown, in the embodiment of the present application, a D flip-flop is used as each flip-flop unit.
[0055] The signal processing circuit provided in the embodiment of the present application is applied to Figure 1 The cross-clock domain circuit module shown in FIG. 1 is specifically applied to the embodiment of the present application. Figure 1 The CDC module in the cross-clock domain circuit module shown is used to process the cross-clock domain signal between the first module and the second module. Next, the embodiment of the present application is described by transmitting the cross-clock domain signal from the first module to the second module. Figure 6 As shown, in the signal processing circuit provided by the embodiment of the present application, the selector receives a pulse signal output by the first module, and the pulse signal is the first signal. The selector selects to output the first level or the second level according to the pulse signal received. The first trigger performs pulse widening processing on the first level and the second level output by the selector to obtain a level signal, i.e., the second signal. Next, the second signal is multi-level sampled through an N-level trigger, and the fourth signal (level signal) obtained by the N-th level sampling and the third signal (level signal) obtained by the N-1-th level sampling are XOR-ed to obtain the pulse signal required by the second module, i.e., the fifth signal.
[0056] The signal processing circuit provided in the embodiment of the present application obtains the second signal, the third signal and the fourth signal respectively according to the reset signal of the first clock domain, so that when the modules in different clock domains are reset, the same reset signal is always used to act on the processing of the cross-clock domain signal, thereby solving the technical problem that when the modules in different clock domains are reset, the cross-clock domain signal is prone to erroneous update because the reset signals of different clock domains do not effectively act on the same cross-clock domain signal at the same time, which causes the cross-clock domain signal to be easily updated.
[0057] The present application also provides a signal processing method. Figure 7 A flow chart of a signal processing method provided by an embodiment of the present application is shown. Figure 7 As shown, the method includes:
[0058] Step S1: Process a first signal belonging to the first clock domain according to a reset signal of the first clock domain and a clock signal of the first clock domain, and output a second signal that can be sampled by the second clock domain. Optionally, the first signal is a pulse signal belonging to the first clock domain, and the embodiment of the present application converts the first signal into a level signal, i.e., the second signal, through the reset signal of the first clock domain and the clock signal of the first clock domain.
[0059] In some embodiments, the embodiments of the present application select to output a preset level signal of high level or low level according to the first signal, and then perform stretching processing on the level signal belonging to the first clock domain, thereby outputting a second signal that can be sampled by the second clock domain.
[0060] Step S2: Perform N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and output a third signal and a fourth signal belonging to the second clock domain, where the third signal is a sampling signal obtained by the N-1th level sampling, and the fourth signal is a sampling signal obtained by the Nth level sampling.
[0061] Step S3: performing a logic operation on the third signal and the fourth signal, and outputting a fifth signal belonging to the second clock domain.
[0062] In some embodiments, the signal processing method provided by the embodiments of the present application is applied to Figure 1 In the cross-clock domain circuit module shown in the figure, the traditional signal processing scheme is as follows Figure 2 and Figure 3As shown, because the reset signal clk_fsm_n of the first module (clock domain is clk_fsm) is pulled low, and the reset signal clk_reg_n of the second module (clock domain is clk_reg) is still at a high level, the level signal asyn_tog output by the trigger FF1 is immediately pulled low, and the trigger FF2, the trigger FF3 and the trigger FF4 will continue to perform three-level sampling on the low-level signal asyn_tog to obtain the low-level signal asyn1, the low-level signal asyn2 and the low-level signal asyn3 in turn, which eventually leads to the abnormal pulse signal flag_pos_syn. In the signal processing method provided in the embodiment of the present application, trigger FF1, trigger FF2, trigger FF3 and trigger FF4 all use the reset signal clk_fsm_n (i.e., the reset signal of the first clock domain) of the first module (clock domain is clk_fsm, i.e., the clock signal of the first clock domain). Therefore, when the reset signal clk_fsm_n of the first module is pulled low, the trigger FF1, trigger FF2, trigger FF3 and trigger FF4 are all invalid, that is, the level signal asyn_tog (i.e., the second signal), level signal asyn1, level signal asyn2 (i.e., the third signal) and level signal asyn3 (i.e., the fourth signal) output by the trigger FF1, trigger FF2, trigger FF3 and trigger FF4 will also be immediately pulled low, so that the abnormal pulse signal flag_pos_syn (i.e., the fifth signal) will not appear.
[0063] The signal processing method provided in the embodiment of the present application obtains the second signal, the third signal and the fourth signal respectively according to the reset signal of the first clock domain, so that when the modules in different clock domains are reset, the same reset signal is always used to act on the processing of the cross-clock domain signal, which solves the technical problem that when the modules in different clock domains are reset, the cross-clock domain signal is prone to erroneous update because the reset signals of different clock domains do not effectively act on the same cross-clock domain signal at the same time, resulting in the cross-clock domain signal being easily updated.
[0064] In some embodiments, in the signal processing method provided in the embodiment of the present application, in step S2: performing N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and outputting the third signal and the fourth signal belonging to the second clock domain, N≥3. Optionally, after the first-level sampling of the second signal, there may be a metastable problem due to crossing the clock domain, so the second signal should also be sampled at least twice and three times, so that logical operations can be performed on the sampling results of the second-level sampling and the sampling results of the three-level sampling. Among them, the sampling level of the second signal should be determined according to the frequency difference between the two clock domains and the sampling capacity of each level. Therefore, in the embodiment of the present application, the sampling level should be no less than three.
[0065] In some embodiments, in the signal processing method provided by the embodiments of the present application, step S3: performing a logical operation on the third signal and the fourth signal, and outputting a fifth signal belonging to the second clock domain, the logical operation is a logical XOR, so as to XOR the third signal and the fourth signal to output a pulse signal identical to the first signal, i.e., the fifth signal.
[0066] The embodiment of the present application also provides a chip, Figure 8 A schematic diagram of a chip provided in an embodiment of the present application is shown, such as Figure 8 As shown, the chip 800 includes the above-mentioned signal processing circuit. The chip (Integrated Circuit, IC) is also called a chip. The chip can be but is not limited to a SOC (System on Chip) chip or a SIP (system in package) chip.
[0067] The present application also provides an electronic device, Fig. 9 A schematic diagram of an electronic device provided by an embodiment of the present application is shown. Fig. 9 As shown, the electronic device includes a device body 90 and a chip 800 as described above, which is arranged in the device body 90. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.
[0068] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A signal processing circuit, characterized in that: include: A clock domain conversion module, configured to process a first signal belonging to the first clock domain according to a reset signal of the first clock domain and a clock signal of the first clock domain, and output a second signal for sampling by the second clock domain; a sampling module, configured to perform N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and output a third signal and a fourth signal, wherein the third signal is a sampling signal obtained by sampling at the N-1th level, the fourth signal is a sampling signal obtained by sampling at the Nth level, and the third signal and the fourth signal belong to the second clock domain; A logic processing module is used to perform a logic operation on the third signal and the fourth signal, and output a fifth signal belonging to the second clock domain.
2. The signal processing circuit according to claim 1, characterized in that The clock domain conversion module includes a selection unit and a first trigger unit. The selection end of the selection unit is used to receive the first signal, the first input end of the selection unit is used to receive a preset first level, the second input end of the selection unit is used to receive a preset second level, and the output end of the selection unit is connected to the first trigger unit, and is used to select and output the first level or the second level according to the first signal; The clock end of the first trigger unit is used to receive the clock signal of the first clock domain, the set end of the first trigger unit is used to receive the reset signal of the first clock domain, the data input end of the first trigger unit is connected to the selection unit, and the data output end of the first trigger unit is connected to the sampling module.
3. The signal processing circuit according to claim 1, characterized in that: The sampling module comprises: N-stage trigger units, wherein the clock terminals of the N-stage trigger units are all used to receive the clock signal of the second clock domain, the set terminals of the N-stage trigger units are all used to receive the reset signal of the first clock domain, and in the N-stage trigger units, the data input terminal of the next-stage trigger unit is connected to the data output terminal of the previous-stage trigger unit, and N≥3; Among them, the data input end of the first-level trigger unit is connected to the clock domain conversion module, and the data output end of the N-1-th level trigger unit and the data output end of the N-th level trigger unit are respectively connected to the logic processing module.
4. The signal processing circuit according to claim 1, characterized in that: The logic processing module includes: An XOR logic unit, wherein an input end of the XOR logic unit is connected to the sampling module and is used to receive the third signal and the fourth signal, and an output end of the XOR logic unit is used to output the fifth signal.
5. The signal processing circuit according to any one of claims 2 to 3, characterized in that: Each of the trigger units is a D trigger.
6. A signal processing method, characterized in that: include: Processing a first signal belonging to the first clock domain according to a reset signal of the first clock domain and a clock signal of the first clock domain, and outputting a second signal for sampling by the second clock domain; Performing N-level sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain, and outputting a third signal and a fourth signal, wherein the third signal is a sampling signal obtained by sampling at the N-1th level, the fourth signal is a sampling signal obtained by sampling at the Nth level, and the third signal and the fourth signal belong to the second clock domain; A logic operation is performed on the third signal and the fourth signal, and a fifth signal belonging to the second clock domain is output.
7. The signal processing method according to claim 6, characterized in that: In the step of performing N-stage sampling on the second signal according to the reset signal of the first clock domain and the clock signal of the second clock domain to output the third signal and the fourth signal, N≥3.
8. The signal processing method according to claim 6, characterized in that: In the step of performing a logic operation on the third signal and the fourth signal to output a fifth signal belonging to the second clock domain, the logic operation is a logical exclusive OR.
9. A chip, characterized in that: The signal processing circuit comprises any one of claims 1 to 5.
10. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 9 arranged in the device body.