Reset circuit and chip

Abstract

The present disclosure provides a reset circuit and a chip. The reset circuit includes a power-on reset circuit, an undervoltage reset circuit and a drive output circuit; the power-on reset circuit includes a resistor voltage divider module, a power supply voltage threshold detection module, a switch module and a power-on reset latch circuit, the undervoltage reset circuit includes a transmission tube voltage divider module, an undervoltage threshold detection module and a clamp module, and the power-on reset circuit and the undervoltage reset circuit are both connected to the drive output circuit; the power-on reset circuit is used to detect the power supply voltage and generate a power-on reset signal, which is sent to the drive output circuit; the undervoltage reset circuit is used to detect the power supply voltage and generate an undervoltage reset signal, which is sent to the drive output circuit; the drive output circuit is used to output a target reset drive signal according to the power-on reset signal and the undervoltage reset signal, so as to drive the chip to enter a reset state or exit a reset state. The present disclosure can independently and accurately adjust the power-on reset voltage and the undervoltage reset voltage, thereby ensuring the robustness of the chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a reset circuit and a chip. Background Art

[0002] To ensure that the integrated circuit works stably and reliably, the reset circuit is an essential part. Among all the reset functions, power-on reset and undervoltage reset are high-priority global resets. The power supply of the integrated circuit must be stable within a constant voltage range for the integrated circuit to work properly. If the voltage is too low, the analog circuit of the chip will not work properly, and the circuit that generates the clock will not work properly, so that it cannot generate a clock that meets the requirements, which will cause the digital circuit inside the chip to not work properly.

[0003] The purpose of power-on reset is to detect the power supply inside the chip during the power-on phase. When the power supply voltage (VDD / VCC) is lower than a specific voltage value, the chip is kept in a reset state. When the power supply voltage is higher than the preset voltage value, the reset signal is released to enable the chip to work normally. Similarly, the purpose of undervoltage reset is to detect the power supply voltage when the system is powered off normally or abnormally. When the power supply voltage drops below the preset voltage value, the reset is initiated to prevent the chip from entering an abnormal working state and protect the chip.

[0004] Some existing reset circuits only have a power-on reset function but no undervoltage reset function, and are unable to perform undervoltage detection; while existing reset circuits that include both a power-on reset function and an undervoltage reset function cannot achieve precise adjustment of the power-on reset voltage and the undervoltage reset voltage, resulting in the yield and reliability of the chip being unable to be guaranteed. Summary of the invention

[0005] The technical problem to be solved by the present disclosure is to overcome the defect in the prior art that it is impossible to accurately adjust the power-on reset voltage and the undervoltage reset voltage in the reset circuit, resulting in the inability to ensure chip yield and reliability, and to provide a reset circuit and chip that can accurately adjust the power-on reset voltage and the undervoltage reset voltage to improve the robustness of the product.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] According to a first aspect of the present disclosure, a reset circuit is provided, the reset circuit comprising a power-on reset circuit, an undervoltage reset circuit and a drive output circuit;

[0008] The power-on reset circuit comprises a resistor voltage divider module, a switch module, a power supply voltage threshold detection module and a power-on reset latch circuit, wherein the resistor voltage divider module, the power supply voltage threshold detection module, the switch module and the power-on reset latch circuit are connected in sequence, and the output end of the power-on reset latch circuit is respectively connected to the switch module and the drive output circuit;

[0009] The undervoltage reset circuit includes a transmission tube voltage divider module, an undervoltage threshold detection module and a clamp module, the output end of the transmission tube voltage divider module is respectively connected to the input end of the undervoltage threshold detection module and the output end of the clamp module, the output end of the clamp module is connected to the input end of the undervoltage threshold detection module, and the output end of the undervoltage threshold detection module is respectively connected to the input end of the power-on reset latch circuit and the drive output circuit;

[0010] The power-on reset circuit is used to detect the power supply voltage and generate a power-on reset signal, and send the power-on reset signal to the drive output circuit;

[0011] The undervoltage reset circuit is used to detect the power supply voltage and generate an undervoltage reset signal, and send the undervoltage reset signal to the drive output circuit;

[0012] The drive output circuit is used to output a target reset drive signal according to the power-on reset signal and the undervoltage reset signal, so as to drive the chip to enter a reset state or exit a reset state.

[0013] Preferably, the drive output circuit comprises a first NOR gate and a first inverter, and the output end of the first NOR gate is connected to the first inverter;

[0014] The first input terminal of the first NOR gate is connected to the output terminal of the power-on reset latch circuit;

[0015] The second input terminal of the first NOR gate is connected to the output terminal of the undervoltage threshold detection module;

[0016] The output end of the first NOR gate and the input end of the first inverter are respectively connected to the resistance voltage divider module.

[0017] Preferably, the undervoltage reset circuit further includes a level conversion module;

[0018] The output end of the undervoltage threshold detection module is connected to the input end of the level conversion module, and the output end of the level conversion module is connected to the second input end of the first NOR gate and the input end of the power-on reset latch circuit;

[0019] The level conversion module is used for converting the undervoltage reset signal of a non-full-swing amplitude into the undervoltage reset signal of a full-swing amplitude.

[0020] Preferably, the clamping module includes a first PMOS (P-Channel-Oxide-Semiconductor) tube, and the undervoltage threshold detection module includes a second PMOS tube and a first NMOS (N-Metal-Oxide-Semiconductor) tube;

[0021] The first PMOS tube includes a first source, a first drain and a first gate;

[0022] The second PMOS tube includes a second source, a second drain and a second gate;

[0023] The first NMOS tube includes a third source, a third drain and a third gate;

[0024] The first source is connected to the power supply voltage, and the first gate and the first drain are both connected to the transmission tube voltage divider module, the second gate, the third gate, and the level conversion module;

[0025] The second source is connected to the transmission tube voltage divider module, the second drain and the third drain are both connected to the level conversion module, and the third source is grounded.

[0026] Preferably, the level conversion module includes a third PMOS tube, a fourth PMOS tube, a second NMOS tube and a third NMOS tube;

[0027] The third PMOS tube includes a fourth source, a fourth drain and a fourth gate;

[0028] The fourth PMOS tube includes a fifth source, a fifth drain and a fifth gate;

[0029] The second NMOS tube includes a sixth source, a sixth drain and a sixth gate;

[0030] The third NMOS tube includes a seventh source, a seventh drain and a seventh gate;

[0031] The fourth source and the fifth source are both connected to the power supply voltage;

[0032] The fourth drain, the fifth gate and the sixth drain are connected;

[0033] The sixth gate is connected to the second drain and the third drain;

[0034] The fourth gate, the fifth drain, and the seventh drain are connected to the input end of the power-on reset latch circuit and the second input end of the first NOR gate;

[0035] The seventh gate is connected to the first gate, the first drain, the second gate, the third gate, and the transmission tube voltage divider module;

[0036] The sixth source and the seventh source are grounded.

[0037] Preferably, the power supply voltage threshold detection module includes a push-pull reverse amplifier, and the switch module includes a fourth NMOS tube;

[0038] The fourth NMOS tube includes an eighth source, an eighth drain and an eighth gate;

[0039] The input end of the push-pull reverse amplifier is connected to the resistance voltage divider module, and the output end of the push-pull reverse amplifier is connected to the eighth source;

[0040] The eighth drain is connected to the input end of the power-on reset latch circuit, and the eighth gate is connected to the output end of the power-on reset latch circuit.

[0041] Preferably, the power-on reset latch circuit includes a second NOR gate, a second inverter, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first capacitor and a second capacitor;

[0042] The fifth NMOS tube includes a ninth source, a ninth drain and a ninth gate;

[0043] The fifth PMOS tube includes a tenth source, a tenth drain and a tenth gate;

[0044] The sixth PMOS tube includes an eleventh source, an eleventh drain and an eleventh gate;

[0045] The sixth NMOS tube includes a twelfth source, a twelfth drain and a twelfth gate;

[0046] The seventh NMOS tube includes a thirteenth source, a thirteenth drain and a thirteenth gate;

[0047] The ninth drain is connected to the eighth drain, one end of the first capacitor, the tenth gate, and the twelfth gate; the ninth gate is connected to the output end of the second NOR gate and the input end of the second inverter, and the ninth source is grounded;

[0048] The tenth source and the eleventh source are both connected to the power supply voltage; the tenth drain, the eleventh gate, the twelfth drain, and the thirteenth gate are connected to each other; the eleventh drain and the thirteenth drain are connected to the first input end of the first NOR gate, the first input end of the second NOR gate, and one end of the second capacitor; the twelfth source and the thirteenth source are grounded;

[0049] The other end of the first capacitor and the other end of the second capacitor are both connected to the power supply voltage;

[0050] The second input end of the second NOR gate is connected to the output end of the undervoltage threshold detection module and the second input end of the first NOR gate respectively; the output end of the second NOR gate is connected to the input end of the second inverter, and the output end of the second inverter is connected to the eighth gate.

[0051] Preferably, the power-on reset circuit further comprises a buffer shaping circuit, and the buffer shaping circuit is composed of a third inverter and a fourth inverter;

[0052] The output terminal of the third inverter is connected to the input terminal of the fourth inverter;

[0053] The input end of the third inverter is connected to the eleventh drain, the thirteenth drain, and one end of the second capacitor respectively;

[0054] An output terminal of the fourth inverter is connected to a first input terminal of the first NOR gate.

[0055] Preferably, the resistor voltage-dividing module comprises a seventh PMOS tube, a first voltage-dividing resistor and a second voltage-dividing resistor;

[0056] The seventh PMOS tube includes a fourteenth source, a fourteenth drain and a fourteenth gate;

[0057] The fourteenth source is connected to the power supply voltage, and the fourteenth gate is respectively connected to the output end of the first NOR gate and the input end of the first inverter;

[0058] One end of the first voltage-dividing resistor is connected to the fourteenth drain, and the other end of the first voltage-dividing resistor and one end of the second voltage-dividing resistor are both connected to the power supply voltage threshold detection module;

[0059] The other end of the second voltage-dividing resistor is grounded;

[0060] and / or,

[0061] The transmission tube voltage-dividing module includes an eighth PMOS tube, a third voltage-dividing resistor and a fourth voltage-dividing resistor;

[0062] The eighth PMOS tube includes a fifteenth source, a fifteenth drain and a fifteenth gate;

[0063] One end of the third voltage-dividing resistor is connected to the power supply voltage, and the other end of the third voltage-dividing resistor is respectively connected to the fifteenth source electrode, the undervoltage threshold detection module, and the clamping module;

[0064] The fifteenth drain electrode is respectively connected to one end of the fourth voltage-dividing resistor and the undervoltage threshold detection module;

[0065] The other end of the fourth voltage-dividing resistor and the fifteenth gate are both grounded.

[0066] According to a second aspect of the present disclosure, a chip is provided, wherein the chip includes the reset circuit described in the first aspect of the present disclosure.

[0067] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0068] The positive progressive effect of the present disclosure is that the power-on reset signal path and the undervoltage reset path are divided into two independent signal paths, which can independently and accurately adjust the power-on reset voltage and the undervoltage reset voltage, ensure the precise adjustment of the power-on reset voltage and the undervoltage reset voltage, ensure the robustness of the chip, and then effectively improve the yield and reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 is a first circuit schematic diagram of the reset circuit disclosed in the present invention;

[0070] Figure 2 is a second circuit schematic diagram of the reset circuit disclosed in the present invention;

[0071] Figure 3 is a third circuit schematic diagram of the reset circuit disclosed in the present invention;

[0072] Figure 4 is a fourth circuit schematic diagram of the reset circuit disclosed in the present invention;

[0073] Figure 5 is a fifth circuit schematic diagram of the reset circuit disclosed in the present invention;

[0074] Figure 6 is a sixth circuit diagram of the reset circuit disclosed in the present invention;

[0075] Figure 7 is a seventh circuit schematic diagram of the reset circuit disclosed in the present invention;

[0076] Figure 8 is an eighth circuit diagram of the reset circuit disclosed in the present invention;

[0077] Fig. 9 is a ninth circuit schematic diagram of the reset circuit disclosed in the present invention;

[0078] Fig.10 is a tenth circuit schematic diagram of the reset circuit disclosed in the present invention;

[0079] Fig.11 The figure is a simulation result of the reset circuit disclosed in the present invention. DETAILED DESCRIPTION

[0080] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0081] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0082] Example 1

[0083] In a specific embodiment of the present disclosure, a reset circuit is provided, such as Figure 1 As shown, the reset circuit includes a power-on reset circuit 1, an undervoltage reset circuit 2 and a drive output circuit 3;

[0084] The power-on reset circuit 1 comprises a resistor voltage divider module 11, a power supply voltage threshold detection module 12, a switch module 13 and a power-on reset latch circuit 14, wherein the resistor voltage divider module 11, the power supply voltage threshold detection module 12, the switch module 13 and the power-on reset latch circuit 14 are connected in sequence, and the output end of the power-on reset latch circuit 14 is respectively connected to the switch module 13 and the drive output circuit 3;

[0085] The undervoltage reset circuit 2 includes a transmission tube voltage divider module 21, an undervoltage threshold detection module 23 and a clamp module 22. The output end of the transmission tube voltage divider module 21 is respectively connected to the input end of the undervoltage threshold detection module 23 and the output end of the clamp module 22. The output end of the clamp module 22 is connected to the input end of the undervoltage threshold detection module 23. The output end of the undervoltage threshold detection module 23 is respectively connected to the input end of the power-on reset latch circuit 14 and the drive output circuit 3.

[0086] The power-on reset circuit 1 is used to detect the power supply voltage and generate a power-on reset signal, and send the power-on reset signal to the drive output circuit 3;

[0087] The undervoltage reset circuit 2 is used to detect the power supply voltage and generate an undervoltage reset signal, and send the undervoltage reset signal to the drive output circuit 3;

[0088] The drive output circuit 3 is used to output a target reset drive signal according to the power-on reset signal and the undervoltage reset signal, so as to drive the chip to enter a reset state or exit a reset state.

[0089] Specifically, the resistor voltage divider module 11 in the power-on reset circuit 1 generates a first voltage-divided signal of the power supply voltage VDD under the drive of the enable signal, and the first voltage-divided signal is transmitted to the power supply voltage threshold detection module 12. The power supply voltage threshold detection module 12 compares the first voltage-divided signal with the first threshold voltage in the power-on stage to determine whether the first voltage-divided signal reaches the flip point, and generates a power-on reset signal POR_UP and sends it to the drive output circuit 3 via the switch module 13 and the power-on reset latch circuit 14. Among them, when the first voltage-divided signal is lower than the first threshold voltage, POR_UP is pulled high, and the output POR_UP is 1, indicating that the power-on reset operation is performed; when the first voltage-divided signal is higher than the first threshold voltage, POR_UP is pulled low, and the output POR_UP is 0, indicating that the power-on reset operation is not performed, and the power-on reset latch circuit 14 drives the switch module 13 to disconnect according to POR_UP to latch POR_UP.

[0090] The transmission tube voltage divider module 21 in the undervoltage reset circuit 2 will continuously track VDD, and generate a second voltage divider signal of VDD to transmit to the undervoltage threshold detection module 23. The undervoltage threshold detection module 23 compares the second voltage divider signal with the second threshold voltage to determine whether the second voltage divider signal is lower than the second threshold voltage, and generates an undervoltage reset signal BOR to send to the drive output circuit 3 and the power-on reset latch circuit 14. Among them, when the second voltage divider signal is higher than the second threshold voltage, BOR is pulled low, and the output BOR is 0, indicating that the undervoltage reset operation is not performed; when the second voltage divider signal is lower than the second threshold voltage, BOR is pulled high, and the output BOR is 1, indicating that the undervoltage reset operation is performed, and the power-on reset latch circuit 14 drives the switch module 13 to close according to the BOR, and enables the power-on reset circuit 1 to enter the power-on voltage detection stage.

[0091] The drive output circuit 3 outputs the corresponding target reset drive signal POR_BOR by performing logical operations on POR_UP and BOR. When any one of the signals POR_UP and BOR is pulled high, POR_BOR will also be pulled high, and the drive chip enters the reset state. When both POR_UP and BOR are pulled low, POR_BOR will also be pulled low, and the drive chip exits the reset state.

[0092] In order to ensure that the chip works more safely and reliably, the flip point (second threshold voltage) of the undervoltage reset circuit 2 is lower than the flip point (first threshold voltage) of the power-on reset circuit 1. For example, the second threshold voltage is about 100mV lower than the first threshold voltage.

[0093] This specific implementation method divides the power-on reset signal path and the undervoltage reset path into two independent signal paths, which can independently and accurately adjust the power-on reset voltage and the undervoltage reset voltage, ensure the precise adjustment of the power-on reset voltage and the undervoltage reset voltage, protect the robustness of the chip, and effectively improve the yield and reliability of the chip.

[0094] In a specific embodiment, Figure 2 As shown, the drive output circuit 3 includes a first NOR gate nor1 and a first inverter inv1, and the output end of the first NOR gate nor1 is connected to the first inverter inv1;

[0095] A first input terminal of the first NOR gate nor1 is connected to an output terminal of the power-on reset latch circuit 14;

[0096] The second input terminal of the first NOR gate nor1 is connected to the output terminal of the undervoltage threshold detection module 23;

[0097] The output end of the first NOR gate nor1 and the input end of the first inverter inv1 are connected to the resistance voltage dividing module 11 respectively.

[0098] Specifically, a first NOR gate nor1 and a first inverter inv1 are set in the drive output circuit 3, and POR_UP and BOR are respectively connected through the two input ends of the first NOR gate nor1, and a logic operation is performed, and the operation result is input to the first inverter inv1 to drive the chip to enter or exit the reset state.

[0099] At the same time, the output end of the first NOR gate nor1 is connected to the resistor voltage divider module 11. When POR_BOR output by the first NOR gate nor1 is pulled low, the resistor voltage divider module 11 is driven to stop working and enter the standby state, thereby achieving zero power consumption of the power-on reset circuit 1 in the standby state.

[0100] In a specific embodiment, Figure 3 As shown, the undervoltage reset circuit 2 further includes a level conversion module 24;

[0101] The output end of the undervoltage threshold detection module 23 is connected to the input end of the level conversion module 24, and the output end of the level conversion module 24 is connected to the second input end of the first NOR gate nor1 and the input end of the power-on reset latch circuit 14;

[0102] The level conversion module 24 is used for converting a non-full-swing undervoltage reset signal into a full-swing undervoltage reset signal.

[0103] Specifically, when VDD drops to a specific value, the second voltage division signal generated by the transmission tube voltage division module 21 generates a non-full-swing detection voltage through the undervoltage threshold detection module 23, and is converted into a full-swing BOR signal by setting the level conversion module 24 to pull up the POR_BOR signal and enter the undervoltage reset state. The full-swing BOR signal is transmitted to the power-on reset latch circuit 14 to drive the switch module 13 to close, and the power-on reset circuit 1 is enabled to enter the power-on voltage detection stage.

[0104] In a specific embodiment, Figure 4 As shown, the clamping module 22 includes a first PMOS tube P1, and the undervoltage threshold detection module 23 includes a second PMOS tube P2 and a first NMOS tube N1;

[0105] The first PMOS transistor P1 includes a first source, a first drain and a first gate;

[0106] The second PMOS transistor P2 includes a second source, a second drain and a second gate;

[0107] The first NMOS transistor N1 includes a third source, a third drain and a third gate;

[0108] The first source is connected to the power supply voltage, and the first gate and the first drain are both connected to the transmission tube voltage divider module, the second gate, the third gate, and the level conversion module;

[0109] The second source is connected to the transmission tube voltage divider module, the second drain and the third drain are both connected to the level conversion module, and the third source is grounded.

[0110] Specifically, the power-on reset circuit 1 in this specific embodiment has zero power consumption in the standby state. In order to meet the under-voltage detection function and ensure sufficiently small standby power consumption, a clamping module 22 composed of a MOS (metal oxide semiconductor field effect transistor) diode is provided in the under-voltage reset circuit 2. For example, a long-channel PMOS diode can be used to ensure that the under-voltage reset circuit 2 does not generate a large current to the ground.

[0111] In a specific embodiment, Figure 5 As shown, the level conversion module includes a third PMOS tube P3, a fourth PMOS tube P4, a second NMOS tube N2 and a third NMOS tube N3;

[0112] The third PMOS transistor P3 includes a fourth source, a fourth drain and a fourth gate; the fourth PMOS transistor P4 includes a fifth source, a fifth drain and a fifth gate; the second NMOS transistor N2 includes a sixth source, a sixth drain and a sixth gate; the third NMOS transistor N3 includes a seventh source, a seventh drain and a seventh gate;

[0113] The fourth source and the fifth source are both connected to the power supply voltage; the fourth drain, the fifth gate and the sixth drain are connected; the sixth gate is connected to the second drain and the third drain; the fourth gate, the fifth drain and the seventh drain are connected to the input end of the power-on reset latch circuit 14 and the second input end of the first NOR gate nor1; the seventh gate is connected to the first gate, the first drain, the second gate, the third gate and the transmission tube voltage divider module 21; the sixth source and the seventh source are grounded.

[0114] In a specific embodiment, Figure 6 As shown, the power supply voltage threshold detection module 12 includes a push-pull reverse amplifier AMP, and the switch module 13 includes a fourth NMOS tube N4;

[0115] The fourth NMOS tube N4 includes an eighth source, an eighth drain and an eighth gate;

[0116] The input end of the push-pull reverse amplifier AMP is connected to the resistor voltage divider module 11, and the output end of the push-pull reverse amplifier AMP is connected to the eighth source; the eighth drain is connected to the input end of the power-on reset latch circuit 14, and the eighth gate is connected to the output end of the power-on reset latch circuit 14. The push-pull reverse amplifier AMP is used to detect the sampling voltage of the power supply voltage VDD, and compare it with the flip threshold (first threshold voltage) of the push-pull reverse amplifier AMP to determine whether the power supply voltage reaches the minimum safe working voltage.

[0117] In a specific embodiment, Figure 7 As shown, the power-on reset latch circuit 14 includes a second NOR gate nor2, a second inverter inv2, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first capacitor C1 and a second capacitor C2;

[0118] The fifth NMOS tube N5 includes a ninth source, a ninth drain and a ninth gate; the fifth PMOS tube P5 includes a tenth source, a tenth drain and a tenth gate; the sixth PMOS tube P6 includes an eleventh source, an eleventh drain and an eleventh gate; the sixth NMOS tube N6 includes a twelfth source, a twelfth drain and a twelfth gate; the seventh NMOS tube N7 includes a thirteenth source, a thirteenth drain and a thirteenth gate;

[0119] The ninth drain is connected to the eighth drain, one end of the first capacitor C1, the tenth gate, and the twelfth gate; the ninth gate is connected to the output end of the second NOR gate nor2 and the input end of the second inverter inv2, and the ninth source is grounded;

[0120] The tenth source and the eleventh source are both connected to the power supply voltage; the tenth drain, the eleventh gate, the twelfth drain, and the thirteenth gate are connected to each other; the eleventh drain and the thirteenth drain are connected to the first input terminal of the first NOR gate nor1, the first input terminal of the second NOR gate nor2, and one end of the second capacitor C2; the twelfth source and the thirteenth source are grounded;

[0121] The other end of the first capacitor C1 and the other end of the second capacitor C2 are both connected to the power supply voltage; the first capacitor C1 and the second capacitor C2 are respectively used to couple the power supply voltage in the power-on stage to initialize the internal nodes of the power-on reset latch circuit 14.

[0122] The second input end of the second NOR gate nor2 is respectively connected to the output end of the undervoltage threshold detection module 23 and the second input end of the first NOR gate nor1; the output end of the second NOR gate nor2 is connected to the input end of the second inverter inv2, and the output end of the second inverter inv2 is connected to the eighth gate.

[0123] In a specific embodiment, Figure 8 As shown, the power-on reset circuit 1 further includes a buffer shaping circuit 15, and the buffer shaping circuit 15 is composed of a third inverter inv3 and a fourth inverter inv4;

[0124] An output terminal of the third inverter inv3 is connected to an input terminal of the fourth inverter inv4;

[0125] An input end of the third inverter inv3 is connected to the eleventh drain, the thirteenth drain, and one end of the second capacitor C2 respectively;

[0126] An output terminal of the fourth inverter inv4 is connected to a first input terminal of the first NOR gate nor1 .

[0127] Specifically, in order to protect various components in the circuit and ensure that the drive output circuit obtains a signal with a smaller conversion time to avoid generating a large switching short-circuit current during the level conversion, a buffer shaping circuit 15 is arranged between the drive output circuit 3 and the second capacitor C2 to achieve isolation between the drive output circuit 3 and the second capacitor C2.

[0128] In a specific embodiment, Fig. 9 As shown, the resistor voltage-dividing module 11 includes a seventh PMOS transistor P7, a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2;

[0129] The seventh PMOS tube P7 includes a fourteenth source, a fourteenth drain and a fourteenth gate;

[0130] The fourteenth source is connected to the power supply voltage, and the fourteenth gate is respectively connected to the output end of the first NOR gate nor1 and the input end of the first inverter inv1; one end of the first voltage-dividing resistor R1 is connected to the fourteenth drain, and the other end of the first voltage-dividing resistor R1 and one end of the second voltage-dividing resistor R2 are both connected to the power supply voltage threshold detection module 12; the other end of the second voltage-dividing resistor R2 is grounded.

[0131] The seventh PMOS tube is used to control the on and off of the resistor voltage divider module 11 .

[0132] The transmission tube voltage dividing module 21 includes an eighth PMOS tube P8, a third voltage dividing resistor R3 and a fourth voltage dividing resistor R4;

[0133] The eighth PMOS tube P8 includes a fifteenth source, a fifteenth drain and a fifteenth gate;

[0134] One end of the third voltage-dividing resistor R3 is connected to the power supply voltage, and the other end of the third voltage-dividing resistor R3 is respectively connected to the fifteenth source and the undervoltage threshold detection module 23; the fifteenth drain is respectively connected to one end of the fourth voltage-dividing resistor R4, the undervoltage threshold detection module 23, and the clamping module 22; the other end of the fourth voltage-dividing resistor R4 and the fifteenth gate are both grounded.

[0135] The eighth PMOS transistor P8, the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4 are combined together to form a transmission transistor voltage-dividing module 21 for power supply voltage undervoltage sampling.

[0136] Specifically, the first voltage-dividing resistor R1, the second voltage-dividing resistor R2, the third voltage-dividing resistor R3, and the fourth voltage-dividing resistor R4 in the resistance voltage-dividing module 11 and the transmission tube voltage-dividing module 21 can adopt large resistors, and the seventh PMOS tube P7 and the eighth PMOS tube P8 can adopt long-channel PMOS diodes to further reduce the overall standby power consumption.

[0137] In a specific example, if Figure 10-11 As shown, Fig.11The horizontal axis is time / us (time / microsecond), and the vertical axis is the V / v (voltage / volt) value corresponding to different signals. In the power-on stage, due to the coupling effect of C1 and C2, the high-effective power-on reset signal PUR and the high-effective reset signal RST will follow the power supply voltage VDD, the high-effective detection enable signal DET_EN is low, the low-effective latch enable signal LATCHb is high, P7 and N4 are both turned on, and the resistor voltage divider module 11 generates a first voltage divider signal DIV. When DIV is lower than the flip point of the power supply voltage threshold detection module 12, the low-effective power-on reset PURb remains high. At this time, POR_UP and POR_BOR both follow the power supply voltage to a high level, and the chip is in a reset state; the BOR signal will also rise with the power supply voltage. When the power supply voltage continues to rise, due to the undervoltage reset circuit 2's flip point (second threshold voltage) is lower than the flip point (first threshold voltage) of the power-on reset circuit 1, so the BOR signal will be pulled low before POR_UP; when the power supply voltage continues to rise to a specific voltage (power-on reset release voltage), DIV exceeds the flip point of the power supply voltage threshold detection module 12, PURb is pulled low, PUR is also pulled low, POR_UP is driven low through the four-stage inverter (P5, P6, N6, N7), the low-effective reset signal RSTb is pulled high, LATCHb is pulled low, the PUR signal is latched as a low level, the POR_BOR signal is pulled low, the chip exits the reset state, DET_EN is pulled high, and the power-on reset circuit 1 enters the zero-power working mode.

[0138] During the power-off stage, the equivalent resistance of P8 will increase, and the voltage of the undervoltage detection signal PD will decrease under the action of R4. When it is lower than the flip point of the undervoltage threshold detection module 23 composed of P2 and N1, the undervoltage detection signal PDb will be pulled up to the voltage of the undervoltage detection circuit power supply signal LS. At this time, the LS voltage is not the full-swing VDD voltage. The PD and PDb signals generate a full-swing high-level BOR signal through the level conversion module 24, and the POR_BOR is pulled up to the VDD voltage through nor1 and inv1, so that the chip enters the reset state, and at the same time, the DET_EN signal is pulled low and the LATCHb signal is pulled high to enable the power-on reset circuit 1 of the upper half, so that the power-on reset circuit 1 enters the power-on voltage detection reset state.

[0139] This specific embodiment divides the power-on reset signal path and the undervoltage reset path into two independent signal paths, so that the power-on reset voltage and the undervoltage reset voltage can be adjusted independently and accurately, thereby ensuring the precise adjustment of the power-on reset voltage and the undervoltage reset voltage, ensuring the robustness of the chip, and thus effectively improving the yield and reliability of the chip.

[0140] Example 2

[0141] In a specific embodiment of the present disclosure, a chip is provided, wherein the chip includes the reset circuit described in any of the above embodiments.

[0142] This specific embodiment divides the power-on reset signal path and the undervoltage reset path into two independent signal paths, so that the power-on reset voltage and the undervoltage reset voltage can be adjusted independently and accurately, thereby ensuring the precise adjustment of the power-on reset voltage and the undervoltage reset voltage, ensuring the robustness of the chip, and thus effectively improving the yield and reliability of the chip.

[0143] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A reset circuit, characterized in that: The reset circuit includes a power-on reset circuit, an undervoltage reset circuit and a drive output circuit; The power-on reset circuit comprises a resistor voltage divider module, a power supply voltage threshold detection module, a switch module and a power-on reset latch circuit, wherein the resistor voltage divider module, the power supply voltage threshold detection module, the switch module and the power-on reset latch circuit are connected in sequence, and the output end of the power-on reset latch circuit is respectively connected to the switch module and the drive output circuit; The undervoltage reset circuit includes a transmission tube voltage divider module, an undervoltage threshold detection module and a clamp module, the output end of the transmission tube voltage divider module is respectively connected to the input end of the undervoltage threshold detection module and the output end of the clamp module, the output end of the clamp module is connected to the input end of the undervoltage threshold detection module, and the output end of the undervoltage threshold detection module is respectively connected to the input end of the power-on reset latch circuit and the drive output circuit; The power-on reset circuit is used to detect the power supply voltage and generate a power-on reset signal, and send the power-on reset signal to the drive output circuit; The undervoltage reset circuit is used to detect the power supply voltage and generate an undervoltage reset signal, and send the undervoltage reset signal to the drive output circuit; The drive output circuit is used to output a target reset drive signal according to the power-on reset signal and the undervoltage reset signal to drive the chip to enter a reset state or exit a reset state; The drive output circuit comprises a first NOR gate; The switch module includes a fourth NMOS tube; the fourth NMOS tube includes an eighth source, an eighth drain and an eighth gate; The power-on reset latch circuit includes a second NOR gate, a second inverter, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first capacitor and a second capacitor; The fifth NMOS tube includes a ninth source, a ninth drain and a ninth gate; The fifth PMOS tube includes a tenth source, a tenth drain and a tenth gate; The sixth PMOS tube includes an eleventh source, an eleventh drain and an eleventh gate; The sixth NMOS tube includes a twelfth source, a twelfth drain and a twelfth gate; The seventh NMOS tube includes a thirteenth source, a thirteenth drain and a thirteenth gate; The ninth drain is connected to the eighth drain, one end of the first capacitor, the tenth gate, and the twelfth gate; The ninth gate is connected to the output end of the second NOR gate and the input end of the second inverter, and the ninth source is grounded; The tenth source and the eleventh source are both connected to the power supply voltage; The tenth drain, the eleventh gate, the twelfth drain, and the thirteenth gate are connected to each other; the eleventh drain and the thirteenth drain are connected to the first input end of the first NOR gate, the first input end of the second NOR gate, and one end of the second capacitor; the twelfth source and the thirteenth source are grounded; The other end of the first capacitor and the other end of the second capacitor are both connected to the power supply voltage; The second input end of the second NOR gate is connected to the output end of the undervoltage threshold detection module and the second input end of the first NOR gate respectively; the output end of the second NOR gate is connected to the input end of the second inverter, and the output end of the second inverter is connected to the eighth gate.

2. The reset circuit according to claim 1, characterized in that: The drive output circuit further includes a first inverter, and the output end of the first NOR gate is connected to the first inverter; The second input terminal of the first NOR gate is also connected to the output terminal of the undervoltage threshold detection module; The output end of the first NOR gate and the input end of the first inverter are respectively connected to the resistance voltage divider module.

3. The reset circuit according to claim 2, characterized in that: The undervoltage reset circuit also includes a level conversion module; The output end of the undervoltage threshold detection module is connected to the input end of the level conversion module, and the output end of the level conversion module is connected to the second input end of the first NOR gate and the second input end of the second NOR gate; The level conversion module is used for converting the undervoltage reset signal of a non-full-swing amplitude into the undervoltage reset signal of a full-swing amplitude.

4. The reset circuit according to claim 3, characterized in that: The clamping module includes a first PMOS tube, and the undervoltage threshold detection module includes a second PMOS tube and a first NMOS tube; The first PMOS tube includes a first source, a first drain and a first gate; The second PMOS tube includes a second source, a second drain and a second gate; The first NMOS tube includes a third source, a third drain and a third gate; The first source is connected to the power supply voltage, and the first gate and the first drain are both connected to the transmission tube voltage divider module, the second gate, the third gate, and the level conversion module; The second source is connected to the transmission tube voltage divider module, the second drain and the third drain are both connected to the level conversion module, and the third source is grounded.

5. The reset circuit according to claim 4, characterized in that: The level conversion module includes a third PMOS tube, a fourth PMOS tube, a second NMOS tube and a third NMOS tube; The third PMOS tube includes a fourth source, a fourth drain and a fourth gate; The fourth PMOS tube includes a fifth source, a fifth drain and a fifth gate; The second NMOS tube includes a sixth source, a sixth drain and a sixth gate; The third NMOS tube includes a seventh source, a seventh drain and a seventh gate; The fourth source and the fifth source are both connected to the power supply voltage; The fourth drain, the fifth gate and the sixth drain are connected; The sixth gate is connected to the second drain and the third drain; The fourth gate, the fifth drain, and the seventh drain are connected to the second input terminal of the second NOR gate and the second input terminal of the first NOR gate; The seventh gate is connected to the first gate, the first drain, the second gate, the third gate, and the transmission tube voltage divider module; The sixth source and the seventh source are grounded.

6. The reset circuit according to claim 2, characterized in that: The power supply voltage threshold detection module includes a push-pull reverse amplifier; The input end of the push-pull reverse amplifier is connected to the resistance voltage divider module, and the output end of the push-pull reverse amplifier is connected to the eighth source; The eighth drain is connected to the input end of the power-on reset latch circuit, and the eighth gate is connected to the output end of the power-on reset latch circuit.

7. The reset circuit according to claim 2, characterized in that: The power-on reset circuit further includes a buffer shaping circuit, wherein the buffer shaping circuit is composed of a third inverter and a fourth inverter; The output terminal of the third inverter is connected to the input terminal of the fourth inverter; The input end of the third inverter is connected to the eleventh drain, the thirteenth drain, and one end of the second capacitor respectively; An output terminal of the fourth inverter is connected to a first input terminal of the first NOR gate.

8. The reset circuit according to any one of claims 2 to 7, characterized in that: The resistor voltage-dividing module includes a seventh PMOS tube, a first voltage-dividing resistor and a second voltage-dividing resistor; The seventh PMOS tube includes a fourteenth source, a fourteenth drain and a fourteenth gate; The fourteenth source is connected to the power supply voltage, and the fourteenth gate is respectively connected to the output end of the first NOR gate and the input end of the first inverter; One end of the first voltage-dividing resistor is connected to the fourteenth drain, and the other end of the first voltage-dividing resistor and one end of the second voltage-dividing resistor are both connected to the power supply voltage threshold detection module; The other end of the second voltage-dividing resistor is grounded; and / or, The transmission tube voltage-dividing module includes an eighth PMOS tube, a third voltage-dividing resistor and a fourth voltage-dividing resistor; The eighth PMOS tube includes a fifteenth source, a fifteenth drain and a fifteenth gate; One end of the third voltage-dividing resistor is connected to the power supply voltage, and the other end of the third voltage-dividing resistor is respectively connected to the fifteenth source electrode, the undervoltage threshold detection module, and the clamping module; The fifteenth drain electrode is respectively connected to one end of the fourth voltage-dividing resistor and the undervoltage threshold detection module; The other end of the fourth voltage-dividing resistor and the fifteenth gate are both grounded.

9. A chip, characterized in that: The chip comprises the reset circuit according to any one of claims 1 to 8.

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