A satellite-borne broadband communication transceiver system

Abstract

The application relates to the field of spaceflight measurement and control communication, in particular to a satellite-borne broadband communication transceiving system, which comprises an interface module, an interface circuit, a radio frequency agile circuit, a high-speed ADDA circuit, a main control FPGA, a communication FPGA, a DSP, a power management circuit and a clock management circuit; the interface module is connected with the interface circuit, the radio frequency agile circuit, the main control FPGA, the communication FPGA, the DSP, the power management circuit and the clock management circuit respectively; the interface circuit is connected with the main control FPGA; the main control FPGA is connected with the communication FPGA, the DSP, the high-speed ADDA circuit, the power management circuit and the clock management circuit respectively; the high-speed ADDA circuit is connected with the radio frequency agile circuit, the power management circuit and the clock management circuit; the communication FPGA is connected with the DSP, the power management circuit and the clock management circuit; and the DSP is connected with the power management circuit and the clock management circuit. The application is applicable to the 0.7-31GHz frequency band, the wide frequency band multi-mode communication can be selected, the clock can be configured, the satellite-borne broadband radio frequency direct sampling and on-orbit refreshing reconstruction are supported, and the application has the advantages that the multi-channel can be flexibly applied.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of spaceflight measurement and control communication, and in particular to a satellite-borne broadband communication transceiving system. BACKGROUND

[0002] With the continuous development of satellite services, the high-frequency signal bandwidth processed by the satellite-borne transceiving system is increasingly large, which makes the communication frequency band of the satellite-borne transceiving system continuously increase, and also makes the noise and signal distortion generated in the conversion process from the analog domain to the digital domain (or from the digital domain to the analog domain) of the analog / digital converter in the system increasingly difficult to compensate, seriously affecting the performance of the satellite-borne transceiving system. By moving the analog / digital converter in the satellite-borne transceiving system closer to the radio frequency end, the conversion of the signal from the analog domain to the digital domain (or from the digital domain to the analog domain) near the radio frequency end is completed earlier, which can compensate the digital signal by using software algorithm processing at the same time, and avoid the introduction of additional noise and signal distortion.

[0003] At present, the sampling rate of the analog / digital conversion technology has reached the order of GSPS, and the significant improvement of the performance of the converter can provide sufficient dynamic range for the satellite-borne communication, and can effectively solve the problems of the satellite platform, such as large task bandwidth of the payload, multiple radio frequency transceiving channels, small space volume, limited energy, and the like. SUMMARY

[0004] The application aims to solve the problems in the prior art, and provides a satellite-borne broadband communication transceiving system, which comprises an interface module, an interface circuit, a radio frequency agile circuit, a high-speed ADDA circuit, a master control FPGA, a communication FPGA, a DSP, a power management circuit and a clock management circuit.

[0005] The interface module is connected with the interface circuit, the radio frequency agile circuit, the master control FPGA, the communication FPGA, the DSP, the power management circuit and the clock management circuit respectively.

[0006] The interface circuit is connected with the master control FPGA.

[0007] The master control FPGA is connected with the communication FPGA, the DSP, the high-speed ADDA circuit, the power management circuit and the clock management circuit respectively.

[0008] The high-speed ADDA circuit is connected with the radio frequency agile circuit, the power management circuit and the clock management circuit respectively.

[0009] The communication FPGA is connected with the DSP, the power management circuit and the clock management circuit, and the communication FPGA is used for processing digital signals and assisting the master control FPGA to complete the logic operation of the data protocol.

[0010] The DSP is connected with the power management circuit and the clock management circuit respectively, and is used to carry out algorithm operation in data processing process, so as to realize high-speed data calculation.

[0011] Preferably, the interface module comprises a front panel connector and a VITA backplane interface, which are used to complete remote command input, analog telemetry output, and access of clock signals, power signals, and digital oscillator signals, so as to realize connection signals.

[0012] Preferably, the interface circuit comprises a level conversion circuit and an interface, wherein the CAN interface, the RS422 interface, the LVDS interface, the TTL interface, and the gigabit network interface in the interface are respectively used to complete interface data generation for physical layer signals and network layer data, so as to realize physical layer interface level standard conversion and network layer data protocol transmission and reception.

[0013] Preferably, the radio frequency agile circuit comprises a receiving channel, a transmitting channel, and an electrically tunable band-pass filter, and the radio frequency agile circuit realizes wide-band mode communication based on an external local oscillator LO signal input by the VITA backplane interface, wherein the external local oscillator LO provides a carrier frequency for the transmitting channel and the receiving channel, so as to realize analog signal up-conversion and down-conversion in a wide frequency band.

[0014] The input end and the output end of the transmitting channel and the receiving channel are connected with the electrically tunable band-pass filter, which is used to complete band-pass filtering of channel analog signals, wherein the receiving channel is used to complete wide-band signal reception, and through multiplexing a detection channel, electromagnetic signal detection is realized, and the transmitting channel is used to transmit the data information.

[0015] The electrically tunable band-pass filter supports multiple frequency ranges, is used to realize channel band-pass filtering, and has a working frequency range covering 0.7-31 GHz, a narrow instantaneous bandwidth of filter response, and a small design volume, so as to effectively improve the performance effect and space utilization of the transceiver system.

[0016] Preferably, the master control FPGA performs protocol processing on data information received from a satellite computer, controls a processing and calculation flow of the data information, so as to complete internal input of received data in the data information and external output of transmitted data in the data information, and in combination with the power management circuit, the communication FPGA and the DSP are powered and configured, wherein the data information comprises task information, tracking data, target indication data, and user telemetry data.

[0017] Preferably, the power management circuit converts the externally input power signal into the voltage within the master FPGA, the communication FPGA, the DSP and the high-speed ADDA circuit through the VI TA backplane interface, and detects the current, voltage and power.

[0018] Preferably, the high-speed ADDA circuit comprises an ADC circuit, a DAC circuit and a fast transceiver circuit.

[0019] The ADC circuit converts the received input signal from the analog domain to the digital domain.

[0020] The DAC circuit converts the transmitted output signal from the digital domain to the analog domain.

[0021] The fast transceiver circuit provides channel signal reception and channel signal transmission.

[0022] Preferably, the clock management circuit comprises an external clock input and a local clock input, the external clock input is a clock mode using the on-board TXCO clock as the clock input, and the local clock input is a clock mode using the external clock directly input through the SMA radio frequency head as the working reference clock.

[0023] Preferably, the high-speed ADDA circuit uses a clock generator as the clock input signal according to the external clock, and the master FPGA, the communication FPGA and the DSP select the local clock direct input or the external clock combined with the clock generator to generate the input clock.

[0024] Preferably, the ADC circuit is configured in a channel mode, supports high sampling frequency and line rate, can meet wide instantaneous bandwidth application, and can directly sample wide frequency band radio frequency.

[0025] The DAC circuit has high dynamic range and fast frequency hopping capability, supports direct radio frequency signal synthesis, can flexibly adjust the number and speed of channels, and has fast effective DAC update rate.

[0026] Preferably, the fast transceiver circuit provides channel signal reception and channel signal transmission, can adapt to wide bandwidth and radio frequency direct sampling when receiving, and has functions such as analog-to-digital conversion and power amplification, and can directly frequency-convert the output signal to the radio frequency band when transmitting.

[0027] Compared with the prior art, the application has the following beneficial effects:

[0028] 1) In the power management circuit, the externally input power signal is converted into the voltage within the master FPGA, the communication FPGA, the DSP and the high-speed ADDA circuit through the VI TA backplane interface, so as to realize efficient power supply and provide current, voltage and power detection.

[0029] 2) The clock management circuit of the application comprises an external clock input and a local clock input, and clock flexibility is realized through the clock management circuit;

[0030] 3) The high-speed ADDA circuit of the application comprises an ADC circuit, a DAC circuit and a fast change transceiver circuit, wherein the ADC circuit is configured in a multi-channel mode, supports high sampling frequency and line rate, can meet wide instantaneous bandwidth application, and can realize wideband radio frequency direct sampling;

[0031] 4) The master control FPGA, the communication FPGA and the DSP in the application all have on-orbit refreshing and reconfiguring capabilities, so that the on-orbit refreshing and reconfiguring of the satellite-borne broadband communication transceiver system is realized. BRIEF DESCRIPTION OF DRAWINGS

[0032] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not meant to limit the present application.

[0033] Figure 1 FIG. 1 is a schematic diagram of a satellite-borne broadband communication transceiver system according to the application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the application more clear, the application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application. Obviously, the described embodiments are part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0035] Those skilled in the art can understand that, unless specifically stated, the singular form "a", "an", "the" used herein can also include the plural form. It should be further understood that the phrase "comprising" used in the specification of the application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0036] EMBODIMENT

[0037] Referring to Figure 1 As shown in the drawings, the satellite-borne broadband communication transceiver system provided by the embodiment comprises an interface module, an interface circuit, a radio frequency fast change circuit, a high-speed ADDA circuit, a master control FPGA, a communication FPGA, a DSP, a power management circuit and a clock management circuit:

[0038] The interface module is connected with the interface circuit, the radio frequency agile circuit, the master control FPGA, the communication FPGA, the DSP, the power management circuit and the clock management circuit respectively;

[0039] The interface circuit is connected with the master control FPGA;

[0040] The master control FPGA is connected with the communication FPGA, the DSP, the high-speed ADDA circuit, the power management circuit and the clock management circuit respectively;

[0041] The high-speed ADDA circuit is connected with the radio frequency agile circuit, the power management circuit and the clock management circuit respectively;

[0042] The communication FPGA is connected with the DSP, the power management circuit and the clock management circuit, wherein the communication FPGA is used for processing digital signals and assisting the master control FPGA to complete logical operation of data protocol, and specifically, in the embodiment, the communication FPGA selects an XCVU9P chip and supports on-orbit refreshing and reconstruction;

[0043] The DSP is connected with the power management circuit and the clock management circuit, and specifically, in the embodiment, the DSP is used for algorithm operation in a data processing process to realize high-speed data calculation, and the DSP selects a 6678 chip, which has a calculation acceleration circuit and can be used for algorithm operation in a data processing process to realize high-speed data calculation and supports on-orbit refreshing and reconstruction.

[0044] Preferably, the interface module includes a front panel connector and a VITA backplane interface, which are used for completing remote control instruction input, analog telemetry output, and access of clock signals, power signals and digital oscillator signals to realize continuous signals.

[0045] Preferably, the interface circuit includes a level conversion circuit and an interface, and the CAN interface, the RS422 interface, the LVDS interface, the TTL interface and the gigabit network port in the interface respectively complete interface data generation for physical layer signals and network layer data to realize physical layer interface level standard conversion and network layer data protocol transmission and reception.

[0046] Preferably, the radio frequency agile circuit includes a receiving channel, a transmitting channel and an electrically tunable bandpass filter, and the radio frequency agile circuit realizes wideband multi-mode communication based on an external local oscillator LO signal input by the VITA backplane interface, wherein the external local oscillator LO provides a carrier frequency for the transmitting channel and the receiving channel to realize analog signal up-conversion and down-conversion, and specifically, in the embodiment, the radio frequency agile circuit includes 4 receiving channels, 4 transmitting channels and 16 electrically tunable bandpass filters;

[0047] The input end and the output end of the transmitting channel and the receiving channel are connected with the electrically tunable band-pass filter, which is used for completing the band-pass filtering of the channel analog signal, wherein the receiving channel is used for completing the wide-band signal receiving, and through multiplexing the receiving channel, the electromagnetic signal listening is realized, the transmitting channel is used for transmitting the data information, specifically, in the embodiment, the input end and the output end of the transmitting channel and the receiving channel are connected with one electrically tunable band-pass filter, which is used for completing the band-pass filtering of the channel analog signal, the four receiving channels can all complete the wide-band signal receiving, and the receiving channel 3 and the receiving channel 4 can be multiplexed as the receiving channel, which is used for realizing the electromagnetic signal listening, and the transmitting channel is all used for transmitting the data information.

[0048] The electrically tunable band-pass filter supports multiple frequency ranges, is used for realizing the multi-channel band-pass filtering, the working frequency range can cover the range of 0.7-31GHz, the instantaneous bandwidth of the filter response is narrow, the design volume is small, and the performance effect and the space utilization of the transceiving system are effectively improved.

[0049] Preferably, the electrically tunable band-pass filter adopts a multi-channel YIG band-pass filter, supports multiple frequency ranges, the working frequency range can cover the P-U wave band, the instantaneous bandwidth of the filter response is narrow and has no parasitic passband, the design volume is small but has multiple interface forms, and the volume and weight of the transceiving system can be greatly reduced.

[0050] Preferably, the main control FPGA performs protocol processing on the data information received from the satellite computer, controls the processing and calculation flow of the data information, completes the internal input of the received data in the data information and the external output of the transmitted data in the data information, and simultaneously, in combination with the power management circuit, performs power-on configuration management on the communication FPGA and the DSP, wherein the data information includes task information, tracking data, target indication data and user telemetry data, and specifically, in the embodiment, the main control FPGA selects an XC7VX690T chip and mainly receives data information from the satellite computer.

[0051] Preferably, the power management circuit converts the externally input power signal into the voltage of the main control FPGA, the communication FPGA, the DSP and the high-speed ADDA circuit through the VITA backplane interface, and detects the current, voltage and power, and specifically, in the embodiment, the power management circuit provides the +12V voltage provided by the secondary power supply to the main control FPGA, the communication FPGA, the DSP and the high-speed ADDA circuit through the VITA backplane, and according to the internal chip condition of each circuit, the required voltage is further distributed.

[0052] Preferably, the high-speed ADDA circuit includes an ADC circuit, a DAC circuit and a fast-changing transceiving circuit.

[0053] The ADC circuit converts the received input signal from the analog domain to the digital domain.

[0054] The DAC circuit converts the transmit output signal from the digital domain to the analog domain;

[0055] The agile transceiver circuit provides multi-channel signal reception and multi-channel signal transmission.

[0056] Preferably, the clock management circuit includes an external clock input and a local clock input, the external clock input is a clock mode in which the on-board TXCO clock is used as the clock input, and the local clock input is a clock mode in which the external clock is directly input through an SMA radio frequency head, and the local clock is used as the working reference clock by default, specifically, in the present embodiment, the external clock is 40MHz.

[0057] In the present embodiment, the high-speed ADDA circuit uses two pieces of HMC7044 (clock generator) as the clock input signal based on the external clock, and the master control FPGA, the communication FPGA and the DSP simultaneously use the local clock and the external clock, and select the local clock directly input or the external clock combined with the clock generator to generate the input clock as needed.

[0058] Preferably, the ADC circuit is configured in a multi-channel mode, supports high sampling frequency and line rate, can meet wide instantaneous bandwidth application, and wide frequency band direct radio frequency sampling, specifically, in the present embodiment, the ADC circuit core device selects the ADC12DJ5200 chip, which can be configured in single / dual channel mode, the sampling frequency can reach 10.4GSPS in single channel mode, the sampling frequency can reach 5.2GSPS in dual channel mode, can support 16 serial channels and has a line rate of up to 17.16Gbps, supports an available input frequency range of up to 10GHz, can meet wide instantaneous bandwidth application, and can directly sample radio frequency signals.

[0059] The DAC circuit has high dynamic range and fast frequency hopping capability, supports direct radio frequency signal synthesis, can flexibly adjust the number and speed of channels, and has fast effective DAC update rate, specifically, in the present embodiment, the DAC circuit core device selects the AD9164 chip, which has high dynamic range and fast frequency hopping capability, signal reconstruction bandwidth can reach 7.5GHz, supports 6GSPS direct radio frequency signal synthesis, includes an 8-channel SERDES interface, can flexibly adjust the number and speed of channels, and can provide an effective DAC update rate of up to 12GSPS.

[0060] Preferably, the agile transceiver circuit provides channel signal receiving and channel signal sending, can adapt wide bandwidth and radio frequency direct sampling when receiving, and has functions such as analog-to-digital conversion, power amplification, etc., and realizes direct frequency conversion of the output signal to the radio frequency band when sending, specifically, in the embodiment, the agile transceiver circuit selects ADRV9009 chip, can provide double-channel transceiver function, the chip receiver can adapt wide bandwidth and radio frequency direct sampling, and has functions such as analog-to-digital conversion, power amplification, etc., the chip transmitter can realize high modulation accuracy and extremely low noise while directly frequency converting the output signal to the radio frequency band, and the whole has the characteristics of high performance and low power consumption.

[0061] The specific process of the on-board broadband communication transceiving in the embodiment is as follows: in the receiving channel, the analog signal accessed by the interface module is first subjected to frequency band filtering by the electrically tunable band-pass filter, then subjected to radio frequency down-conversion and re-filtering under the control of the externally input local oscillator LO, under the control of the main control FPGA, the filtered intermediate frequency analog signal is converted to the digital domain by the analog-to-digital converter in the high-speed ADDA circuit, the obtained digital signal is forwarded to the communication FPGA and DSP for calculation and processing under the control of the main control FPGA, the feature extraction of the digital signal is realized, and complete data information is formed at the main control FPGA, is processed by the interface circuit, is transmitted to the external information processing module through the interface module, and the data processing and forwarding are completed;

[0062] In the transmitting channel, that is, in the transmitting state, the external information processing module transmits data information to the interface circuit through the interface module, the data information is forwarded to the main control FPGA after processing, the main control FPGA controls the data to be sent to the communication FPGA and DSP based on the high-speed serial port to jointly complete the encoding and modulation of the data, and then the main control FPGA uniformly forwards the data to the high-speed ADDA circuit, obtains the intermediate frequency analog signal by using the digital-to-analog converter, and completes the frequency conversion process of the intermediate frequency signal to the radio frequency band and the signal filtering before and after the frequency conversion in combination with the externally input local oscillator LO signal and the band-pass filter in the radio frequency agile circuit, so that the radio frequency signal is generated.

[0063] The above only describes the preferred embodiments of the present application, the protection scope of the present application is not limited to the above-mentioned embodiments, any technical scheme falling within the idea of the present application belongs to the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and decorations without departing from the principle of the present application can also be considered as the protection scope of the present application.

Claims

1. A space-borne broadband communication transceiver system, characterized by The interface module is connected with the interface circuit, the radio frequency agile circuit, the high-speed ADDA circuit, the main control FPGA, the communication FPGA, the power management circuit and the clock management circuit. The interface circuit is connected with the main control FPGA. The main control FPGA is connected with the communication FPGA, the DSP, the high-speed ADDA circuit, the power management circuit and the clock management circuit. The high-speed ADDA circuit is connected with the radio frequency agile circuit, the power management circuit and the clock management circuit. The communication FPGA is connected with the DSP, the power management circuit and the clock management circuit, and is used for processing digital signals and assisting the main control FPGA to complete logical operation of data protocol. The DSP is connected with the power management circuit and the clock management circuit, and is used for algorithm operation in data processing process to realize high-speed data calculation. The interface module includes a front panel connector and a VITA backplane interface, which is used for realizing remote control instruction input, analog telemetry output, clock signal access, power signal access and digital oscillator signal access to realize continuous signal transmission. The radio frequency agile circuit includes a receiving channel, a transmitting channel and an electrically tunable band-pass filter, and realizes wide-band mode communication based on an external local oscillator (LO) signal input by the VITA backplane interface. The transmitting channel and the receiving channel are connected with the electrically tunable band-pass filter at input ends and output ends, and are used for completing band-pass filtering of channel analog signals. The electrically tunable band-pass filter supports multiple frequency ranges and is used for realizing channel band-pass filtering and covering a frequency range of 0.7-31 GHz. The interface circuit includes a level conversion circuit and an interface, and the CAN interface, the RS422 interface, the LVDS interface, the TTL interface and the gigabit network interface in the interface are used for completing interface data generation for physical layer signals and network layer data, realizing physical layer interface level standard conversion and network layer data protocol transmission and reception.

2. A space-borne broadband communication transceiving system according to claim 1, wherein, The main control FPGA processes data information received from a satellite computer, controls processing and calculation flow of the data information, completes internal input of received data in the data information and external output of transmitted data in the data information, and performs power-on configuration management on the communication FPGA and the DSP in combination with the power management circuit.

3. The system of claim 1, wherein the plurality of transceivers are configured to transmit and receive signals in a plurality of frequency bands. The data information includes task information, tracking data, target indication data and user telemetry data.

4. The system of claim 1, wherein the system is a satellite-based broadband communication transceiver system. The power management circuit converts the externally input power signal into input voltage of the master FPGA, the communication FPGA, the DSP and the high-speed ADDA circuit through the VITA backplane interface, and detects current, voltage and power.

5. The system of claim 1, wherein the system is a satellite-based broadband communication transceiver system. The high-speed ADDA circuit comprises an ADC circuit, a DAC circuit and a fast changeover transceiver circuit. The ADC circuit converts a received input signal from an analog domain to a digital domain. The DAC circuit converts a transmitted output signal from a digital domain to an analog domain. The fast changeover transceiver circuit provides channel signal reception and channel signal transmission.

6. The system of claim 1, wherein the system is a satellite-based broadband communication transceiver system. The clock management circuit comprises an external clock input and a local clock input, the external clock input is a clock mode of taking a board-mounted TXCO clock as a clock input, and the local clock input is a clock mode of taking a local clock as a working reference clock by directly connecting an external clock to an SMA radio frequency head. The high-speed ADDA circuit uses a clock generator as a clock input signal according to an external clock, and the master FPGA, the communication FPGA and the DSP select a local clock direct input or an external clock combined with a clock generator to generate an input clock.

7. A space-borne broadband communication transceiving system according to claim 5, wherein, The ADC circuit is configured in a channel mode, supports high sampling frequency and line rate, can meet wide instantaneous bandwidth application and wide frequency band direct radio frequency sampling, and has high dynamic range and fast frequency hopping capability. The DAC circuit supports direct radio frequency signal synthesis, can flexibly adjust the number and speed of channels, and has a fast effective DAC update rate.

8. A space-borne broadband communication transceiving system according to claim 7, wherein, The fast changeover transceiver circuit provides channel signal reception and channel signal transmission, can adapt to wide bandwidth and radio frequency direct sampling when receiving, and has functions of analog-to-digital conversion and power amplification, and can directly convert an output signal to a radio frequency band when transmitting.

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