A time synchronization device
Through the combination solution of FPGA chip and clock chip, the problem of insufficient clock synchronization accuracy between devices in the prior art is solved, and high-precision submicron-second clock synchronization is achieved, providing a stable time reference for the coordinated work between devices.
CN119254376BActive Publication Date: 2025-03-18杭州初灵信息技术股份有限公司
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Patent Information
- Application Number
- CN202411784026.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2044-12-06
AI Technical Summary
Technical Problem
In the prior art, inter-device clock synchronization depends on integrated chips, and higher precision clock synchronization cannot be achieved, and the chip cannot be replaced.
Method used
Using a combination scheme of FPGA chip and clock chip, the FPGA chip divides the clock frequency of the initial clock synchronization signal into multiple clock frequency points, and achieves high-precision clock synchronization through a phase-locked loop and a pulse generator.
Benefits of technology
It improves the accuracy of clock synchronization, realizes submicron-second clock synchronization, provides a foundation of higher accuracy, and provides a stable time reference for coordinated work between devices.
✦ Generated by Eureka AI based on patent content.
Abstract
The present application relates to a time synchronization device, wherein the time synchronization device includes: an FPGA chip, which is used to divide the clock frequency of the received initial clock synchronization signal into a first clock frequency and a second clock frequency; the clock chip includes a first phase-locked loop and a second phase-locked loop, the first phase-locked loop is used to obtain a system clock according to the first clock frequency, and send the system clock to the second phase-locked loop; the second phase-locked loop is used to obtain a PTP clock offset frequency according to the system clock, and send the PTP clock offset frequency to the FPGA chip; the FPGA chip includes a pulse generator, the pulse generator is used to generate a pulse signal per second, and adjust the phase of the pulse signal per second according to the PTP clock offset frequency, so that the phase is consistent with the pulse phase of the initial clock synchronization signal per second, and time synchronization is completed. Through the present application, the clock synchronization of the present application device and the upstream device is realized by using the FPGA chip and the clock chip.
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