Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a gate stack structure including interlayer insulating layers and conductive layers alternately stacked; a channel structure extending in a vertical direction in the gate stack structure; and a memory structure interposed between the conductive layer and the channel structure. Each of the memory structures includes a blocking insulating layer and a charge trapping layer sequentially formed on a sidewall of each of the conductive layers. A side wall of the interlayer insulating layer in contact with the channel structure is located on the same line as a side wall of the charge trapping layer in contact with the channel structure, or a side portion of the interlayer insulating layer in contact with the channel structure protrudes further than the side wall of the charge trapping layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0085853 filed on July 3, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0004] A nonvolatile memory device is a memory device in which data stored therein remains intact even when power is interrupted. As the degree of integration of a two-dimensional nonvolatile memory device in which memory cells are formed in a single layer over a substrate reaches a limit, a three-dimensional nonvolatile memory device in which memory cells are vertically stacked over a substrate has recently been proposed.

[0005] A three-dimensional nonvolatile memory device includes: interlayer insulating layers and gate electrodes alternately stacked, and a channel layer penetrating the interlayer insulating layers and the gate electrodes, and memory cells are stacked along the channel layer. Various structures and various manufacturing methods have been developed to improve the operational reliability of such a nonvolatile memory device having a three-dimensional structure. Summary of the invention

[0006] According to one embodiment of the present disclosure, a semiconductor device is provided, which includes: a gate stack structure, including interlayer insulating layers and conductive layers alternately stacked; a channel structure, extending in a vertical direction in the gate stack structure; and a memory structure, inserted between the conductive layer and the channel structure, wherein each memory structure in the memory structure includes a blocking insulating layer and a charge trapping layer, the blocking insulating layer and the charge trapping layer are sequentially formed on the side walls of each conductive layer in the conductive layer, and wherein the side wall of the interlayer insulating layer in contact with the channel structure is located on the same line as the side wall of the charge trapping layer in contact with the channel structure, or the side of the interlayer insulating layer in contact with the channel structure protrudes further toward the channel structure than the side wall of the charge trapping layer.

[0007] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a vertical hole, the vertical hole penetrating at least a portion of a stacked structure, in which a first material layer and a second material layer are alternately stacked; forming a recessed area by etching the sidewall of the second material layer exposed through the vertical hole to a certain thickness; forming a blocking insulating layer by oxidizing the sidewall of the second material layer exposed through the recessed area; forming a charge trapping layer in the corresponding recessed area, wherein the charge trapping layers are spaced apart from each other in a vertical direction by the first material layer; and sequentially forming a tunnel insulating layer and a channel layer along the sidewall of the vertical hole.

[0008] According to one embodiment of the present disclosure, a semiconductor device is provided, which includes: a gate stack structure, including interlayer insulating layers and conductive layers alternately stacked; a channel structure, extending in a vertical direction in the gate stack structure; and a memory structure, inserted between the conductive layer and the channel structure, wherein each memory structure in the memory structure includes a blocking insulating layer, a charge trapping layer and a tunnel insulating layer, and the blocking insulating layer, the charge trapping layer and the tunnel insulating layer are sequentially formed on the side walls of each conductive layer in the conductive layer, and wherein the side wall of the interlayer insulating layer in contact with the channel structure is located on the same line as the side wall of the tunnel insulating layer in contact with the channel structure, or the side of the interlayer insulating layer in contact with the channel structure further protrudes toward the channel structure compared with the side wall of the tunnel insulating layer.

[0009] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a vertical hole, the vertical hole penetrating at least a portion of a stacked structure, in which a first material layer and a second material layer are alternately stacked; forming a first recessed region by etching a sidewall of the second material layer exposed through the vertical hole to a certain thickness; forming a blocking insulating layer by oxidizing the sidewall of the second material layer exposed through the first recessed region; forming a charge trapping layer in the corresponding first recessed region, wherein the charge trapping layers are spaced apart from each other in a vertical direction by the first material layer; forming a second recessed region by etching the sidewall of the charge trapping layer exposed through the vertical hole to a certain thickness; forming a tunnel insulating layer in the corresponding second recessed region; and forming a channel layer along the sidewall of the vertical hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0011] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0012] Figure 1 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 2 is a cross-sectional view illustrating a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 4 is a cross-sectional view illustrating a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G and Figure 5H is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0017] Figure 6 is a block diagram illustrating a solid state drive (SSD) system to which the semiconductor device of the present disclosure is applied. DETAILED DESCRIPTION

[0018] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0019] Embodiments provide a semiconductor device and a method of manufacturing the semiconductor device, in which charge trapping layers of a plurality of memory cells stacked in a vertical direction are electrically and physically spaced apart from each other.

[0020] Figure 1 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0021] refer to Figure 1 , the semiconductor device 1100 may include: a memory cell array 110 in which data is stored; and peripheral circuits 120 to 170 capable of performing programming, reading, or erasing operations.

[0022] The memory cell array 110 may include a plurality of memory blocks in which data is stored. Each of the memory blocks may include a plurality of memory cells, and the plurality of memory cells may be nonvolatile memory cells. The nonvolatile memory cells may be implemented as a three-dimensional structure in which the nonvolatile memory cells are stacked in a vertical direction above a substrate.

[0023] The peripheral circuits 120 to 170 may include a row decoder 120 , a voltage generator 130 , a page buffer group 140 , a column decoder 150 , an input / output circuit 160 , and a control logic circuit 170 .

[0024] The row decoder 120 may select one memory block among memory blocks included in the memory cell array 110 according to the row address RADD and transmit the operating voltage Vop to the selected memory block.

[0025] The voltage generator 130 may generate and output an operation voltage Vop required for various operations in response to the operation code OPCD. For example, in response to the operation code OPCD, the voltage generator 130 may generate a set voltage, a reset voltage, a turn-on voltage, a turn-off voltage, a read voltage, an erase voltage, etc., and selectively output the generated voltage. According to this embodiment, the voltage generator 130 may generate a voltage of 0V or higher as a voltage to be applied to a word line, and includes a device that generates a negative voltage lower than 0V.

[0026] The page buffer group 140 may be connected to the memory cell array 110 via a bit line. For example, the page buffer group 140 may include a page buffer connected to a corresponding bit line. The page buffers may operate simultaneously in response to a page buffer control signal PBSIG and store data in a programming or reading operation. In a read or verification operation, the page buffer may sense a current of a bit line that varies according to a threshold voltage of a memory cell. The words "simultaneously" and "simultaneously" as used herein with respect to a process mean that the process occurs at overlapping time intervals. For example, if a first process occurs over a first interval of time and a second process occurs simultaneously over a second interval of time, the first interval and the second interval at least partially overlap each other, so that there is a time when both the first process and the second process occur.

[0027] The column decoder 150 may transfer data DATA between the input / output circuit 160 and the page buffer group 140 according to the column address CADD.

[0028] The input / output circuit 160 may be connected to an external device through an input / output line IO. For example, the external device may be a controller capable of transmitting a command CMD, an address ADD, or data DATA to the memory device 1100. The input / output circuit 160 may input / output a command CMD, an address ADD, and data DATA through the input / output line IO. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external device through the input / output line IO to the control logic circuit 170, and transmit the data DATA received from the external device through the input / output line IO to the column decoder 150. The input / output circuit 160 may output the data DATA received from the column decoder 150 to an external device through the input / output line IO.

[0029] The control logic circuit 170 outputs an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, the control logic circuit 170 may include software configured to execute an algorithm in response to the command CMD and hardware configured to output the address ADD and various control signals.

[0030] Figure 2 is a cross-sectional view illustrating a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 1 The memory cell array 110 shown in FIG. 1 may include a memory block including a plurality of nonvolatile memory cells and Figure 2 0 illustrates a portion of a string included in a memory block.

[0032] refer to Figure 2 The string may include a plurality of nonvolatile memory cells MC, and the plurality of nonvolatile memory cells MC may be connected to a conductive layer CDL corresponding to a word line. Each of the plurality of nonvolatile memory cells MC may be configured to include a conductive layer CDL, a blocking insulating layer BOX, a charge trapping layer CTN, a tunnel insulating layer TIL, and a channel layer CHL.

[0033] An interlayer insulating layer ISL may be formed between the conductive layers CDL. The conductive layer CDL and the interlayer insulating layer ISL may extend in the X direction, which is a horizontal direction relative to the substrate. A gate stack structure GST including the conductive layer CDL and the interlayer insulating layer ISL may be formed. For example, the interlayer insulating layer ISL and the conductive layer CDL may be alternately stacked on top of a lower structure (not shown). The lower structure may include at least one of the following: a substrate, or a source line, a source selection line, and a peripheral circuit formed on the substrate. Each conductive layer CDL in the conductive layer CDL may be used as a word line or a selection line. For example, when the interlayer insulating layer ISL and the conductive layer CDL are alternately stacked on the substrate, the conductive layer CDL may include a word line and a selection line. The interlayer insulating layer ISL may be formed of an oxide, and the conductive layer CDL may be formed of a metal such as tungsten.

[0034] A vertical hole VH may be formed in the string, the vertical hole VH penetrating the interlayer insulating layer ISL and the conductive layer CDL in the Z direction which is a direction perpendicular to the substrate. The vertical hole VH may have a width that narrows as it approaches its bottom end. For example, the width VH_U of the bottom end of the vertical hole VH may be narrower than the width VH_T of the top end of the vertical hole VH.

[0035] Compared with the conductive layer CDL, the interlayer insulating layer ISL may protrude further in the direction adjacent to the vertical hole VH. That is, the blocking insulating layer BOX and the charge trapping layer CTN may be interposed in the space between the protruding portions of the interlayer insulating layers adjacent to each other in the Z direction which is a direction perpendicular to the substrate. That is, the blocking insulating layer BOX and the charge trapping layer CTN may be interposed between the conductive layer CDL and the vertical hole VH. In one embodiment of the present disclosure, the blocking insulating layer BOX and the charge trapping layer CTN may be defined as a memory structure.

[0036] The tunnel insulating layer TIL and the channel layer CHL may be sequentially formed along the sidewalls of the vertical hole VH. For example, the tunnel insulating layer TIL may be formed along the sidewalls of the vertical hole VH (i.e., the sidewalls of the interlayer insulating layer ISL and the charge trapping layer CTN), and the channel layer CHL may be formed along the sidewalls of the tunnel insulating layer TIL. The insulating core layer CO may be formed in the central region of the vertical hole VH. In one embodiment of the present disclosure, the tunnel insulating layer TIL, the channel layer CHL, and the insulating core layer CO may be defined as a vertical channel structure.

[0037] The tunnel insulating layer TIL may be a layer in which charges are tunneled by FN tunneling or the like, and includes an insulating material such as an oxide or a nitride. The charge trapping layer CTN may include a plurality of trapping sites, and in a programming operation, charges introduced while passing through the tunnel insulating layer TIL may be trapped in the charge trapping layer CTN. The charge trapping layer CTN may include a nitride, a chalcogenide, or a metal oxide. In one embodiment, the blocking insulating layer BOX may prevent or mitigate charges trapped in the charge trapping layer CTN from moving to the conductive layer CDL, and includes a high dielectric constant material such as aluminum oxide (Al2O3). 2 O 3 ), hafnium oxide (HfO x ) or hafnium silicon oxide (HfSiO x ). The channel layer CHL may be used to allow current to flow in the strings, and is formed of polysilicon.

[0038] The channel layer CHL may have a columnar structure extending in the vertical hole VH in the Z direction as the vertical direction. The tunnel insulating layer TIL may extend in the vertical hole VH in the Z direction as the vertical direction and be formed to surround an outer wall of the channel layer CHL.

[0039] The charge trapping layer CTN may be formed as a portion of an outer wall surrounding the tunnel insulating layer TIL, and the charge trapping layer CTN corresponding to one nonvolatile memory cell MC may have a structure isolated from the charge trapping layer CTN corresponding to another nonvolatile memory cell MC by an interlayer insulating layer ISL, the other nonvolatile memory cell MC being adjacent to the one nonvolatile memory cell MC in the Z direction which is a vertical direction. Therefore, in one embodiment, interference and disturbance phenomena between nonvolatile memory cells MC adjacent to each other in the Z direction may be reduced.

[0040] In addition, the blocking insulating layer BOX can be formed as an outer wall surrounding the charge trapping layer CTN, and the blocking insulating layer BOX corresponding to one nonvolatile memory cell MC can have a structure isolated from the blocking insulating layer BOX corresponding to another nonvolatile memory cell MC by an interlayer insulating layer ISL, and the other nonvolatile memory cell MC is adjacent to the one nonvolatile memory cell MC in the Z direction which is the vertical direction.

[0041] The vertical thickness T1 of the blocking insulating layer BOX corresponding to one nonvolatile memory cell MC and the vertical thickness T2 of the charge trapping layer CTN corresponding to the one nonvolatile memory cell MC may be the same. The side wall of the interlayer insulating layer ISL in contact with the vertical hole VH may be located on the same line as the side wall of the charge trapping layer CTN in contact with the vertical hole VH, or the side of the interlayer insulating layer ISL in contact with the vertical hole VH may be formed to protrude further than the side wall of the charge trapping layer CTN in contact with the vertical hole VH. In addition, the upper surface heights of the conductive layer CDL, the blocking insulating layer BOX, and the charge trapping layer CTN corresponding to one nonvolatile memory cell MC may be the same. In addition, the lower surface heights of the conductive layer CDL, the blocking insulating layer BOX, and the charge trapping layer CTN corresponding to one nonvolatile memory cell MC may be the same.

[0042] Figures 3A to 3G is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0043] refer to Figure 3A , a stacked structure ST may be formed on the substrate SUB. The stacked structure ST may include first material layers 11 and second material layers 12 that are alternately stacked. The first material layers 11 and the second material layers 12 may extend in an X direction that is a horizontal direction relative to the substrate SUB. The first material layers 11 and the second material layers 12 may be stacked in a Z direction that is a direction perpendicular to the substrate SUB. The first material layers 11 and the second material layers 12 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0044] The first material layer 11 may include a material having a high etching selectivity with respect to the second material layer 12. In one example, the first material layer 11 may include an insulating material such as an oxide, and the second material layer 12 may include a sacrificial material such as a nitride. In another example, the first material layer 11 may include an insulating material such as an oxide, and the second material layer 12 may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal.

[0045] Subsequently, a vertical hole VH penetrating the stack structure ST may be formed. The vertical hole VH may have a columnar shape extending in the Z direction. The vertical hole VH may be formed such that a width VH_T at a top end thereof is wider than a width VH_U at a bottom end thereof.

[0046] refer to Figure 3B, the sidewall of the second material layer 12 exposed through the vertical hole VH may be etched to a certain depth, thereby forming a recessed region R. That is, the sidewall of the second material layer 12 may be etched to a certain depth so that the first material layer 11 protrudes in the horizontal direction compared with the second material layer 12. Therefore, the sidewall of the vertical hole VH may be formed into a structure in which uneven portions are sequentially arranged in the Z direction which is a direction perpendicular to the substrate SUB.

[0047] refer to Figure 3C , the sidewall of each of the second material layers 12 exposed through the vertical hole VH can be oxidized by an oxidation process to form a blocking insulating layer 13. The oxidation process can be performed as a free radical oxidation process or a wet oxidation process. The sidewall of each of the second material layers 12 can be oxidized to a certain thickness by an oxidation process to form a blocking insulating layer 13.

[0048] refer to Figure 3D , a charge trapping source layer 14 may be formed along the sidewall of the vertical hole VH. The charge trapping source layer 14 may be formed by adjusting its thickness so that Figure 3C The recessed region R shown in FIG. 1 is completely buried. The charge trapping source layer 14 may include a charge trapping material, a nitride, a variable resistance material or a nanostructure, a chalcogenide, or a metal oxide, or any combination thereof.

[0049] refer to Figure 3E , an etching process may be performed so that the charge trapping source layer ( Figure 3D 14) shown in FIG. 14) is retained only in the recessed area ( Figure 3C In each recessed region of the R shown in FIG. 1 , a charge trapping layer 14P is formed. That is, the charge trapping source layer ( Figure 3D 14) shown in the figure can be etched and removed, thereby forming a recessed area ( Figure 3C The charge trapping layers 14P in the R) shown in FIG. 1 are physically and electrically isolated from each other. That is, the charge trapping layers 14P adjacent to each other in the Z direction may have a structure in which the charge trapping layers 14P are spaced apart from each other by one first material layer 11.

[0050] refer to Figure 3F , the tunnel insulating layer 15 and the channel layer 16 can be arranged along the vertical hole ( Figure 3E The sidewalls of the VH) shown in FIG. 1 are formed in sequence. The tunnel insulating layer 15 may be a layer in which charges are tunneled by FN tunneling or the like, and includes an insulating material such as oxide or nitride. The channel layer 16 may include polysilicon.

[0051] The tunnel insulating layer 15 may be formed along the sidewalls of the first material layer 11 and the charge trapping layer 14P. The tunnel insulating layer 15 and the channel layer 16 may be formed to extend in the Z direction.

[0052] Thereafter, an insulating core layer 17 may be formed so that the vertical holes ( Figure 3E The central region of the VH shown in FIG. 1 is filled with an insulating core layer 17. The insulating core layer 17 may include an oxide. Figure 3E When the central area of ​​VH) shown in FIG. 1 is filled with the channel layer 16, the process of forming the insulating core layer 17 can be skipped.

[0053] refer to Figure 3G , the second material layer ( Figure 3F 12) shown in FIG. 1 can be replaced by a conductive layer 18. For example, the stacked structure ( Figure 3F ST) is etched to form a slit extending in the X direction, thereby exposing the second material layer ( Figure 3F 12) shown in FIG. Thereafter, the second material layer ( Figure 3F 12) shown in FIG. 1 can be selectively etched and removed, and the second material layer ( Figure 3F The space 12) shown in FIG. 1 may be filled with a conductive material to form a conductive layer 18 .

[0054] The first material layer 11 and the conductive layer 18 may be defined as a gate stack structure GST.

[0055] Figure 4 is a cross-sectional view illustrating a memory cell array of a semiconductor device according to an embodiment of the present disclosure.

[0056] Figure 1 The memory cell array 110 shown in FIG. 1 may include a memory block including a plurality of nonvolatile memory cells and Figure 4 0 illustrates a portion of a string included in a memory block.

[0057] refer to Figure 4 The string may include a plurality of nonvolatile memory cells MC, and the plurality of nonvolatile memory cells MC may be connected to a conductive layer CDL corresponding to a word line. Each of the plurality of nonvolatile memory cells MC may be configured to include a conductive layer CDL, a blocking insulating layer BOX, a charge trapping layer CTN, a tunnel insulating layer TIL, and a channel layer CHL.

[0058] An interlayer insulating layer ISL may be formed between the conductive layers CDL. The conductive layer CDL and the interlayer insulating layer ISL may extend in the X direction, which is a horizontal direction relative to the substrate. A gate stack structure GST including the conductive layer CDL and the interlayer insulating layer ISL may be formed. For example, the interlayer insulating layer ISL and the conductive layer CDL may be alternately stacked on top of a lower structure (not shown). The lower structure may include at least one of the following: a substrate, or a source line, a source selection line, and a peripheral circuit formed on the substrate. Each conductive layer CDL in the conductive layer CDL may be used as a word line or a selection line. For example, when the interlayer insulating layer ISL and the conductive layer CDL are alternately stacked on the substrate, the conductive layer CDL may include a word line and a selection line. The interlayer insulating layer ISL may be formed of an oxide, and the conductive layer CDL may be formed of a metal such as tungsten.

[0059] A vertical hole VH may be formed in the string, the vertical hole VH penetrating the interlayer insulating layer ISL and the conductive layer CDL in the Z direction which is a direction perpendicular to the substrate. The vertical hole VH may have a width that narrows as it approaches its bottom end. For example, the width VH_U of the bottom end of the vertical hole VH may be narrower than the width VH_T of the top end of the vertical hole VH.

[0060] Compared with the conductive layer CDL, the interlayer insulating layer ISL may protrude further in the direction adjacent to the vertical hole VH. That is, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL may be interposed in the space between the protruding portions of the interlayer insulating layers adjacent to each other in the Z direction which is a direction perpendicular to the substrate. That is, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL may be interposed between the conductive layer CDL and the vertical hole VH. In one embodiment of the present disclosure, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL may be defined as a memory structure.

[0061] The channel layer CHL may be formed along the sidewall of the vertical hole VH. For example, the channel layer CHL may be formed along the sidewall of the vertical hole VH (i.e., the sidewall of the interlayer insulating layer ISL and the tunnel insulating layer TIL). The insulating core layer CO may be formed in the central region of the vertical hole VH. In one embodiment of the present disclosure, the channel layer CHL and the insulating core layer CO may be defined as a vertical channel structure.

[0062] The tunnel insulating layer TIL may be a layer in which charges are tunneled by FN tunneling or the like, and includes an insulating material such as an oxide or a nitride. The charge trapping layer CTN may include a plurality of trapping sites, and in a programming operation, charges introduced while passing through the tunnel insulating layer TIL may be trapped in the charge trapping layer CTN. The charge trapping layer CTN may include a nitride, a chalcogenide, or a metal oxide. In one embodiment, the blocking insulating layer BOX may prevent or mitigate charges trapped in the charge trapping layer CTN from moving to the conductive layer CDL, and includes a high dielectric constant material such as aluminum oxide (Al2O3). 2 O 3 ), hafnium oxide (HfO x ) or hafnium silicon oxide (HfSiO x ). In one embodiment, the channel layer CHL may be used to allow current to flow in the string, and is formed of polysilicon.

[0063] The channel layer CHL may have a columnar structure extending in the vertical hole VH in the Z direction as a vertical direction.

[0064] The tunnel insulating layer TIL may be formed as a portion of an outer wall surrounding the channel layer CHL, and the tunnel insulating layer TIL corresponding to one nonvolatile memory cell MC may have a structure in which it is isolated from the tunnel insulating layer TIL corresponding to another nonvolatile memory cell MC by an interlayer insulating layer ISL, and the other nonvolatile memory cell MC is adjacent to the one nonvolatile memory cell MC in the Z direction which is a vertical direction.

[0065] The charge trapping layer CTN may be formed as an outer wall surrounding the tunnel insulating layer TIL, and the charge trapping layer CTN corresponding to one nonvolatile memory cell MC may have a structure isolated from the charge trapping layer CTN corresponding to another nonvolatile memory cell MC by an interlayer insulating layer ISL, the other nonvolatile memory cell MC being adjacent to the one nonvolatile memory cell MC in the Z direction which is a vertical direction. Therefore, in one embodiment, interference and disturbance phenomena between nonvolatile memory cells MC adjacent to each other in the Z direction may be reduced.

[0066] In addition, the blocking insulating layer BOX can be formed as an outer wall surrounding the charge trapping layer CTN, and the blocking insulating layer BOX corresponding to one nonvolatile memory cell MC can have a structure isolated from the blocking insulating layer BOX corresponding to another nonvolatile memory cell MC by an interlayer insulating layer ISL, and the other nonvolatile memory cell MC is adjacent to the one nonvolatile memory cell MC in the Z direction which is the vertical direction.

[0067] The vertical thickness T1 of the blocking insulating layer BOX corresponding to one nonvolatile memory cell MC, the vertical thickness T2 of the charge trapping layer CTN corresponding to the one nonvolatile memory cell MC, and the vertical thickness T3 of the tunnel insulating layer TIL corresponding to the one nonvolatile memory cell MC may be the same. The side wall of the interlayer insulating layer ISL in contact with the vertical hole VH may be located on the same line as the side wall of the tunnel insulating layer TIL in contact with the vertical hole VH, or the side of the interlayer insulating layer ISL in contact with the vertical hole VH may be formed to protrude further than the side wall of the tunnel insulating layer in contact with the vertical hole VH. In addition, the upper surface heights of the conductive layer CDL, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL corresponding to one nonvolatile memory cell MC may be the same. In addition, the lower surface heights of the conductive layer CDL, the blocking insulating layer BOX, the charge trapping layer CTN, and the tunnel insulating layer TIL corresponding to one nonvolatile memory cell MC may be the same.

[0068] FIG. 5A to FIG. 5H is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0069] refer to Figure 5A , a stacked structure ST may be formed on the substrate SUB. The stacked structure ST may include first material layers 21 and second material layers 22 that are alternately stacked. The first material layers 21 and the second material layers 22 may extend in an X direction that is a horizontal direction relative to the substrate SUB. The first material layers 21 and the second material layers 22 may be stacked in a Z direction that is a direction perpendicular to the substrate SUB. The first material layers 21 and the second material layers 22 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0070] The first material layer 21 may include a material having a high etching selectivity with respect to the second material layer 22. In one example, the first material layer 21 may include an insulating material such as an oxide, and the second material layer 22 may include a sacrificial material such as a nitride. In another example, the first material layer 21 may include an insulating material such as an oxide, and the second material layer 22 may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal.

[0071] Subsequently, a vertical hole VH penetrating the stack structure ST may be formed. The vertical hole VH may have a columnar shape extending in the Z direction. The vertical hole VH may be formed such that a width VH_T at a top end thereof is wider than a width VH_U at a bottom end thereof.

[0072] refer to Figure 5B, the sidewall of the second material layer 22 exposed by the vertical hole VH may be etched to a certain depth, thereby forming the first recessed region R1. That is, the sidewall of the second material layer 22 may be etched to a certain depth so that the first material layer 21 protrudes in the horizontal direction compared with the second material layer 22. Therefore, the sidewall of the vertical hole VH may be formed into a structure in which uneven portions are sequentially arranged in the Z direction which is a direction perpendicular to the substrate SUB.

[0073] refer to Figure 5C , the sidewall of each of the second material layers 22 exposed by the vertical hole VH can be oxidized by an oxidation process to form a blocking insulating layer 23. The oxidation process can be performed as a free radical oxidation process or a wet oxidation process. The sidewall of each of the second material layers 22 can be oxidized to a certain thickness by an oxidation process to form a blocking insulating layer 23.

[0074] refer to Figure 5D , a charge trapping source layer 24 may be formed along the sidewall of the vertical hole VH. The charge trapping source layer 24 may be formed by adjusting its thickness so that Figure 5C The first recessed region R1 shown in FIG. 2 is buried. The charge trapping source layer 24 may be formed such that the first recessed region R1 is completely buried or partially buried.

[0075] The charge trapping source layer 24 may include a charge trapping material, a nitride, a variable resistance material or nanostructure, a chalcogenide, or a metal oxide, or any combination thereof.

[0076] refer to Figure 5E , an etching process may be performed so that the charge trapping source layer ( Figure 5D 24) shown in FIG. 24) is retained only in the first recessed area ( Figure 5C In each first recessed region R1 shown in FIG. 1 , a charge trapping layer 24P is formed. That is, the charge trapping source layer ( Figure 5D 24) shown in the figure can be etched and removed, thereby forming a first recessed area ( Figure 5C The charge trapping layers 24P in R1) shown in FIG. 1 are physically and electrically isolated from each other. That is, the charge trapping layers 24P adjacent to each other in the Z direction may have a structure in which the charge trapping layers 24P are spaced apart from each other by one first material layer 21.

[0077] Thereafter, the charge trapping layer 24P exposed by the vertical hole VH may be etched to a certain thickness through an additional etching process to form a second recessed region R2. That is, the sidewall of the charge trapping layer 24P may be etched to a certain depth so that the first material layer 21 protrudes in the horizontal direction compared to the charge trapping layer 24P.

[0078] refer to Fig. 5F , it is possible to Figure 5E A tunnel insulating layer 25 is formed in each second recessed region in R2) shown in FIG. Through an oxidation process, the tunnel insulating layer 25 may be formed to contact the sidewall of each of the charge trapping layers 24P. The tunnel insulating layer 25 may be a layer through which charges are tunneled by FN tunneling or the like, and includes an insulating material such as oxide or nitride.

[0079] refer to Figure 5G , can be along the vertical hole ( Fig. 5F The sidewall of the VH) shown in FIG. 1 forms a channel layer 26. The channel layer 26 may include polysilicon.

[0080] The channel layer 26 may be formed along the sidewalls of the first material layer 21 and the sidewalls of the tunnel insulating layer 25. The channel layer 26 may be formed to extend in the Z direction.

[0081] Thereafter, an insulating core layer 27 may be formed so that the vertical holes ( Fig. 5F The central region of the VH) shown in FIG. 1 is filled with an insulating core layer 27. The insulating core layer 27 may include an oxide. Fig. 5F When the central area of ​​VH) shown in FIG. 1 is filled with the channel layer 26, the process of forming the insulating core layer 27 can be skipped.

[0082] refer to Figure 5H , the second material layer ( Figure 5G 22) shown in FIG. 2 can be replaced by a conductive layer 28. For example, the stacked structure ( Figure 5G ST) is etched to form a slit extending in the X direction, thereby exposing the second material layer ( Figure 5G Thereafter, the second material layer ( Figure 5G 22) shown in FIG. 2 can be selectively etched and removed, and the second material layer ( Figure 5G The space 22) shown in FIG. 2 may be filled with a conductive material to form a conductive layer 28.

[0083] The first material layer 21 and the conductive layer 28 may be defined as a gate stack structure GST.

[0084] Figure 6is a block diagram illustrating a solid state drive (SSD) system to which the semiconductor device of the present disclosure is applied.

[0085] refer to Figure 6 , the SSD system 2000 includes a host 2100 and an SSD 2200. The SSD 2200 can exchange signals with the host 2100 through a signal connector 2001, and be supplied with power through a power connector 2002. The SSD 2200 includes a controller 2210, a plurality of memory devices 2221 to 222n, an auxiliary power supply 2230, and a buffer memory 2240.

[0086] The controller 2210 may control the plurality of memory devices 2221 to 222n in response to a signal received from the host 2100. For example, the signal may be transmitted based on an interface between the host 2100 and the SSD 2200. For example, the signal may be defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0087] The plurality of memory devices 2221 to 222n may be configured to store data and include a plurality of nonvolatile memory cells. Each of the plurality of memory devices 2221 to 222n may be connected to Figure 1 The semiconductor device 1100 shown in FIG. 1 is configured identically.

[0088] The auxiliary power supply 2230 may be connected to the host 2100 through the power connector 2002. The auxiliary power supply 2230 may receive power input from the host 2100 and be charged with the input power. When the supply of power from the host 2100 is not stable, the auxiliary power supply 2230 may provide power to the SSD 2200. For example, the auxiliary power supply 2230 may be located in the SSD 2200, or located outside the SSD 2200. For example, the auxiliary power supply 2230 may be located on the mainboard and provide auxiliary power to the SSD 2200.

[0089] The buffer memory 2240 may be used as a buffer memory of the SSD 2200. For example, the buffer memory 2240 may temporarily store data received from the host 2100 or data received from the plurality of memory devices 2221 to 222n, or store metadata (e.g., a mapping table) of the plurality of memory devices 2221 to 222n. The buffer memory 2240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0090] According to an embodiment of the present disclosure, charge trapping layers of a plurality of memory cells stacked in a vertical direction are electrically and physically spaced apart from each other, thereby reducing interference and disturbance phenomena between memory cells adjacent to each other in the vertical direction.

[0091] Although the present disclosure has been shown and described with reference to certain embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0092] In the above-described embodiments, all steps may be selectively performed, or some steps in the steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0093] Meanwhile, embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, those specific terms are only used to explain embodiments of the present disclosure. Therefore, the present disclosure is not restricted to the above-described embodiments, and within the spirit and scope of the present disclosure, many variations are possible. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

Claims

1. A semiconductor device comprising: A gate stack structure, comprising alternately stacked interlayer insulating layers and conductive layers; a channel structure extending in a vertical direction in the gate stack structure; as well as a memory structure interposed between the conductive layer and the channel structure, Each of the memory structures comprises a blocking insulating layer and a charge trapping layer, wherein the blocking insulating layer and the charge trapping layer are sequentially formed on the sidewalls of each of the conductive layers, and The side wall of the interlayer insulating layer in contact with the channel structure is located on the same line as the side wall of the charge trapping layer in contact with the channel structure, or the side of the interlayer insulating layer in contact with the channel structure protrudes further toward the channel structure than the side wall of the charge trapping layer.

2. The semiconductor device according to claim 1, wherein the interlayer insulating layer protrudes further toward the channel structure than the conductive layer, and wherein the blocking insulating layer and the charge trapping layer are interposed in a space between the protruding interlayer insulating layers.

3. The semiconductor device according to claim 1, The charge trapping layers formed on the side walls of the corresponding conductive layers are spaced apart from each other.

4. The semiconductor device according to claim 1, The upper surfaces of the blocking insulating layer and the charge trapping layer corresponding to any one of the conductive layers are substantially the same in height.

5. The semiconductor device according to claim 1, The lower surfaces of the blocking insulating layer and the charge trapping layer corresponding to any one of the conductive layers are substantially the same in height.

6. The semiconductor device according to claim 1, The channel structure comprises: a tunnel insulating layer extending in the vertical direction along the sidewalls of the interlayer insulating layer and the sidewalls of the charge trapping layer; as well as The channel layer extends in the vertical direction along the sidewall of the tunnel insulating layer.

7. A method for manufacturing a semiconductor device, the method comprising: forming a vertical hole that penetrates at least a portion of a stacked structure in which first material layers and second material layers are alternately stacked; forming a recessed area by etching a sidewall of the second material layer exposed by the vertical hole to a certain thickness; forming a blocking insulating layer by oxidizing the sidewall of the second material layer exposed through the recessed area; forming charge trapping layers in the corresponding recessed regions, wherein the charge trapping layers are spaced apart from each other in a vertical direction by the first material layer; as well as A tunnel insulating layer and a channel layer are sequentially formed along the sidewalls of the vertical hole.

8. The method according to claim 7, When forming the blocking insulating layer, the sidewall of the second material layer is oxidized to a certain thickness through a free radical oxidation process or a wet oxidation process to form the blocking insulating layer.

9. The method according to claim 7, The vertical thickness of the second material layer, the vertical thickness of the blocking insulating layer and the vertical thickness of the charge trapping layer are substantially the same.

10. The method according to claim 7, further comprising: After forming the channel layer, the second material layer is replaced by a conductive layer.

11. The method according to claim 7, The height of the upper surface of the second material layer, the height of the upper surface of the blocking insulating layer and the height of the upper surface of the charge trapping layer are substantially the same, and the height of the lower surface of the second material layer, the height of the lower surface of the blocking insulating layer and the height of the lower surface of the charge trapping layer are substantially the same.

12. A semiconductor device comprising: A gate stack structure comprising alternately stacked interlayer insulating layers and conductive layers; a channel structure extending in a vertical direction in the gate stack structure; as well as a memory structure interposed between the conductive layer and the channel structure, Each of the memory structures comprises a blocking insulating layer, a charge trapping layer and a tunnel insulating layer, wherein the blocking insulating layer, the charge trapping layer and the tunnel insulating layer are sequentially formed on the sidewalls of each of the conductive layers, and The sidewall of the interlayer insulating layer in contact with the channel structure is located on the same line as the sidewall of the tunnel insulating layer in contact with the channel structure, or the side of the interlayer insulating layer in contact with the channel structure protrudes further toward the channel structure than the sidewall of the tunnel insulating layer.

13. The semiconductor device according to claim 12, wherein the interlayer insulating layer protrudes further toward the channel structure than the conductive layer, and The blocking insulating layer, the charge trapping layer and the tunnel insulating layer are interposed in a space between the protruding interlayer insulating layers.

14. The semiconductor device according to claim 12, The charge trapping layers formed on the side walls of the corresponding conductive layers are spaced apart from each other.

15. The semiconductor device according to claim 12, The top surfaces of the blocking insulating layer, the charge trapping layer and the tunnel insulating layer corresponding to any one of the conductive layers are substantially the same in height.

16. The semiconductor device according to claim 12, The lower surfaces of the blocking insulating layer, the charge trapping layer and the tunnel insulating layer corresponding to any one of the conductive layers are substantially the same in height.

17. A method for manufacturing a semiconductor device, the method comprising: forming a vertical hole that penetrates at least a portion of a stacked structure in which first material layers and second material layers are alternately stacked; forming a first recessed area by etching a sidewall of the second material layer exposed by the vertical hole to a certain thickness; forming a blocking insulating layer by oxidizing the sidewall of the second material layer exposed by the first recessed area; forming charge trapping layers in the corresponding first recessed regions, wherein the charge trapping layers are spaced apart from each other in a vertical direction by the first material layer; forming a second recessed region by etching a sidewall of the charge trapping layer exposed by the vertical hole to a certain thickness; forming a tunnel insulating layer in the corresponding second recessed region; as well as A channel layer is formed along the sidewalls of the vertical hole.

18. The method according to claim 17, When forming the blocking insulating layer, the sidewall of the second material layer is oxidized to a certain thickness through a free radical oxidation process or a wet oxidation process to form the blocking insulating layer.

19. The method according to claim 17, further comprising: After forming the channel layer, the second material layer is replaced by a conductive layer.

20. The method according to claim 17, wherein the height of the upper surface of the second material layer, the height of the upper surface of the blocking insulating layer, the height of the upper surface of the charge trapping layer and the height of the upper surface of the tunnel insulating layer are substantially the same, and the height of the lower surface of the second material layer, the height of the lower surface of the blocking insulating layer, the height of the lower surface of the charge trapping layer and the height of the lower surface of the tunnel insulating layer are substantially the same.

Images