High speed TX topology with common mode controlled serialization stage embedded in output stage

Abstract

A high speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, a transmitter comprises: a serialization circuit configured to convert parallel data into serial data using one or more serialization stages; a logic circuit configured to connect each input of a last one of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of the output circuit via a respective logic function; and an output circuit configured to implement an output stage using an NMOS transistor to generate a signal based on the received input. Furthermore, the logic circuit is configured to a desired voltage value (e.g., a common mode of the output circuit) such that the switching point of the NMOS gm stage can be reduced and the gm stage can be activated for a reduced time.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 340,370, filed on May 10, 2022, entitled “High Speed ​​Tx Topology with a Common Mode Controlled Serialization Stage Embedded in the Output Stage,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a transmitter system that uses a common-mode controlled serialization stage embedded in an output stage, thereby achieving fast operation and high reliability. background

[0003] The transmitter (Tx) is an important part of the physical layer communication system. It is an electronic component that converts the digital signal from the encoder into an analog signal, which can be propagated through the transmission medium (e.g., wired, wireless channel) and received by the receiver (Rx). The data transmitted by the Tx is usually generated by the logic part. Typically, the logic part generates data at a speed much lower than the data rate that the Tx can handle. Therefore, parallel input, serial output (PISO) conversion is widely used in Tx to achieve the required data rate. Serialization is usually implemented by a chain of multiplexers (mux) to output a single signal with a high frequency. However, this topology (especially the last mux) has significant speed limitations and therefore can hardly or cannot meet the speed requirements of cutting-edge Tx systems. Overview

[0004] To address the above shortcomings, a high-speed transmitter system using a common-mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes: a serialization circuit configured to convert parallel data into serial data using one or more serialization stages; a logic circuit configured to connect each input of the last stage of the one or more serialization stages of the serialization circuit to a corresponding dedicated output stage of the output circuit via a corresponding logic function; and an output circuit configured to implement the output stage using NMOS transistors to generate a signal based on the received input. In addition, the logic circuit is configured to a desired voltage value (e.g., the common mode of the output circuit) so that the switching point of the NMOS gm stage can be lowered and the gm stage can be activated in a reduced time.

[0005] The above and other preferred features, including various novel implementation details and combinations of elements, will now be described in more detail with reference to the accompanying drawings and pointed out in the claims. It should be understood that the specific methods and devices are shown only by way of illustration and not as limitations. As will be appreciated by those skilled in the art, the principles and features explained herein can be used in various and numerous embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The disclosed embodiments have advantages and features that will be more readily apparent from the detailed description, the appended claims, and the accompanying drawings (or figures). The following is a brief description of the drawings.

[0007] Figure 1 An exemplary topology of a digital-to-analog converter (DAC) of a Tx is shown in accordance with some embodiments.

[0008] Figure 2 An exemplary n:1 level load is shown in accordance with some embodiments.

[0009] Figure 3 An exemplary n:1 circuit for reducing data load and increasing data processing speed according to some embodiments is shown.

[0010] Figure 4 An exemplary n:1 circuit is shown in which the grounding of the logic circuit is controllable according to some embodiments.

[0011] Figure 5 An exemplary process for configuring and implementing a transmitter having a common-mode controlled serialization stage embedded in the output stage is shown. Detailed Description

[0012] The drawings and the following description relate to preferred embodiments by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will readily be recognized as viable alternatives that can be employed without departing from the principles of the claimed invention.

[0013] Reference will now be made in detail to some embodiments, examples of which are shown in the accompanying drawings. Note that similar or like reference numerals may be used in the drawings whenever possible, and similar or like functions may be indicated. The drawings depict embodiments of the disclosed systems (or methods) for illustrative purposes only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods shown herein may be employed without departing from the principles described herein.

[0014] Figure 1An exemplary DAC-based Tx topology 100 is shown. It should be noted that while a DAC-based Tx is presented, in the present disclosure, the systems and methods described herein are not limited to only DAC-based Tx topologies, but to all Tx topologies using analog output drivers. Figure 1 The example DAC-based Tx in Figure 1 consists of three parts (a), (b), and (c). Figure 1 In (a), the logic section or data acquisition circuit generates the data for Tx transmission. In this example, the data is generated in m parallel branches or links.

[0015] The data generated in the m parallel branches has a data rate significantly lower than the data rate of TX (e.g., as in Figure 1 , which is 1 / 160 of the data rate of TX). As mentioned above, due to this low-speed data generation from the logic part, Tx usually uses PISO to increase the data rate. PISO allows data to be converted from a parallel format to a serial format. Data is loaded to Tx in a parallel format, which means that the data bits are generated and presented simultaneously in multiple low-speed branches (e.g., separate lines). The data is then output after serialization, which means that the data bits are output sequentially in time on a single line or branch. In other words, PISO conversion can allow parallel received data to be stored, shifted based on the clock, and delayed by a number of stages multiplied by the clock period until a single data sequence is obtained. Figure 1 (b) shows PISO or serialization, where data with a lower rate is serialized to achieve the higher data rate required for Tx.

[0016] like Figure 1 As depicted in (b), the serialization process can be implemented by a chain of multiplexers (e.g., mux 102, 104, and 106). Each mux is controlled by a clock phase so that the correct data can be routed to the output at the appropriate time. The result of the serialization process is a single signal with a high frequency. Unfortunately, this topology (mainly the last mux) is limited in speed, which generally cannot meet the speed requirements of Tx. The inventive system described herein solves the speed limitation problem and significantly improves system performance.

[0017] In some embodiments, once the data is serialized, the output stage 112 is driven to convert the input serialized data 108 into an analog signal 110, such as Figure 1 (c) as shown.

[0018] In non-return-to-zero (NRZ) Tx, each analog symbol is represented by a single logical bit. But in DAC-based Tx and when equalization is used, each analog symbol can include multiple digital bits, where the combination of digital bits creates the analog symbol. As can be seen in Figure 1As seen in FIG. 1 , analog symbol 110 may be generated by m analog stages, where m is a positive integer. In this example, the m analog stages are transconductance (gm) stages. Analog or gm stage 112 is fed digital data 108. The output of the analog / gm stage is short-circuited to a common resistor load, which then produces analog symbol 110, as shown in FIG. Figure 1 In contrast, NRZ Tx has only a single gm level because each analog symbol is represented by a single bit.

[0019] Figure 1 (For example Figure 1 (b) shows a method for implementing serialization. Serialization is performed in multiple chained stages. As the number of parallel data branches decreases in the next stage (e.g., mux 104 operates after mux 102), the data rate increases. The number of parallel data branches continues to decrease until the serialization proceeds to the last serialization stage, where the remaining parallel data branches are serialized to a single data branch at a high data rate (e.g., 108). This last serialization stage is the most challenging because it operates at the highest speed.

[0020] In some embodiments, the load of the last PISO or serialization stage is the other "closed" branches of the last PISO or serialization stage and the subsequent analog buffers. Figure 2 Shows Figure 1 The last serialization stage 200 of the embodiment of the present invention comprises an "n to 1" or n:1 mux, such as Figure 1 (b) shows a 4:1 mux 106. The n:1 mux has n-1 “off” passgates (e.g., n-1 branches that are turned off) and a gm stage. This load is typically too heavy to support the high-speed data rates found in cutting-edge Tx. For example, a fin field effect transistor (FinFET) based Tx can process data at speeds exceeding tens of gigahertz (GHz). It is important to note that this speed issue exists in the same way in both NRZ and DAC-based topologies. Therefore, although the solution to the speed issue is described in the context of a DAC-based topology in this article, the solution is also applicable to NRZ as well as other topologies.

[0021] A conventional way to reduce the load and achieve the required bandwidth is to reduce the size of the transistor. However, this will cause the signal to be attenuated. The attenuated signal needs to be compensated by a large amount of power consumption, which further leads to significant reliability issues.

[0022] Figure 3 An example n:1 (eg, 4:1) circuit structure 300 is shown. The structure is Figure 1 An improved configuration of the last PISO stage in Figure 3 As depicted, in some embodiments, the speed limitation of the last PISO stage can be addressed by having each input 302 of the last PISO stage connected to a dedicated analog stage 304 (e.g., a gm stage) through a logic function or unit 306. The input 302 is connected to the analog stage 304 with an associated clock phase (not shown) so that the analog stage 304 can be activated at the appropriate time. For example, the logic function can be an AND function between the input 302 and the associated clock phase. As described above in Figure 1 (b) and Figure 2 As shown in , the last PISO stage is a 4:1 mux 106. Using this 4:1 mux as an example, Figure 3 In the example, the four-bit input of the 4:1 mux 106 can be connected to four logic functions and four gm stages. Figure 1 In the example DAC topology in , this occurs m times. Figure 3 The structure can reduce the data load and increase the processing speed. In addition, connecting each bit to a dedicated analog stage allows gain mismatch calibration for each bit.

[0023] like Figure 3 As shown, transistors can be used to amplify or switch electrical signals and power. A transistor typically includes at least three terminals (e.g., 308, 310, and 312) for connecting to an electronic circuit. When a voltage is applied to the transistor, it can control the current through a pair of terminals. For example, when a voltage is applied to the gate 308 of the transistor, it generates an electric field that controls the flow of charge carriers (e.g., electrons) between the source 310 (e.g., the terminal where the current enters the transistor) and the drain 312 (e.g., the terminal where the current leaves the transistor). Because the output power can be higher than the control or input power, the transistor can amplify the signal to obtain an output signal 314.

[0024] When the gm stage is used for an analog stage, the voltage at the source of the input pair is the drain voltage of the current source, i.e., V ds This shows that, in order to operate the gm stage, the gate voltage should be higher than the current source voltage V ds With the transistor's V t Since the logic function / cell 306 is at ground (V ss ) and the supply voltage (V dd ), so it may take some time for gate 308 to switch from V ss Charge to V ds +V t The gate charging time is not negligible for cutting-edge Tx systems, thus adversely affecting Tx performance in terms of speed, gain, efficiency, etc.

[0025] The transmitter topology in the present disclosure is further improved to address this shortcoming, as shown in reference Figure 4 Specifically, the ground of the logic circuit is controllable and can therefore be easily raised to approach the switching point of the NMOS gm stage. Figure 4 In the scenario where the ground of the logic circuit / function 402 driving the analog output circuit / unit is not V ss In contrast, the ground of the logic circuit is derived from the common mode of the analog circuit, as shown at 404. This means that the output of the logic circuit 402 will switch near the switching point of the analog circuit 406. The switching point is the point (e.g., a specific voltage value) at which the circuit of the analog output stage 406 is turned on. As a result, the activation of the analog circuit can be much faster, and the on-period of the analog circuit can be longer.

[0026] In the system of the present invention, the analog stage or analog output stage is implemented using NMOS devices / transistors, that is, the analog gm stage is an NMOS-based stage. NMOS transistor or NMOS refers to an n-channel metal oxide semiconductor (MOS) field effect transistor (MOSFET). An NMOS transistor may include three terminals, such as a gate 408, a source 410, and a drain 412, such as Figure 4 When the gate voltage is higher than the source voltage plus the threshold voltage, the NMOS transistor is turned on (eg, turned on). If the ground of the logic circuit 402 is set to zero, its output is between zero and the power supply voltage V dd In this case, to activate the analog gm stage 406, i.e., to turn on the NMOS transistor, the gate voltage of gm must be raised from zero to the V t The voltage V of the current source d The sum of V d +V t This rise time may be too long for effective transmitter operation. Figure 4 As shown, the system of the present invention derives the ground of the logic circuit 402 from the common mode of the analog circuit 406 through the analog function 414. That is, the ground of the logic function is configured to be close to a specified desired voltage, such as V d Therefore, when the gate voltage increases by only V t When the analog gm stage 406 can be activated, this significantly shortens the stage activation time, thereby enabling the analog stage to operate much faster and improve operating efficiency.

[0027] Figure 4Another feature of the topology shown is the use of an external reference voltage 416. This external reference voltage 416 can be used to force the input common mode of the analog stage 406 to any desired voltage. In addition, the external reference voltage 416 can ensure that the current source remains in saturation mode. Moreover, since the external reference voltage 416 controls the ground, it can be further used to determine the output range of the digital circuit. Therefore, the use of an external reference voltage can increase the transmitter speed and gain, obtain the desired current, and improve the common mode rejection ratio (CMRR).

[0028] System Flowchart The inventive system discloses a transmitter topology having a common-mode controlled serialization stage embedded in the output stage, which not only improves the operating speed, but also improves the transmitter gain, stability, etc. In order to achieve these technical advances, the inventive system includes several different features. The inventive transmitter system uses a unique gm stage for each bit in the last serialization stage, so that the speed limitation associated with the last stage can be eliminated. This unique connection feature alone can solve the speed problems existing in various types of transmitters (e.g., DAC transmitters, NRZ transmitters). In addition, the inventive transmitter system uses an NMOS-based gm stage to generate analog signals. Specifically, the ground of the logic circuit based on the NMOS gm stage that drives the analog circuit is derived from the common mode of the analog circuit. Therefore, in order to turn on the NMOS transistor and thus activate the analog gm stage, the gate voltage of gm is only increased by V t Instead of V d +V t This reduces the activation time of the GM stage, thereby speeding up GM stage operation and further improving transmitter performance.

[0029] Figure 5 An exemplary process 500 for configuring and implementing a transmitter having a common-mode controlled serialization stage embedded in an output stage is shown. In some embodiments, the transmitter includes data acquisition circuitry, serialization circuitry, logic circuitry, and output circuitry that are electrically and communicatively coupled to operate in a fast and reliable manner.

[0030] In some embodiments, the transmitter can be a DAC transmitter, an NRZ transmitter, etc. In the context of a DAC transmitter, a data acquisition circuit can generate or collect digital data associated with multiple data branches. Serialization circuits and logic circuits can receive data from these data branches in parallel and convert the received data into a single data sequence for enabling an output circuit to generate a signal, such as an analog signal.

[0031] At step 505, data from a plurality of data branches is received at a serialization circuit. The serialization circuit may include one or more serialization stages, such as Figure 1(b) depicted. The last stage in the serialization stage (e.g., Figure 1 The 4:1 mux implementation in (b) typically lacks the ability to handle large data loads at the required high data rates, resulting in degraded performance.

[0032] At step 510, the logic circuit connects each input of the last stage to a corresponding dedicated output stage of the output circuit via a corresponding logic function. For example, if the last stage is a 4:1 mux, four bits of data are connected to four logic functions and four gm stages. In this way, data load is reduced and processing speed is increased.

[0033] At step 515, the output circuit uses an NMOS to implement an output stage to generate a signal based on the received input. In some embodiments, the output stage is a gm stage based on NMOS. The grounding of the logic circuit is configured to a desired voltage value, for example, the common mode of the output circuit. By deriving the grounding of the logic circuit from the common mode of the output circuit, the switching point of the NMOS gm stage is reduced so that the gm stage can be activated in a reduced time, thereby further speeding up the transmitter operation. In some embodiments, each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.

[0034] Additional Considerations In some implementations, at least a portion of the above methods may be implemented by instructions that, when executed, cause one or more processing devices to perform the above processes and functions. Such instructions may include, for example, interpreted instructions, such as script instructions or executable code, or other instructions stored in a non-transitory computer-readable medium. The storage device 830 may be implemented in a distributed manner over a network, such as as a server farm or a group of widely distributed servers, or may be implemented in a single computing device.

[0035] Although an example processing system has been described, the embodiments, functional operations, and processes of the subject matter described in this specification may be implemented in other types of digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more computer program instruction modules encoded on a tangible non-volatile program carrier for execution by a data processing device or for controlling the operation of the data processing device. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical signal, optical signal, or electromagnetic signal) that is generated to encode information for transmission to an appropriate receiver device for execution by a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0036] The term "system" may cover all kinds of devices, apparatuses and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. A processing system may include special-purpose logic circuits, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, a processing system may also include code that creates an execution environment for the computer program in question, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0037] A computer program (which may also be referred to or described as a program, software, software application, module, software module, script or code) may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it may be deployed in any form, including deployment as a standalone program or as a module, component, subroutine or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing portions of one or more modules, subroutines or code). A computer program may be deployed to execute on one computer or on multiple computers that are located at one location or distributed at multiple locations and interconnected by a communication network.

[0038] The processes and logic flows described in this specification may be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by, and the apparatus may also be implemented as, a special purpose logic circuit, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0039] As an example, a computer suitable for executing a computer program may include a general or special microprocessor or both, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory or a random access memory or both. A computer typically includes a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data or be operably coupled to receive data from one or more mass storage devices for storing data or to transfer data to it or both. However, a computer does not need to have such a device. In addition, to name just a few examples, a computer may be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive).

[0040] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including, for example: semiconductor memory devices, such as EPROM, EEPROM and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0041] To provide interaction with a user, embodiments of the subject matter described in this specification may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube), or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input). In addition, the computer may interact with the user by sending documents to and receiving documents from a device used by the user; for example, by sending a web page to a web browser on a user device of the user in response to a request received from the web browser.

[0042] Embodiments of the subject matter described in this specification may be implemented in a computing system that includes a back-end component (e.g., as a data center) or includes a middleware component (e.g., an application server) or includes a front-end component (e.g., a client computer with a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described in this specification) or any combination of one or more such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks (LANs) and wide area networks (WANs), such as the Internet.

[0043] A computing system may include clients and servers. Generally speaking, clients and servers are remote from each other and usually interact through a communication network. The relationship between client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0044] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular embodiment. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0045] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in order, or to perform all operations shown, to achieve desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of the various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can be integrated together in a single software product or packaged into multiple software products.

[0046] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order or sequence shown to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous. Additional steps or levels may be provided for the described processes, or steps or levels may be eliminated. Therefore, other implementations are within the scope of the appended claims.

[0047] The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0048] The term "about", the phrase "approximately equal to" and other similar phrases (e.g., "X has a value of approximately Y" or "X is approximately equal to Y") as used in the specification and claims should be understood to mean that one value (X) is within a predetermined range of another value (Y). Unless otherwise specified, the predetermined range may be plus or minus 20%, 10%, 5%, 3%, 1%, 0.1%, or less than 0.1%.

[0049] As used in the specification and claims, the indefinite articles "a" and "an" shall be understood to mean "at least one" unless clearly indicated to the contrary. As used in the specification and in the claims, the phrase "and / or" shall be understood to mean "any one or both" of the elements so combined, i.e., elements present in combination in some cases and separately in other cases. Multiple elements listed with "and / or" should be interpreted in the same manner, i.e., "one or more" of the elements so combined. In addition to the elements specifically referred to by the "and / or" clause, other elements may optionally be present, whether related or unrelated to those specifically referred to. Thus, as a non-limiting example, a reference to "A and / or B", when used in conjunction with open language such as "comprising", may refer to only A (optionally including elements other than B) in one embodiment; to only B (optionally including elements other than A) in another embodiment; to both A and B (optionally including other elements) in yet another embodiment, and so on.

[0050] As used in the specification and in the claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" should be interpreted as inclusive, that is, including at least one element, but also including multiple elements or more than one element in a list of elements, and optionally, including additional unlisted items. Unless the term clearly indicates the opposite meaning, for example, "only one of..." or "only one of..." or when "consisting of..." is used in the claims, it will refer to including multiple elements or only one element in a list of elements. Generally, the term "or", as used, when guided by exclusive terms such as "any one", "one of...", "only one of..." or "only one of...", should only be interpreted as indicating an exclusive alternative form (i.e., "one or the other but not both"). When "consisting of..." is used in the claims, it should have its ordinary meaning used in the field of patent law.

[0051] As used in the specification and in the claims, the phrase "at least one" when used for a list of one or more elements should be understood to refer to at least one element selected from any one or more elements in the list of elements, but does not necessarily include at least one of each element specifically listed in the list of elements, and does not exclude any combination of elements in the list of elements. This definition also allows that elements other than the elements specifically identified in the list of elements to which the phrase "at least one" refers may optionally be present, whether related or unrelated to those specifically identified elements. Thus, as a non-limiting example, "at least one of A and B" (or, equivalently "at least one of A or B", or equivalently "at least one of A and / or B") may refer to at least one, optionally including more than one A, without B present (and optionally including elements other than B) in one embodiment; to at least one, optionally including more than one B, without A present (and optionally including elements other than A) in another embodiment; to at least one, optionally including more than one A, and at least one, optionally including more than one B (and optionally including other elements) in yet another embodiment, and so on.

[0052] The use of "including," "comprising," "having," "including," "involving," and variations thereof herein are meant to encompass the items listed thereafter as well as additional items.

[0053] The use of ordinal terms such as "first," "second," "third," etc., in the claims to modify claim elements does not, by itself, imply any priority, precedence, or order of one claim element relative to another claim element or the temporal order in which the actions of the method are performed. Ordinal terms are used solely as labels to distinguish one claim element having a particular name from another element having the same name (but with respect to the use of the ordinal terms) to distinguish claim elements.

[0054] Having thus described several aspects of at least one embodiment of the present invention, it will be appreciated that various changes, modifications and enhancements will readily occur to those skilled in the art. Such changes, modifications and enhancements are intended to be a part of this disclosure and are intended to be within the spirit and scope of the present invention. Therefore, the foregoing description and accompanying drawings are intended only as examples.

Claims

1. A transmitter, comprising: a serialization circuit configured to convert the parallel data to serial data using one or more serialization stages; a logic circuit electrically coupled to the serialization circuit and the output circuit, the logic circuit configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of the output circuit via a respective logic function; as well as The output circuit is configured to implement an output stage using an n-channel metal oxide semiconductor (NMOS) field effect transistor to generate a signal based on a received input, wherein a ground of the logic circuit is configured to a desired voltage value.

2. The transmitter according to claim 1, wherein The dedicated output stage is an NMOS based transconductance (gm) stage.

3. The transmitter according to claim 2, wherein: By configuring the ground of the logic circuit to the desired voltage value, the switching point of the NMOS gm stage is lowered so that the gm stage can be activated in a reduced time, The switching point is the threshold voltage value at which the NMOS transistor turns on, and The desired voltage value includes a common mode of the output circuit.

4. The transmitter according to claim 1, wherein: The serialization circuit includes a series of multiplexers in the one or more serialization stages, The last serialization stage is an n:1 multiplexer, and The logic circuit is configured to connect the n-bit input from the last serialization stage to the n gm stages through n logic functions.

5. The transmitter according to claim 4, wherein: The inputs of the last serialization stage are connected to the corresponding output stages with related clock phases.

6. The transmitter according to claim 5, wherein: The serialization circuit and the output circuit are connected by the logic circuit in a manner that reduces the data load of the last serialization stage and increases the operating speed of the transmitter.

7. The transmitter according to claim 1, wherein: Each output stage is fed with digital data and outputs to a common resistor load to generate an analog symbol.

8. The transmitter according to claim 1, further comprising: a data acquisition circuit configured to generate the parallel data in a plurality of data branches, The serialization circuit and the logic circuit are configured to convert the parallel data received from the plurality of data branches into a single data sequence.

9. The transmitter according to claim 1, wherein: The transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return-to-zero (NRZ) transmitter, or other types of transmitters.

10. The transmitter according to claim 1, wherein: The logic circuit is connected to an external reference voltage and is adjusted to enable the current source to operate in saturation.

11. A method for configuring and implementing a transmitter, comprising: receiving data in parallel from a plurality of data branches by a serialization circuit, the serialization circuit comprising one or more serialization stages; connecting each input of a last stage of the one or more serialization stages to a respective dedicated output stage of the output circuit via a respective logic function of the logic circuit; as well as An output stage is implemented by the output circuit using an n-channel metal oxide semiconductor (NMOS) field effect transistor to generate a signal based on a received input, wherein a ground of the logic circuit is configured to a desired voltage value.

12. The method according to claim 11, wherein: The dedicated output stage is an NMOS based transconductance (gm) stage.

13. The method according to claim 12, further comprising: By configuring the ground of the logic circuit to the desired voltage value, the switching point of the NMOS gm stage is lowered so that the gm stage can be activated in a reduced time, The switching point is the threshold voltage value at which the NMOS transistor turns on, and The desired voltage value includes the common mode of the output circuit.

14. The method according to claim 11, further comprising: configuring a series of multiplexers in the one or more serialization stages of the serialization circuit, wherein the last serialization stage is an n:1 multiplexer, and The n-bit input from the last serialization stage is connected to n gm stages by the logic circuit through n logic functions.

15. The method according to claim 14, wherein: The inputs of the last serialization stage are connected to the corresponding output stages with related clock phases.

16. The method according to claim 15, wherein: The serialization circuit and the output circuit are connected by the logic circuit in a manner that reduces the data load of the last serialization stage and increases the operating speed of the transmitter.

17. The method according to claim 11, wherein: Each output stage is fed with digital data and outputs to a common resistor load to generate an analog symbol.

18. The method according to claim 11, further comprising: generating the data in the plurality of data branches, and The data received in parallel from the plurality of data branches is converted into a single data sequence.

19. The method according to claim 12, wherein: The transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return-to-zero (NRZ) transmitter, or other types of transmitters.

20. The method of claim 12, further comprising: connecting the logic circuit to an external reference voltage; as well as The logic circuit is adjusted to enable the current source to operate in a saturation state.

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