Programming method of memory device, memory device, and memory system

Abstract

The invention provides a programming method, a memory device and a memory system. The method includes dividing target programming states into N groups based on a coupling offset, each group corresponding to a different first programming state, with an ith group having Ki different target programming states and corresponding to an ith first programming state. The at least two sets of target programming states have two different numbers of target programming states. The method further includes performing a first program operation to program the memory cells to respective first program states; and performing a second program operation to program the i-th group of memory cells in the i-th first program state to Ki different target program states.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS AND INCORPORATION BY REFERENCE

[0002] This application claims priority to Chinese patent application No. 202210203975.9 filed on March 3, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of memory, and relates to, but is not limited to, a programming method of a memory device, a memory device, and a memory system. Background Art

[0004] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells.

[0005] In a 3D NAND memory device, a memory array may include a plurality of memory strings arranged vertically on a substrate, each memory string having a plurality of memory cells stacked vertically. Thus, the storage density per unit area may be greatly increased. In a 3D NAND memory device, memory cells sharing the same word line may be programmed and read simultaneously.

[0006] In order to further increase the storage capacity in the 3D NAND memory device, each memory cell can be programmed in a multi-level manner. For example, in a multi-level cell flash memory (multi-level cell, MLC) mode, each memory cell can store 2 bits of data. In a triple-level cell flash memory (triple-level cell, TLC) mode, each memory cell can store 3 bits of data. And in a quad-level cell flash memory (quad-level cell, QLC) mode, each memory cell can store 4 bits of data. As the number of bits stored in each memory cell increases, the time required to program the memory device also increases. In addition, when the number of bits stored in the memory cell increases, the read margin decreases. Therefore, a method for effectively programming a memory cell and more accurately reading it after programming is needed. Summary of the invention

[0007] Embodiments of a programming method of a memory device, a memory device, and a memory system are described in the present disclosure.

[0008] One aspect of the present disclosure provides a programming method for a memory device. The method includes performing a first programming operation on a memory cell to be programmed, so that each memory cell is programmed to a corresponding first programming state of N different first programming states; wherein N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory cell. The method also includes performing a second programming operation on a subset of memory cells in the i-th first programming state, so that the subset of memory cells is programmed from the i-th first programming state to k target programming states, wherein k is greater than or equal to 1 and less than n; and i is greater than or equal to 1, and less than or equal to N. At least two first programming states correspond to different k values.

[0009] In some embodiments, the method further includes dividing the target programming state into N groups corresponding to the N first programming states. The division of the N groups is based on the coupling offset of the target programming state caused by the first and / or second programming operations. Each of the N groups corresponds to k target programming states.

[0010] In some embodiments, performing the first programming operation includes performing the first programming operation according to N groups, wherein each memory cell is programmed to a corresponding one of N different first programming states according to the N groups.

[0011] In some implementations, the method further includes grouping adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

[0012] In some embodiments, the method further includes grouping a first group of adjacent target programming states having a coupling offset less than a first preset threshold into a first group; grouping a second group of adjacent target programming states having a coupling offset greater than or equal to the first preset threshold but less than a second preset threshold into a second group; and grouping a third group of adjacent target programming states having a coupling offset greater than or equal to the second preset threshold into a third group.

[0013] In some implementations, the method further includes measuring a coupling offset from a target programmed state of a memory cell coupled to an adjacent word line.

[0014] In some embodiments, the method further includes, after performing the first programming operation, performing a first verification operation on each memory cell to determine whether each memory cell is programmed to a corresponding one of the N different first programming states.

[0015] In some embodiments, the method further includes performing a first programming operation on each memory cell during each of the one or more loops, wherein after each of the one or more loops, determining whether to proceed to the next loop based on a result of the first verification operation. If the result shows that the memory cell passes the first verification operation, the first programming operation is stopped. Otherwise, the first programming operation proceeds to the next loop until each memory cell is programmed to a corresponding one of the N different first programming states.

[0016] In some embodiments, the method further includes determining N different first program states using N different first verification voltages.

[0017] In some embodiments, the method further includes performing a second verification operation on each memory cell to determine whether each memory cell is programmed to a target programming state after performing the second programming operation, wherein different second verification voltages are used to determine whether a subset of memory cells in the i-th first programming state are programmed to K different target programming states.

[0018] In some embodiments, a respective first verification voltage corresponding to the i-th first program state is less than any second verification voltage used to verify the k target program states.

[0019] In some implementations, each memory cell is a triple level cell (TLC) with 8 states or a quad level cell (QLC) with 16 states.

[0020] Another aspect of the present disclosure discloses a memory device, the memory device including a memory array having memory cells. The memory device also includes a peripheral circuit, the peripheral circuit is coupled to the memory array and is configured to perform a first programming operation on the memory cells, so that each memory cell is programmed to a corresponding first programming state of N different first programming states; wherein N is a positive integer greater than 1 and less than M, and M is the total number of target programming states of the memory cells. The peripheral circuit is also configured to perform a second programming operation on a subset of the memory cells in the i-th first programming state, so that the subset of the memory cells is programmed from the i-th first programming state to k target programming states, wherein k is greater than or equal to 1 and less than n; and i is greater than or equal to 1 and less than or equal to N. At least two first programming states correspond to different k values.

[0021] In some embodiments, after performing the first programming operation, the peripheral circuit is further configured to perform a first verification operation on each memory cell to determine whether each memory cell is programmed to a corresponding one of the N different first programming states.

[0022] In some embodiments, after performing the second programming operation, the peripheral circuit is further configured to perform a second verification operation on each memory cell to determine whether each memory cell is programmed to a target programming state, wherein different second verification voltages are used to determine whether a subset of memory cells in the i-th first programming state are programmed to k target programming states.

[0023] In some implementations, each memory cell is a triple level cell (TLC) with 8 states or a quad level cell (QLC) with 16 states.

[0024] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0026] Figure 1A A block diagram of an exemplary system having a memory device according to some embodiments of the present disclosure is shown.

[0027] Figure 1B A diagram showing an exemplary memory card having a memory device according to some embodiments of the present disclosure is shown.

[0028] Figure 1C A diagram of an exemplary solid-state drive (SSD) having a memory device according to some embodiments of the present disclosure is shown.

[0029] Figure 1D A schematic diagram of an exemplary memory device according to some embodiments of the present disclosure is shown.

[0030] Figure 1E A block diagram of an exemplary memory device including a memory array and peripheral circuits according to some embodiments of the present disclosure is shown.

[0031] Figure 1F A cross section of an exemplary memory array including NAND memory strings is shown according to some embodiments of the present disclosure.

[0032] Figure 1G Threshold voltage distributions in a memory device according to some embodiments of the present disclosure are shown.

[0033] Figure 1HA mapping scheme of binary codes and logic states of a memory device according to some embodiments of the present disclosure is shown.

[0034] Figure 2 and 3 A method for performing a program operation in a memory device according to some embodiments of the present disclosure is shown.

[0035] Figure 4 Threshold voltage distributions after performing a second program operation to an i-th first program state according to some embodiments of the present disclosure are shown.

[0036] Figure 5 A method for performing a program operation in a memory device according to some embodiments of the present disclosure is shown.

[0037] Figure 6 and 7 Different multi-pass programming schemes for programming memory cells to a first program state and then to a corresponding target program state are shown in accordance with some embodiments of the present disclosure.

[0038] The features and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which the same reference numerals identify corresponding elements throughout. In the accompanying drawings, the same reference numerals generally indicate the same, functionally similar and / or structurally similar elements.

[0039] Embodiments of the present disclosure will be described with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the drawings, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. DETAILED DESCRIPTION

[0040] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0041] It should be noted that references in the specification to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant field to implement such a feature, structure, or characteristic in conjunction with other embodiments.

[0042] Typically, a term can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one", "an" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily be intended to express an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0043] As used herein, the term "nominal / nominal" refers to an expected value or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "approximately" may indicate a value of a given quantity that varies within, for example, 10-30% of a value (e.g., ±10%, ±20%, or ±30% of a value).

[0044] Unless otherwise defined, all technical and scientific terms used herein have similar meanings to those commonly understood by ordinary technicians in the field to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0045] Figure 1A A block diagram of an exemplary system 10 having a host 20 and a memory system 30 according to some aspects of the present disclosure is shown. The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system 30. The host 20 may be a processor of the electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 20 may be configured to send data to or receive data from the memory system 30.

[0046] In some embodiments, the memory system 30 includes one or more memory devices 34 and a memory controller 32. The memory device 34 can be any memory device, including but not limited to NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0047] According to some embodiments, the memory controller 32 is coupled to the memory device 34 and the host 20 and is configured to control the memory device 34. In some embodiments, the memory controller 32 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 32 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which can be used as a data storage device and an enterprise storage array for mobile devices such as smart phones, tablet computers, laptops, etc. The memory controller 32 can manage data stored in the memory device 34 and communicate with the host 20. The memory controller 32 can be configured to control the operation of the memory device 34, such as read, erase, and program operations. The memory controller 32 can also be configured to manage various functions related to data stored or to be stored in the memory device 34, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 32 is further configured to process error correction codes (ECC) on data read from or written to the memory device 34. Any other suitable functions may also be performed by the memory controller 32, such as formatting the memory device 34. The memory controller 32 may communicate with an external device (e.g., the host 20) according to a specific communication protocol. For example, the memory controller 32 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0048] The memory controller 32 and one or more memory devices 34 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 30 may be implemented and packaged into different types of terminal electronic products. Figure 1BIn one example shown, the memory controller 32 and the single memory device 34 may be integrated into a memory card 40. The memory card 40 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may also include a computer that connects the memory card 40 to a host (e.g., Figure 1A The memory card connector 42 is coupled to the host 20 in the embodiment. Figure 1C In another example shown, the memory controller 32 and the plurality of memory devices 34 may be integrated into the SSD 50. The SSD 50 may also include a processor that interfaces the SSD 50 with a host (e.g., Figure 1A In some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0049] The memory device described in the present disclosure may be a semiconductor memory, which is a solid-state electronic device that stores data information and is manufactured using a semiconductor integrated circuit process. 1D shows a schematic circuit diagram of an exemplary memory device 60 including peripheral circuits according to some aspects of the present disclosure. The memory device 60 may be Figure 1A 34 in FIG. 3. Memory device 60 may include a memory array 61 (also referred to as a "memory cell array" or "array") and peripheral circuitry 64 coupled to memory array 61. Memory array 61 may include an array of memory cells 63. In some implementations, memory array 61 includes memory strings 66 (also referred to as "NAND memory strings"), each memory string having a plurality of memory cells 63 coupled in series.

[0050] In some embodiments, the memory device 60 can be formed based on floating gate technology. In some embodiments, the memory device 60 can be formed based on charge trapping technology to provide high storage density and high inherent reliability. In some embodiments, each memory cell 63 can hold a continuous analog value, such as a voltage that depends on the amount of charge (e.g., electrons) trapped in the storage layer of the memory cell 63. The stored data or logic state can be determined by, for example, a threshold voltage V of the memory cell 63 based on the amount of charge trapped in the storage layer. th In some implementations, the memory device 60 may be a three-dimensional (3D) memory device in which the memory cells 63 may be stacked vertically on top of each other.

[0051] In some embodiments, each memory cell 63 is a single level cell (SLC) having two possible logic states (also referred to as "state" and "level") and can therefore store one bit of data. For example, a logic "0" can correspond to a first range of threshold voltages, and a logic "1" can correspond to a second range of threshold voltages. Initially, all memory cells 63 can be reset to an erased state ER or P0 (e.g., logic "1") by removing all trapped charge in the storage layer of the memory cell. By programming or writing, charge can be injected into the storage layer of the memory cell 63, thereby increasing the threshold voltage V of the memory cell 63. th . Thus, the memory cell 63 can be programmed to a programming state P1 (e.g., logic "0"). In some embodiments, each memory cell 63 can store more than one bit of data. For example, a multi-level cell (MLC) can have four states (P0-P3) and store two bits per memory cell. The memory cell 63 can be programmed from an erased state ER (P0) to one of three programming states (P1, P2, P3). Similarly, a triple-level cell (TLC) can have eight states (P0-P7) and each memory cell stores 3 bits, and a quad-level cell (QLC) can have sixteen states (P0-P15) and each memory cell stores 4 bits. Generally speaking, a memory cell in nLC mode can have 2 n states and can store n bits of data, where n is an integer.

[0052] like Figure 1DAs shown in , each memory string 66 may also include a source select gate (SSG) transistor 67 at its source terminal and a drain select gate (DSG) transistor 68 at its drain terminal. The SSG transistor 67 and the DSG transistor 68 may be configured to activate the selected memory string 66 (column of the array) during read and program operations. In some embodiments, the sources of the memory strings 66 in the same block 62 (also referred to as a "memory block") are coupled through the same source line 82 (e.g., a common source line). In some embodiments, the common source line 82 of all memory strings 66 in the memory array 61 is coupled to an array common source (ACS). According to some embodiments, the drain of each memory string 66 is coupled to a corresponding bit line 69, from which data can be read or written. In some embodiments, each storage string 66 is configured to be selected or unselected by applying a selection voltage or an unselection voltage to the gate of the corresponding DSG transistor 68 via one or more DSG lines 81 and / or by applying a selection voltage or an unselection voltage to the gate of the corresponding SSG transistor 67 via one or more SSG lines 83.

[0053] like Figure 1D As shown, the memory strings 66 can be organized into a plurality of blocks 62, each of which can have a common source line 82. In some embodiments, each block 62 is a basic data unit for an erase operation, i.e., all memory cells 63 in the same block 62 are erased at the same time. In some embodiments, the control gates (gate electrodes) of the memory cells 63 in a row can be connected to the same word line 65. Therefore, a row of memory cells 63 coupled to the same word line 65 can be read and programmed simultaneously during read and program operations. Therefore, a page 80 (also referred to as a "memory page" or "physical memory page") of memory cells 63 coupled to the same word line 65 can be a basic data unit for read and program operations.

[0054] The peripheral circuit 64 may be coupled to the memory array 61 through the bit lines 69, the word lines 65, the source lines 82, the SSG lines 83, and the DSG lines 81. The peripheral circuit 64 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 61 by applying and sensing voltage signals and / or current signals to and from each target memory cell 63 via the bit lines 69, the word lines 65, the source lines 82, the SSG lines 83, and the DSG lines 81. The peripheral circuit 64 may include various types of peripheral circuits formed using metal oxide semiconductor (MOS) technology. Figure 1ESome peripheral circuits including page buffer / sense amplifier 71, column decoder / bit line driver 72, row decoder / word line driver 73, voltage generator 74, control logic 75, register 76, interface 77 and data bus 78 are shown. It should be understood that in some examples, it may also include Figure 1E Additional peripheral circuits not shown.

[0055] refer to Figure 1D and Figure 1E , the page buffer / sense amplifier 71 can be configured to read data from the memory array 61 and program (write) data into the memory array 61 according to control signals from the control logic 75. In one example, the page buffer / sense amplifier 71 can store a logical page of programming data (write data) to be programmed into a memory page 80 of the memory array 61. In another example, the page buffer / sense amplifier 71 can verify the programming state of the target memory cell 63 coupled to the selected word line 65 in each programming / verification cycle (cycle) during the programming operation to ensure that the data in the logical page has been properly programmed into the target memory cell 63. In yet another example, the page buffer / sense amplifier 71 can also sense a low power signal from the bit line 69 representing the data stored in the target memory cell 63, and amplify the low power signal to a recognizable logical state of the target memory cell 63 in a read operation. In some embodiments, each page buffer / sense amplifier 71 may include a storage module (e.g., a latch, a cache, a register, etc.) for temporarily storing n-bit data received from the data bus 78 and providing the n-bit data to the corresponding target memory cell 63 via the corresponding bit line 69.

[0056] The column decoder / bit line driver 72 may be controlled by the control logic 75 to apply the bit line voltage generated from the voltage generator 74 to select one or more memory strings 66. The row decoder / word line driver 73 may be controlled by the control logic 75 to select / unselect the block 62 of the memory array 61 and select / unselect the word line 65 of the block 62. The row decoder / word line driver 73 may be further configured to drive the word line 65 using the word line voltage generated from the voltage generator 74. In some embodiments, the row decoder / word line driver 73 may also select / unselect and drive the SSG line 83 and the DSG line 81. The voltage generator 74 may be controlled by the control logic 75 to generate a word line voltage (e.g., a read voltage, a program voltage, an erase voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be provided to the memory array 61.

[0057] The control logic 75 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The register 76 may be coupled to the control logic 75 and include a status register, a command register, and an address register to store status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 77 may be coupled to the control logic 75 and act as a control buffer to buffer and relay control commands received from the host 20 (in FIG. 1 ) to the control logic 75 and status information received from the control logic 75 to the host 20. The interface 77 may also be coupled to the column decoder / bit line driver 72 via a data bus 78 and act as a data input / output (I / O) interface and a data buffer to buffer and relay data to and from the memory array 61.

[0058] Figure 1F 1 shows a cross-sectional view of an exemplary memory array 61 according to some embodiments of the present disclosure. Figure 1F As shown in FIG, memory strings 66 of memory array 61 may extend vertically through a memory stack 85 above a substrate 84. Substrate 84 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0059] The memory stack 85 may include interleaved conductive layers 86 and dielectric layers 87. The number of pairs of conductive layers 86 and dielectric layers 87 in the memory stack 85 may determine the number of memory cells 63 in the memory array 61. The conductive layers 86 may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each conductive layer 86 includes a metal layer, such as a tungsten layer. In some embodiments, each conductive layer 86 includes a doped polysilicon layer. The conductive layers 86 may be used as memory cells 63, DSG transistors 68, and SSG transistors 67 (see Figure 1D ) has a gate electrode and can extend laterally to form a DSG line 81 at a top portion of the memory stack 85, an SSG line 83 at a bottom portion of the memory stack 85, and a word line 65 between the DSG line 81 and the SSG line 83.

[0060] like Figure 1FAs shown in , the memory string 66 includes a channel structure 88 extending vertically through the memory stack 85. In some embodiments, the channel structure 88 includes a channel hole, wherein the sidewalls of the channel hole are covered by a semiconductor channel 92 and a storage film 91. In some embodiments, the semiconductor channel 92 includes silicon, such as polysilicon. In some embodiments, the storage film 91 is a composite dielectric layer including a tunneling layer 93, a storage layer 94 (also referred to as a "charge trapping / storage layer"), and a barrier layer 95. The channel structure 88 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel 92, the tunneling layer 93, the storage layer 94, and the barrier layer 95 are arranged sequentially from the center toward the outer surface of the column in the radial direction. The tunneling layer 93 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 94 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 95 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 91 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] like Figure 1F As shown in FIG. 1 , according to some embodiments, a well 89 (eg, a P-well and / or an N-well) is formed in the substrate 84, and the source terminal of the memory string 66 contacts the well 89. For example, the source line 82 (in Figure 1D During the erase operation, the erase voltage (V erase ) is applied to the well 89. In some embodiments, the memory string 66 also includes a channel plug 90 at the drain end of the memory string 66. In some embodiments, the channel plug 90 of each memory string 66 is coupled to a corresponding bit line 69 (at Figure 1D It should be understood that although Figure 1F Not shown, but additional features of the memory array 61 may be formed, including but not limited to gate gap / source contacts, local contacts, interconnect layers, etc.

[0062] Figure 1G 1 shows the threshold voltage V of a memory cell of a memory device programmed in nLC mode according to some embodiments of the present disclosure. th Distribution. Due to various changes, each state of the memory cell includes a threshold voltage V th range, where each state threshold voltage V th The distribution can be represented by a probability density. In some embodiments, each state of the nLC mode (SLC, MLC, TLC, QLC, etc.) can be programmed by using an incremental step pulse programming (ISPP) scheme, where the step pulse V stepTo incrementally increase the programming voltage applied to the selected word line. For example, the eight TLC states can be first programmed from state P0 to state P1 with a lower threshold voltage, then to state P2, P3, ..., until state P7 with a higher threshold voltage. In some embodiments, the 2 n The states can be programmed from state P0 to state P1, P2, ..., P(2 n -1). Figure 1G As shown in the figure, from state P0 to state P(2 n -1), the threshold voltage of the memory cell V th Therefore, state P0 is also called the lowest state, and state P(2 n -1) is also called the highest state. The upper state has a higher threshold voltage, and the lower state has a lower threshold voltage.

[0063] The state of a memory cell can be mapped to data in the form of a binary code stored in a NAND memory device. n The states can be represented in the form of a Gray code. Gray code (i.e., reflected binary code (RBC) or reflected binary (RB)) is an ordering of the binary number system so that two consecutive values ​​differ in only one bit (binary digit). Using Gray code allows for easier error correction in programming and / or reading data because the codes for any adjacent states differ by only one binary digit.

[0064] Figure 1H A mapping scheme of a 3-bit binary code and a state of a memory device programmed in TLC mode according to some embodiments of the present disclosure is shown. In this example, the eight states (states P0-P7) in the TLC mode can correspond to the 3-bit binary codes (111), (110), (100), (000), (010), (011), (001), and (101), respectively. In the TLC mode, the 3 bits of the binary code can be named as the most significant bit (MSB), the middle significant bit (CSB), and the least significant bit (LSB) when read from left to right. For example, state P5 can be mapped to the binary code (011), where the MSB, CSB, and LSB are "0", "1", and "1", respectively. In some embodiments, the same physical memory page (e.g., Figure 1D The memory cells in the page 80 in the same physical memory page can be programmed according to the programming data in the logical page, for example, in the TLC mode, the lower page (LP), the middle page (MP) and the upper page (UP) correspond to the LSB, CSB and MSB of the binary code, respectively.

[0065] During programming, a logical page of n-bit binary code (ie, programming data) may be temporarily stored in a page buffer 71 ( Figure 1E ). The memory device can be programmed and / or read on a page-by-page basis. In nLC mode, a physical memory page can be programmed according to data in n logical pages, where each memory cell can be programmed to a 2-bit binary code represented by n bits in the n logical pages. n In other words, one physical memory page can store n logical pages of data. Note that the scope of the present disclosure is not limited to Figure 1H The memory device, system, and method disclosed herein can be applied to 2 n A set of different binary codes associated with each state.

[0066] Return to reference Figure 1G , the threshold voltage of the memory cell can be th With one or more read reference voltages V R (For example, V R1 、V R2 , ...) (also referred to as a "verify voltage") is compared to determine the state of the memory cell. The state or data stored in the memory cell can thereby be determined. The read reference voltage V can be selected within a read margin between two adjacent states (i.e., between the highest possible threshold voltage of the lower state and the lowest possible threshold voltage of the higher state). R .use Figure 1G As an example, the eight TLC states P0-P7 in R1 -V R7 Applied to the selected word line 65 coupled to the target memory cell, the threshold voltage V th For example, to verify whether the target memory cell is in state P0, the read reference voltage V R1 If the target memory cell is in state P0, the threshold voltage V th Below the reading reference voltage V R1 The target memory cell can be turned on and form a conductive path in the channel. If the target memory cell is in any of the states P1-P7, the threshold voltage V th Higher than the reading reference voltage V R1 The target memory cell is thus turned off. By measuring or sensing the current through the target memory cell or the voltage drop at the corresponding bit line, the threshold voltage V of the target memory cell can be determined. th or status.

[0067] To determine the two states P0 and P1 stored in SLC mode, only the reference voltage V R1 To determine the four states P0-P3 in the MLC mode, the read reference voltage V R1 、V R2 and V R3 To determine the eight states P0-P7 of the TLC mode, the read reference voltage V R1 -V R7 For example, in TLC mode, the threshold voltage of state P0 is lower than V R1 , and the threshold voltage of state P7 is higher than V R7 , where the threshold voltage of state P1 is V R1 and V R2 States P2-P6 can be determined similarly. Similarly, in QLC mode, 15 read reference voltages can be used to verify 16 states (P0-P15). To verify 2 in nLC mode n states, you can use 2 n -1 to read the reference voltage.

[0068] In some embodiments, the state of the memory cell is read and determined according to the logical page of the mapping scheme. Figure 1H In the TLC mode of the mapping scheme shown, the first subset of reference voltages (i.e., V R3 and V R7 ) can be used to determine the MSB of the target memory cell (corresponding to the upper page of the binary code), where a "1" is flipped to a "0" or a "0" is flipped to a "1". Similarly, the second subset of read reference voltages (i.e., V R2 、V R4 and V R6 ) can be used to determine the CSB of the target memory cell (corresponding to the middle page of the binary code), and read the third subset of reference voltages (i.e., V R1 and V R5 ) can be used to determine the LSB of the target memory cell (corresponding to the lower page of the binary code). Figure 1H In the example in , the data bits of the upper page (UP) can be determined by performing 2 read operations. The data bits of the middle page (MP) can be determined by performing 3 read operations. The data bits of the lower page (LP) can be determined by performing 2 read operations.

[0069] Similarly, in QLC mode, 16 states can be represented by a set of 4-bit binary codes. Table 1 shows an exemplary one-to-one mapping of binary codes and 16 states P0-P15. For example, state P0 corresponds to (1111) and state P15 corresponds to (0111). Each memory cell of the same physical memory page can be programmed to one of the 16 states according to the data in the logical page (i.e., lower page (LP), middle page (MP), upper page (UP), and extra page (XP)).

[0070] Table 1

[0071] state P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Reading# XP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 3 UP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 4 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 4 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 4

[0072] When adjacent bits in the same logical page change from "0" to "1" or from "1" to "0", it counts as one flip. According to Mapping Table 1, the number of flips for logical pages XP, UP, MP, and LP are 3, 4, 4, and 4, respectively. In order to determine 16 QLC states according to the mapping in Table 1, LP requires 4 reads, MP requires 4 reads, and UP reads require 4 reads and XP requires 3 reads. When the number of flips between logical pages is similar, it is a balanced Gray code. The Gray code shown in Table 1 is an example of a balanced Gray code. Balanced Gray code can increase the reading speed. For example, when the balanced Gray code in Table 1 is used, the maximum number of read operations per logical page is limited to 4. However, when an unbalanced Gray code is used, there may be a large number of flips for a certain logical page, which may cause a read bottleneck for other logical pages.

[0073] In some embodiments, each memory cell can be programmed using a multiple-pass programming scheme to reduce programming time and increase read margin. For example, a memory cell can be programmed to an intermediate state (also referred to as a "first programming state") during coarse programming (also referred to as a "first programming operation" or "first pass"), and then the memory cell can be programmed to a final state (also referred to as a "target programming state") during fine programming (also referred to as a "second programming operation" or "second pass"). For example, in QLC mode, using an 8-16 two-pass programming scheme, the memory cell can first be programmed to 8 intermediate states, and then programmed to 16 final states in fine programming. In another example using a 16-16 two-pass programming scheme, the memory cell can first be programmed to 16 intermediate states, and then programmed to 16 final states.

[0074] Taking a QLC memory device as an example, in a 16-16 two-pass programming scheme, data in logical pages LP, MP, UP, and XP can be used in both the first pass (coarse programming) and the second pass (fine programming). In the first pass, the memory cells are programmed to 16 intermediate states with a wider threshold voltage distribution. In the second pass, the memory cells are reprogrammed to 16 final states with a narrower threshold voltage distribution. Although the programming speed of the 16-16 two-pass programming scheme may be slow, after the second pass programming, the read margin can be increased and the read time can be shorter.

[0075] In the 8-16 two-pass programming scheme, during the first pass, memory cells can be programmed in TLC mode. Table 2a shows a similar Figure 1H An exemplary mapping scheme for the eight TLC states.

[0076] Table 2a

[0077] state P0 P1 P2 P3 P4 P5 P6 P7 Reading# UP 1 1 1 0 0 0 0 1 2 MP 1 1 0 0 1 1 0 0 3 LP 1 0 0 0 0 1 1 1 2

[0078] The memory cells can be programmed using data from logical pages LP, MP, and UP. Figure 1G and 1H The eight TLC states are verified by reading the reference voltages described, where the "0" and "1" codes in UP, MP, and LP can be determined after 2, 3, and 2 reads, respectively. Subsequently, in the second pass, the memory cells can be programmed in QLC mode using data from logical pages LP, MP, UP, and XP. Table 2b shows an exemplary mapping scheme for the 16 final states of the QLC mode in the second pass.

[0079] Table 2b

[0080] state P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Reading# XP 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 8 UP 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 2 MP 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 3 LP 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 2

[0081] In this example, each state in the TLC mode from the first pass is split into two states in the QLC mode (compare Table 2a with Table 2b), represented by "0" and "1" in the additional XP. After the second pass, 16 states can be verified, where the "0" and "1" codes in XP, UP, MP, and LP can be determined after 8, 2, 3, 2 reads. In this 8-16 two-pass programming scheme, the codes in XP require a large number (eight) of reads. In addition, the read margins for the 16 final states may be very narrow and may result in a large number of failed bit counts and read failures.

[0082] Figure 2A method 200 for programming a memory device according to some embodiments of the present disclosure is shown. It should be understood that the method 200 is not exhaustive, and other operating steps may also be performed before, after, or between any of the illustrated operating steps. In some embodiments, some operating steps of the method 200 may be omitted, or other operating steps may be included, which are not described herein for simplicity. In some embodiments, the operating steps of the method 200 may be performed and / or varied in a different order.

[0083] The method 200 includes step S201, in which a first programming operation may be performed on a memory cell to be programmed (target memory cell). In the first programming operation, each memory cell may be programmed to a corresponding first programming state of N different first programming states. Here, N is a positive integer greater than 1 and not greater than M, and M is the total number of target programming states of the memory cell to be programmed.

[0084] In step S202, a second programming operation may be performed on the i-th group of memory cells in the i-th first programming state. After the second programming operation, the i-th group of memory cells in the i-th first programming state may be programmed to K i Here, i is greater than or equal to 1 and less than or equal to N, and K i is greater than or equal to 1 and not greater than N. After the second programming operation, at least two groups of memory cells in two different first programming states may be programmed to different numbers of target programming states. For example, after the second programming operation, the jth group of memory cells in the jth first programming state may be programmed to K j different target programming states. Here, j is greater than or equal to 1 and less than or equal to N, and K j is greater than or equal to 1 and not greater than N. In some embodiments, K i and K j are different numbers, i.e., K i ≠K j .

[0085] As described above, for a memory device configured in nLC mode, a memory cell can be programmed from an erased state (ER or P0) to a 2 n -1 target programming state P1, P2, ..., P(2 n According to method 200, after the first programming operation, each memory cell may be programmed to one of N different first programming states, where 1≤N≤M, and M is the total number of target programming states (i.e., M=2 n-1). In some embodiments, after completing the first programming operation, at least two memory cells with different target programming states may be programmed into the same first programming state. In some embodiments, the first programming state may be understood as an intermediate or temporary state in the programming process. In some embodiments, the first programming state may be any logical state that is not related to the programming data or the target programming state. However, in some embodiments, the first programming state may be defined in some way by the programming data.

[0086] For example, after a first programming operation according to method 200, memory cells may be programmed to N first programming states S1, S2, . . . , S N , these first programming states may correspond to K1, K2, ..., K N In other words, the memory cells to be programmed to K1 different target programming states can all be programmed to the same first programming state S1, and the memory cells to be programmed to K2 different target programming states can all be programmed to the same first programming state S2. The i-th first programming state can correspond to K i different target programming states. N The memory cells with different target programming states are all programmed to the same first programming state S N It should be noted that each group of K1, K2, ..., K i , …, K N The target programming states within each target programming state are different from each other. i , …, K N The target programming states of the groups of target programming states are also different from each other. i , …, and K N The sum of is the total number of target programming states, i.e. K1+K2+…+K N =M=2 n -1.

[0087] Therefore, a second programming operation may be subsequently performed to program the memory cells in the N different first programming states to 2 n -1 target programming state. For example, a memory cell in the first programming state S1 after the first programming operation can be programmed to K1 different target programming states during the second programming operation. A memory cell in the first programming state S2 after the first programming operation can be programmed to K2 different target programming states during the second programming operation. Similarly, a memory cell in the first programming state S N The memory cells can be programmed to K during the second programming operation Ndifferent target programming states.

[0088] In the embodiments disclosed in the present disclosure, a group of memory cells to be programmed to different target programming states can be first programmed to the same first programming state in a first programming operation. Therefore, it takes less time to complete the first programming operation. It should be noted that the first programming state described in method 200 is directly related to the target programming state defined by the programming data. There is no separate Gray code mapping for the first programming operation, which is different from the 8-16 two-pass programming scheme described in Table 2a and Table 2b. However, method 200 does not limit the use of Gray code for the first programming state. In addition, for the second programming operation, balanced Gray code can be used for programming and / or reading. Using balanced Gray code in the second programming operation can improve read margin. With less read failure bit counts, data readability and reliability can also be improved.

[0089] Figure 3 A method 300 for programming a memory device according to some embodiments of the present disclosure is shown. It should be understood that method 300 is not exhaustive, and other operating steps may also be performed before, after, or between any of the illustrated operating steps. In some embodiments, some operating steps of method 300 may be omitted, or other operating steps may be included, which are not described herein for simplicity. In some embodiments, the operating steps of method 300 may be performed and / or varied in a different order. Method 300 may be similar to method 200, wherein the differences will be described in detail below.

[0090] At step S301, before the first programming operation, a coupling offset of a target programming state may be predetermined. The coupling offset of the target programming state may be determined based on a threshold voltage offset of a memory cell in the target programming state affected by an adjacent memory cell. A reduction in the threshold voltage of a memory cell is defined as a left offset, and an increase in the threshold voltage of a memory cell is defined as a right offset. Using a memory cell with charge capture as an example, due to the influence of coupling capacitance, the trapped charge in the storage layer of a memory cell may be changed by the trapped charge in the storage layer of an adjacent memory cell. The coupling capacitance may be inversely proportional to the distance between adjacent memory cells: the shorter the distance, the greater the coupling capacitance, and thus the greater the mutual influence. Therefore, when programming adjacent memory cells, an offset of the threshold voltage of the memory cell (i.e., a coupling offset) may be generated. The coupling offset may change the threshold voltage distribution of the programming state, which may cause a read failure during a read operation.

[0091] Table 3 shows exemplary coupling offsets of programming states in a TLC mode according to some embodiments of the present disclosure. As shown in Table 3, memory cells in each of the seven programming states (P1-P7) may be affected by adjacent memory cells. The coupling offset depends on the programming state of the adjacent memory cells. In Table 3, the first column represents the programming state (i.e., victim state) of the target memory cell coupled to the selected word line, where the top row represents the programming state of the adjacent memory cell coupled to the adjacent word line. Generally, the higher the state (i.e., threshold voltage) of the adjacent memory cell, the greater the impact on the target memory cell, and the greater the coupling offset. In addition, the lower the state of the target memory cell, the greater the impact received from the adjacent memory cell. Vice versa.

[0092] Table 3

[0093]

[0094] In some embodiments, the coupling offset of the target programming state can be obtained by measuring the threshold voltage offset of the target memory cell programmed to the target programming state relative to the adjacent memory cells programmed to various states. The target memory cell can be addressed by selecting a word line. In some embodiments, adjacent memory cells can be addressed by adjacent word lines.

[0095] The coupling offset depends on the structure of the memory device and may be affected by the manufacturing process, the number of bits (nLC mode), materials, etc. Different memory devices may have different coupling offsets. In some embodiments, the coupling offset may be determined at product testing in the factory and may be characterized as an inherent property of a particular memory device.

[0096] In some embodiments, the coupling offset can be determined by silicon testing. Taking a QLC memory device as an example, a memory cell under test (i.e., a victim cell) can be programmed to a corresponding one of states P1 to P15, and an adjacent memory cell can be in states P0 to P15. The memory cell under test is coupled to a selected word line, and an adjacent memory cell is coupled to an adjacent word line. The shift in the threshold voltage of the memory cell under test affected by the state of the adjacent memory cell is the corresponding coupling offset. The coupling offset of different memory devices can also be obtained by silicon testing.

[0097] In step S302 of method 300, the target programming states may be divided (or classified) into N groups according to the coupling offset, wherein the i-th group includes K i different target programming states (1≤i≤N). For example, the first group includes K1 different target programming states, the second group includes K2 different target programming states, and so on. The i-th group includes Ki different target programming states. The Nth group includes K N different target programming states. K1, K2, ..., K i , …, and K N The sum of is the total number of target programming states, i.e. K1+K2+…+K N =M=2 n -1. Here, the N groups of target programming states are disjoint. That is, any target programming state does not appear in more than one of the N groups. Each of the target programming states is included in one and only one of the N groups. In some embodiments, at least two of the groups include different numbers of target programming states. For example, between the i-th group and the j-th group, the target programming state K i and K j The number of different (K i ≠K j ).

[0098] The target programming states to be programmed to each memory cell can be grouped flexibly. In some embodiments, target programming states with similar coupling offsets can be grouped together into the same group. By grouping one or more target programming states with similar coupling offsets into the same intermediate state (first programming state), not only can programming time be saved in multiple programming passes, but also the coupling offsets of the target programming states can be minimized after the second programming operation is completed for all memory cells.

[0099] In some embodiments, adjacent target programming states with coupling offsets within a predetermined range can be grouped into the same group. In some embodiments, the predetermined range can be selected so that the target programming states can be divided into N groups, each group including the same number of target programming states, i.e., K1, K2, ..., K N In some embodiments, one or more target programming states with a smaller coupling offset may be grouped in the same group. In some embodiments, one or more target programming states with a larger coupling offset may be grouped in the same group. The predetermined range of coupling offsets used to group target programming states may also follow other user-defined rules. For example, multiple predetermined ranges may be used to group target programming states.

[0100] In some embodiments, target programming states in the same group may be adjacent target programming states. However, adjacent target programming states may not necessarily be in the same group. If the coupling offsets of two adjacent target programming states differ greatly, the two adjacent target programming states may be classified or divided into two different groups. In some embodiments, target programming states having coupling offsets exceeding a predetermined range may be classified into separate groups.

[0101] In some embodiments, adjacent target programming states having a coupling offset less than a first preset threshold value may be classified as a first group. Adjacent target programming states having a coupling offset greater than or equal to the first preset threshold value and less than a second preset threshold value may be classified as a second group. Adjacent target programming states having a coupling offset greater than or equal to the second preset threshold value may be classified as a third group. In an embodiment of the present disclosure, the first preset threshold value may be less than the second preset threshold value. It should be noted that the above-mentioned first group, second group, and third group are exemplary classifications of target programming states. The N groups of target programming states are not limited to three, and may be any combination of the above-mentioned first group, second group, and third group. In addition, the first preset threshold value and the second preset threshold value are used for illustrative purposes. If desired, multiple preset threshold values ​​may be used, such as a third preset threshold value and a fourth preset threshold value. For example, the second group may be further divided according to a third preset threshold value between the first preset threshold value and the second preset threshold value. After classification, one or more target programming states may exist in the group.

[0102] For example, as shown in Table 3, considering both left and right offsets, the coupling offset between any two adjacent memory cells in the TLC mode may range from 1 mV to 183 mV. If the first preset range is set to be less than 40 mV, states P1 and P2 may be grouped into a first group because the coupling offset of states P1 and P2 affected by states P0, P1, and P2 is less than 40 mV. If the second preset range is set to be less than 100 mV, states P3, P4, and P5 may be grouped into a second group because the coupling offset of states P3, P4, and P5 affected by states P0-P5 is less than 100 mV. And states P6 and P7 may be grouped into a third group because the coupling offset of states P6 and P7 affected by states P0-P7 may be greater than 100 mV.

[0103] In some embodiments, after the coupling offset is determined by silicon testing at the factory, a margin loss test can be performed on memory cells programmed to a target programming state for each of the possible classification schemes (e.g., 6 groups, 8 groups, 10 groups). The classification scheme with the smallest read margin loss can be set as the default scheme for the memory device.

[0104] In some embodiments, a coupling offset ratio ratio may also be used instead of a coupling offset to divide the target programming state into N groups. The coupling offset ratio of the target programming state may be determined based on a ratio of a coupling offset (e.g., a threshold voltage offset) and a threshold voltage associated with the target programming state that is not affected by the coupling capacitance effect. For ease of description, the coupling offset is used for description in the present disclosure, but the coupling offset ratio may be used similarly.

[0105] At step S303, a first programming operation is performed on the memory cells to be programmed according to the grouping of the target programming states, so that the memory cells can be programmed to the first programming state. Each first programming state corresponds to a corresponding group of the N groups of target programming states. For example, the first programming state S1 corresponds to a first group including K1 different target programming states, and the second programming state S2 corresponds to a second group including K2 different target programming states, and so on. The i-th first programming state S i Corresponding to including K i The i-th group of different target programming states. N Corresponding to including K N Therefore, the N first programming states S1, S2, . . . , S N is associated with N groups of target programming states. That is, after considering the coupling offset, the first programming states S1, S2, . . . , S N Similar to method 200, in method 300, memory cells may be programmed to respective first programming states S1, S2, . . . , S according to respective target programming states of the memory cells based on programming data. N .

[0106] At step S304, similar to step S202 of method 200, a second programming operation may be performed to program the memory cells to the target programming state. Thus, a subset of the memory cells in the i-th first programming state may be programmed to the K i different target programming states.

[0107] In some embodiments, the method 300 further includes: after performing the first programming operation on all memory cells to be programmed, performing a first verification operation on each memory cell using a first verification voltage associated with the first programming state to determine whether each memory cell is programmed to the corresponding first programming state. For different target programming states in the same group (i-th group), the same verification voltage can be used for the first verification operation (to verify the i-th first programming state). That is, one first programming state corresponds to one first verification voltage. N different first verification voltages can be used to verify N different first programming states, respectively.

[0108] In some embodiments, the threshold voltage of the memory cell is increased during the second programming operation due to the additional programming pulses. The target programming state can be higher than the corresponding first programming state, wherein the associated threshold voltage of the target programming state can also be higher than the threshold voltage of the first programming state. In this example, the first verification voltage for verifying the first programming state can be lower than the second verification voltage corresponding to the target programming state. Therefore, one first verification voltage can be used to verify each group of target programming states, which can save verification time and increase overall programming speed.

[0109] In some embodiments, memory cells to be programmed to the same first programming state may also be grouped together. A first programming operation may be performed on a group of memory cells to be programmed to a certain first programming state, followed by a first verification operation. When all memory cells in the group pass verification, a first programming operation may then be performed on the next group of memory cells to be programmed to another first programming state, followed by another first verification operation. Thus, programming and verification may be performed on the memory cells group by group until all N groups of memory cells are programmed to the corresponding N first programming states.

[0110] In some embodiments, a first programming operation may be performed during each of a plurality of loops (e.g., a first set of loops), wherein after each programming, it may be determined whether to perform the first programming operation in a subsequent loop based on a verification result of the first verification operation. If the verification result indicates that the memory cell has been programmed to the corresponding first programming state, the first programming operation may be stopped. If the verification result indicates that the memory cell has not been programmed to the corresponding first programming state and therefore the first verification fails, the first programming operation may proceed to the next loop to program those failed memory cells again until all memory cells are programmed to the corresponding N different first programming states. Memory cells that pass the first verification may be prohibited from being programmed in subsequent loops. In some embodiments, the first programming operation includes incremental step pulse programming (ISPP), in which a programming voltage V applied to a selected word line coupled to a target memory cell is increased. pgm In each cycle, the step pulse V step Increase in increments.

[0111] In some embodiments, the method 300 further includes: after performing the second programming operation on all memory cells to be programmed, performing a second verification operation on each memory cell using a second verification voltage associated with the target programming state to determine whether each memory cell is programmed to the corresponding target programming state. Different second verification voltages may be used to verify the K of the i-th group. i In some embodiments, the Ki In some embodiments, the first verification voltage for verifying the i-th first programming state may be smaller than the first verification voltage for verifying the K i any second verification voltage for a target programmed state.

[0112] Similar to the first programming operation, in some embodiments, the second programming operation may also be performed during each of a plurality of loops (e.g., a second set of loops), and the ISPP method may also be used. In addition, during the second programming operation, programming and verification may be performed on the memory cells group by group until each group of memory cells is programmed to the corresponding M(2 n For example, the i-th group of memory cells programmed to the i-th first programming state during the first programming operation can be further divided into K i During the second programming operation, each subset of memory cells may be programmed to a corresponding target programming state in the i-th set of target programming states. i The second verification operation may be performed after programming each of the K subgroups. i A second verification operation is performed after programming the subgroups.

[0113] Figure 4 An example of a multi-pass programming scheme 400 is shown in accordance with some embodiments of the present disclosure. Figure 4 3 shows the threshold voltage distribution of the i-th first programming state and the i-th group of corresponding target programming states according to method 300. In this example, four target programming states F1, F2, F3, and F4 are grouped into the i-th group of target programming states, namely, K i =4. The i-th first programming state S i Corresponding to the four target program states F1, F2, F3 and F4 in the i-th group. During the first programming operation, the memory cells to be programmed to the target program states F1, F2, F3 and F4 may be programmed to the first program state S i The first programming state S i The lower edge of the threshold voltage distribution is V th After the second programming operation, the first programming state S i The memory cells are respectively programmed to the target programming states F1, F2, F3 or F4 corresponding to the higher threshold voltage. Figure 4 As shown, the lower edge of the threshold voltage distribution of the target programming states F1, F2, F3 and F4 is V th _F1, V th _F2, V th _F3 and Vth _F4, they are all higher than V th Since a lower verification voltage can be used to verify a lower state with a lower threshold voltage, the first programming state S for verifying the i-th first programming state S i The first verification voltage of may be lower than any second verification voltage used to verify the four target program states F1-F4.

[0114] It should be noted that the first programming state S i The lower edge V th _Si is lower than the lower edge V of the lowest target programming state F1 in the i-th group of target programming states. th Therefore, during the first programming operation, it is necessary to control the programming voltage applied to the selected word line to avoid programming the i-th first programming state S i over programming and ensure that the lower edge V th _Si is not higher than the lower edge V th _F1.

[0115] exist Figure 4 In the example of FIG. 1 , during the second programming operation, the i-th first programming state S i The maximum threshold voltage offset between the highest target programmed state F4 in the i-th group can be expressed as V th _F4-V th _Si+W_V th _F4, where W_V th _F4 is the width of the threshold voltage distribution of the target programming state F4. The total threshold voltage offset between the first programming state and the target programming state may also include a coupling offset between adjacent memory cells.

[0116] Table 4 shows an example of a multiple-pass programming scheme according to some embodiments of the present disclosure. In this example, the memory device is configured in a QLC mode, where each memory cell can have 16 states P0 to P15. The target programming states P1-P15 can be divided into 9 groups. The first group includes states P1, P2, and P3. The second group includes states P4 and P5. The third group includes states P6 and P7. The fourth group includes states P8 and P9. The fifth group includes states P10 and P11. The sixth group includes state P12. The seventh group includes state P13. The eighth group includes state P14, and the ninth group includes state P15. In some embodiments, the nine groups are classified according to the coupling offset between adjacent memory cells. Target programming states with similar coupling offsets can be grouped together. Memory cells in higher states (e.g., states P14, P15) can induce larger coupling offsets in adjacent memory cells, thereby being grouped separately from lower states or forming groups with a single state. In Table 4, balanced Gray code is used to map the target programming state to improve the read speed and read margin.

[0117] Table 4

[0118]

[0119] After the target programming states are divided into 9 groups, a first programming operation can be performed on the memory cells to be programmed. For example, the memory cells to be programmed to the first group of target programming states P1-P3 can be programmed to the first programming state S1. The threshold voltage of the first programming state S1 can be lower than the threshold voltage of the target programming states P1, P2 and P3. After the first programming operation, a first verification voltage can be used to verify whether the memory cell is programmed to the first programming state S1. The time required for the first programming operation here can be shorter than that of the 16-16 two-pass programming scheme because the memory cells to be programmed to the target programming states P1-P3 are programmed to the same first programming state S1 using the same programming voltage. In the 16-16 two-pass programming scheme, during the first programming operation, the memory cells are programmed to 16 different first programming states, and the 16 different first programming states have threshold voltages slightly lower than the corresponding 16 target programming states.

[0120] After all memory cells are programmed to the respective first program states S1-S9, a second program operation may be performed to program the memory cells to the respective target program states P1-P15. For example, the memory cells in the first program state S1 may be programmed to the target program states P1, P2 or P3, respectively.

[0121] Table 5 shows another example of a multi-pass programming scheme according to some embodiments of the present disclosure. In this example, the 15 target programming states P1-P15 of the QLC mode can be divided into 5 groups, where the first group includes states P1-P4, the second group includes states P5-P8, the third group includes states P9-P11, the fourth group includes states P12-P13, and the fifth group includes states P14-P15. Here, a balanced Gray code can be used to map the target programming states so that the flip count and the number of reads of each logical page can be similar (balanced) to avoid congestion or overload at a certain logical page. Therefore, the number of failed bits can be minimized.

[0122] Table 5

[0123]

[0124] After the target programming states P1-P15 are divided into 5 groups, a first programming operation can be performed to program the memory cells to the first programming states S1-S5, respectively. For example, during the first programming operation, the memory cells to be programmed to the first group of target programming states P1-P4 can be programmed to the first programming state S1. After the first programming operation, a first verification voltage can be used to verify whether the memory cells have been programmed to the first programming states S1-S5. For example, after the first programming operation, the same first verification voltage can be used for the memory cells to be programmed to the target programming states P1-P4 to verify whether these memory cells have been programmed to the same first programming state S1. The first programming state S1 corresponds to a threshold voltage lower than the threshold voltage of the target programming states P1-P4. The first verification voltage for verifying the first programming state S1 can also be lower than the second verification voltage for verifying the target programming states P1-P4. Compared with the 16-16 two-pass programming scheme, programming memory cells to the same first programming state for a group of target programming states can save time.

[0125] Then, according to the grouping of the target program states, the second program operation to the target program states P1-P15 can be performed on the memory cells in the first program states S1-S5, respectively. For example, for the first group, the memory cells in the first program state S1 can be programmed to the target program states P1-P4, respectively.

[0126] Implementations of the programming methods disclosed in this disclosure may have one or more of the following benefits:

[0127] 1. Save time on the first pass by grouping multiple target program states into one first program state for the first programming operation.

[0128] 2. Compared with the 8-16 two-pass programming scheme, the read margin and read accuracy are improved by mapping the logic states using balanced Gray code.

[0129] 3. If a Gray code similar to that in the 8-16 two-pass programming scheme is used, similar read margins are achieved.

[0130] 4. Avoid remapping of the Gray code in the first programming operation by directly using the Gray code of the target programming state.

[0131] 5. All required operations are completed within the memory die without resorting to other additional operations outside the memory die.

[0132] Figure 5 A method 500 for programming a memory device according to some embodiments of the present disclosure is shown. It should be understood that method 500 is not exhaustive, and other operating steps may also be performed before, after, or between any of the illustrated operating steps. In some embodiments, some operating steps of method 500 may be omitted, or other operating steps may be included, which are not described herein for simplicity. In some embodiments, the operating steps of method 500 may be performed and / or varied in a different order. Method 500 may be similar to method 300, wherein the differences will be described in detail below.

[0133] In step S501 , similar to step 301 of method 300 , a coupling offset of a target programming state may be determined.

[0134] In step S502, similar to step 302 of method 300, the target programming states may be divided into N groups according to corresponding coupling offsets, wherein the i-th group includes K i different target programming states.

[0135] In step S503, a higher target programming state may be selected. In some embodiments, the higher second programming state may have a higher threshold voltage compared to other second programming states in the same group of target programming states. The higher second programming state may be, for example, state P2 and / or P3 in the first group of target programming states (corresponding to the first programming state S1), state P5 in the second group (corresponding to the first programming state S2), state P7 in the third group (corresponding to the first programming state S3), state P9 in the fourth group (corresponding to the first programming state S4), and state P11 in the fifth group (corresponding to the first programming state S5) as shown in Table 4. As shown in Table 5, the higher second programming state may be, for example, state P3 and / or P4 in the first group (corresponding to the first programming state S1), state P7 and / or P8 in the second group (corresponding to the first programming state S2), state P11 in the third group (corresponding to the first programming state S3), state P13 in the fourth group (corresponding to the first programming state S4), and state P15 in the fifth group (corresponding to the first programming state S5).

[0136] In some embodiments, the higher target programming state may have a higher threshold voltage than other second programming states in other groups of target programming states. In some embodiments, the higher second programming state may be a single target programming state after the division of step S502, and is associated with the higher first programming state in a one-to-one correlation. In some embodiments, the higher second programming state may be, for example, states P12, P13, P14, and / or P15 in Table 4 corresponding to higher first programming states S6, S7, S8, and / or S9, respectively. The higher second programming state may be, for example, states P12, P13, P14, and / or P15 in Table 5 corresponding to first programming states S4 and / or S5.

[0137] In step S504 , similar to step S303 in method 300 , a first programming operation may be performed on the memory cells to be programmed according to the grouping of the target programming states, wherein the i th group of memory cells may be programmed to the i th first programming state.

[0138] At step S505, a third programming operation (also referred to as a "further programming operation") may be performed on the memory cells to be programmed to the higher target programming state selected at step S503. For example, a subset of the i-th group of memory cells may be programmed from the i-th first programming state to the i-th third programming state, wherein the i-th third programming state may have a higher threshold voltage than the i-th first programming state, and the i-th third programming state corresponds to the higher target programming state.

[0139] At step S506, similar to step S304 of method 300, a second programming operation may be performed to program the memory cells to corresponding target programming states. Unlike method 300, in method 500, when programming the i-th group of memory cells, a subset of the i-th group of memory cells in the i-th third programming state may be programmed to a higher target programming state, and the remaining i-th group of memory cells in the i-th first programming state may be programmed to the remaining K i different target programming states.

[0140] In some embodiments, a higher target programming state can have a higher threshold voltage than other second programming states in the same group of target programming states. For example, in Table 4, the higher second programming state can be selected as state P2 and / or P3 in the first group of target programming states, state P5 in the second group, state P7 in the third group, state P9 in the fourth group, and state P5 in the fifth group at step S503. Within each group of target programming states, a third programming state (e.g., S1') can be created from a corresponding first programming state (e.g., S1) during a third programming operation at step S505. During a second programming operation at step S506, memory cells in the first programming state (e.g., S1) and the third programming state (e.g., S1') can be programmed to corresponding second programming states (e.g., S1 to P1 and S1' to P2 / P3) in a group (e.g., first group). Similarly, in Table 5, the higher second programming state can be selected as P3 and / or P4 in the first group of target programming states, state P7 and / or P8 in the second group, state P11 in the third group, state P13 in the fourth group, and state P15 in the fifth group. Within each group of target programming states, a third programming state (e.g., S2') can be created from a corresponding first programming state (e.g., S2) during a third programming operation. During the second programming operation, memory cells in the first programming state (e.g., S2) and the third programming state (e.g., S2') can be programmed to corresponding second programming states (e.g., S2 to P5 / P6 and S2' to P7 / P8) in a group (e.g., second group).

[0141] In some embodiments, in Table 4, the higher second programming state can be selected as state P12, P13, P14 and / or P15 at step S503. Here, the higher second programming state (e.g., P14) corresponds to a single target programming state in a group (e.g., the 8th group). In some embodiments, the higher second programming state (e.g., P14) corresponds to a higher first programming state (e.g., S8). During the third programming operation of step S505, a third programming state (e.g., S8') can be created from the higher first programming state (e.g., S8). The memory cells (e.g., all memory cells of the 8th group) programmed to the higher first programming state (e.g., S8) can be programmed to the third programming state (e.g., S8'). During the second programming operation, the memory cells in the third programming state (e.g., S8') can be programmed to the corresponding second programming state (e.g., P14). In other words, the first programming state S8 in Table 4 can be moved to the third programming state S8' during the third programming operation, and the third programming state S8' can be moved to the target programming state P14 during the second programming operation. Similarly, in Table 5, the higher second programming states can be states P12 / P13 and P14 / P15, corresponding to the higher first programming states S4 and S5, respectively. During the third programming operation, the memory cells in the higher first programming state (e.g., S5) can be programmed to the third programming state (e.g., S5'), and during the second programming operation, the memory cells in the third programming state (e.g., S5') can be programmed to the corresponding higher target programming states (e.g., P14 and P15).

[0142] Figure 6 A multi-pass programming scheme 600 according to some embodiments of the present disclosure is shown. The multi-pass programming scheme 600 may be similar to Figure 5 The method 500 shown in Figure 6 A set of threshold voltage distributions of the second programmed state and corresponding first and third programmed states are provided.

[0143] According to the multi-pass programming scheme 600, after the memory cells have been programmed to N first programming states by the first programming operation and have been verified by the first verification operation, a third programming operation may be performed on a subset of the memory cells to be programmed to a higher target programming state among each group of target programming states. For example, after the first programming operation, the i-th group of memory cells may be programmed to the i-th first programming state S corresponding to the i-th group of target programming states. i Unlike methods 200 and 300 and multi-pass programming scheme 400, before performing the second programming operation, a third programming operation may be performed to program a subset of the i-th group of memory cells to a third programming state S i', where the third programming state S i ' can be higher than the first programming state S i , that is, corresponding to a larger threshold voltage. For example, the third programming state S i The lower edge of the threshold voltage distribution V th _Si' can be higher than the first programming state S i The lower edge V th Next, during the second programming operation, the third programming state S i A subset of the memory cells of the ith group may be programmed to target program states F3 and F4, while the remaining memory cells in the ith group may be programmed to target program states F1 and F2. Figure 6 As shown, among the i-th group of target programming states, states F3 and F4 are higher than states F1 and F2.

[0144] In some embodiments, the program voltage used in the third program operation may be similar to the step pulse V used in the ISPP scheme. step In some embodiments, a verification operation may be performed or omitted after the third programming operation.

[0145] By using an additional third programming operation, the coupling effect between adjacent word lines can be reduced when programming is performed using a multiple-pass programming scheme. In some embodiments, a first programming operation can be performed on a memory cell coupled to a first word line. After verifying that the memory cell coupled to the first word line has been successfully programmed to the first programming state, the first programming operation can be performed on a memory cell coupled to a second word line adjacent to the first word line. After verifying that the memory cell coupled to the second word line has been successfully programmed to the first programming state, a second programming operation can be performed on the memory cell coupled to the first word line, followed by a second programming operation on the memory cell coupled to the second word line. Therefore, multiple-pass programming can be performed alternately on the memory cell coupled to the adjacent word line. However, when the second programming operation is performed on the memory cell coupled to the first word line, a higher programming voltage can be used for a higher target programming state. Therefore, the memory cell coupled to the second word line may be susceptible to capacitive coupling effects from the memory cell coupled to the second word line. By using at least one additional programming voltage (during a third programming operation) after the first programming operation and the first verification operation, memory cells to be programmed to a higher target programming state (e.g., F3 or F4) may be programmed to a higher target programming state than the first programming state (e.g., S i ) of the third programming state (eg, S i '). Therefore, during the second programming operation, a lower programming voltage may be used to program the memory cell from the third programming state (eg, S i') to a higher target programming state (e.g., F3 or F4). Similarly, for each group with two or more target programming states, a subset of memory cells can be programmed from a first programming state to a third programming state higher than the first programming state, and from the third programming state to the target programming state. By using an additional programming operation between the first programming operation and the second programming operation, the programming voltage for the target programming state can be reduced during the second programming operation. Therefore, for a multi-pass programming scheme, the capacitive coupling effect between adjacent word lines can be improved.

[0146] In some embodiments, the third programming operation may be performed after the first programming operation and the first verification operation have been performed for all first programming states. In some embodiments, the third programming operation may be performed after the first programming operation and the first verification operation have been performed for each first programming state or a certain first programming state.

[0147] exist Figure 6 In the example, the third programming state S i ' corresponds to two target programming states F3 and F4. It should be noted that the scope of the present disclosure is not limited to the 1-2 correspondence between the third programming state and the target programming state. i ' can correspond to K in the i-th group i , 1, 2, 3, . . . or any suitable number of target programming states within a target programming state.

[0148] Figure 7 A multi-pass programming scheme 700 according to some embodiments of the present disclosure is shown. The multi-pass programming scheme 700 may be similar to Figure 6 600 in the multi-pass programming scheme. Unlike the multi-pass programming scheme 600, according to the multi-pass programming scheme 700, after the third programming operation, the third programming state does not necessarily have a higher threshold voltage than the corresponding first programming state. Instead, the third programming state has a wider threshold voltage distribution than the corresponding first programming state.

[0149] According to the multi-pass programming scheme 700, after the memory cells have been programmed to N first programming states by the first programming operation and have been verified by the first verification operation, a third programming operation may be performed on a subset of the memory cells to be programmed to a higher target programming state among each group of target programming states. For example, after the first programming operation, the i-th group of memory cells may be programmed to the i-th first programming state S corresponding to the i-th group of target programming states. i Unlike the multi-pass programming scheme 600, before performing the second programming operation, a third programming operation may be performed to program a subset of the i-th group of memory cells to a third programming state S i', where the third programming state S i ' can have a higher programming state than the first programming state S i For example, the third programming state S i The width W of the threshold voltage distribution i ' can be greater than the first programming state S i Width W i Next, during the second programming operation, the third programming state S i A subset of the memory cells of the ith group may be programmed to target program states F3 and F4, while the remaining memory cells in the ith group may be programmed to target program states F1 and F2. Figure 7 As shown in , among the i-th group of target programming states, states F3 and F4 are higher than states F1 and F2.

[0150] According to the multi-pass programming scheme 700, by using at least one additional programming voltage (during a third programming operation) after the first programming operation and the first verification operation, the memory cells to be programmed to a higher target programming state (e.g., F3 or F4) can be programmed to have a higher target programming state than the first programming state (e.g., S i ) a third programming state (eg, S i '). Therefore, during the second programming operation, a lower programming voltage may be used to program the memory cell from the third programming state (eg, S i ') to a higher target programming state (e.g., F3 or F4). Similarly, for each group having two or more target programming states, a subset of memory cells can be programmed from a first programming state to a third programming state having a wider threshold voltage distribution than the first programming state, and from the third programming state to the target programming state. By using an additional programming operation between the first programming operation and the second programming operation, the programming voltage of the target programming state can be reduced during the second programming operation. Therefore, for a multi-pass programming scheme, the capacitive coupling effect between adjacent word lines can be improved.

[0151] exist Figure 7 In the example, the third programming state S i ' corresponds to two target programming states F3 and F4. It should be noted that the scope of the present disclosure is not limited to the 1-2 correspondence between the third programming state and the target programming state. i ' can correspond to K in the i-th group i , 1, 2, 3, . . . or any suitable number of target programming states within a target programming state.

[0152] In summary, the present disclosure provides a programming method for a memory device. The method includes performing a first programming operation on memory cells to be programmed, so that each memory cell is programmed to a corresponding first programming state among N different first programming states, where N is a positive integer greater than 1 and less than M; and M is the total number of target programming states of the memory cells. The method also includes performing a second programming operation to program the i-th group of memory cells in the i-th first programming state to K i different target programming states, where K i is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; and at least two first programmed states correspond to different k values.

[0153] In some embodiments, the method further includes dividing the target programming state into N groups corresponding to N different first programming states based on the coupling offset of the target programming state during programming, wherein the i-th group of target programming states has K i target programming state.

[0154] In some embodiments, performing the first programming operation includes performing the first programming operation according to N groups of target programming states, wherein each memory cell is programmed to a corresponding one of N different first programming states according to the N groups.

[0155] In some implementations, the method further includes grouping adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

[0156] In some embodiments, the method further includes grouping a first group of adjacent target programming states having a coupling offset less than a first preset threshold into a first group; grouping a second group of adjacent target programming states having a coupling offset greater than or equal to the first preset threshold but less than a second preset threshold into a second group; and grouping a third group of adjacent target programming states having a coupling offset greater than or equal to the second preset threshold into a third group.

[0157] In some implementations, the method further includes determining a coupling offset of the target programmed state by measuring a change in a threshold voltage of a memory cell coupled to a selected word line affected by a threshold voltage of a memory cell coupled to an adjacent word line.

[0158] In some implementations, the method further includes, after performing the first programming operation, performing a first verification operation to determine whether each memory cell is programmed to a corresponding first program state.

[0159] In some embodiments, the method further includes performing a first programming operation on the memory cell during each of the one or more loops; after each of the one or more loops, determining whether to proceed to the next loop based on a result of the first verification operation; stopping the first programming operation if the result shows that the memory cell passes the first verification operation; and proceeding to the next loop until each memory cell is programmed to a corresponding one of N different first programming states.

[0160] In some embodiments, the method further includes determining N different first program states using N different first verification voltages.

[0161] In some embodiments, the method further includes, after performing the second programming operation, performing a second verification operation to determine whether each memory cell is programmed to a corresponding target programming state, wherein a different second verification voltage is used to verify K i different target programming states.

[0162] In some embodiments, the i-th first verification voltage for verifying the i-th first programming state is less than the i-th first verification voltage for verifying the K i any second verification voltage for a target programmed state.

[0163] In some embodiments, the method further includes programming the memory cells in a triple-level cell (TLC) mode, wherein each memory cell has 8 states; or programming the memory cells in a quad-level cell (QLC) mode, wherein each memory cell has 16 states.

[0164] The present disclosure also provides a programming method for a memory device. The method includes performing a first programming operation to program memory cells of the memory device to a first programming state, wherein each first programming state corresponds to a group of target programming states, and at least two groups have different numbers of target programming states; performing a further programming operation on a subset of memory cells in a selected first programming state, wherein the selected first programming state corresponds to a selected target programming state; and performing a second programming operation to program the subset of memory cells to the selected target programming state, and programming the remaining memory cells to the remaining target programming states according to the correspondence between each first programming state and the corresponding group of target programming states.

[0165] In some implementations, the method further includes dividing the target program states into different groups based on coupling offsets of the target program states during programming.

[0166] In some implementations, the method further includes grouping adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

[0167] In some implementations, the method further includes determining a coupling offset of the target programmed state by measuring a change in a threshold voltage of a memory cell coupled to a selected word line affected by a threshold voltage of a memory cell coupled to an adjacent word line.

[0168] In some implementations, the method further includes selecting a selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than other target program states within the same group.

[0169] In some implementations, the method further includes selecting a selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than any target program state in another group.

[0170] In some embodiments, the method further includes performing a first programming operation during each cycle in a first cycle set; and performing a second programming operation during each cycle in a second cycle set, wherein the programming voltage is incrementally increased in each cycle in the first cycle set and / or in each cycle in the second cycle set.

[0171] In some embodiments, the method further includes performing a first verification operation after the first programming operation to verify whether each memory cell is in a corresponding first programming state; and performing a second verification operation after the second programming operation to verify whether each memory cell is in a corresponding second programming state.

[0172] In some implementations, the method further includes programming the memory cells in a quad level cell (QLC) mode, wherein each memory cell has 16 states.

[0173] The present disclosure also provides a memory device, the memory device comprising: a memory array including memory cells; and a peripheral circuit coupled to the memory array. The peripheral circuit is configured to perform a first programming operation on the memory cells to be programmed, so that each memory cell is programmed to a corresponding first programming state among N different first programming states, where N is a positive integer greater than 1 and less than M; and M is the total number of target programming states of the memory cells. The peripheral circuit is also configured to perform a second programming operation to program the i-th group of memory cells in the i-th first programming state to K i target programming states, where K iis greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; and at least two first programmed states correspond to different k values.

[0174] In some embodiments, the peripheral circuit is further configured to divide the target programming state into N groups corresponding to N different first programming states based on the coupling offset of the target programming state during programming, wherein the i-th group of target programming states has K i target programming state.

[0175] In some embodiments, the peripheral circuit is further configured to perform a first programming operation according to N groups of target programming states, wherein each memory cell is programmed to a corresponding one of N different first programming states according to the N groups.

[0176] In some embodiments, the peripheral circuit is further configured to group adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

[0177] In some embodiments, the peripheral circuit is further configured to group a first group of adjacent target programming states having a coupling offset less than a first preset threshold into a first group; group a second group of adjacent target programming states having a coupling offset greater than or equal to the first preset threshold but less than a second preset threshold into a second group; and group a third group of adjacent target programming states having a coupling offset greater than or equal to the second preset threshold into a third group.

[0178] In some implementations, the peripheral circuit is further configured to determine a coupling offset of the target programming state by measuring a change in threshold voltages of memory cells coupled to the selected word line affected by threshold voltages of memory cells coupled to adjacent word lines.

[0179] In some embodiments, the peripheral circuit is further configured to perform a first verification operation to determine whether each memory cell is programmed to a corresponding first program state after performing the first program operation.

[0180] In some embodiments, the peripheral circuit is further configured to perform a first programming operation on the memory cell during each of one or more loops; after each of the one or more loops, determine whether to proceed to the next loop based on the result of the first verification operation; if the result shows that the memory cell passes the first verification operation, stop the first programming operation; and proceed to the next loop until each memory cell is programmed to a corresponding one of N different first programming states.

[0181] In some embodiments, the peripheral circuit is further configured to verify the N different first program states using the N different first verification voltages.

[0182] In some embodiments, the peripheral circuit is further configured to perform a second verification operation after performing the second programming operation to determine whether each memory cell is programmed to a corresponding target programming state, wherein different second verification voltages are used to verify K i different target programming states.

[0183] In some embodiments, the i-th first verification voltage for verifying the i-th first programming state is less than the i-th first verification voltage for verifying the K i any second verification voltage for a target programmed state.

[0184] In some embodiments, the peripheral circuit is further configured to program the memory cells in a triple-level cell (TLC) mode, where each memory cell has 8 states; or to program the memory cells in a quad-level cell (QLC) mode, where each memory cell has 16 states.

[0185] The present disclosure also provides a memory device, the memory device comprising: a memory array including memory cells; and a peripheral circuit coupled to the memory array. The peripheral circuit is configured to perform a first programming operation to program the memory cells of the memory device to a first programming state, wherein each first programming state corresponds to a group of target programming states, and at least two groups have different numbers of target programming states. The peripheral circuit is also configured to perform a further programming operation on a subset of the memory cells in a selected first programming state, wherein the selected first programming state corresponds to a selected target programming state. The peripheral circuit is also configured to perform a second programming operation to program a subset of the memory cells to the selected target programming state, and program the remaining memory cells to the remaining target programming states according to the correspondence between each first programming state and the corresponding group of target programming states.

[0186] In some embodiments, the peripheral circuit is further configured to divide the target program states into different groups based on coupling offsets of the target program states during programming.

[0187] In some embodiments, the peripheral circuit is further configured to group adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

[0188] In some implementations, the peripheral circuit is further configured to determine a coupling offset of the target programming state by measuring a change in threshold voltages of memory cells coupled to the selected word line affected by threshold voltages of memory cells coupled to adjacent word lines.

[0189] In some implementations, the peripheral circuit is further configured to select a selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than other target program states within the same group.

[0190] In some implementations, the peripheral circuit is further configured to select a selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than any target program state in another group.

[0191] In some embodiments, the peripheral circuit is also configured to perform a first programming operation during each cycle in a first cycle set; and to perform the second programming operation during each cycle in a second cycle set, wherein the programming voltage is increased in an incremental manner in each cycle in the first cycle set and / or in each cycle in the second cycle set.

[0192] In some embodiments, the peripheral circuit is further configured to perform a first verification operation after the first programming operation to verify whether each memory cell is in a corresponding first programming state; and to perform a second verification operation after the second programming operation to verify whether each memory cell is in a corresponding second programming state.

[0193] In some embodiments, the peripheral circuit is further configured to program the memory cells in a quad level cell (QLC) mode, where each memory cell has 16 states.

[0194] The present disclosure also provides a memory system, the memory system comprising: a memory controller; and a memory device. The memory device comprises: a memory array, comprising memory cells; and a peripheral circuit coupled to the memory array. The peripheral circuit is configured to perform a first programming operation on the memory cells to be programmed, so that each memory cell is programmed to a corresponding first programming state among N different first programming states, wherein N is a positive integer greater than 1 and less than M; and M is the total number of target programming states of the memory cells. The peripheral circuit is also configured to perform a second programming operation to program the i-th group of memory cells in the i-th first programming state to K i target programming states, where K i is greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; and at least two first programmed states correspond to different k values.

[0195] The present disclosure also provides a memory system, which has a memory controller; and a memory device. The memory device includes: a memory array, including memory cells; and a peripheral circuit coupled to the memory array. The peripheral circuit is configured to perform a first programming operation to program the memory cells of the memory device to a first programming state, wherein each first programming state corresponds to a group of target programming states, and at least two groups have different numbers of target programming states; perform a further programming operation on a subset of memory cells in a selected first programming state, wherein the selected first programming state corresponds to a selected target programming state; and perform a second programming operation to program a subset of memory cells to the selected target programming state, and program the remaining memory cells to the remaining target programming states according to the correspondence between each first programming state and the corresponding group of target programming states.

[0196] The foregoing description of the specific embodiments will disclose the general nature of the present disclosure so fully that others can easily modify and / or adjust such specific embodiments for various applications by applying knowledge within the art without undue experimentation and without departing from the general concepts of the present disclosure. Therefore, based on the disclosure and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalent transformations of the disclosed embodiments. It should be understood that the words or terms herein are for descriptive purposes and are not restrictive, so that the terms or words of this specification will be interpreted by those skilled in the art in accordance with the disclosure and guidance.

[0197] Embodiments of the present disclosure have been described above by means of the functional building blocks of the embodiments of the specified functions and their relationships. For ease of description, the limits of these functional building blocks have been arbitrarily defined herein. As long as specific functions and their relationships are appropriately performed, replaceable limits can be defined.

[0198] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0199] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method for programming a memory device, comprising: A first programming operation is performed on the memory cells to be programmed, so that each of the memory cells is programmed to a corresponding one of N different first programming states; wherein: N is a positive integer greater than 1 and less than M; and M is the total number of target programming states for the memory cells; and A second programming operation is performed to program the i-th group of memory cells in the i-th first programming state to K i different target programming states, among which, K i Greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; and At least two first programming states correspond to different K i value.

2. The method according to claim 1, further comprising: During programming, the target programming state is divided into N groups corresponding to the N different first programming states based on the coupling offset of the target programming state, wherein the i-th group of target programming states has K i target programming state.

3. The method according to claim 2, wherein: Performing a first programming operation includes performing the first programming operation according to the target programming states of the N groups, wherein each of the memory cells is programmed to the corresponding one of the N different first programming states according to the N groups.

4. The method according to claim 3, further comprising: When the coupling offsets of the adjacent target program states are within a predetermined range, the adjacent target program states are grouped in the same group.

5. The method according to claim 4, further comprising: grouping a first group of adjacent target programming states having coupling offsets less than a first preset threshold into a first group; grouping a second group of adjacent target programming states having coupling offsets greater than or equal to the first preset threshold but less than a second preset threshold into a second group; as well as A third group of adjacent target programming states having coupling offsets greater than or equal to the second preset threshold are grouped into a third group.

6. The method according to claim 2, further comprising: The coupling offset of the target programmed state is determined by measuring a change in threshold voltage of a memory cell coupled to a selected word line as affected by threshold voltages of memory cells coupled to adjacent word lines.

7. The method according to claim 1, further comprising: After performing the first programming operation, a first verification operation is performed to determine whether each of the memory cells is programmed to the corresponding one of the N different first programming states.

8. The method according to claim 7, further comprising: performing the first programming operation on the memory cell during each of one or more cycles; After each of the one or more cycles, determining whether to proceed to the next cycle according to a result of the first verification operation; If the result shows that the memory cell passes the first verification operation, stopping the first programming operation; as well as The next loop is performed until each of the memory cells is programmed to the corresponding one of the N different first programmed states.

9. The method according to claim 7, further comprising: The N different first program states are determined using N different first verification voltages.

10. The method according to claim 7, further comprising: After performing the second programming operation, performing a second verification operation to determine whether each of the memory cells is programmed to a corresponding target programming state, wherein a different second verification voltage is used to verify the K i different target programming states.

11. The method according to claim 10, wherein: The i-th first verification voltage for verifying the i-th first programming state is less than the voltage for verifying the K i any one of the second verification voltages of the target programming states.

12. The method according to claim 1, further comprising: Programming the memory cells in a triple-level cell (TLC) mode, wherein each of the memory cells has eight states; or The memory cells are programmed in a quad level cell (QLC) mode, wherein each of the memory cells has 16 states.

13. A method for programming a memory device, comprising: performing a first programming operation to program memory cells of the memory device to first programming states, wherein each of the first programming states corresponds to a group of target programming states, and at least two groups have different numbers of target programming states; performing a further programming operation on a subset of the memory cells in a selected first programming state, wherein the selected first programming state corresponds to a selected target programming state; and A second programming operation is performed to program the subset of the memory cells to the selected target programming state, and to program the remaining memory cells to the remaining target programming states according to a correspondence between each of the first programming states and a respective group of the target programming states.

14. The method according to claim 13, further comprising: The target program states are divided into different groups based on their coupling offsets during programming.

15. The method according to claim 14, further comprising: When the coupling offsets of the adjacent target program states are within a predetermined range, the adjacent target program states are grouped in the same group.

16. The method according to claim 14, further comprising: The coupling offset of the target programmed state is determined by measuring a change in threshold voltage of a memory cell coupled to a selected word line as affected by threshold voltages of memory cells coupled to adjacent word lines.

17. The method according to claim 13, further comprising: The selected target program state is selected from the target program states, wherein the selected target program state has a higher threshold voltage than other target program states within the same group.

18. The method according to claim 13, further comprising: The selected target program state is selected from the target program states, wherein the selected target program state has a higher threshold voltage than any target program state in another group.

19. The method according to claim 13, further comprising: performing the first programming operation during each cycle in a first set of cycles; as well as performing the second programming operation during each loop in a second set of loops, Wherein, the programming voltage is increased in an incremental manner in each cycle in the first cycle set and / or in each cycle in the second cycle set.

20. The method of claim 13, further comprising: performing a first verification operation after the first programming operation to verify whether each of the memory cells is in a corresponding first programming state; as well as A second verification operation is performed after the second programming operation to verify whether each of the memory cells is in a corresponding second programming state.

21. The method of claim 13, further comprising: The memory cells are programmed in a quad level cell (QLC) mode, wherein each of the memory cells has 16 states.

22. A memory device comprising: A memory array including memory cells; as well as A peripheral circuit is coupled to the memory array and is configured to: A first programming operation is performed on the memory cells to be programmed, so that each of the memory cells is programmed to a corresponding one of N different first programming states, wherein: N is a positive integer greater than 1 and less than M; and M is the total number of target programming states for the memory cells; and A second programming operation is performed to program the i-th group of memory cells in the i-th first programming state to K i target programming states, where: K i Greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; and At least two first programming states correspond to different K i value.

23. The memory device of claim 22, wherein: The peripheral circuit is further configured as: During programming, the target programming state is divided into N groups corresponding to the N different first programming states based on the coupling offset of the target programming state, wherein the i-th group of target programming states has K i target programming state.

24. The memory device of claim 23, wherein: The peripheral circuit is further configured to perform the first programming operation according to the target programming states of the N groups, wherein each of the memory cells is programmed to the corresponding one of the N different first programming states according to the N groups.

25. The memory device of claim 24, wherein: The peripheral circuit is further configured to group adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

26. The memory device of claim 25, wherein: The peripheral circuit is further configured as: grouping a first group of adjacent target programming states having coupling offsets less than a first preset threshold into a first group; grouping a second group of adjacent target programming states having coupling offsets greater than or equal to the first preset threshold but less than a second preset threshold into a second group; as well as A third group of adjacent target programming states having coupling offsets greater than or equal to the second preset threshold are grouped into a third group.

27. The memory device of claim 23, wherein: The peripheral circuit is further configured to determine the coupling offset of the target program state by measuring a change in threshold voltage of memory cells coupled to a selected word line affected by threshold voltages of memory cells coupled to adjacent word lines.

28. The memory device of claim 22, wherein: The peripheral circuit is further configured to perform a first verification operation after performing the first programming operation to determine whether each of the memory cells is programmed to the corresponding one of the N different first programming states.

29. The memory device of claim 28, wherein: The peripheral circuit is further configured as: performing the first programming operation on the memory cell during each of one or more cycles; After each of the one or more cycles, determining whether to proceed to the next cycle according to a result of the first verification operation; If the result shows that the memory cell passes the first verification operation, stopping the first programming operation; as well as The next loop is performed until each of the memory cells is programmed to the corresponding one of the N different first programmed states.

30. The memory device of claim 28, wherein: The peripheral circuit is further configured to verify the N different first program states using N different first verification voltages.

31. The memory device of claim 28, wherein: The peripheral circuit is further configured to perform a second verification operation after performing the second programming operation to determine whether each of the memory cells is programmed to a corresponding target programming state, wherein different second verification voltages are used to verify K i different target programming states.

32. The memory device of claim 31, wherein: The i-th first verification voltage for verifying the i-th first programming state is less than the voltage for verifying the K i any one of the second verification voltages of the target programming states.

33. The memory device of claim 22, wherein: The peripheral circuit is further configured as: Programming the memory cells in a triple-level cell (TLC) mode, wherein each of the memory cells has eight states; or The memory cells are programmed in a quad level cell (QLC) mode, wherein each of the memory cells has 16 states.

34. A memory device comprising: A memory array including memory cells; as well as A peripheral circuit is coupled to the memory array and is configured to: performing a first programming operation to program the memory cells of the memory device to first programming states, wherein each of the first programming states corresponds to a group of target programming states and at least two groups have different numbers of target programming states; performing a further programming operation on a subset of memory cells in a selected first programming state, wherein the selected first programming state corresponds to a selected target programming state; and A second programming operation is performed to program the subset of the memory cells to the selected target programming state, and to program the remaining memory cells to the remaining target programming states according to a correspondence between each of the first programming states and a respective group of the target programming states.

35. The memory device of claim 34, wherein: The peripheral circuit is also configured to divide the target program states into different groups based on coupling offsets of the target program states during programming.

36. The memory device of claim 35, wherein: The peripheral circuit is further configured to group adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

37. The memory device of claim 35, wherein: The peripheral circuit is further configured to determine the coupling offset of the target program state by measuring a change in threshold voltage of memory cells coupled to a selected word line affected by threshold voltages of memory cells coupled to adjacent word lines.

38. The memory device of claim 34, wherein: The peripheral circuit is further configured to select the selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than other target program states within the same group.

39. The memory device of claim 34, wherein: The peripheral circuit is further configured to select the selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than any target program state in another group.

40. The memory device of claim 34, wherein: The peripheral circuit is further configured as: performing the first programming operation during each cycle in a first set of cycles; as well as performing the second programming operation during each loop in a second set of loops, Wherein, the programming voltage is increased in an incremental manner in each cycle in the first cycle set and / or in each cycle in the second cycle set.

41. The memory device of claim 34, wherein: The peripheral circuit is further configured as: performing a first verification operation after the first programming operation to verify whether each of the memory cells is in a corresponding first programming state; as well as A second verification operation is performed after the second programming operation to verify whether each of the memory cells is in a corresponding second programming state.

42. The memory device of claim 34, wherein: The peripheral circuit is also configured to program the memory cells in a quad-level cell (QLC) mode, wherein each of the memory cells has 16 states.

43. A memory system comprising: Memory controller; as well as A memory device, the memory device comprising: a memory array comprising memory cells; and A peripheral circuit is coupled to the memory array and is configured to: A first programming operation is performed on the memory cells to be programmed, so that each of the memory cells is programmed to a corresponding one of N different first programming states, wherein: N is a positive integer greater than 1 and less than M; and M is the total number of target programming states for the memory cells; and A second programming operation is performed to program the i-th group of memory cells in the i-th first programming state to K i target programming states, where: K i Greater than or equal to 1 and less than N; i is greater than or equal to 1 and less than or equal to N; and At least two first programming states correspond to different K i value.

44. The memory system of claim 43, wherein: The peripheral circuit is further configured as: During programming, the target programming state is divided into N groups corresponding to the N different first programming states based on the coupling offset of the target programming state, wherein the i-th group of target programming states has K i target programming state.

45. The memory system of claim 44, wherein: The peripheral circuit is further configured to perform the first programming operation according to the target programming states of the N groups, wherein each of the memory cells is programmed to the corresponding one of the N different first programming states according to the N groups.

46. ​​The memory system of claim 45, wherein: The peripheral circuit is further configured to group adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

47. The memory system of claim 46, wherein: The peripheral circuit is further configured as: grouping a first group of adjacent target programming states having coupling offsets less than a first preset threshold into a first group; grouping a second group of adjacent target programming states having coupling offsets greater than or equal to the first preset threshold but less than a second preset threshold into a second group; as well as A third group of adjacent target programming states having coupling offsets greater than or equal to the second preset threshold are grouped into a third group.

48. The memory system of claim 44, wherein: The peripheral circuit is further configured to determine the coupling offset of the target program state by measuring a change in threshold voltage of memory cells coupled to a selected word line affected by threshold voltages of memory cells coupled to adjacent word lines.

49. The memory system of claim 43, wherein: The peripheral circuit is further configured to perform a first verification operation after performing the first programming operation to determine whether each of the memory cells is programmed to the corresponding one of the N different first programming states.

50. The memory system of claim 49, wherein: The peripheral circuit is further configured as: performing the first programming operation on the memory cell during each of one or more cycles; After each of the one or more cycles, determining whether to proceed to the next cycle according to a result of the first verification operation; If the result shows that the memory cell passes the first verification operation, stopping the first programming operation; as well as The next loop is performed until each of the memory cells is programmed to the corresponding one of the N different first programmed states.

51. The memory system of claim 49, wherein: The peripheral circuit is further configured to verify the N different first program states using N different first verification voltages.

52. The memory system of claim 49, wherein: The peripheral circuit is further configured to perform a second verification operation after performing the second programming operation to determine whether each of the memory cells is programmed to a corresponding target programming state, wherein different second verification voltages are used to verify K i different target programming states.

53. The memory system of claim 52, wherein: The i-th first verification voltage for verifying the i-th first programming state is less than the voltage for verifying the K i any one of the second verification voltages of the target programming states.

54. The memory system of claim 43, wherein: The peripheral circuit is further configured as: Programming the memory cells in a triple-level cell (TLC) mode, wherein each of the memory cells has eight states; or The memory cells are programmed in a quad level cell (QLC) mode, wherein each of the memory cells has 16 states.

55. A memory system comprising: Memory controller; as well as A memory device, the memory device comprising: a memory array comprising memory cells; and A peripheral circuit is coupled to the memory array and is configured to: performing a first programming operation to program the memory cells of the memory device to first programming states, wherein each of the first programming states corresponds to a group of target programming states and at least two groups have different numbers of the target programming states; performing a further programming operation on a subset of memory cells in a selected first programming state, wherein the selected first programming state corresponds to a selected target programming state; and A second programming operation is performed to program the subset of the memory cells to the selected target programming state, and to program the remaining memory cells to the remaining target programming states according to a correspondence between each of the first programming states and a respective group of the target programming states.

56. The memory system of claim 55, wherein: The peripheral circuit is also configured to divide the target program states into different groups based on coupling offsets of the target program states during programming.

57. The memory system of claim 56, wherein: The peripheral circuit is further configured to group adjacent target program states into a same group when coupling offsets of the adjacent target program states are within a predetermined range.

58. The memory system of claim 56, wherein: The peripheral circuit is further configured to determine the coupling offset of the target program state by measuring a change in threshold voltage of memory cells coupled to a selected word line affected by threshold voltages of memory cells coupled to adjacent word lines.

59. The memory system of claim 55, wherein: The peripheral circuit is further configured to select the selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than other target program states within the same group.

60. The memory system of claim 55, wherein: The peripheral circuit is further configured to select the selected target program state from the target program states, wherein the selected target program state has a higher threshold voltage than any target program state in another group.

61. The memory system of claim 55, wherein: The peripheral circuit is further configured as: performing the first programming operation during each cycle in a first set of cycles; as well as performing the second programming operation during each loop in a second set of loops, Wherein, the programming voltage is increased in an incremental manner in each cycle in the first cycle set and / or in each cycle in the second cycle set.

62. The memory system of claim 55, wherein: The peripheral circuit is further configured as: performing a first verification operation after the first programming operation to verify whether each of the memory cells is in a corresponding first programming state; as well as A second verification operation is performed after the second programming operation to verify whether each of the memory cells is in a corresponding second programming state.

63. The memory system of claim 55, wherein: The peripheral circuit is also configured to program the memory cells in a quad-level cell (QLC) mode, wherein each of the memory cells has 16 states.

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