Noise shaping in multi-level analog-to-digital converter

Abstract

Methods and apparatus for noise shaping in a multi-stage analog-to-digital converter (ADC). An example ADC generally includes a first conversion stage having a residual output; an amplifier having an input selectively coupled to the residual output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched capacitor network configured to provide a second order or higher order noise transfer function for noise shaping of quantization noise of the second conversion stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 804,779, filed on May 31, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated by reference in its entirety, as if fully set forth below and for all applicable purposes. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits and, more particularly, to techniques and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). Background Art

[0004] Electronic devices include computing devices such as desktop computers, notebook computers, tablet computers, smart phones, wearable devices such as smart watches, Internet servers, etc. These various electronic devices provide information, entertainment, social interaction, security, safety, productivity, transportation, manufacturing and other services for human users. Many functions of these various electronic devices rely on wireless communication. Wireless communication systems and devices are widely deployed to provide various communication services such as telephone, video, data, message reception and transmission, broadcasting, etc. Such wireless communication devices can send and / or receive radio frequency (RF) signals via any radio access technology (RAT) in various suitable radio access technologies (RAT), including but not limited to 5G new radio (NR), long term evolution (LTE), code division multiple access (CDMA), time division multiple access (TDMA), wideband CDMA (WCDMA), global system for mobile (GSM), Bluetooth, Bluetooth low energy (BLE), ZigBee, wireless local area network (WLAN) RAT (e.g., WiFi), etc.

[0005] Wireless devices in these and other communication systems may include one or more analog-to-digital converters (ADCs) for converting received, amplified, filtered, and down-converted analog signals into digital signals for use in, for example, additional signal processing in the digital domain. Several types of ADCs are available, some more suitable for specific applications than others. For example, a successive approximation register (SAR) ADC may provide an area and power efficient architecture for low to medium precision analog-to-digital conversion applications. A SAR ADC may use a digital-to-analog converter (DAC) and a comparator to approximate a digital value corresponding to an analog input. Another type of ADC, called a "flash ADC," may provide a faster conversion speed than a SAR ADC at the expense of an exponential increase in power and area consumption. Another type of ADC having a faster sampling rate than a SAR ADC but lower power and area consumption than a flash ADC is referred to as a "pipelined ADC." Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desired characteristics. Without limiting the scope of the present application as expressed by the subsequent claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," it will be understood how the features of the present disclosure provide advantages, including: increased noise shaping flexibility in a multi-stage analog-to-digital converter (ADC), increased dynamic range, increased operating speed or reduced power consumption of the ADC, and reduced lateral area (e.g., footprint) of the ADC compared to some other analog-to-digital converter (ADC) topologies.

[0007] Certain aspects of the present disclosure provide an ADC. The ADC generally includes: a first conversion stage having a residual output; an amplifier having an input selectively coupled to the residual output of the first conversion stage; a second conversion stage having an input selectively coupled to the output of the amplifier; and a switched capacitor network having a first port coupled to the input of the amplifier and a second port coupled to the input of the second conversion stage, the switched capacitor network being configured to provide a second-order or higher-order noise transfer function for noise shaping of quantization noise of the second conversion stage.

[0008] Certain aspects of the present disclosure provide an ADC. The ADC generally includes: a first conversion stage having a residual output; an amplifier having an input selectively coupled to the residual output of the first conversion stage; a second conversion stage having an input selectively coupled to the output of the amplifier; and a switched capacitor network having a first port coupled to the input of the amplifier and a second port coupled to the input of the second conversion stage, the switched capacitor network having a first capacitive element having a first terminal coupled to the second port and having a second terminal selectively coupled to a reference potential node of the ADC and selectively coupled to the first port.

[0009] Certain aspects of the present disclosure provide a wireless device. The wireless device includes an ADC as described herein, one or more antennas, and one or more receive paths coupled between the one or more antennas and one or more inputs of the ADC.

[0010] Certain aspects of the present disclosure provide an analog-to-digital conversion method using an ADC, the ADC generally comprising a first conversion stage, a second conversion stage, an amplifier selectively coupled between the first conversion stage and the second conversion stage, and a switched capacitor network coupled between an input terminal of the amplifier and an input terminal of the second conversion stage. The method generally comprises: coupling a first capacitive element of the switched capacitor network in parallel with a capacitive element associated with the second conversion stage during a conversion phase of the ADC, and coupling the first capacitive element between the input terminal of the amplifier and an output terminal of the amplifier during an amplification phase of the ADC.

[0011] Certain aspects of the present disclosure provide an ADC. The ADC generally includes a first component for converting an analog input signal into a first digital output signal, a component for amplifying a residue from the first component for converting, a second component for converting the amplified residue into a second digital output signal, and a component for providing a second or higher order noise transfer function for noise shaping of quantization noise of the second component for converting.

[0012] To achieve the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0014] Figure 1 is an illustration of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0015] Figure 2 is a block diagram conceptually illustrating designs of example base stations (BSs) and user equipment (UEs) in which aspects of the present disclosure may be practiced.

[0016] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0017] Figure 4 is a block diagram of an example multi-stage analog-to-digital converter (ADC) in which aspects of the present disclosure may be practiced.

[0018] Figure 5 is a schematic diagram of a portion of an example multi-stage ADC illustrating an example switched capacitor network in accordance with certain aspects of the present disclosure.

[0019] Fig. 6A During a first switching cycle, certain aspects of the present disclosure are illustrated. Figure 5 Example switch configuration in a switched capacitor network.

[0020] Figure 6B During the second switching cycle according to certain aspects of the present disclosure, Figure 5 Example switch configuration in a switched capacitor network.

[0021] Figure 6C During a first amplification cycle, certain aspects of the present disclosure are illustrated. Figure 5 Example switch configuration in a switched capacitor network.

[0022] Fig.6D During the second amplification cycle, certain aspects of the present disclosure are illustrated. Figure 5 Example switch configuration in a switched capacitor network.

[0023] Figure 7 is a flow chart of example operations for analog-to-digital conversion in accordance with certain aspects of the present disclosure.

[0024] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0025] Certain aspects of the present invention relate to techniques and apparatus for performing noise shaping in a multi-stage analog-to-digital converter (ADC) (e.g., a pipeline ADC) to push quantization error and a portion of circuit noise out of the signal band and thereby increase the dynamic range of the ADC. A switched capacitor network may be implemented in the last stage of the multi-stage ADC to produce a second-order (or higher-order) delay for noise shaping. For certain aspects, the capacitive element may be used: (1) as a feedback capacitor during inter-stage amplification, (2) for reference scaling during quantization of the last stage, and (3) for preserving a residual at the end of quantization.

[0026] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functions, or structures and functions other than the various aspects of the disclosure set forth herein or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims.

[0027] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0028] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0029] Example Wireless System

[0030] Figure 1 An example wireless communication network 100 in which aspects of the present disclosure may be practiced is illustrated. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to IEEE standards such as one or more of the 802.11 standards.

[0031] like Figure 1As shown in , the wireless communication network 100 may include several base stations (BSs) 110a to 110z (each also individually referred to as BS 110 or collectively referred to as BS 110 herein) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB) or some other terminology.

[0032] BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or may move depending on the location of mobile BS 110. In some examples, BS 110 may be interconnected with each other and / or connected to one or more other BSs or network nodes (not shown) in wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network. Figure 1 In the example shown, BSs 110a, 110b, and 110c may be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x may be a pico BS for pico cell 102x. BSs 110y and 110z may be femto BSs for femto cells 102y and 102z, respectively. A BS may support one or more cells.

[0033] The BS 110 communicates with one or more user equipment (UE) 120a to 120y (each also individually or collectively referred to herein as UE 120) in the wireless communication network 100. A UE may be fixed or mobile, and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smart phone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet computer, a personal computer, etc.

[0034] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a "transmitting entity" is an independently operated device or apparatus capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates a downlink, and the subscript "up" indicates an uplink. N may be selected. up UEs are used for simultaneous transmission on the uplink, N dn UEs are used for simultaneous transmission on the downlink. up May or may not be equal to Ndn , and N up and N dn It may be a static value or may change for each scheduling interval.Beam steering or some other spatial processing technique may be used at the BS 110 and the UE 120.

[0035] UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include a relay station (e.g., relay station 110r) (also referred to as a repeater, etc.) that receives transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and transmits transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relays transmissions between UEs 120 to facilitate communication between devices.

[0036] BS 110 may communicate on the downlink and uplink with one or more UEs 120 at any given moment. The downlink (i.e., forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., reverse link) is the communication link from UE 120 to BS 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0037] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The BS 110 may be equipped with several (N ap A group of (N) antennas can be used to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u Each UE 120 may receive downlink transmissions and send uplink transmissions. Each UE 120 may send user-specific data to and / or receive user-specific data from BS 110. Typically, each UE 120 may be equipped with one or more antennas. u The UEs 120 may have the same or different numbers of antennas.

[0038] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., where additional costs can be supported).

[0039] The network controller 130 (sometimes also referred to as a "system controller") may communicate with a set of BSs 110 and provide coordination and control (e.g., via backhaul) for these BSs 110. In some cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 may communicate with a core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network open functions, network repository functions, network slice selection functions, etc.

[0040] In certain aspects of the present disclosure, BS 110 and / or UE 120 may include a multi-stage analog-to-digital converter (ADC) with improved noise shaping, as described herein.

[0041] Figure 2 1 and 120a (eg, from a BS 110a) in which various aspects of the present disclosure may be practiced. Figure 1 Example components of a wireless communication network 100).

[0042] On the downlink, at BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be transmitted on different transport channels. For example, control information may be designated for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. Data may be designated for a physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for the exchange of control commands between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0043] The processor 220 may process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS).

[0044] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and may provide an output symbol stream to a modulator (MOD) in a transceiver 232a-232t. Each modulator 232a-232t in the transceiver may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM) or the like) to obtain an output sample stream. Each transceiver 232a-232t may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from the transceivers 232a-232t may be transmitted via antennas 234a-234t, respectively.

[0045] At UE 120a, antennas 252a-252r may receive downlink signals from BS110a and may provide received signals to transceivers 254a-254r, respectively. Transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 may obtain received symbols from all demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols (where applicable), and provide detected symbols. Receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to data sink 260, and provide decoded control information to controller / processor 280.

[0046] On the uplink, at the UE 120a, a transmit processor 264 may receive and process data from a data source 262 (e.g., for a physical uplink shared channel (PUSCH)) and control information from a controller / processor 280 (e.g., for a physical uplink control channel (PUCCH)). The transmit processor 264 may also generate reference symbols for reference signals (e.g., for a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be pre-decoded by a TX MIMO processor 266 (if applicable), further processed by a modulator (MOD) in the transceivers 254a to 254r (e.g., for single carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators in transceivers 232a-232t, detected by MIMO detector 236 (if applicable), and further processed by receive processor 238 to obtain decoded data and control information transmitted by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to controller / processor 240.

[0047] Memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. Memories 242 and 282 may also interface with controllers / processors 240 and 280, respectively. Scheduler 244 may schedule UEs for data transmission on the downlink and / or uplink.

[0048] The antennas 252, processors 258, 264, 266 and / or controller / processor 280 of the UE 120a and / or the antennas 234, processors 220, 230, 238 and / or controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0049] In certain aspects of the present disclosure, transceiver 232 and / or transceiver 254 may include a multi-stage ADC with improved noise shaping, as described in more detail herein.

[0050] NR can use orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. NR can use time division duplex (TDD) to support half-duplex operation. OFDM and single carrier frequency division multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are also commonly referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into subbands. For example, one subband can cover multiple resource blocks (RBs).

[0051] Example RF Transceiver

[0052] Figure 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via antenna 306. When TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via interface 308, which can include any of a variety of suitable RF devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0053] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0054] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process produces sum and difference frequencies between the LO frequency and the frequency of the baseband signal of interest. The sum and difference frequencies are referred to as "beat frequencies." The beat frequencies are typically in the RF range, so that the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or by the PA 318 before being transmitted by the antenna 306. Although one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and thereafter upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0055] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC that includes the TX path components, or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to a digital I and / or Q signal by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0056] For certain aspects, ADC 330 can be implemented by any of a variety of suitable high speed ADC topologies, such as a pipeline ADC or other multi-stage ADC. For certain aspects, ADC 330 can be implemented with improved noise shaping to push a portion of quantization error and circuit noise out of the signal frequency band, as described in more detail below.

[0057] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by the amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by the amplifier 334 before being mixed with the RF signal in the mixer 326. For certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0058] Controller 336 (eg, Figure 2 Controller / processor 280 in the RF transceiver circuit 300A may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. Controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 The memory 282 in the controller 336 may store data and / or program codes for operating the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (eg, complementary metal oxide semiconductor (CMOS) logic).

[0059] Although Figures 1 to 3 Wireless communications are provided as an example application in which certain aspects of the disclosure may be implemented to facilitate understanding, but certain aspects described herein may be used for digital-to-analog conversion (e.g., video or image processing) in any of a variety of other suitable systems.

[0060] Example Noise Shaping in a Multistage Analog-to-Digital Converter

[0061] Pipeline analog-to-digital converters (ADCs) and other multi-stage ADCs can be used in devices such as fifth generation (5G) transceivers in the receive chain of the transceiver front end, such as Figure 3 The pipeline ADC can be used, for example, at sampling rates from a few megasamples per second (Msps) to around 1000Msps and higher.

[0062] Figure 44 is a block diagram of an example multi-stage ADC 400. As shown, each stage of the pipeline ADC 400 includes at least an ADC 402, a digital-to-analog converter (DAC) 404, and an analog combiner 406. ADC 402 may be a relatively low-resolution ADC and may be implemented by a flash ADC or any other suitable type of ADC.

[0063] ADC 402 has one or more input nodes for receiving one or more analog inputs. The one or more analog inputs may include the residual output of the previous stage of ADC 400 after quantization. Although illustrated as having a single input node, in some cases, ADC 402 may alternatively be implemented with a pair of differential input nodes. ADC 402 generates a digital output (e.g., the output of the corresponding stage) based on the analog input. DAC 404 receives the digital output signal of ADC 402 as an input signal with an input terminal coupled to the output terminal of ADC 402. DAC 404 regenerates the digital input received from ADC 402 into an analog voltage. Although illustrated with a single output node, DAC 404 may alternatively be implemented with a pair of differential output nodes. Analog combiner 406 may then output the voltage difference between the analog input to the stage and the analog output from DAC 404. This voltage difference is called the residual voltage of a given stage and can be used as the input of the next stage of ADC 400. Therefore, each stage may have two outputs: a digital output and a residual output.

[0064] Each stage of the pipeline ADC 400 can be configured to output one or more bits. As shown, the bit output by the first stage (e.g., stage 1) of the ADC 400 can represent the most significant bit (MSB) of the digital output, and the bit output by the last stage (e.g., stage k) of the ADC 400 can represent the least significant bit (LSB) of the digital output. The multi-stage ADC 400 can also include a digital combiner 408 for combining the output bits from each stage to generate a complete digital output. As illustrated, the digital output can be the sum of the bits output by each of the stages of the ADC 400 (e.g., after considering the relative significance of the bits).

[0065] In theory, an ADC (such as ADC 400) can operate at a maximum sampling rate known as the Nyquist rate, which is equal to half the sampling rate of the ADC. The oversampling ratio (OSR) of an ADC can be defined as the sampling frequency (f s ) and the maximum input bandwidth of the ADC (f in ) (e.g., OSR = 0.5f s / f in). Many applications (e.g., wireless communications) operate with an OSR greater than 1. In this case, incorporating noise shaping into the ADC can further increase the dynamic range of the ADC.

[0066] Noise shaping typically involves pushing some portion of the quantization error and circuit noise to higher frequencies outside the signal band. For example, if the input bandwidth is limited to [0fs / 8] (i.e., OSR=4), then it may be necessary to reduce the noise in this band and move the noise to frequencies much higher than the input bandwidth in the output spectrum (e.g., >>fs / 8).

[0067] Thus, aspects of the present disclosure provide noise shaping techniques for a multi-stage ADC, such as ADC 400. The techniques disclosed herein can improve noise shaping in the last stage of an ADC and can be applied to ADCs with an OSR greater than 2. ADC topologies that generate higher-order noise transfer functions (NTFs) can allow for more complex noise shaping. However, some multi-stage ADC topologies only generate first-order NTFs. Thus, aspects of the present disclosure provide multi-stage ADC topologies with second-order (or higher-order) NTFs, as explained in more detail below.

[0068] Figure 5 is a schematic diagram of a portion of an example multi-stage ADC 500 (e.g., a pipelined ADC) according to aspects of the present disclosure. For ease of description and to avoid clutter in the drawings, switches may sometimes be referred to herein in terms of control signals associated with the switches, and the names of the control signals may indicate the control signal phase. Similarly, capacitive elements may sometimes be referred to herein in terms of their capacitance.

[0069] ADC 500 may have a first conversion stage 501 (also referred to as a "first stage") that includes a first ADC that may be implemented. Figure 4 4. The first capacitor digital-to-analog converter (CDAC) 502 of the DAC 404 in the embodiment of the present invention is shown. The first CDAC 502 may have an output terminal selectively coupled to a first input terminal of an inter-stage amplifier 504 (e.g., an operational transconductance amplifier (OTA)) via a first switch S1 and coupled to a first port 512 of a switched capacitor network 510. Although not illustrated, the first stage 501 may also include a quantizer (e.g., ADC 402), and the ADC 500 may have other previous stages before the first stage (e.g., the first stage may not be an initial stage of the ADC 500).

[0070] The first stage 501 of the ADC 500 may quantize an input voltage and generate a residual voltage by calculating the error between the input voltage and the voltage represented by the quantized value. The residual voltage generated by a given stage (e.g., stage n) may be equal to the input voltage minus the product of the digital output of the stage and the least significant bit (LSB) of the stage (e.g., Vres，n =V in，n -D n *LSB n The residual voltage of the first stage 501 may be stored in a capacitor of the first CDAC 502 as the residual output of the first stage (eg, by capacitor C dac1 express).

[0071] The second conversion stage 503 (also referred to as the "second stage") of the ADC 500 may include a quantizer 506 and a second CDAC 508. The input of the second stage 503 may be coupled to the second port 514 of the switched capacitor network 510 and selectively coupled to the output of the amplifier 504 via the second switch S2. The second stage 503 may quantize the residual voltage output by the first CDAC 502 and amplified by the amplifier 504. The second stage 503 may be the last stage of the ADC 500. The second stage 503 of the ADC 500 may compare the residual voltage with a reference voltage and generate additional output bits, as explained in more detail below. The additional output bits may then be combined with the digital output of the previous stage to generate the final output of the ADC 500 (as described above with respect to Figure 4 explained).

[0072] The quantizer 506 may quantize the amplified version of the residual voltage and output a digital signal representing the residual voltage. In some aspects, the quantizer 506 may be a successive approximation register (SAR) quantizer, in which case the second CDAC 508 is controlled by a digital code from the SAR logic in the quantizer 506. The second CDAC 508 may convert the digital output signal of the quantizer 506 into an analog voltage, subtract the generated voltage from the residual voltage of the previous stage, and output a voltage difference (e.g., the residual voltage of the last stage of the ADC 500). The second CDAC 508 may have a capacitor C dac2 Represents the total internal capacitance.

[0073] As illustrated, the switched capacitor network 510 generally includes a first capacitive element C fix1 and the second capacitive element C fix2 , which can be repeated and used for reference scaling. The first capacitive element C fix1 The first capacitive element C may have a first terminal coupled to the second port 514 of the switched capacitor network 510 and a second terminal selectively coupled to the first port 512 of the switched capacitor network 510 via a third switch S3. fix1 The second terminal of the The second capacitive element C is selectively coupled to a reference potential node (eg, electrical ground) of the ADC 500. fix2 May have a fifth switch selectively coupled to the first port 512 and via the sixth switch The first terminal is selectively coupled to the reference potential node of the ADC. The second capacitive element C fix2 It is also possible to have a seventh switch The second capacitive element C is selectively coupled to the second terminal of the second port 514. fix2 The second terminal of the A third port 516 (eg, a residual sense port) is selectively coupled to the switched capacitor network 510 .

[0074] During the conversion period, the fourth switch is configured to be closed, and the first switch S1, the second switch S2 and the third switch S3 are configured to be open, so that the first capacitive element C fix1 With capacitor C dac2 During the transition, the fifth switch and the eighth switch can be configured to be disconnected, and the sixth switch and the seventh switch can be configured to be closed so that the second capacitive element C fix2 With the first capacitance element C fix1 and capacitor C dac2 Amplifier 504 does not operate during the conversion period and can therefore be turned off to save power.

[0075] During the amplification period, the first switch S1, the second switch S2 and the third switch S3 may be configured to be closed, and the fourth switch can be configured to be disconnected so that the first capacitive element C fix1 is feedback coupled to the amplifier 504. During the amplification period, the fifth switch and the seventh switch can be configured to be closed, and the sixth switch and the eighth switch can be configured to be disconnected so that the second capacitive element C fix2 The first capacitive element C coupled to the amplifier 504 is feedback coupled to the amplifier 504. fix1 Parallel coupling.

[0076] The amplifier 504 may be configured to amplify the residual voltage from the first stage of the ADC 500 (eg, the residual voltage output by the first CDAC 502). The gain of the amplifier 504 may be equal to the capacitance C dac1 divided by the total capacitance of the switched capacitor network 510 (eg, C fix1 +C fix2 ).

[0077] According to aspects of the present disclosure, the switched capacitor network 510 can be configured to provide a second-order or higher-order NTF for noise shaping of the quantization noise of the second conversion stage 503. To introduce a second-order term to the NTF, the ADC 500 is configured to store the residual voltage from two sampling periods before the current period in addition to the residual voltage from one sampling period before the current period. Thus, in some aspects, the second capacitive element C fix2 Two capacitors C of the same size can be used fix2A and C fix2B Implementation, such as FIG. 6A to FIG. 6D In this case, the capacitor C fix2A The capacitor C may be referred to as the second capacitive element of the switched capacitor network 510 and fix2B It can be called the third capacitive element of the switched capacitor network. Capacitor C fix2A The residual voltage samples from two sampling cycles before the current cycle can be stored, and the capacitor C fix2B The residual voltage samples from a sampling cycle before the current cycle, or vice versa, can be stored. fix2 The two capacitors of generate a second order term in the NTF of ADC 500, which allows for higher degrees of freedom and more programmability / control of noise shaping. The second capacitor element C fix2 One or more additional capacitors (and associated switches) may be added in the switched capacitor network 510 to store residual voltage samples later than two previous sampling periods and thereby achieve a higher order NTF.

[0078] At a given time (e.g., during amplification or conversion), the capacitor C fix2A and C fix2B Only one of them can be connected to the first capacitive element C fix1 In some aspects, the capacitor C fix2A or C fix2B The other of (for example, a switch that can be closed or switch ). Capacitor C fix2A or C fix2B The readout of the residual on ADC may enable more processing (eg, additional noise shaping using a feed-forward topology and / or sending the residual to another sub-ADC in a time-interleaved (TI) ADC).

[0079] Fig. 6A FIG. 5 shows an example switch configuration of the switched capacitor network 510 during the first conversion cycle of the ADC 500. As shown, the capacitor C fix2A May have a fifth switch selectively coupled to the first port 512 and via the sixth switch A first terminal selectively coupled to a reference potential node of the ADC. Capacitor C fix2A It is also possible to have a seventh switch is selectively coupled to a second terminal of the second port 514. In some aspects, the capacitor C fix2A The second terminal of An optional third port 516 is selectively coupled to the switched capacitor network 510 for residual readout.

[0080] Capacitor C fix2B Can have through the ninth switch is selectively coupled to the first port 512 and via a tenth switch A first terminal selectively coupled to a reference potential node of ADC 500. Capacitor C fix2B It is also possible to have an eleventh switch is selectively coupled to a second terminal of the second port 514. In some aspects, the capacitor C fix2B The second terminal of the A third port 516 is selectively coupled to the switched capacitor network 510 .

[0081] As shown, during the first switching cycle, the switch closed, thereby the capacitor C fix1 is coupled between the second port 514 and the reference potential node. and closed, thereby the capacitor C fix2A With capacitor C fix1 When coupled in parallel, the capacitor C fix1 and C fix2A Can be collectively referred to as capacitor C fix , which also represents the effective capacitance of the switched capacitor network 510 at any time. Capacitor C fix The capacitance of C scales the effective reference voltage of the second stage of ADC 500. According to certain aspects, the capacitance C fix During some periods it may be equal to C fix1 +C fix2A (e.g., even switching cycles).

[0082] At the end of the first switching cycle, capacitor C dac2 Holding voltage V dac2 , which is equal to the residual voltage corresponding to the quantization error generated during the first conversion cycle (e.g., V res As illustrated by the dashed box 602a, the capacitor C fix1 and C fix2A also with Fig. 6AThe capacitor C in the equivalent circuit at the bottom dac2 Therefore, capacitor C fix1 and C fix2A Keep with capacitor C dac2 During the first switching cycle, capacitor C fix2B Optionally, by closing the switch and It is read out by other circuits, as shown in the figure.

[0083] In some aspects, the control signal Through the and Perform the operation to obtain the capacitor C fix2A and C fix2B The charging of the control signals and their respective clock signals can be interleaved. Can have twice the period of Can be Delayed A version of a cycle.

[0084] As illustrated, the second CDAC 508 may be selectively coupled at a second port 514 to an electrical ground or a reference voltage (eg, V ref ) between the electrical ground and the reference voltage. When the capacitor is switched between the electrical ground and the reference voltage, there is a difference between the capacitance of the switched capacitor and the total capacitance of the circuit (e.g., C dac2 +C fix ). For the smallest capacitor in the second CDAC 508 (e.g., the least significant bit (LSB) of the second CDAC 508), the voltage jump can define the full-scale reference of the second CDAC 508. The full scale of the quantizer 506 can be different from the full scale of the second CDAC 508. Reference scaling (e.g., reference reduction) can be used to reduce the voltage jump. By including an effective capacitance C fix , the total capacitance of ADC 500 becomes larger, thereby reducing the voltage jump and the full scale of the last stage.

[0085] In addition, aspects of the present disclosure can increase the speed of the ADC. In some ADC topologies, at any given time, the capacitor C fix (Except capacitor C dac2 Capacitor C fix Can have a specific capacitance C dac2Much larger capacitance, and large load capacitance can slow down the operation of the amplifier. Therefore, aspects of the present disclosure provide a smaller load to the interstage amplifier during amplification. For example, during amplification, C fix No capacitor is coupled between the output of amplifier 504 and a reference potential (eg, electrical ground). Thus, amplifier 504 has a reduced load and can operate faster (eg, the settling time of amplifier 504 can be reduced by up to 40% or potentially more) and with higher power efficiency.

[0086] Some ADC topologies include repeated C fix capacitor, which contributes to the lateral area consumed by the ADC (eg, footprint). Thus, aspects of the present disclosure provide a method for implementing a method having only one C fix1 The switched capacitor topology reduces the footprint of the ADC. In addition, compared with the open-loop amplification topology, the closed-loop amplification topology (e.g., Figure 5 ) to achieve increased interstage gain accuracy (Gain = C dac1 / ∑C fixn ). In addition to feeding the LSB back to C dac2 In addition, no dedicated residual processing is required and no extra time for noise shaping is needed.

[0087] Figure 6B FIG. 5 shows an example switch configuration of the switched capacitor network 510 during the second conversion cycle of the ADC 500. As shown, during the second conversion cycle, the switches closed, thereby the capacitor C fix1 is coupled between the second port 514 and the reference potential node. and closed, thereby the capacitor C fix2B With capacitor C fix1 When coupled in parallel, the capacitor C fix1 and C fix2B Can be collectively referred to as capacitor C fix According to certain aspects, during odd cycles, C fix Can be equal to C fix1 +C fix2B .

[0088] At the end of the second switching cycle, capacitor C dac2 Holding voltage V dac2 , which is equal to the residual voltage corresponding to the quantization error generated during the second conversion cycle (e.g., V res As illustrated by the dashed box 602b, the capacitor C fix1 and C fix2B also with Figure 6B The capacitor C in the equivalent circuit at the bottomdac2 Therefore, capacitor C fix1 and C fix2B Keep with capacitor C dac2 During the second switching cycle, capacitor C fix2A Optionally, by closing the switch and It is read out by other circuits, as shown in the figure.

[0089] Figure 6C FIG. 5 shows an example switch configuration of the switched capacitor network 510 during a first amplification cycle (sometimes referred to as an “integration cycle”) of the ADC 500. As illustrated, during the first amplification cycle, switches S1, S2, and S3 (each of which is controlled by a control signal Φ int The control) will be closed, thereby coupling the output of the first CDAC 502 to the first input of the amplifier 504 and the capacitor C in the feedback loop. fix1 is coupled to amplifier 504. In addition, during the first amplification cycle, switch and will also close, making the capacitor C fix2B With capacitor C fix1 Coupled in parallel (eg, in a feedback loop with amplifier 504).

[0090] During the amplification period, amplifier 504 is active and operates with a gain of C dac1 / C fix The capacitor C fix1 Carrying residual samples from previous conversion cycles (e.g., V res [n-1]), and capacitor C fix2B Carries residual samples from the previous two conversion cycles (e.g., V res [n-2]). During the first amplification cycle, the current stored in capacitor C fix1 and C fix2B The voltage on the V is fed back to the input of the amplifier 504. Thus, a new voltage (e.g., V dac2 [n]). The new voltage can be expressed by the following equation:

[0091] V dac2 [n]=-V dac1 +C fix1 V res [n-1] / C fix +C fix2 V res [n-2] / C fix

[0092] Among them C fix2 = ... fix2B and is equal to the capacitance of capacitor C during the second amplification cycle (e.g., during the even-numbered amplification cycle). fix2A The capacitance of Fig.6D Describe in more detail.

[0093] This equation can be expressed in the z domain by equaling 1-a1z -1 -a2z -2 The second-order noise transfer function (NTF) is expressed as n =C fixn / C fix And |a1|+|a2|+... = 1. The second-order NTF is a high-pass function that can filter out noise at low frequencies but allow noise to pass at higher frequencies, thereby achieving programmable noise shaping.

[0094] As mentioned above, by using the capacitor C fix2A and C fix2B The additional capacitor C coupled in a similar manner fix2 To generate a higher order noise transfer function (e.g., third order, fourth order, etc.). For example, to generate a third order NTF, switches can be used as about capacitor C fix2A and C fix2B A capacitor C is added in a similar manner as described fix2C (Size and capacitor C fix2A and C fix2B The same) is selectively coupled between different nodes. In this case, the residual voltage samples from the previous one, two and three conversion cycles can be stored and used to generate a new residual voltage during a given cycle.

[0095] During the first amplification cycle, capacitor C fix2A Optionally, by closing the switch and It is read out by other circuits, as shown in the figure.

[0096] Fig.6D 5 shows an example switch configuration of the switched capacitor network 510 during the second amplification cycle of the ADC 500. As was the case during the first amplification cycle, during the second amplification cycle, switches S1, S2, and S3 will be closed, thereby coupling the first CDAC 502 to the first input terminal of the amplifier 504 and connecting the capacitor C in the feedback loop. fix1 is coupled to amplifier 504. In addition, during the second amplification cycle, switch and will also close, making the capacitor C fix2A With capacitor C fix1 is coupled in parallel (e.g., in a feedback loop with amplifier 504). Thus, the current stored in capacitor C fix1 and C fix2A The voltage on is fed back to the input of amplifier 504 .

[0097] During the second amplification cycle, amplifier 504 is active and operates in a closed loop configuration. Capacitor C fix1 Carrying residual samples from previous conversion cycles (e.g., V res [n-1]), and capacitor C fix2A Carries residual samples from the previous two conversion cycles (e.g., V res [n-2]). During the second amplification cycle, the current stored in capacitor C fix1 and C fix2A The voltage on the V is fed back to the input of the amplifier 504. Thus, a new voltage (e.g., V dac2 [n]), as described above.

[0098] During the second amplification cycle, capacitor C fix2B Optionally, by closing the switch and It is read out by other circuits, as shown in the figure.

[0099] Example Transformation Operation

[0100] Figure 7 7 is a flow chart of example operations 700 for performing analog-to-digital conversion using an analog-to-digital converter (ADC) (e.g., ADC 500) according to certain aspects of the present disclosure. The ADC generally includes a first conversion stage (e.g., first stage 501), a second conversion stage (e.g., second stage 503), an amplifier (e.g., amplifier 504) selectively coupled between the first conversion stage and the second conversion stage, and a switched capacitor network (e.g., switched capacitor network 510) coupled between an input of the amplifier and an input of the second conversion stage.

[0101] Operations 700 may generally involve, at block 702, during a conversion phase of an ADC (e.g., via a switch ) the first capacitive element of the switched capacitor network (eg, the first capacitive element C fix1 ) is associated with a capacitive element (eg, capacitor C DAC2Operation 700 may also involve coupling a first capacitive element between an input of the amplifier and an output of the amplifier (eg, via switches S2 and S3) during an amplification phase of the ADC at block 704.

[0102] In certain aspects, the operation 700 may further involve decoupling the input of the amplifier from the residual output of the first conversion stage (e.g., the output of the first CDAC 502) during the conversion phase. In this case, coupling the first capacitive element in parallel with the capacitive element associated with the second conversion stage may include coupling a terminal of the first capacitive element to a reference potential node (e.g., electrical ground) of the ADC. For certain aspects, the operation 700 may also include decoupling the output of the amplifier from the switched capacitor network and from the input of the second conversion stage during the conversion phase.

[0103] According to certain aspects, operation 700 may further involve coupling the input of the amplifier to the residual output of the first conversion stage during the amplification phase. In this case, coupling the first capacitive element between the input of the amplifier and the output of the amplifier may include coupling the output of the amplifier to a switched capacitor network and an input of the second conversion stage. For certain aspects, operation 700 may also involve decoupling a terminal of the first capacitive element from a reference potential node of the ADC during the amplification phase.

[0104] According to certain aspects, operation 700 may further involve switching a second capacitive element (eg, capacitor C ) of the switched capacitor network during every nth cycle (eg, every odd-numbered cycle, where n=2) of the conversion phase. fix2A ) is coupled in parallel with the first capacitive element and the capacitive element associated with the second conversion stage, wherein n is a positive integer; and during every n cycles of the amplification stage, the second capacitive element is coupled between the input of the amplifier and the output of the amplifier so that the second capacitive element is connected in parallel with the first capacitive element.

[0105] In certain aspects, operation 700 may further involve switching a third capacitive element (eg, capacitor C ) of the switched capacitor network during a cycle after every nth cycle of the conversion phase (eg, every even-numbered cycle, where n=2). fix2B ) is coupled in parallel with the first capacitive element and the capacitive element associated with the second conversion stage, wherein the second capacitive element is decoupled from the input of the second conversion stage during the cycle; and during the cycle after every nth cycle of the amplification stage, a third capacitive element is coupled between the input of the amplifier and the output of the amplifier, so that the third capacitive element is connected in parallel with the first capacitive element, wherein the second capacitive element is decoupled from the input and output of the amplifier during the cycle.

[0106] According to certain aspects, operation 700 further involves at least one of: sensing a residual voltage from the second capacitive element during a period after every nth period of the conversion phase; or sensing a residual voltage from the third capacitive element during every nth period of the conversion phase.

[0107] Example aspects

[0108] In addition to the above-mentioned aspects, specific combinations of the aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0109] Aspect 1: An analog-to-digital converter (ADC), comprising: a first conversion stage, the first conversion stage having a residual output; an amplifier, the amplifier having an input selectively coupled to the residual output of the first conversion stage; a second conversion stage, the second conversion stage having an input selectively coupled to the output of the amplifier; and a switched capacitor network, the switched capacitor network having a first port coupled to the input of the amplifier and a second port coupled to the input of the second conversion stage, the switched capacitor network being configured to provide a second-order or higher-order noise transfer function for noise shaping of quantization noise of the second conversion stage.

[0110] Aspect 2: The ADC according to aspect 1, wherein the switched capacitor network comprises a first capacitive element having a first terminal coupled to the second port and having a second terminal selectively coupled to a reference potential node of the ADC and selectively coupled to the first port.

[0111] Aspect 3: An ADC according to Aspect 2, wherein the ADC is configured to: during a conversion phase, couple the first capacitive element in parallel with the capacitive element associated with the second conversion stage; and during an amplification phase, couple the first capacitive element between the input end of the amplifier and the output end of the amplifier.

[0112] Aspect 4: According to the ADC of Aspect 2 or Aspect 3, the ADC also includes: a first switch, the first switch is coupled between the residual output of the first conversion stage and the input end of the amplifier; a second switch, the second switch is coupled between the output end of the amplifier and the second port of the switched capacitor network; a third switch, the third switch is coupled between the first port of the switched capacitor network and the second terminal of the first capacitive element; and a fourth switch, the fourth switch is coupled between the second terminal of the first capacitive element and the reference potential node.

[0113] Aspect 5: An ADC according to Aspect 4, wherein: during the amplification phase, the first switch, the second switch and the third switch are configured to be closed and the fourth switch is configured to be open; and during the conversion phase, the fourth switch is configured to be closed and the first switch, the second switch and the third switch are configured to be open.

[0114] Aspect 6: An ADC according to any one of Aspects 2 to 5, wherein the switched capacitor network further comprises a second capacitive element having a first terminal selectively coupled to the first port and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port.

[0115] Aspect 7: The ADC of aspect 6, wherein the second terminal of the second capacitive element is selectively coupled to a third port of the switched capacitor network.

[0116] Aspect 8: According to the ADC of Aspect 6 or 7, the ADC also includes: a first switch, the first switch is coupled between the first port of the switched capacitor network and the first terminal of the second capacitive element; a second switch, the second switch is coupled between the first terminal of the second capacitive element and the reference potential node of the ADC; and a third switch, the third switch is coupled between the second terminal of the second capacitive element and the second port of the switched capacitor network.

[0117] Aspect 9: An ADC according to any one of Aspects 6 to 8, wherein the switched capacitor network further comprises a third capacitive element having a first terminal selectively coupled to the first port and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port.

[0118] Aspect 10: The ADC of aspect 9, wherein the second terminal of the third capacitive element is selectively coupled to a third port of the switched capacitor network.

[0119] Aspect 11: According to the ADC of Aspect 9 or 10, the ADC also includes: a first switch, the first switch is coupled between the first port of the switched capacitor network and the first terminal of the second capacitor element; a second switch, the second switch is coupled between the first terminal of the second capacitor element and the reference potential node of the ADC; a third switch, the third switch is coupled between the second terminal of the second capacitor element and the second port of the switched capacitor network; a fourth switch, the fourth switch is coupled between the first port of the switched capacitor network and the first terminal of the third capacitor element; a fifth switch, the fifth switch is coupled between the first terminal of the third capacitor element and the reference potential node of the ADC; and a sixth switch, the sixth switch is coupled between the second terminal of the third capacitor element and the second port of the switched capacitor network.

[0120] Aspect 12: An ADC according to Aspect 11, wherein: during a first conversion phase, the second switch, the third switch and the fifth switch are configured to be closed, and the first switch, the fourth switch and the sixth switch are configured to be open; and during a second conversion phase, the second switch, the fifth switch and the sixth switch are configured to be closed, and the first switch, the third switch and the fourth switch are configured to be open.

[0121] Aspect 13: The ADC according to any one of the preceding aspects, wherein the second conversion stage is the last stage of the ADC.

[0122] Aspect 14: The ADC according to any of the preceding aspects, wherein the ADC comprises a pipeline ADC.

[0123] Aspect 15: An analog-to-digital converter (ADC), comprising: a first conversion stage, the first conversion stage having a residual output; an amplifier, the amplifier having an input terminal selectively coupled to the residual output of the first conversion stage; a second conversion stage, the second conversion stage having an input terminal selectively coupled to the output terminal of the amplifier; and a switched capacitor network, the switched capacitor network having a first port coupled to the input terminal of the amplifier and a second port coupled to the input terminal of the second conversion stage, the switched capacitor network having a first capacitive element, the first capacitive element having a first terminal coupled to the second port and having a second terminal selectively coupled to a reference potential node of the ADC and selectively coupled to the first port.

[0124] Aspect 16: An ADC according to Aspect 15, wherein the ADC is configured to: during a conversion phase, couple the first capacitive element in parallel with the capacitive element associated with the second conversion stage; and during an amplification phase, couple the first capacitive element between the input end of the amplifier and the output end of the amplifier.

[0125] Aspect 17: According to the ADC of Aspect 15 or Aspect 16, the ADC also includes: a first switch, the first switch is coupled between the residual output of the first conversion stage and the input terminal of the amplifier; a second switch, the second switch is coupled between the output terminal of the amplifier and the second port of the switched capacitor network; a third switch, the third switch is coupled between the first port of the switched capacitor network and the second terminal of the first capacitive element; and a fourth switch, the fourth switch is coupled between the second terminal of the first capacitive element and the reference potential node.

[0126] Aspect 18: An ADC according to Aspect 17, wherein: during the amplification phase, the first switch, the second switch and the third switch are configured to be closed and the fourth switch is configured to be open; and during the conversion phase, the fourth switch is configured to be closed and the first switch, the second switch and the third switch are configured to be open.

[0127] Aspect 19: An ADC according to any one of Aspects 15 to 18, wherein the switched capacitor network further comprises a second capacitive element having a first terminal selectively coupled to the first port of the switched capacitor network and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port of the switched capacitor network.

[0128] Aspect 20: An ADC according to Aspect 19, wherein the switched capacitor network further comprises a third capacitive element having a first terminal selectively coupled to the first port of the switched capacitor network and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port of the switched capacitor network.

[0129] Aspect 21: The ADC according to any one of aspects 15 to 20, wherein the second conversion stage is the last stage of the ADC.

[0130] Aspect 22: The method according to any one of aspects 15 to 21, wherein the ADC comprises a pipeline ADC.

[0131] Aspect 23: A method for analog-to-digital conversion using an analog-to-digital converter (ADC), the analog-to-digital converter comprising a first conversion stage, a second conversion stage, an amplifier selectively coupled between the first conversion stage and the second conversion stage, and a switched capacitor network coupled between an input end of the amplifier and an input end of the second conversion stage, the method comprising: during a conversion phase of the ADC, coupling a first capacitive element of the switched capacitor network in parallel with a capacitive element associated with the second conversion stage; and during an amplification phase of the ADC, coupling the first capacitive element between the input end of the amplifier and the output end of the amplifier.

[0132] Aspect 24: According to the method described in Aspect 23, during the conversion phase, the method also includes: decoupling the input of the amplifier from the residual output of the first conversion stage, wherein coupling the first capacitive element in parallel with the capacitive element associated with the second conversion stage includes coupling the terminal of the first capacitive element to the reference potential node of the ADC; and decoupling the output of the amplifier from the switched capacitor network and from the input of the second conversion stage.

[0133] Aspect 25: According to the method of Aspect 24, the method also includes, during the amplification stage: coupling the input of the amplifier to the residual output of the first conversion stage, wherein coupling the first capacitive element between the input of the amplifier and the output of the amplifier includes coupling the output of the amplifier to the switched capacitor network and the input of the second conversion stage; and decoupling the terminals of the first capacitive element from the reference potential node of the ADC.

[0134] Aspect 26: According to the method described in any one of Aspects 23 to 25, the method further includes: during each nth cycle of the conversion phase, coupling the second capacitance element of the switching capacitor network in parallel with the first capacitance element and the capacitance element associated with the second conversion stage, wherein n is a positive integer; and during each nth cycle of the amplification phase, coupling the second capacitance element between the input terminal of the amplifier and the output terminal of the amplifier so that the second capacitance element is connected in parallel with the first capacitance element.

[0135] Aspect 27: According to the method described in Aspect 26, the method also includes: during the cycle after every nth cycle of the conversion stage, coupling the third capacitor element of the switching capacitor network in parallel with the first capacitor element and the capacitor element associated with the second conversion stage, wherein the second capacitor element is decoupled from the input end of the second conversion stage during the cycle; and during the cycle after every nth cycle of the amplification stage, coupling the third capacitor element between the input end of the amplifier and the output end of the amplifier so that the third capacitor element is connected in parallel with the first capacitor element, wherein the second capacitor element is decoupled from the input end and the output end of the amplifier during the cycle.

[0136] Aspect 28: According to the method described in Aspect 27, the method also includes at least one of the following steps: after every nth cycle of the conversion phase, reading the residual voltage from the second capacitor element during the cycle; or reading the residual voltage from the third capacitor element during every nth cycle of the conversion phase.

[0137] Aspect 29: An analog-to-digital converter (ADC), comprising: a first component for converting an analog input signal into a first digital output signal; a component for amplifying a residue from the first component for conversion; a second component for converting the amplified residue into a second digital output signal; and a component for providing a second-order or higher-order noise transfer function for noise shaping of quantization noise of the second component for conversion.

[0138] in conclusion

[0139] An analog-to-digital converter (ADC) circuit design for noise shaping in a multi-stage ADC is described herein. Certain aspects of the present disclosure provide a switched capacitor network coupled between a first conversion stage and a second conversion stage of the ADC. During a conversion phase of the ADC, a capacitive element in the switched capacitor network is selectively coupled in parallel with a capacitive element associated with the second conversion stage. During an amplification phase of the ADC, the capacitive element in the switched capacitor network is coupled in a feedback path of an interstage amplifier for the ADC. The switched capacitor network can be configured to provide a second-order or higher-order noise transfer function for noise shaping of quantization noise of the second conversion stage.

[0140] The above description provides examples, but does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Each example may ignore, replace or add each process or component as appropriate. For example, the method described may be performed in a different order than described, and various steps may be added, omitted or combined. In addition, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functional functions or structures and functionality other than or different from the various aspects of the present disclosure given herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims. The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described as "exemplary" herein is not necessarily interpreted as being preferred or having advantages over other aspects.

[0141] The various operations of the above methods may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where there are operations illustrated in the accompanying drawings, these operations may have corresponding corresponding means plus functional components. For example, a first means for converting an analog input signal into a first digital output signal may include a first conversion stage, such as Figure 5 or FIG. 6A to FIG. 6D The first conversion stage (including the first CDAC 502) of FIG. 5A may include an amplifier (eg, an interstage amplifier) ​​such as Figure 5 or FIG. 6A to FIG. 6D The second means for converting the amplified residue into a second digital output signal may include a second conversion stage, such as Figure 5 or FIG. 6A to FIG. 6D The second conversion stage (including quantizer 506 and second CDAC 508) of FIG. 5 may include a switched capacitor network such as a quantizer 506 and a second CDAC 508. The means for providing a second or higher order noise transfer function for noise shaping of the quantization noise of the second means for conversion may include a switched capacitor network such as Figure 5 or FIG. 6A to FIG. 6D A switched capacitor network 510 is provided.

[0142] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0143] The methods disclosed herein include one or more steps or actions for implementing the described methods. The method steps and / or actions may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0144] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An analog-to-digital converter (ADC), the analog-to-digital converter (ADC) comprising: a first conversion stage having a residual output; an amplifier having an input selectively coupled to the residual output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched capacitor network being configured to provide a second or higher order noise transfer function for noise shaping of quantization noise of the second conversion stage.

2. The ADC of claim 1 , wherein the switched capacitor network comprises a first capacitive element having a first terminal coupled to the second port and having a second terminal selectively coupled to a reference potential node of the ADC and selectively coupled to the first port.

3. The ADC according to claim 2, wherein the ADC is configured as: During a conversion phase, coupling the first capacitive element in parallel with a capacitive element associated with the second conversion stage; and The first capacitive element is coupled between the input of the amplifier and the output of the amplifier during an amplification phase.

4. The ADC according to claim 2, further comprising: a first switch coupled between the residual output of the first conversion stage and the input of the amplifier; a second switch coupled between the output of the amplifier and the second port of the switched capacitor network; a third switch coupled between the first port of the switched capacitor network and the second terminal of the first capacitive element; and A fourth switch is coupled between the second terminal of the first capacitive element and the reference potential node.

5. The ADC of claim 4, wherein: During an amplification phase, the first switch, the second switch, and the third switch are configured to be closed and the fourth switch is configured to be open; and During a conversion phase, the fourth switch is configured to be closed, and the first switch, the second switch, and the third switch are configured to be open.

6. The ADC of claim 2, wherein the switched capacitor network further comprises a second capacitive element having a first terminal selectively coupled to the first port and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port.

7. The ADC of claim 6, wherein the second terminal of the second capacitive element is selectively coupled to a third port of the switched capacitor network.

8. The ADC according to claim 6, further comprising: a first switch coupled between the first port of the switched capacitor network and the first terminal of the second capacitive element; a second switch coupled between the first terminal of the second capacitive element and the reference potential node of the ADC; and A third switch is coupled between the second terminal of the second capacitive element and the second port of the switched capacitor network.

9. The ADC of claim 6, wherein the switched capacitor network further comprises a third capacitive element having a first terminal selectively coupled to the first port and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port.

10. The ADC of claim 9, wherein the second terminal of the third capacitive element is selectively coupled to a third port of the switched capacitor network.

11. The ADC according to claim 9, further comprising: a first switch coupled between the first port of the switched capacitor network and the first terminal of the second capacitive element; a second switch coupled between the first terminal of the second capacitive element and the reference potential node of the ADC; a third switch coupled between the second terminal of the second capacitive element and the second port of the switched capacitor network; a fourth switch coupled between the first port of the switched capacitor network and the first terminal of the third capacitive element; a fifth switch coupled between the first terminal of the third capacitive element and the reference potential node of the ADC; and A sixth switch is coupled between the second terminal of the third capacitive element and the second port of the switched capacitor network.

12. The ADC of claim 11, wherein: During a first conversion phase, the second switch, the third switch, and the fifth switch are configured to be closed, and the first switch, the fourth switch, and the sixth switch are configured to be open; and During a second conversion phase, the second switch, the fifth switch, and the sixth switch are configured to be closed, and the first switch, the third switch, and the fourth switch are configured to be open.

13. The ADC of claim 1, wherein the second conversion stage is a last stage of the ADC.

14. The ADC of claim 1, wherein the ADC comprises a pipeline ADC.

15. An analog-to-digital converter (ADC), the analog-to-digital converter (ADC) comprising: a first conversion stage having a residual output; an amplifier having an input selectively coupled to the residual output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched capacitor network having a first capacitive element having a first terminal coupled to the second port and having a second terminal selectively coupled to a reference potential node of the ADC and selectively coupled to the first port.

16. The ADC of claim 15, wherein the ADC is configured to: During a conversion phase, coupling the first capacitive element in parallel with a capacitive element associated with the second conversion stage; and The first capacitive element is coupled between the input of the amplifier and the output of the amplifier during an amplification phase.

17. The ADC of claim 15, further comprising: a first switch coupled between the residual output of the first conversion stage and the input of the amplifier; a second switch coupled between the output of the amplifier and the second port of the switched capacitor network; a third switch coupled between the first port of the switched capacitor network and the second terminal of the first capacitive element; and A fourth switch is coupled between the second terminal of the first capacitive element and the reference potential node.

18. The ADC of claim 17, wherein: During an amplification phase, the first switch, the second switch, and the third switch are configured to be closed and the fourth switch is configured to be open; and During a conversion phase, the fourth switch is configured to be closed, and the first switch, the second switch, and the third switch are configured to be open.

19. The ADC of claim 15, wherein the switched capacitor network further comprises a second capacitive element having a first terminal selectively coupled to the first port of the switched capacitor network and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port of the switched capacitor network.

20. The ADC of claim 19, wherein the switched capacitor network further comprises a third capacitive element having a first terminal selectively coupled to the first port of the switched capacitor network and selectively coupled to the reference potential node of the ADC and having a second terminal selectively coupled to the second port of the switched capacitor network.

21. The ADC of claim 15, wherein the second conversion stage is a last stage of the ADC.

22. The ADC of claim 15, wherein the ADC comprises a pipeline ADC.

23. A method of analog-to-digital conversion using an analog-to-digital converter (ADC), the analog-to-digital converter (ADC) comprising a first conversion stage, a second conversion stage, an amplifier selectively coupled between the first conversion stage and the second conversion stage, and a switched capacitor network coupled between an input terminal of the amplifier and an input terminal of the second conversion stage, the method comprising: coupling a first capacitive element of the switched capacitor network in parallel with a capacitive element associated with the second conversion stage during a conversion phase of the ADC; as well as During an amplification phase of the ADC, the first capacitive element is coupled between the input of the amplifier and an output of the amplifier.

24. The method of claim 23, further comprising during the conversion phase: decoupling the input of the amplifier from a residual output of the first conversion stage, wherein coupling the first capacitive element in parallel with the capacitive element associated with the second conversion stage comprises coupling a terminal of the first capacitive element to a reference potential node of the ADC; and The output of the amplifier is decoupled from the switched capacitor network and from the input of the second conversion stage.

25. The method of claim 24, further comprising during the amplification phase: coupling the input of the amplifier to the residual output of the first conversion stage, wherein coupling the first capacitive element between the input of the amplifier and the output of the amplifier comprises coupling the output of the amplifier to the switched capacitor network and the input of the second conversion stage; and The terminal of the first capacitive element is decoupled from the reference potential node of the ADC.

26. The method according to claim 23, further comprising: coupling a second capacitive element of the switched capacitor network in parallel with the first capacitive element and the capacitive element associated with the second conversion stage during every nth cycle of the conversion phase, wherein n is a positive integer; as well as During every nth cycle of the amplification phase, the second capacitive element is coupled between the input of the amplifier and the output of the amplifier such that the second capacitive element is connected in parallel with the first capacitive element.

27. The method according to claim 26, further comprising: coupling a third capacitive element of the switched capacitor network in parallel with the first capacitive element and the capacitive element associated with the second conversion stage during a cycle after every nth cycle of the conversion phase, wherein the second capacitive element is decoupled from the input of the second conversion stage during the cycle; as well as During a cycle after every nth cycle of the amplification phase, the third capacitive element is coupled between the input of the amplifier and the output of the amplifier such that the third capacitive element is connected in parallel with the first capacitive element, wherein the second capacitive element is decoupled from the input and the output of the amplifier during the cycle.

28. The method of claim 27, further comprising at least one of the following: reading a residual voltage from the second capacitive element during the period after every n periods of the switching phase; or A residual voltage is read out from the third capacitive element during every nth cycle of the conversion phase.

29. An analog-to-digital converter (ADC), the analog-to-digital converter (ADC) comprising: first means for converting an analog input signal into a first digital output signal; means for amplifying a residue from said first means for converting; second means for converting the amplified residue into a second digital output signal; and Means for providing a second or higher order noise transfer function for noise shaping of quantization noise of said second means for converting.

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