Three-dimensional memory devices including memory opening monitoring regions and methods of making same

Abstract

A method of forming a three-dimensional semiconductor device includes forming an alternating stack of insulating layers and spacer material layers over a substrate; forming a memory opening formed in the memory array region and a monitor opening formed in the monitor region through the alternating stack; forming a memory opening filling structure in the memory opening; forming a monitor opening fill structure by depositing a monitor opening fill material in the monitor opening; recessing first portions of the alternating stack located in the contact region and second portions of the alternating stack located in the monitoring region; and determining at least one characteristic of the recessed surface of the monitor opening filling structure. At least one characteristic of the memory opening or the memory opening filling structure can be determined based on determining at least one characteristic of the recessed surface of the monitor opening filling structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] For all purposes, this application claims the benefit of the entire contents of U.S. non-provisional application No. 17 / 936,012, filed on September 28, 2022, and entitled “THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MEMORY OPENING MONITORING AREA AND METHODS OF MAKING THE SAME,” and the contents are hereby incorporated by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and in particular to a three-dimensional memory device including a dummy memory opening monitoring area and a method for manufacturing the same. Background Art

[0004] In a three-dimensional memory device, a memory opening is formed through an alternating stack of insulating layers and sacrificial material layers, and a memory opening filling structure is formed in the memory opening. The memory opening filling structure includes a memory film and a vertical semiconductor channel. Summary of the invention

[0005] According to one aspect of the present disclosure, a method for forming a three-dimensional semiconductor device includes: forming an alternating stack of insulating layers and spacer material layers above a substrate, wherein the spacer material layer is formed as a conductive layer, or is formed as a sacrificial material layer having at least a portion located in a memory array region and in a contact region that is subsequently replaced by a conductive layer; forming an opening through the alternating stack, wherein the opening includes a memory opening formed in the memory array region and a monitor opening formed in a monitoring region, and wherein the memory opening and the monitor opening are formed as a two-dimensional array having the same two-dimensional periodicity; forming a monitor opening filling structure by depositing a monitor opening filling material in the monitor opening; recessing a first portion of the alternating stack located in the contact region and a second portion of the alternating stack located in the monitoring region, so that a first horizontal surface of the spacer material layer is physically exposed in the contact region and a second horizontal surface of the spacer material layer and a recessed surface of the monitor opening filling structure are physically exposed in the monitoring region; and determining at least one characteristic of the recessed surface of the monitor opening filling structure.

[0006] According to another aspect of the present invention, a device structure includes a three-dimensional memory array and a monitor structure located on a substrate. The three-dimensional memory array includes: a first alternating stack of insulating layers and conductive layers, the first alternating stack having a contact region; a memory opening extending vertically through the first alternating stack, located in the memory array region and arranged as a first two-dimensional array having a two-dimensional periodicity; a memory opening filling structure located in the memory opening and including a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; and a contact via structure contacting the top surface of a corresponding one of the conductive layers. The monitor structure includes: a second alternating stack of a first material layer and a second material layer; a monitor opening extending vertically from a second stepped surface to at least an upper portion of the substrate, wherein a horizontal cross-sectional profile of the monitor opening at the bottommost level of the second alternating stack has a periodicity identical to the two-dimensional periodicity of the memory opening; and a monitor opening filling structure located in the monitor opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming at least one peripheral device, a semiconductor material layer, and a gate dielectric layer according to the first embodiment of the present disclosure.

[0008] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers according to the first embodiment of the present disclosure.

[0009] Figure 3 is a plan view of a unit area of ​​a semiconductor wafer including a die region and a kerf region according to the first embodiment of the present disclosure.

[0010] Figure 4A is a vertical cross-sectional view of a die region in a first exemplary structure after forming a memory opening and a support opening according to the first embodiment of the present disclosure.

[0011] Figure 4B yes Figure 4A A top view of a memory array region including an array of memory openings at a processing step of FIG.

[0012] Figure 4C yes Figure 4A and Figure 4B Top view of a contact area including a support opening at a processing step of FIG.

[0013] Figure 4D yes FIG. 4A to FIG. 4C A vertical cross-sectional view of the monitoring area in the first exemplary structure at a processing step of .

[0014] Figure 4E yes Figure 4D A top view of the monitoring area.

[0015] Figure 5A is a vertical cross-sectional view of a die region of the first exemplary structure after forming a patterned sacrificial cap layer according to the first embodiment of the present disclosure.

[0016] Figure 5B yes Figure 5A A vertical cross-sectional view of a monitoring area of ​​a first exemplary structure at a processing step of .

[0017] Fig. 6A is a vertical cross-sectional view of a die region of the first exemplary structure after depositing a layer of dielectric fill material according to the first embodiment of the present disclosure.

[0018] Figure 6B yes Fig. 6A A vertical cross-sectional view of a monitoring area of ​​a first exemplary structure at a processing step of .

[0019] Fig. 7A is a vertical cross-sectional view of a die region of the first exemplary structure after forming a support post structure and a monitoring post structure and removing a patterned sacrificial cover layer according to the first embodiment of the present disclosure.

[0020] Figure 7B yes Fig. 7A A vertical cross-sectional view of a monitoring area of ​​a first exemplary structure at a processing step of .

[0021] FIG. 8A to FIG. 8H are sequential schematic vertical cross-sectional views of a memory opening within a first exemplary structure during formation of a memory stack structure, an optional dielectric core, and a drain region therein according to a first embodiment of the present disclosure.

[0022] Fig. 9A is a vertical cross-sectional view of a die region of the first exemplary structure after forming a memory opening filling structure according to the first embodiment of the present disclosure.

[0023] Fig. 9B yes Fig. 9A A vertical cross-sectional view of a monitoring area of ​​a first exemplary structure at a processing step of .

[0024] Fig. 10A is a vertical cross-sectional view of a die region of a first exemplary structure during formation of stepped surfaces in contact and monitoring regions according to a first embodiment of the present disclosure.

[0025] Fig. 10B yes Fig. 10A A vertical cross-sectional view of a monitoring area of ​​a first exemplary structure at a processing step of .

[0026] Fig.11A is a vertical cross-sectional view of a die region of the first exemplary structure after forming stepped surfaces in the contact region and the monitoring region according to the first embodiment of the present disclosure.

[0027] Fig. 11B yes Fig.11A Top view of the contact area at the processing step.

[0028] Fig. 11C yes Fig.11A and Fig. 11B A vertical cross-sectional view of a monitoring area of ​​a first exemplary structure at a processing step of .

[0029] Fig.11D yes FIG. 11A to FIG. 11C Top view of the monitoring area at the processing step.

[0030] Fig. 12A is a vertical cross-sectional view of a die region of the first exemplary structure after forming a backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0031] Fig. 12B yes Fig. 12A A vertical cross-sectional view of a monitoring area of ​​a first exemplary structure at a processing step of .

[0032] Fig.13A is a vertical cross-sectional view of a die region of a first exemplary structure during formation of backside trenches according to a first embodiment of the present disclosure.

[0033] Fig. 13B yes Fig.13A A top view of the memory array region in the first exemplary structure.

[0034] Fig. 13C yes Fig.13A and Fig. 13B A top view of the contact area in the first exemplary structure.

[0035] Fig.14 is a schematic vertical cross-sectional view of a die region of a first exemplary structure after forming a backside recess according to a first embodiment of the present disclosure.

[0036] Fig.15 is a schematic vertical cross-sectional view of a die region of a first exemplary structure after forming a conductive layer according to a first embodiment of the present disclosure.

[0037] Fig.16 is a schematic vertical cross-sectional view of a die region of the first exemplary structure after forming insulating spacers and backside contact structures in each backside trench according to the first embodiment of the present disclosure.

[0038] Fig.17A is a schematic vertical cross-sectional view of a die region of the first exemplary structure after forming an additional contact via structure according to the first embodiment of the present disclosure.

[0039] Fig. 17B is a schematic vertical cross-sectional view of a monitoring region of the first exemplary structure after forming an additional contact via structure according to the first embodiment of the present disclosure.

[0040] Fig. 17C is a schematic vertical cross-sectional view of a monitoring region of an alternative embodiment of the first exemplary structure after forming an additional contact via structure according to the first embodiment of the present disclosure.

[0041] Fig.18A is a vertical cross-sectional view of a die region of a second exemplary structure after forming a patterned hard mask layer according to the second embodiment of the present disclosure.

[0042] Fig.18B yes Fig.18A A vertical cross-sectional view of a monitoring area of ​​a second exemplary structure at a processing step of .

[0043] Fig.19A is a vertical cross-sectional view of a die region of a second exemplary structure during formation of a contact via cavity and a monitor via cavity according to a second embodiment of the present disclosure.

[0044] Fig.19B yes Fig.19A A vertical cross-sectional view of a monitoring area of ​​a second exemplary structure at a processing step of .

[0045] Fig. 20A is a vertical cross-sectional view of a die region of a second exemplary structure after forming a contact via cavity and a monitoring via cavity according to a second embodiment of the present disclosure.

[0046] Fig. 20B yes Fig. 20A A vertical cross-sectional view of a monitoring area of ​​a second exemplary structure at a processing step of .

[0047] Fig.21A is a vertical cross-sectional view of a die region of a second exemplary structure after forming a sacrificial contact via fill structure and a sacrificial monitor via fill structure according to the second embodiment of the present disclosure.

[0048] Fig. 21B yes Fig.21A A vertical cross-sectional view of a monitoring area of ​​a second exemplary structure at a processing step of .

[0049] Fig.22Ais a vertical cross-sectional view of a die region of a second exemplary structure during formation of a contact-level dielectric layer and backside trenches according to a second embodiment of the present disclosure.

[0050] Fig. 22B yes Fig.22A A top view of the memory array region in the second exemplary structure.

[0051] Fig. 22C yes Fig.22A and Fig. 22B A top view of the contact region in the second exemplary structure.

[0052] Fig.23 is a schematic vertical cross-sectional view of a die region of a second exemplary structure after forming a backside recess according to a second embodiment of the present disclosure.

[0053] Fig.24 is a schematic vertical cross-sectional view of a die region of a second exemplary structure after forming a conductive layer according to a second embodiment of the present disclosure.

[0054] Fig.25 is a schematic vertical cross-sectional view of a die region of a second exemplary structure after forming an insulating spacer and a backside contact structure in each backside trench according to the second embodiment of the present disclosure.

[0055] Fig.26A is a schematic vertical cross-sectional view of a die region of a second exemplary structure after forming an additional contact via structure according to the second embodiment of the present disclosure.

[0056] Fig.26B is a schematic vertical cross-sectional view of a monitoring region of a second exemplary structure after forming an additional contact via structure according to the second embodiment of the present disclosure.

[0057] Fig.26C is a schematic vertical cross-sectional view of a monitoring region of an alternative embodiment of a second exemplary structure after forming an additional contact via structure according to the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] In order to provide consistent device characteristics, performance, reliability and yield, it is necessary to control the shape of the memory opening. Although characterization methods such as cross-sectional scanning electron microscopy, transmission electron microscopy, tilted scanning electron microscopy and sheet transmission electron microscopy can be used to measure the horizontal cross-sectional shape of the memory opening, such methods are destructive and not online (in-line) (i.e., cannot be used to monitor memory devices in process). Therefore, there is a significant time delay between forming the memory opening and the characterization data being available, and a portion of the product is lost due to destructive sampling.

[0059] As discussed above, embodiments of the present disclosure are directed to a three-dimensional memory device including a monitor structure including a monitor opening located outside of a memory array region in which an active memory opening is formed. The monitor opening is a dummy memory opening filled with a monitor (i.e., dummy) opening filling structure that will not be used to store data, but will be used to monitor the shape of the active memory opening. The active memory opening is filled with an active memory opening filling structure for storing data (e.g., a portion of an active NAND memory string). The monitor structure is then patterned to form a monitor stepped surface while forming a stepped surface in a contact region of the memory device, or to form a monitoring through-hole cavity while forming a contact through-hole cavity in a contact region. The physically exposed recessed surface of the monitor opening filling structure provided at each level reflects the horizontal cross-sectional shape of the active memory opening at the corresponding level, and the shape of the active memory opening can be monitored online without destroying any product wafers. Therefore, a non-destructive online measurement method measures the shape of the monitor opening in the monitor structure to characterize the shape of the active memory opening formed in the same lithography and etching steps as the monitor opening.

[0060] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0061] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0062] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0063] Generally speaking, a semiconductor die or a semiconductor package may include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four dies). A die is the smallest unit that can independently execute a command or report a status. Each die contains one or more planes (usually one or two planes). Although there are some limitations, the same concurrent operations can occur on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased by a single erase operation. Each block contains multiple pages, which are the smallest units that can be programmed, that is, the smallest units on which a read operation can be performed.

[0064] According to an embodiment of the present disclosure, a monitor structure including a monitor opening is formed outside a memory array region in which a memory opening is formed. The monitor structure is filled with a monitor filling material to provide a monitor opening filling structure. The monitor structure is then patterned to form a monitor stepped surface while forming a stepped surface in a contact region, or to form a monitoring through-hole cavity while forming a contact through-hole cavity in a contact region. The physically exposed recessed surface of the monitor opening filling structure provided at each level reflects the horizontal cross-sectional shape of the memory opening at the corresponding level, and the shape of the memory opening can be monitored online without damaging any product wafers.

[0065] refer to Figure 1 , shows a first exemplary structure according to an embodiment of the present disclosure, which can be used, for example, to manufacture a device structure including a vertical NAND memory device. The first exemplary structure includes a substrate (9, 10), which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer (e.g., a silicon wafer) 9 and an optional semiconductor material layer (e.g., a doped well in a silicon wafer or an epitaxial silicon layer located on a silicon wafer) 10. The substrate can have a main surface 7, which can be, for example, the topmost surface of the substrate semiconductor layer 9. In one embodiment, the main surface 7 can be a single crystal semiconductor surface, such as a single crystal silicon surface.

[0066] As used herein, "semiconductor material" refers to a semiconductor material having a-6 S / cm to 1.0×10 5 S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm, and can produce materials with electrical conductivity in the range of 1.0 S / cm to 1.0×10 5 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -6 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -6 S / cm to 1.0×10 5 S / cm) in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0067] At least one semiconductor device 700 of the peripheral circuit may be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device may include, for example, a field effect transistor. For example, at least one shallow trench isolation structure 720 may be formed by etching a portion of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer may be formed over the substrate semiconductor layer 9, and may be subsequently patterned to form at least one gate structure (750, 752, 754, 758), each of which may include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrode (752, 754) may include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 may be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric liner. An active region 730 may be formed in the upper portion of the substrate semiconductor layer 9, for example, by introducing electrical dopants using the at least one gate structure (750, 752, 754, 758) as a masking structure. Additional masks may be employed as needed. The active region 730 may include source and drain regions of a field effect transistor.

[0068] A first dielectric liner 761 and a second dielectric liner 762 may be optionally formed. Each of the first dielectric liner and the second dielectric liner (761, 762) may include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide and non-stoichiometric silicon oxide having more or less than two oxygen atoms for each silicon atom. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 761 may be a silicon oxide layer, and the second dielectric liner 762 may be a silicon nitride layer. At least one semiconductor device of the peripheral circuit may include a driver circuit of a subsequently formed memory device, which may include at least one NAND device.

[0069] A dielectric material such as silicon oxide may be deposited over the at least one semiconductor device and may be subsequently planarized to form a planarized dielectric layer 770. In one embodiment, the planarized top surface of the planarized dielectric layer 770 may be coplanar with the topmost surface of the dielectric liner (761, 762). Subsequently, the planarized dielectric layer 770 and the dielectric liner (761, 762) may be removed from a certain area to physically expose the top surface of the substrate semiconductor layer 9. As used herein, a surface is "physically exposed" if the surface is in physical contact with a vacuum or a gaseous material (such as air).

[0070] The optional semiconductor material layer 10, if present, may be formed on the top surface of the substrate semiconductor layer 9 by depositing a single crystalline semiconductor material (e.g., by selective epitaxy) before or after forming the at least one semiconductor device 700. The single crystalline semiconductor material of the semiconductor material layer 10 may be epitaxially aligned with the single crystalline structure of the substrate semiconductor layer 9. The portion of the deposited semiconductor material positioned above the top surface of the planarization dielectric layer 770 may be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer 10 may have a top surface that is coplanar with the top surface of the planarization dielectric layer 770.

[0071] A region (i.e., area) of at least one semiconductor device 700 is referred to herein as a peripheral region 200. A region where a memory array is subsequently formed is referred to herein as a memory array region 100. A contact region 300 for subsequently forming a stepped terrace of a conductive layer may be provided between the memory array region 100 and the peripheral region 200.

[0072] In an alternative embodiment, the peripheral device region 200 containing at least one semiconductor device 700 for peripheral circuits can be located under the memory array region 100 in an under-array CMOS configuration. In another alternative embodiment, the peripheral device region 200 can be located on a separate substrate that is subsequently bonded to the memory array region 100.

[0073] refer to Figure 2 , a stack of alternating multiple first material layers (which may be insulating layers 32) and second material layers (which may be sacrificial material layers 42) is formed above the top surface of the substrate (9, 10). The alternating multiple first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instances of the first element and the second element may form a unit that is periodically repeated within the alternating multiple elements.

[0074] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer 42. In this case, the stack may include a plurality of insulating layers 32 and sacrificial material layers 42 alternating, and the insulating layers 32 and sacrificial material layers 42 are stacked alternately in the process of forming the insulating layers 32 and the sacrificial material layers 42. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0075] Insulating materials that can be used for insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials, which are generally referred to as high dielectric constant (high-k) dielectric oxides. In one embodiment, the first material of insulating layer 32 may be silicon oxide.

[0076] The second material of the sacrificial material layer 42 is a sacrificial material that can be selectively removed for the first material of the insulating layer 32. As used herein, if the removal process removes the first material at a rate at least twice the removal rate of the second material, the removal of the first material is "selective" for the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. The sacrificial material layer 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer including silicon nitride, and may be substantially composed of silicon nitride.

[0077] In one embodiment, insulating layer 32 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0078] The thickness of the insulating layer 32 and the sacrificial material layer 42 can be in the range of 20nm to 50nm, but lesser and greater thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the insulating layer 32 and sacrificial material layer 42 pair can be in the range of 2 to 1,024, typically 8 to 256, but more repetitions can also be used. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially constant within each respective sacrificial material layer 42.

[0079] Although embodiments are described in which the spacer material layer is a sacrificial material layer 42 that is subsequently replaced by a conductive layer, embodiments are expressly contemplated in which the sacrificial material layer is formed as a conductive layer. In this case, the step of replacing the spacer material layer with a conductive layer may be omitted.

[0080] Optionally, an insulating capping layer 70 may be formed over the alternating stack (32, 42). The insulating capping layer 70 includes a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating capping layer 70 may include a dielectric material that may be used for the insulating layer 32 as described above. The insulating capping layer 70 may have a greater thickness than each insulating layer 32. The insulating capping layer 70 may be deposited by, for example, chemical vapor deposition. In one embodiment, the insulating capping layer 70 may be a silicon oxide layer.

[0081] Generally speaking, the first exemplary structure may be formed within a unit area of ​​a semiconductor (eg, silicon) wafer in which a two-dimensional array of semiconductor dies is formed.

[0082] refer to Figure 3 , showing a unit area UA of a semiconductor wafer. The unit area UA includes a die region DR in which a semiconductor die is formed, and a kerf region KR providing a lateral spacing between the die region DR and a corresponding adjacent die region DR of an adjacent semiconductor die. In an illustrative example, the die region DR may include a plurality of memory planes (P0, P1, P2, P3), each of which includes at least one (e.g., two to four) corresponding memory array region 100, at least one corresponding contact region 300, and optionally at least one corresponding peripheral region 200. Alternatively, the peripheral region 200 may be located below the memory array region 100 and / or the contact region 300. According to one aspect of the present disclosure, at least one monitoring region 400 is provided within the kerf region KR. As described below, a monitor structure is formed in at least one monitoring region 400 so that the shape of a memory opening subsequently formed in the memory array region 100 can be indirectly monitored using the shape of the monitor opening in at least one monitoring region 400 using an online measurement device.

[0083] refer to FIG. 4A to FIG. 4E Various openings (49, 19, 29) may be formed through the alternating stacks (32, 42) in the various regions (100, 300, 400). Figure 4A It is a vertical cross-sectional view of the die region DR.

[0084] Figure 4B is a top view of the memory array area 100 . Figure 4C is a top view of the contact area 300 . Figure 4D is a vertical cross-sectional view of the monitoring area 400 . Figure 4E is a top view of the monitoring area 400 .

[0085] Specifically, a photoresist layer (not shown) may be applied over the first exemplary structure, and an opening may be formed through the structure by photolithographic exposure and development. For example, a pattern of a two-dimensional periodic array of openings having a first periodicity along the first horizontal direction hd1 and a second periodicity along the second horizontal direction hd2 may be formed in the region of the memory array region 100. A replica of the pattern of the two-dimensional periodic array of openings may be formed in the monitoring region 400. The replica of the pattern in the monitoring region 400 may have the same size as the size of each pattern of the two-dimensional periodic array of openings in a corresponding one of the memory array regions 100, and may have the same size as or smaller than the size of each pattern of the two-dimensional periodic array of openings in the contact region 300. In one embodiment, each pattern of the two-dimensional periodic array of openings in the memory array region 100 may include a two-dimensional circular array of openings, and the replica pattern may include another two-dimensional circular array of openings having the same diameter. The size, the periodicity along the first horizontal direction hd1, and the periodicity along the second horizontal direction hd2 may be the same between each pattern of the two-dimensional periodic array of openings and the replica pattern. Additional openings having the same or a larger width or diameter may be formed through the photoresist layer in each contact region 300. The additional openings may be formed in areas where support post structures will subsequently be formed.

[0086] The opening pattern in the photoresist layer can be transferred to the top surface of the semiconductor material layer 10 through the alternating stack (32, 42) by performing an anisotropic etching process to form various openings (49, 19, 29) extending vertically through each layer within the alternating stack (32, 42) and the insulating cap layer 70. The various openings include memory openings 49 formed in the memory array area 100, support openings 19 formed in the contact area 300, and monitor openings 29 formed in the monitoring area 400. As used herein, "memory openings" refers to structures in which active memory elements (such as memory stack structures for storing data) are subsequently formed. As used herein, "support openings" refers to structures in which support structures (such as support pillar structures) that mechanically support other elements are subsequently formed. As used herein, "monitor openings" refers to structures that replicate memory openings 49. The memory openings 49 and the monitor openings 29 are formed as two-dimensional arrays having the same two-dimensional periodicity and preferably having the same size (e.g., diameter). The support opening 19 may have the same size as the memory opening 49 and the monitor opening 29, or may have a different (e.g., larger) size than the memory opening 49 and the monitor opening 29. The photoresist layer may then be removed, for example, by ashing. Thus, in one embodiment, the memory opening and the monitor opening have the same diameter and are formed during the same etching step.

[0087] refer to Figure 5A and Figure 5B , a sacrificial capping material may be deposited over the first exemplary structure and may be patterned to cover the memory array region 100 but not the contact region 300 or the monitoring region 400. The patterned sacrificial capping material forms a patterned sacrificial capping layer 13 that covers the memory opening 49 but not the monitor opening 29 or the support opening 19. In one embodiment, the patterned sacrificial capping layer 13 comprises a carbon-based material, such as amorphous carbon (e.g., Advanced Patterned Film (APF) available from Applied Materials, Inc.) tm ), diamond-like carbon, etc. In one embodiment, the atomic percentage of carbon atoms in the patterned sacrificial capping layer 13 may be at least 50%.

[0088] refer to Fig. 6A and Figure 6B , a dielectric fill material is conformally deposited in the support opening 19 and the monitor opening 29 and over the patterned sacrificial cover layer 13. In one embodiment, the dielectric fill material may include a silicon oxide material, such as undoped silicate glass or doped silicate glass. The dielectric fill material fills the monitor opening 29 and may therefore be referred to as a monitor opening fill material. In addition, the dielectric fill material fills the support opening 19 and may therefore be referred to as a support post material.

[0089] refer to Fig. 7A and Figure 7B The portion of the dielectric filling material overlying the top surface of the insulating cap layer 70 can be removed by performing an etch back process, which can include a wet etching process using dilute hydrofluoric acid and / or a chemical mechanical polishing process. Each remaining portion of the dielectric filling material filling the monitor opening 29 (i.e., the monitor opening filling material) constitutes a monitor opening filling structure 30. Each remaining portion of the dielectric filling material filling the support opening 19 constitutes a support column structure 20.

[0090] In general, the monitor opening filling structure 30 can be formed by depositing a monitor opening filling material (e.g., a dielectric filling material) in the monitor opening 29. An additional portion of the monitor opening filling material is deposited in the support opening 19 to form the support post structure 20. In other words, the support post structure 20 is formed by depositing the monitor opening filling material in the support opening 19 while forming the monitor opening filling structure 30. Subsequently, the patterned sacrificial cover layer 13 can be removed, for example, by ashing.

[0091] FIG. 8A to FIG. 8H are sequential schematic vertical cross-sectional views of a memory opening within a first exemplary structure during formation of a memory stack structure, an optional dielectric core, and a drain region therein according to a first embodiment of the present disclosure.

[0092] refer to Fig. 8A , showing Fig. 7A and Figure 7B Memory opening 49 in the first exemplary device structure. Memory opening 49 extends through insulating cap layer 70, alternating stack (32, 42), and optionally extends into an upper portion of semiconductor material layer 10. Optionally, sacrificial material layer 42 may be partially laterally recessed, for example by isotropic etching, to form a lateral recess (not shown).

[0093] refer to Figure 8B, the blocking dielectric layer 52 may be deposited by a conformal deposition process. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is essentially composed of a dielectric metal oxide. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include multiple dielectric metal oxide layers having different material compositions. Alternatively or in addition, the blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. The thickness of the blocking dielectric layer 52 may be in the range of 3nm to 20nm, but smaller and larger thicknesses may also be used. Alternatively, the blocking dielectric layer 52 may be omitted, and the backside blocking dielectric layer may be formed after forming a backside recess on the surface of the memory film to be formed subsequently.

[0094] refer to Figure 8C , a memory material layer 54, an optional dielectric liner 56, and an optional sacrificial capping material layer 601 may be deposited. In general, the memory material layer 54 may include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store a data bit in the form of the presence or absence of charge, ferroelectric polarization direction, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the memory material layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within a lateral recess. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer.

[0095] The optional dielectric layer 56 (if present) comprises a dielectric material. In one embodiment, the optional dielectric layer 56 comprises a tunneling dielectric layer through which charge tunneling can be performed under suitable electrical bias conditions. The optional dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the optional dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the optional dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the optional dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be employed. The combination of the blocking dielectric layer 52, the memory material layer 54, and the optional dielectric layer 56 constitutes the memory film 50.

[0096] The optional sacrificial covering material layer 601 includes a sacrificial material that is subsequently selectively removed relative to the material of the dielectric layer 56. In one embodiment, the sacrificial covering material layer 601 may include a semiconductor material such as amorphous silicon, or may include a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial covering material layer 601 may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial covering material layer 601 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. The memory cavity 49' is formed in the space of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 601).

[0097] refer to Fig.8D , the optional sacrificial covering material layer 601, the dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 overlying the insulating cap layer 70 are sequentially anisotropically etched using at least one anisotropic etching process. Portions of the sacrificial covering material layer 601, the dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 located above the top surface of the insulating cap layer 70 may be removed by at least one anisotropic etching process. In addition, horizontally extending portions of the sacrificial covering material layer 601, the dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 at the bottom of each memory cavity 49' may be removed to form openings in the remaining portions thereof. Each of the sacrificial covering material layer 601, the dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 may be etched by a corresponding anisotropic etching process using a corresponding etching chemistry, which may be the same or different for the various material layers.

[0098] Each remaining portion of the sacrificial capping material layer 601 may have a tubular configuration. The memory material layer 54 may include a charge trapping material, a floating gate material, a ferroelectric material, a resistive memory material that can provide at least two different levels of resistivity (such as a phase change material), or any other memory material that can store information through a change of state. In one embodiment, each memory material layer 54 may include a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the memory material layer 54 may be a continuous memory material layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0099] A set of blocking dielectric layers 52, memory material layers 54, and dielectric layers 56 located in the memory opening 49 constitute a memory film 50, which includes a plurality of charge storage regions (including portions of the memory material layer 54), which are insulated from surrounding materials by the blocking dielectric layer 52 and the dielectric layer 56. In one embodiment, the sacrificial capping material layer 601, the dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 may have vertically overlapping sidewalls. The sacrificial capping material layer 601 may then be selectively removed relative to the material of the dielectric layer 56. In the case where the sacrificial capping material layer 601 includes a semiconductor material, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) may be performed to remove the sacrificial capping material layer 601. Alternatively, the sacrificial capping material layer 601 may be retained.

[0100] refer to Fig. 8E , the semiconductor channel layer 60L can be deposited directly on the dielectric layer 56 in the memory opening 49. The semiconductor channel layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L may have a first conductivity type of doping, which is the same as the conductivity type of the semiconductor material layer 10 and the base channel portion 11. The semiconductor channel layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The semiconductor channel layer 60L can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0101] refer to Figure 8FIn the case where the memory cavity 49' in each memory opening 49 is not completely filled with the semiconductor channel layer 60L, a dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarization deposition process such as spin coating.

[0102] refer to Figure 8G , horizontal portions of dielectric core layer 62L may be removed, for example, by a recess etching process, so that each remaining portion of dielectric core layer 62L is located within a corresponding memory opening 49 and has a corresponding top surface below a horizontal plane including a top surface of insulating cap layer 70. Each remaining portion of dielectric core layer 62L constitutes dielectric core 62.

[0103] refer to Figure 8H , a doped semiconductor material having a doping of the second conductivity type may be deposited in each recessed region above the dielectric core 62. The deposited semiconductor material may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material may be between 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0104] Excess portions of the deposited semiconductor material of the horizontal portion of the doped semiconductor channel layer 60L having the second conductivity type may be removed (e.g., by chemical mechanical planarization (CMP) or a recess etching process) from above the horizontal plane including the top surface of the insulating cap layer 70. Each remaining portion of the doped semiconductor material having the second conductivity type constitutes a drain region 63. Each remaining portion of the doped semiconductor channel layer 60L having the first conductivity type constitutes a vertical semiconductor channel 60.

[0105] Each set of adjacent blocking dielectric layers 52, memory material layers 54, and dielectric layers 56 together constitute a memory film 50 that can store charge or ferroelectric polarization for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and a backside blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0106] Each combination of memory film 50 and vertical semiconductor channel 60 within memory opening 49 constitutes memory stack structure 55. Memory stack structure 55 is a combination of semiconductor channel 60, dielectric layer 56, multiple memory elements including portions of memory material layer 54, and optional blocking dielectric layer 52. The entire set of material portions filling memory opening 49 is referred to herein as memory opening filling structure 58.

[0107] Generally, a memory opening filling structure 58 may be formed within each memory opening 49. The memory opening filling structure 58 includes an optional blocking dielectric layer 52, a memory material layer 54, an optional dielectric layer 56, and a vertical semiconductor channel 60. The dielectric layer 56 may laterally surround the vertical semiconductor channel 60. The memory material layer 54 may laterally surround the dielectric layer 56.

[0108] refer to Fig. 9A and Fig. 9B , shows a first exemplary structure after forming a memory opening filling structure 58 within the memory opening 49. Fig. 7A and Figure 7B An instance of memory opening fill structure 58 is formed within each memory opening 49 of the structure.

[0109] refer to Fig. 10A and Fig. 10B , a first portion of the alternating stack (32, 42) located in the contact area 300 and a second portion of the alternating stack (32, 42) located in the monitoring area 400 can be recessed so that a first horizontal surface of the spacer material layer (such as the sacrificial material layer 42) is physically exposed in the contact area 300, and a second horizontal surface of the spacer material layer (such as the sacrificial material layer 42) and a recessed surface of the monitor opening filling structure 30 are physically exposed in the monitoring area 400.

[0110] In one embodiment, a stepped surface is formed in the contact zone 300 and the monitoring zone 400. As used herein, "stepped surface" refers to a group of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface, and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. Specifically, a first stepped surface is formed in each contact zone 300, and a second stepped surface is formed in the monitoring zone 400 at the same time as the first stepped surface is formed. A first stepped cavity is formed above the first stepped surface in each contact zone 300. A second stepped cavity is formed above the second stepped surface in the monitoring zone 400. A "stepped cavity" refers to a cavity having a stepped surface.

[0111] In one embodiment, a trimmable mask layer 37 may be formed over the alternating stack (32, 42) such that a first edge of the trimmable mask layer 37 is formed in the contact region 300 and a second edge of the trimmable mask layer 37 is formed in the monitoring region 400. A set of unit processing sequences may be iteratively performed multiple times. The set of unit processing sequences includes an anisotropic etching step of etching at least one pair of insulating layers 32 and spacer material layers (such as sacrificial material layers 42) within the alternating stack (32, 42) and a mask trimming step of isotropically trimming the trimmable mask layer 37. In one embodiment, the monitor opening filling structure 30 and the support column structure 20 are recessed in parallel during the recessing of the portions of the alternating stack (32, 42) located in the contact region 300 and located in the monitoring region 400. Each iteration of the group of unit processing sequences vertically recesses physically exposed horizontal surface segments of the alternating stack (32, 42) through a pair of insulating layers 32 and spacer material layers (such as sacrificial material layers 42), and recesses the trimmable mask layer 37 laterally, so that new horizontal surface segments of the topmost spacer material layer (such as the topmost sacrificial material layer 42) or the insulating cap layer 70 are physically exposed.

[0112] refer to FIG. 11A to FIG. 11D , the set of unit processing sequences may be repeated as many times as the total number of spacer material layers (such as sacrificial material layers 42) in the alternating stack (32, 42). Each set of first stepped surfaces in the corresponding contact area 300 may extend continuously from the top surface of the semiconductor material layer 10 to the top surface of the insulating cap layer 70. The set of second stepped surfaces in the monitoring area 400 may extend continuously from the top surface of the semiconductor material layer 10 to the top surface of the insulating cap layer 70. A first stepped cavity 69 may be formed above each set of first stepped surfaces in the contact area. A second stepped cavity 169 may be formed above each set of second stepped surfaces in the monitoring area 400. The trimmable mask layer 37 may then be removed, for example, by ashing.

[0113] Generally, a first stepped surface may be formed in the contact region 300 such that the first stepped surface includes a first horizontal surface segment of a spacer material layer (such as sacrificial material layer 42) and a first vertical surface segment of the insulating layer 32 and the spacer material layer (such as sacrificial material layer 42). A second stepped surface may be formed in the monitoring region 400 such that the second stepped surface includes a second horizontal surface segment of a spacer material layer (such as sacrificial material layer 42) and a second vertical surface segment of the insulating layer 32 and the spacer material layer (such as sacrificial material layer 42). In one embodiment, the physically exposed horizontal surface of the alternating stack (32, 42) may include a horizontal surface of the sacrificial material layer 42.

[0114] In addition, the recessed top surface of the monitor opening filling structure 30 can be physically exposed in the monitoring area 400, and the recessed top surface of the support column structure 20 can be physically exposed in the contact area 300. The sacrificial material layer 42 can have a different material composition than the monitor opening filling structure 30. In one embodiment, the sacrificial material layer 42 can include silicon nitride, and the monitor opening filling structure 30 can include silicon oxide. The different materials in the sacrificial material layer 20 and the monitor opening filling structure 30 increase the contrast of the image of the monitor opening filling structure 30 that is subsequently generated.

[0115] According to one aspect of the present invention, a scanning electron microscope and / or an optical image measurement tool (such as an optical microscope, a camera and / or a photodetector) may be used to measure the characteristics of the recessed surface of the monitor opening filling structure 30. The measured characteristics of the recessed surface of the monitor opening filling structure 30 may include geometric characteristics of the recessed top surface of the monitor opening filling structure 30, such as shape, size, and various parameters that can be derived therefrom. In one embodiment, the measured characteristics of the recessed surface of the monitor opening filling structure 30 may include a change in the area of ​​the recessed surface of the monitor opening filling structure 30, which depends on the vertical distance between the substrate 9 and the recessed surface of the monitor opening filling structure 30. In one embodiment, the characteristics of the recessed surface of the monitor opening filling structure 30 include a change in the average lateral dimension (e.g., diameter) of the recessed surface of the monitor opening filling structure 30, which depends on the vertical distance between the substrate 9 and the recessed surface of the monitor opening filling structure 30. For a monitor opening filling structure 30 having a circular horizontal cross-sectional shape, the "average lateral dimension" of the two-dimensional closed shape refers to the diameter of a circle having the same area as the two-dimensional closed shape. In one embodiment, the characteristic of the recessed surface of the monitor opening filling structure 30 includes a change in the ellipticity of the recessed surface of the monitor opening filling structure 30, which depends on the vertical distance between the substrate and the recessed surface of the monitor opening filling structure 30. The ellipticity of the two-dimensional closed shape refers to the ellipticity of the ellipse that provides the minimum root mean square error during fitting of the two-dimensional closed shape with the ellipse.

[0116] Generally speaking, FIG. 4A to FIG. 4E The shape of the monitor opening 29 formed at the processing step of FIG. 4A to FIG. 4EThe shape of the memory opening 49 formed at the processing step of the monitor opening 29 and the monitor opening filling structure 30 is the same. Therefore, the horizontal cross-sectional profiles of the monitor opening 29 and the monitor opening filling structure 30 may be statistically the same as the horizontal cross-sectional profiles of the memory opening 49 and the memory opening filling structure 58. Therefore, by performing online measurement of the recessed top surface of the monitor opening filling structure 30, as the height of the second stepped surface changes from one side of the captured image to the other side of the captured image, images of horizontal profiles of different levels of the monitor opening filling structure 30 are generated. An optical measurement tool or a scanning electron microscope can be used to perform image capture. In one embodiment, the method also includes determining at least one characteristic of the memory opening 49 or the memory opening filling structure 58 (for example, at least one geometric characteristic described above) based on the step of determining at least one characteristic of the recessed surface of the monitor opening filling structure 30.

[0117] refer to Fig. 12A and Fig. 12B , a backward stepped dielectric material portion (65, 165) (i.e., an insulating fill material portion) may be formed therein by depositing a dielectric material in the stepped cavity (69, 169). For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity (69, 169). Excess portions of the deposited dielectric material may be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP). Each remaining portion of the deposited dielectric material that fills the stepped cavity constitutes a backward stepped dielectric material portion (65, 165). As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the backward stepped dielectric material portion (65, 165), the silicon oxide of the backward stepped dielectric material portion (65, 165) may or may not be doped with dopants such as B, P and / or F. The backward stepped dielectric material portion (65, 165) includes a first backward stepped dielectric material portion 65 and a second backward stepped dielectric material portion 165.

[0118] refer to FIG. 13A to FIG. 13C A contact-level dielectric layer 80 may be formed over the alternating stacks (32, 42) of insulating layers 32 and sacrificial material layers 42 and over the rearward stepped dielectric material portions (65, 165). The contact-level dielectric layer 80 includes a dielectric material different from the dielectric material of the sacrificial material layers 42. For example, the contact-level dielectric layer 80 may include silicon oxide. The contact-level dielectric layer 80 may have a thickness in the range of 50 nm to 500 nm, although lesser and greater thicknesses may also be employed.

[0119] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and photolithographically patterned to form openings in the areas between the clusters of memory opening fill structures 58. The pattern in the photoresist layer may be transferred through the contact level dielectric layer 80, the alternating stacks (32, 42) and / or the back stepped dielectric material portions (65, 165) using anisotropic etching to form backside trenches 79 extending vertically from at least the top surface of the contact level dielectric layer 80 to the top surface of the substrate (9, 10) and extending laterally through the memory array region 100 and the contact region 300.

[0120] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction hd1, and may be laterally spaced apart from each other along a second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1. The memory stack structures 55 may be arranged in rows extending along the first horizontal direction hd1. The drain selection level isolation structure 72 may extend laterally along the first horizontal direction hd1. Each backside trench 79 may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain selection level isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, which does not change with translation along the first horizontal direction hd1. The multi-row memory stack structures 55 may be located between an adjacent pair of backside trenches 79 and drain selection level isolation structures 72, or between an adjacent pair of drain selection level isolation structures 72. In one embodiment, the backside trench 79 may include a source contact opening, wherein a source contact via structure may be subsequently formed. The photoresist layer may be removed, for example, by ashing.

[0121] Source regions 61 may be formed at the surface portion of the semiconductor material layer 10 beneath each backside trench 79 by implanting electrical dopants into the physically exposed surface portion of the semiconductor material layer 10 .

[0122] refer to Fig.14 , an etchant that selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32 may be introduced into the backside trench 79, for example, using an etching process. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the second material of the sacrificial material layer 42 may be selective to the first material of the insulating layer 32, the material of the back stepped dielectric material portion (65, 165), the semiconductor material of the semiconductor material layer 10, and the outermost material of the memory film 50. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32 and the back stepped dielectric material portion (65, 165) may be selected from silicon oxide and dielectric metal oxide.

[0123] The etching process for selectively removing the second material from the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which the first exemplary structure is immersed in a wet etching tank including phosphoric acid, which etches silicon nitride in a manner that is selective to silicon oxide, silicon, and various other materials used in the art. When the backside recess 43 exists within the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the rear stepped dielectric material portion (65, 165), and the memory opening filling structure 58 provide structural support.

[0124] Each back side recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back side recess 43 may be greater than the height of the back side recess 43. Multiple back side recesses 43 may be formed in the volume of the second material from which the sacrificial material layer 42 is removed. The memory opening in which the memory stack structure 55 is formed is referred to herein as the front side opening or the front side cavity, in contrast to the back side recess 43. In one embodiment, the memory array area 100 includes a three-dimensional NAND string array having a plurality of device levels disposed above the substrate (9, 10). In this case, each back side recess 43 may define a space for receiving a corresponding word line of the three-dimensional NAND string array.

[0125] Each of the plurality of backside recesses 43 may extend substantially parallel to the top surface of the substrate (9, 10). The backside recess 43 may be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each backside recess 43 may have a uniform height throughout.

[0126] refer to Fig.15 , an optional backside blocking dielectric layer (not shown) may be formed. The backside blocking dielectric layer, if present, comprises a dielectric material that serves as a control gate dielectric for a control gate to be subsequently formed in the backside recess 43. In the case where a blocking dielectric layer 52 is present within each memory opening, the backside blocking dielectric layer is optional. In the case where the blocking dielectric layer 52 is omitted, the backside blocking dielectric layer is present.

[0127] The backside blocking dielectric layer may be formed in the backside recess 43 and on the sidewalls of the backside trench 79. The backside blocking dielectric layer may be formed directly on the horizontal surface of the insulating layer 32 in the backside recess 43 and on the sidewalls of the memory stack structure 55. In one embodiment, the backside blocking dielectric layer may be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer may be substantially composed of aluminum oxide. The thickness of the backside blocking dielectric layer may be in the range of 1 nm to 15 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses may also be used.

[0128] At least one metal material may be conformally deposited in the back side recess 43. In one embodiment, the at least one metal material may include a metal barrier layer and a metal filler material. The metal barrier layer includes a conductive metal material, which may be used as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2nm to 8nm, such as 3nm to 6nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer may be substantially composed of a conductive metal nitride such as TiN.

[0129] The metal filling material is deposited in a plurality of backside recesses 43, on the sidewalls of at least one backside trench 79, and above the top surface of the contact level dielectric layer 80 to form a metal filling material layer. The metal filling material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. In one embodiment, the metal filling material layer can be substantially composed of at least one elemental metal. The at least one elemental metal of the metal filling material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filling material layer can be substantially composed of a single elemental metal. In one embodiment, the metal filling material layer can be deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal filling material layer can be a tungsten layer including residual level fluorine atoms as impurities. The metal filling material layer is spaced apart from the insulating layer 32 and the memory stack structure 55 by a metal barrier layer, which is a metal barrier layer that blocks fluorine atoms from diffusing therethrough.

[0130] A plurality of conductive layers 46 may be formed in the plurality of backside recesses 43, and a continuous metal material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal filling material layer located between a pair of vertically adjacent dielectric material layers, such as a pair of insulating layers 32. The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal filling material layer located in the backside trench 79 or over the contact-level dielectric layer 80.

[0131] Each sacrificial material layer 42 may be replaced by a conductive layer 46. A backside cavity exists in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer and the continuous metal material layer.

[0132] The deposited metallic material of the continuous conductive material layer is etched back from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 80, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recess 43 constitutes a conductive layer 46. Each conductive layer 46 may be a conductive line structure.

[0133] Each conductive layer 46 can be used as a combination of multiple control gate electrodes located at the same level and word lines electrically interconnected (i.e., electrically shorted) with the multiple control gate electrodes located at the same level. The multiple control gate electrodes within each conductive layer 46 are control gate electrodes for vertical memory devices including the memory stack structure 55. In other words, each conductive layer 46 can be a word line used as a common control gate electrode for multiple vertical memory devices. One or more topmost and bottommost conductive layers 46 can be used as corresponding drain select gate electrodes and source select gate electrodes.

[0134] In one embodiment, the continuous conductive layer may be selectively removed for the material of the backside blocking dielectric layer. In this case, a horizontal portion of the backside blocking dielectric layer may be present in the bottom of each backside trench 79. In another embodiment, the continuous conductive material layer may not be selectively removed for the material of the backside blocking dielectric layer, or a backside blocking dielectric layer may not be used. The planar dielectric portion may be removed during the removal of the continuous conductive material layer. The bottommost conductive layer 46 provided when forming the conductive layer 46 in the alternating stack (32, 46) may include a select gate electrode for a field effect transistor. A backside cavity is present in each backside trench 79.

[0135] refer to Fig.16, an insulating material layer may be formed in the backside trench 79 and above the contact level dielectric layer 80 by a conformal deposition process. A first exemplary conformal deposition process includes, but is not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organic silicate glass, or a combination thereof. In one embodiment, the insulating material layer may include silicon oxide. The insulating material layer may be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer may be in the range of 1.5 nm to 60 nm, but smaller and larger thicknesses may also be used.

[0136] Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer 80 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity exists within the volume surrounded by each insulating spacer 74. The top surface of the semiconductor material layer 10 may be physically exposed at the bottom of each backside trench 79.

[0137] The backside contact via structure 76 can be formed in each backside cavity. Each contact via structure 76 can fill the corresponding cavity. The contact via structure 76 can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside groove 79. For example, the at least one conductive material may include a conductive pad and a conductive filling material portion. The conductive pad may include a conductive metal pad such as TiN, TaN, WN, TiC, TaC, WC, their alloys, or their stacks. The thickness of the conductive pad may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The conductive filling material portion may include a metal or a metal alloy. For example, the conductive filling material portion may include W, Cu, Al, Co, Ru, Ni, their alloys, or their stacks.

[0138] A contact level dielectric layer 80 overlying the alternating stack (32, 46) can be used as a stop layer to planarize the at least one conductive material. If a chemical mechanical planarization (CMP) process is used, the contact level dielectric layer 80 can be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes a backside contact via structure 76.

[0139] The backside contact via structure 76 extends through the alternating stack (32, 46) and contacts the top surface of the source region 61. If a backside blocking dielectric layer is employed, the backside contact via structure 76 may contact the sidewalls of the backside blocking dielectric layer.

[0140] Alternatively, the insulating material layer may be formed in the backside trench 79 to completely fill the entire volume of the backside trench 79 and may be substantially composed of at least one dielectric material. In this alternative embodiment, the source region 61 and the backside trench via structure 76 may be omitted, and a horizontal source line (e.g., a direct stripe contact) may contact one side of the lower portion of the semiconductor channel 60.

[0141] refer to Fig.17A and Fig. 17B , additional contact via structures (88, 86, 8P) may be formed through the contact level dielectric layer 80 and optionally through the first backward stepped dielectric material portion 65. For example, a drain contact via structure 88 may be formed through the contact level dielectric layer 80 on each drain region 63. A layer contact via structure 86 may be formed through the contact level dielectric layer 80 and through the backward stepped dielectric material portion (65, 165) on the conductive layer 46. A peripheral device contact via structure 8P may be formed directly on a corresponding node of a peripheral device through the first backward stepped dielectric material portion 65. In one embodiment, after forming the contact via structures (88, 86, 8P), the second backward stepped dielectric material portion 165 does not include any openings therethrough.

[0142] refer to Fig. 17C , shows the monitoring region 400 of an alternative embodiment of the first exemplary structure after forming additional contact via structures (88, 86, 8P). In an alternative embodiment of the first exemplary structure, the sacrificial material layer 42 is not replaced by the conductive layer 46 in the monitoring region 400. For example, this modification can be provided by not forming the backside trench 79 in or around the monitoring region 400.

[0143] refer to Fig.18A and Fig.18B By forming a patterned hard mask layer 130 above the alternating stack (32, 42), Fig. 9A and Fig. 9B The second exemplary structure according to the second embodiment of the present disclosure is obtained in the first exemplary structure shown. The patterned hard mask layer 130 includes a hard mask material such as a dielectric metal oxide and / or a metal material. The patterned hard mask layer 130 can be formed, for example, by depositing a hard mask material layer, applying a photoresist layer over the hard mask material layer and photolithographically patterning the photoresist layer, and by an anisotropic etching process, which transfers the opening pattern in the photoresist layer through the hard mask material layer, and the hard mask material layer becomes the patterned hard mask layer 130 when the opening is formed therethrough. The photoresist layer can then be removed, for example, by ashing.

[0144] The patterned hard mask layer 130 includes a first opening in each contact region 300 and a second opening in the monitoring region 400. The first opening may be formed outside the region of the support pillar structure 20, and the second opening may be formed such that each region of the second opening includes a region of at least one monitor opening filling structure 29.

[0145] Reference Fig.19A and Fig.19B , a contact via cavity 85 may be formed in the contact region 300 by recessing a first portion of the alternating stack (32, 42) such that the bottom surface of the contact via cavity 85 includes a first horizontal surface of a spacer material layer (such as the sacrificial material layer 42), and a monitoring via cavity 185 may be formed in the monitoring region 400 by recessing a second portion of the alternating stack (32, 42) such that the bottom surface of the monitoring via cavity 185 includes a recessed surface of the monitor opening filling structure 30.

[0146] In one embodiment, a series of mask anisotropic etching processes are performed to vertically transfer the pattern of a corresponding subset of the openings in the patterned hard mask layer 130 through a corresponding subset of the layers within the alternating stack (32, 42). Each mask anisotropic etching process in the series of mask anisotropic etching processes employs a different photoresist mask 131_i that covers the corresponding subset of the first and second openings and etches a corresponding number of pairs of different insulating layers 32 and sacrificial material layers 42. In the series of mask anisotropic etching processes, the corresponding numbers may be different.

[0147] In an illustrative example, N different photoresist layers 131_i (0 < i < (N + 1)) may be employed in combination with N anisotropic etching processes. For each positive integer i starting from 1 and ending at N, the i-th anisotropic etching process may employ the i-th patterned photoresist mask 131_i to etch through 2 (N-1) pairs of the insulating layer 32 and the sacrificial material layer 42. Each patterned photoresist mask 131_i may be removed, for example, by ashing after the corresponding anisotropic etching process. Each etched volume of the alternating stack (32, 42) located below the first opening constitutes the contact via cavity 85. Each etched volume of the alternating stack (32, 42) and the monitor opening filling structure 30 constitutes the monitoring via cavity 185. Up to 2 N mask or maskless combinations may be provided by the N patterned photoresist masks 131_i. Thus, the contact via cavity 85 and up to 2 N different depths. By selecting the number N such that 2 N is greater than the total number of sacrificial material layers 42 in the alternating stack (32, 42), the contact via cavity 85 and the monitoring via cavity 185 may extend to the top surface of each sacrificial material layer in the sacrificial material layers 42.

[0148] In one embodiment, the support post structures 20 are recessed in parallel during the recessing of the portions of the alternating stack (32, 42) located in the contact area 300. In one embodiment, each of the top surfaces of the support post structures 20 is adjacent to and coplanar with a corresponding one of the first horizontal surfaces of the spacer material layer (such as the sacrificial material layer 42).

[0149] refer to Fig. 20A and Fig. 20B , shows a second exemplary structure after performing the last (e.g., Nth) patterned anisotropic etching process and after removing the last (e.g., Nth) patterned photoresist layer (which serves as the last etching mask). The contact via cavity 85 is present in the contact region 300, and the monitoring via cavity 185 is present in the monitoring region 400. The contact via cavity 85 and the monitoring via cavity 185 may have the same or different diameters.

[0150] According to one aspect of the present invention, a scanning electron microscope and / or an optical image measurement tool (such as an optical microscope, a camera and / or a photodetector) can be used to measure the characteristics of the recessed surface of the monitor opening filling structure 30. The measured characteristics of the recessed surface of the monitor opening filling structure 30 may include geometric characteristics of the recessed top surface of the monitor opening filling structure 30, such as shape, size, and various parameters that can be derived therefrom. In one embodiment, the measured characteristics of the recessed surface of the monitor opening filling structure 30 may include a change in the area of ​​the recessed surface of the monitor opening filling structure 30, which depends on the vertical distance between the substrate 9 and the recessed surface of the monitor opening filling structure 30. In one embodiment, the characteristics of the recessed surface of the monitor opening filling structure 30 include a change in the average lateral dimension of the recessed surface of the monitor opening filling structure 30, which depends on the vertical distance between the substrate 9 and the recessed surface of the monitor opening filling structure 30. In one embodiment, the characteristic of the recessed surface of the monitor opening filling structure 30 includes a change in the ellipticity of the recessed surface of the monitor opening filling structure 30, which depends on the vertical distance between the substrate and the recessed surface of the monitor opening filling structure 30. The ellipticity of the two-dimensional closed shape refers to the ellipticity of the ellipse that provides the minimum root mean square error during fitting of the two-dimensional closed shape with the ellipse.

[0151] Generally speaking, FIG. 4A to FIG. 4E The shape of the monitor opening 29 formed at the processing step of FIG. 4A to FIG. 4EThe monitor opening 29 and the monitor opening filling structure 30 may have the same shape as the memory opening 49 formed at the processing step of the monitor opening 29. Therefore, the horizontal cross-sectional profile of the monitor opening 29 and the monitor opening filling structure 30 may be statistically the same as the horizontal cross-sectional profile of the memory opening 49 filled with the memory opening filling structure 58. Therefore, by performing online measurement of the recessed top surface of the monitor opening filling structure, as the height of the second stepped surface changes from one side of the captured image to the other side of the captured image, an image that is the same as the image of the horizontal profile of different levels of the monitor opening filling structure 30 is generated. An optical measurement tool or a scanning electron microscope may be used to perform image capture. An image of the physically exposed recessed top surface of the monitor opening filling structure 30 may be measured below the monitor via cavity 185. Multiple images of the monitor opening filling structure 30 are measured when the focus of the image measurement tool changes from the top surface of the substrate (9, 10) to the top surface of the insulating cap layer 70, and vice versa.

[0152] refer to Fig.21A and Fig. 21B , sacrificial fill material may be deposited in the contact via cavity 85 and the monitoring via cavity 185. The sacrificial fill material may include an optional insulating liner such as a silicon oxide liner and a fill material such as a carbon-based fill material (such as amorphous carbon or diamond-like carbon), a semiconductor fill material (such as amorphous silicon or silicon germanium alloy), an organic silicate glass fill material, or a polymer fill material. Excess portions of the sacrificial fill material may be removed from above a level including the top surface of the insulating cap layer 70. Each remaining portion of the sacrificial fill material filling the contact via cavity 85 constitutes a sacrificial contact via filling structure 83. Each remaining portion of the sacrificial fill material filling the monitoring via cavity 185 constitutes a monitoring via cavity filling structure 183.

[0153] refer to FIG. 22A to FIG. 22C , you can execute reference FIG. 13A to FIG. 13C The processing steps are described to form the contact level dielectric layer 80 and the backside trenches 79 .

[0154] refer to Fig.23 , you can execute reference Fig.14 The processing steps are described to form the backside trenches 43 .

[0155] refer to Fig.24 , you can execute reference Fig.15 The processing steps are described to form a conductive layer 46 in the backside trenches 43 .

[0156] refer to Fig.25 , you can execute reference Fig.16 The processing steps are described to form insulating spacers 74 and backside contact structures 76 in each backside trench 79 .

[0157] Reference Fig.26Aand Fig.26B , an opening through the contact level dielectric layer 80 may be formed above each sacrificial contact via cavity filling structure 83. Alternatively, the contact level dielectric layer 80 is removed and a new contact level dielectric layer 80 is re-formed before forming the opening. Subsequently, at least a portion of the sacrificial contact via cavity filling structure 83 may be selectively removed relative to the alternating stack of insulating layers 32 and conductive layers 46. For example, if an insulating liner is present in the sacrificial contact via cavity filling structure 83, the filling material (e.g., carbon or amorphous silicon filling material) may be selectively removed relative to the insulating liner. The insulating liner is then anisotropically etched using a sidewall spacer etching process to form an insulating via spacer 82 at the periphery of each cavity in the cavity (85, 185). A drain contact via cavity may be formed through the contact level dielectric layer 80 above the drain region 63. Additional via cavities may be formed as needed.

[0158] At least one conductive material, such as at least one metallic material, may be deposited within the volume of the cavity (85, 185) laterally surrounded by the insulating via spacers 82, in the drain contact via cavity, and in any additional via cavities to form various contact via structures. A layer contact via structure 86 may be formed within each volume laterally surrounded by the insulating via spacers 82. A drain contact via structure 88 may be formed within each drain contact via cavity. Additional contact via structures (not shown) may be formed as desired.

[0159] refer to Fig.26C , shows the monitoring region 400 of an alternative embodiment of the second exemplary structure after forming various contact via structures (88, 86). In an alternative embodiment of the first exemplary structure, the sacrificial material layer 42 is not replaced by the conductive layer 46 in the monitoring region 400. For example, this modification can be provided by not forming the backside trench 79 in or around the monitoring region 400.

[0160] refer to Figures 1 to 26CA device structure is provided, which includes a three-dimensional memory array and a monitor structure located on a substrate (9, 10). The three-dimensional memory array includes: a first alternating stack (32, 46) of insulating layers 32 and conductive layers 46, the first alternating stack including a contact area 300; a memory opening 49, which vertically extends through the first alternating stack (32, 46) and is located in a memory array area 100 and is arranged in a first two-dimensional array with a two-dimensional periodicity; a memory opening filling structure 58, which is located in the memory opening 49 and includes a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory elements (e.g., a portion of a memory film 50); and a contact via structure 86, which contacts the top surface of the corresponding conductive layer of the conductive layer 46. The monitor structure includes: a second alternating stack (32, 42 or 46) of first material layers and second material layers; a monitor opening 29, which extends vertically through a corresponding subset of the layers within the second alternating stack (32, 42 or 46) and extends to at least an upper portion of the substrate, wherein a horizontal cross-sectional profile of the monitor opening 29 at the level of the bottommost layer of the second alternating stack (32, 42 or 46) has a periodicity that is the same as the two-dimensional periodicity of the memory opening 49; and a monitor opening filling structure 30, which is located in the monitor opening 29.

[0161] In a first embodiment, the three-dimensional memory array further includes: a first stepped surface located in a contact region of a first alternating stack; a first backward stepped dielectric material portion 65 overlying the first stepped surface, wherein a contact via structure 86 extends vertically through the first backward stepped dielectric material portion 65; and a second stepped surface in a second alternating stack; and a second backward stepped dielectric material portion 165 overlying the second stepped surface, wherein the second backward stepped dielectric material portion 165 does not have any conductive structure embedded therein and does not include any openings therethrough.

[0162] In a second embodiment, the three-dimensional memory array further includes: insulating via spacers 82 extending vertically through a corresponding subset of layers within the first alternating stack (32, 46) and contacting a top surface of a corresponding one of the conductive layers 46 in the contact region 300, wherein the contact via structure 86 is laterally surrounded by a corresponding one of the insulating via spacers 82. The monitor structure further includes a monitor via cavity filling structure 183 extending vertically from a horizontal plane including the topmost surface of the second alternating stack (32, 42, or 46) to a top surface of a corresponding subset of the monitor opening filling structures 30 and including a monitor cavity filling material different from the materials of the second alternating stack (32, 42, or 46) and the monitor opening filling structure 30.

[0163] In one embodiment, the device structure further includes a support pillar structure 20 extending vertically through the first alternating stack (32, 46) in the contact region 300 and comprising a dielectric fill material, wherein the monitor opening fill structure 30 consists essentially of the dielectric fill material. In one embodiment, the memory opening fill structure 58 and the monitor opening fill structure 30 have the same diameter, and the support pillar structure 20 has a larger diameter than the memory opening fill structure and the monitor opening fill structure. In one embodiment, the three-dimensional memory array is located in the memory die and the monitor structure is located in the kerf region.

[0164] Various embodiments of the present disclosure may provide in-situ monitoring of the horizontal cross-sectional shape of a memory opening 49 or a memory opening filling structure 58 without requiring destructive analysis of the device. Thus, embodiments of the present disclosure provide for rapid and cost-effective monitoring of the shape of a memory opening 49 and / or a memory opening filling structure during fabrication of a three-dimensional memory device.

[0165] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A method for forming a three-dimensional semiconductor device, the method comprising: forming an alternating stack of insulating layers and spacer material layers over the substrate, wherein the spacer material layers are formed as conductive layers or as sacrificial material layers having at least portions located in the memory array region and in the contact region that are subsequently replaced by the conductive layers; forming openings through the alternating stacks, wherein the openings include memory openings formed in the memory array region and monitor openings formed in the monitor region, and wherein the memory openings and the monitor openings are formed as a two-dimensional array having the same two-dimensional periodicity; forming a monitor opening filling structure by depositing a monitor opening filling material in the monitor opening; recessing a first portion of the alternating stack in the contact region and a second portion of the alternating stack in the monitoring region such that a first horizontal surface of the spacer material layer is physically exposed in the contact region and a second horizontal surface of the spacer material layer and a recessed surface of the monitor opening filling structure are physically exposed in the monitoring region; as well as At least one characteristic of the recessed surface of the monitor opening filling structure is determined.

2. The method of claim 1 , wherein the at least one characteristic of the recessed surface of the monitor opening filling structure comprises a variation in an average lateral dimension of the recessed surface of the monitor opening filling structure, the variation depending on a vertical distance between the substrate and the recessed surface of the monitor opening filling structure.

3. The method of claim 1 , wherein the at least one characteristic of the recessed surface of the monitor opening filling structure comprises a change in the ellipticity of the recessed surface of the monitor opening filling structure, the change depending on a vertical distance between the substrate and the recessed surface of the monitor opening filling structure.

4. The method of claim 1, further comprising determining at least one characteristic of the memory opening or a memory opening filling structure based on determining at least one characteristic of the recessed surface of the monitor opening filling structure.

5. The method of claim 1, wherein the step of determining at least one characteristic of the recessed surface of the monitor opening filling structure comprises determining at least one characteristic of the recessed surface of the monitor opening filling structure using a scanning electron microscope or an optical image measurement tool.

6. The method according to claim 1, wherein: said openings through said alternating stack further comprising support openings formed in said contact regions; forming a support post structure by depositing the monitor opening filling material in the support opening while forming the monitor opening filling structure; and The support post structures are recessed in parallel during recessing of the portions of the alternating stacks located in the contact regions.

7. The method according to claim 6, wherein: The monitor opening filling material includes a dielectric filling material; The support post structures are recessed in parallel during recessing of the portions of the alternating stacks located in the contact regions; and Each of the top surfaces of the support post structures is adjacent to and coplanar with a corresponding one of the first horizontal surfaces of the spacer material layer.

8. The method according to claim 6, further comprising: forming a first stepped surface in the contact region such that the first stepped surface includes a first horizontal surface segment of the spacer material layer and first vertical surface segments of the insulating layer and the spacer material layer; as well as A second stepped surface is formed in the monitoring region such that the second stepped surface includes a second horizontal surface section of the spacer material layer and second vertical surface sections of the insulating layer and the spacer material layer.

9. The method according to claim 8, further comprising: forming a first backward stepped dielectric material portion over the first stepped surface; forming a second backward stepped dielectric material portion over the second stepped surface; as well as forming a contact via structure through the first backward stepped dielectric material portion on a top surface of a corresponding one of the conductive layers, Wherein after forming the contact via structure, the second backward stepped dielectric material portion does not include any opening therethrough.

10. The method according to claim 6, wherein: forming a contact via cavity in the contact region by recessing the first portions of the alternating stacks, wherein a bottom surface of the contact via cavity includes the first horizontal surface of the spacer material layer; as well as A monitoring via cavity is formed in the monitoring area by recessing the second portions of the alternating stack, wherein a bottom surface of the monitoring via cavity includes the recessed surface of the monitor opening filling structure.

11. The method according to claim 10, further comprising: forming a patterned hard mask layer over the alternating stack, wherein the patterned hard mask layer includes a first opening in the contact region and a second opening in the monitoring region; A series of mask anisotropic etching processes are performed, wherein each mask anisotropic etching process in the mask anisotropic etching processes uses a different photoresist mask, and the different photoresist masks cover corresponding subsets of the first openings and the second openings and etch corresponding numbers of pairs of insulating layers and sacrificial material layers, and the corresponding numbers are different in the series of mask anisotropic etching processes.

12. The method according to claim 10, wherein: The spacer material layer is formed as a sacrificial material layer; and The method further comprises: forming a sacrificial contact through hole cavity filling structure in the contact through hole cavity and a monitoring through hole cavity filling structure in the monitoring through hole cavity by depositing a sacrificial filling material in the contact through hole cavity and the monitoring through hole cavity; After forming the sacrificial contact via cavity filling structure, replacing at least a portion of the sacrificial material layer in the memory array region and in the contact region with a conductive layer; and After replacing the sacrificial material layer, the sacrificial contact via cavity filling structure is replaced with a contact via structure.

13. The method according to claim 1, further comprising: forming a patterned sacrificial cover layer covering the memory opening but not covering the monitor opening, wherein a portion of the monitor opening fill material is deposited over the patterned sacrificial cover layer; The portion of the monitor opening fill material is recessed from above the patterned sacrificial cover layer, wherein a remaining portion of the monitor opening fill material constitutes the monitor opening fill structure.

14. The method of claim 1, wherein the reservoir opening and the monitor opening have the same diameter and are formed during the same etching step.

15. A device structure comprising a three-dimensional memory array and a monitor structure on a substrate, The three-dimensional memory array comprises: a first alternating stack of insulating and conductive layers, the first alternating stack having contact regions; memory openings extending vertically through the first alternating stacks, located in a memory array region and arranged in a first two-dimensional array having a two-dimensional periodicity; a memory opening filling structure located in the memory opening and comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements; and a contact via structure contacting a top surface of a corresponding one of the conductive layers, And wherein the monitoring structure comprises: a second alternating stack of first material layers and second material layers; a monitor opening extending vertically from the second stepped surface to at least an upper portion of the substrate, wherein a horizontal cross-sectional profile of the monitor opening at a bottommost level of the second alternating stack has the same periodicity as the two-dimensional periodicity of the memory opening; and A monitor opening filling structure is located in the monitor opening.

16. The device structure according to claim 15, further comprising: a first stepped surface, the first stepped surface being located in the contact region of the first alternating stack; a first backward stepped dielectric material portion overlying the first stepped surface, wherein the contact via structure extends vertically through the first backward stepped dielectric material portion; a second stepped surface in the second alternating stack; and A second backward stepped dielectric material portion overlies the second stepped surface, wherein the second backward stepped dielectric material portion does not have any conductive structures embedded therein and does not include any openings therethrough.

17. The device structure according to claim 15, further comprising: an insulating via spacer extending vertically through a respective subset of layers within the first alternating stack and contacting a top surface of a respective one of the conductive layers in the contact region, wherein the contact via structure is laterally surrounded by a respective one of the insulating via spacers; and A monitoring via cavity filling structure extends vertically from a horizontal plane including a topmost surface of the second alternating stack to a top surface of a corresponding subset of the monitor opening filling structures.

18. The device structure of claim 15, further comprising a support post structure extending vertically through the first alternating stack in the contact region and comprising a dielectric fill material, wherein the monitor opening fill structure consists essentially of the dielectric fill material.

19. The device structure according to claim 18, wherein: The reservoir opening filling structure and the monitor opening filling structure have the same diameter; and The support post structure has a larger diameter than the reservoir opening filling structure and the monitor opening filling structure.

20. The device structure of claim 15, wherein the three-dimensional memory array is located in a memory die and the monitor structure is located in a kerf region.

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