Circuit board hole wall stripping risk identification method

Abstract

The invention relates to a circuit board hole wall stripping risk identification method. According to the technical scheme, the method is characterized by comprising the steps that a high-risk condition is preset; marking all plated-through holes needing risk identification on the circuit board to obtain corresponding holes to be identified; obtaining the layer through which the hole ring of each to-be-identified hole passes, and obtaining the layer information corresponding to each to-be-identified hole; calculating the maximum interlayer bonding pad distance of the corresponding to-be-identified hole based on the layer information; according to the high-risk condition and the maximum interlayer bonding pad distance of each to-be-identified hole, judging whether the corresponding to-be-identified hole has a hole wall stripping risk, and if so, giving an alarm; the area with the hole wall stripping risk is identified before machining, so that the inner-layer hole ring is added at the front end in time, and the reliability risk of hole wall stripping of subsequent products is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and more specifically, to a circuit board hole wall peeling risk identification method. Background Art

[0002] In the design of circuit boards, it is inevitable to design some large metalized part holes or some memory bar slots. In a server motherboard, there are basically dozens or even hundreds of such large holes. With the improvement of circuit board precision and capabilities, the level and thickness of products are also increasing. For the above-mentioned large holes, there is a risk of hole wall peeling after the circuit board undergoes reflow soldering. The risk of peeling of the hole walls of these large holes is not only related to the hole size and hole shape, but also to the distance between the inner pads of the hole. Generally speaking, the larger the distance between the inner pads of the hole, the worse the internal connection strength of the hole wall.

[0003] When making circuit boards, the circuit boards need to be reflowed at least twice, which increases the risk of large hole wall peeling. At present, for the above-mentioned large holes, it is usually necessary to identify the inner pads of the large holes during design, identify the high-risk areas in advance, and add non-functional rings to the inner layer positions corresponding to the high-risk areas to pull the hole copper of the hole wall in the inner layer to increase the internal connection strength of the hole wall copper.

[0004] Due to the lack of methods for identifying high-risk areas of large holes in circuit boards, manual identification is usually required. The number of holes in a circuit board ranges from dozens to hundreds, and manual identification is inefficient and has a high error rate. Therefore, how to accurately identify high-risk areas of hole wall peeling in circuit boards has become a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0005] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a method for identifying the risk of hole wall peeling in a circuit board to solve the above technical problems.

[0006] The above technical objectives of the present invention are achieved through the following technical solutions: A circuit board hole wall peeling risk identification method, comprising:

[0007] Set high-risk conditions in advance;

[0008] Mark all the metallized holes on the circuit board that need to be identified for risk, and obtain the corresponding holes to be identified;

[0009] Obtain the layer level that the hole ring of each hole to be identified passes through, and obtain the layer level information corresponding to each hole to be identified;

[0010] Calculate the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information;

[0011] According to the high-risk condition and the maximum inter-layer pad distance of each hole to be identified, it is judged whether there is a risk of hole wall peeling corresponding to the hole to be identified. If yes, an alarm is issued.

[0012] High-risk conditions are related to the pre-collected hole wall peeling data. Usually, the corresponding high-risk conditions are set according to the hole diameter, hole shape, and distance between hole pads of each hole in the hole wall peeling data. After setting the high-risk conditions, it is determined whether the holes on the circuit board need to be identified for risk. Since hole wall peeling usually occurs in metallized holes with a hole diameter greater than a certain size, metallized holes with a hole diameter greater than a certain size are identified as metallized holes that need to be identified for risk, and these metallized holes are marked as holes to be identified.

[0013] Then, the layers that the hole rings of each hole to be identified pass through are identified, and all the layers connected by the hole rings of each hole to be identified are marked to obtain the layer information corresponding to each hole to be identified. Since hole wall peeling only occurs between adjacent layers of hole rings, the distance between adjacent layers that the hole rings in each hole to be identified pass through is calculated based on the layer information corresponding to each hole to be identified, and all the obtained layer distances are compared to obtain the maximum interlayer pad distance. The pre-set high-risk condition is then compared with the maximum interlayer pad distance. If the maximum interlayer pad distance of the hole to be identified meets the high-risk condition, it means that there is a risk of hole wall peeling at the position corresponding to the maximum interlayer pad distance in the hole to be identified.

[0014] Areas with hole wall peeling risks are identified before processing, so that inner hole rings can be added in time at the front end to avoid the reliability risk of hole wall peeling in subsequent products.

[0015] Optionally, marking all metallized holes on the circuit board that need to be risk identified to obtain corresponding holes to be identified includes:

[0016] Get the graphic design information of the circuit board;

[0017] Identifying hole shapes of all metallized holes on the circuit board according to the graphic design information;

[0018] Obtaining the aperture risk range of the corresponding metallized holes according to the hole shapes of the metallized holes;

[0019] Determine whether the aperture of each metallized hole is within the corresponding aperture risk range. If yes, determine that the metallized hole needs to be identified for risk;

[0020] Mark all the metallized holes that need to be identified as holes to be identified.

[0021] The graphic design information of the circuit board contains the hole shape information and aperture information of all metallized holes. Since the reliability risk of hole wall peeling is usually related to the hole shape and aperture of the metallized hole, all the metallized holes in the circuit board are identified through the graphic design information to obtain the hole shape and aperture of each metallized hole. The hole shape of each metallized hole is matched with the high-risk condition to obtain the aperture risk range corresponding to each hole shape. The aperture of each metallized hole is compared with the aperture risk range. If the aperture of the corresponding metallized hole is within the aperture risk range, it means that the metallized hole needs to be identified for risk, so the metallized hole is marked as a hole to be identified.

[0022] Optionally, the step of acquiring the layer through which the hole ring of each hole to be identified passes, and obtaining the layer information corresponding to each hole to be identified, includes:

[0023] Identify the layers that the hole rings of the holes to be identified pass through according to the graphic design information;

[0024] Each hole to be identified is marked according to the layer through which the hole ring of each hole to be identified passes, so as to obtain the layer information of each hole to be identified.

[0025] The graphic design information records the layers that each metallized hole passes through. The layers that each hole to be identified passes through can be determined based on the number or position of each hole to be identified combined with the graphic design information. The layers that each hole to be identified passes through are marked to obtain the layer information of each hole to be identified.

[0026] Optionally, the calculating the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information includes:

[0027] Obtain the stacking design information of the circuit board;

[0028] Calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of the corresponding hole to be identified;

[0029] The distances of all pads in the hole to be identified are compared to obtain the maximum inter-layer pad distance of the hole to be identified.

[0030] The stacking design information of the circuit board includes the materials and thicknesses used between the layers. Therefore, through the stacking design information of the circuit board and the layer information corresponding to the hole to be identified, the pad distances between all the layers passed through in the hole to be identified can be calculated, and all the pad distances of the hole to be identified can be compared to obtain the maximum inter-layer pad distance of the hole to be identified.

[0031] Optionally, the calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of each hole to be identified includes:

[0032] Matching the layer information of each hole to be identified with the stacking design information to obtain the interlayer information of each hole to be identified;

[0033] According to the inter-layer information of each hole to be identified, the layer type between two adjacent layers of each hole to be identified is obtained;

[0034] Obtain the ply thickness of each ply type in the stack design information;

[0035] The pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness.

[0036] According to the stacking design information of the circuit board, the materials and corresponding thickness of each layer in the circuit board are obtained, and the stacking design information is matched according to the layer information of each hole to be identified, so that the materials and corresponding thicknesses stacked between two adjacent layers in each hole to be identified can be determined, and the interlayer information of each hole to be identified can be obtained. Then, according to the interlayer information of each hole to be identified, the types of layers and the corresponding number of layers between two adjacent layers in the corresponding hole to be identified are counted. Combined with the thickness of the layer in the stacking design information, the pad distance between two adjacent layers in the corresponding hole to be identified can be calculated.

[0037] Optionally, the pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness, and the calculation is performed using the following formula:

[0038] L=L pp +L core +L cu ;

[0039] Where, L is the pad distance, L pp L is the total thickness of the prepreg between two adjacent layers; core is the total thickness of the core plate between two adjacent layers, L cu It is the total copper layer thickness between two adjacent layers excluding the associated copper layer.

[0040] Since the types of layers in a circuit board usually include a copper layer, one or more prepregs (PP) between two copper layers, and a copper-clad core board (Core) with copper films on the top and bottom; therefore, when calculating the thickness of two adjacent layers in the identification hole, it is necessary to calculate the total thickness of all prepregs between the two layers, the total thickness of the core board without copper thickness in the copper-clad core board, and the total copper layer thickness excluding the copper layers corresponding to the two layers.

[0041] Optionally, the high-risk conditions include:

[0042] When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within a first preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the first preset distance;

[0043] When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within the second preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the second preset distance;

[0044] The hole shape of the metallized hole is elliptical, and when the hole diameter of the metallized hole is within a third preset range, the maximum interlayer pad distance of the metallized hole is greater than or equal to the third preset distance.

[0045] Since the hole wall peeling of the metallized hole is not only related to the pad distance, but also related to the hole shape and aperture of the metallized hole, generally speaking, different hole shapes result in different maximum pad distances for hole wall peeling, and the larger the aperture, the smaller the maximum pad distance for hole wall peeling. Therefore, it is necessary to use the pre-stated maximum pad distance for hole wall peeling of metallized holes with different hole shapes and apertures as a high-risk condition.

[0046] Optionally, judging whether there is a hole wall peeling risk for the corresponding hole to be identified according to the high-risk condition and the maximum inter-layer pad distance of each hole to be identified includes:

[0047] Matching corresponding high-risk conditions according to the hole shape and hole diameter of the hole to be identified;

[0048] The maximum inter-layer pad distance of the hole to be identified is compared with the corresponding high-risk condition. If the maximum inter-layer pad distance of the hole to be identified meets the corresponding high-risk condition, it is determined that the hole to be identified has a risk of hole wall peeling.

[0049] After obtaining the maximum interlayer pad distance of the hole to be identified, the hole shape and aperture of the hole to be identified are matched with the corresponding high-risk conditions. For example, if the hole to be identified is circular and the aperture is within a first preset range, the maximum interlayer pad distance of the hole to be identified is compared with the first preset distance. If the maximum interlayer pad distance of the hole to be identified is greater than the first preset distance, it means that there is a risk of hole wall peeling in the hole to be identified.

[0050] Optionally, after determining that the hole to be identified has a risk of hole wall peeling, the method further includes:

[0051] Mark the layer corresponding to the maximum inter-layer pad distance of the hole to be identified.

[0052] After determining that there is a risk of hole wall peeling in the hole to be identified, in order to facilitate the subsequent addition of an inner hole ring in the hole to be identified, it is necessary to mark the hole to be identified in the graphic design information and mark the two layers corresponding to the maximum inter-layer pad distance of the hole to be identified.

[0053] Optionally, after marking the layer corresponding to the maximum inter-layer pad distance of the hole to be identified, the method further includes:

[0054] According to the layer corresponding to the maximum inter-layer pad distance of the hole to be identified and the corresponding high-risk condition, a layer recommendation for adding a non-functional ring is output.

[0055] Since the maximum inter-layer pad distance is too large, it is necessary to combine the corresponding high-risk conditions so that after adding the non-functional ring, the distance between the layer corresponding to the non-functional ring and the two layers corresponding to the maximum inter-layer pad distance is not greater than the distance corresponding to the high-risk conditions.

[0056] In summary, the present invention has the following beneficial effects:

[0057] By identifying all the metallized holes in the graphic design information and marking the metallized holes that need to be identified as holes to be identified, the layers passing through the hole rings in each hole to be identified are identified and the distance between adjacent layers is calculated in combination with the stacking design information to obtain the maximum inter-layer pad distance. This is then compared with the preset high-risk conditions to determine whether there is a risk of hole wall peeling for each hole to be identified.

[0058] Areas with hole wall peeling risks are identified before processing, so that inner hole rings can be added in time at the front end to avoid the reliability risk of hole wall peeling in subsequent products. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a flow chart of the method of the present invention;

[0060] Figure 2 This is a schematic diagram of the circuit board hole wall peeling;

[0061] Figure 3 It is a schematic diagram of the stacking structure of the circuit board of the present invention. DETAILED DESCRIPTION

[0062] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings. Several embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0063] In the present invention, unless otherwise expressly specified and limited, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0064] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0065] Embodiment 1

[0066] This embodiment provides a circuit board hole wall peeling risk identification method, such as Figure 1-3 As shown, including: pre-setting high-risk conditions;

[0067] Mark all the metallized holes on the circuit board that need to be identified for risk, and obtain the corresponding holes to be identified;

[0068] Obtain the layer level that the hole ring of each hole to be identified passes through, and obtain the layer level information corresponding to each hole to be identified;

[0069] Calculate the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information;

[0070] According to the high-risk condition and the maximum inter-layer pad distance of each hole to be identified, it is judged whether there is a risk of hole wall peeling corresponding to the hole to be identified. If yes, an alarm is issued.

[0071] High-risk conditions are related to the pre-collected hole wall peeling data. Usually, the corresponding high-risk conditions are set according to the hole diameter, hole shape, and distance between hole pads of each hole in the hole wall peeling data. After setting the high-risk conditions, it is determined whether the holes on the circuit board need to be identified for risk. Since hole wall peeling usually occurs in metallized holes with a hole diameter greater than a certain size, metallized holes with a hole diameter greater than a certain size are identified as metallized holes that need to be identified for risk, and these metallized holes are marked as holes to be identified.

[0072] Then, the layers that the hole rings of each hole to be identified pass through are identified, and all the layers connected by the hole rings of each hole to be identified are marked to obtain the layer information corresponding to each hole to be identified. Since hole wall peeling only occurs between adjacent layers of hole rings, the distance between adjacent layers that the hole rings in each hole to be identified pass through is calculated based on the layer information corresponding to each hole to be identified, and all the obtained layer distances are compared to obtain the maximum interlayer pad distance. The pre-set high-risk condition is then compared with the maximum interlayer pad distance. If the maximum interlayer pad distance of the hole to be identified meets the high-risk condition, it means that there is a risk of hole wall peeling at the position corresponding to the maximum interlayer pad distance in the hole to be identified.

[0073] Areas with hole wall peeling risks are identified before processing, so that inner hole rings can be added in time at the front end to avoid the reliability risk of hole wall peeling in subsequent products.

[0074] Optionally, marking all metallized holes on the circuit board that need to be risk identified to obtain corresponding holes to be identified includes:

[0075] Get the graphic design information of the circuit board;

[0076] Identifying hole shapes of all metallized holes on the circuit board according to the graphic design information;

[0077] Obtaining the aperture risk range of the corresponding metallized holes according to the hole shapes of the metallized holes;

[0078] Determine whether the aperture of each metallized hole is within the corresponding aperture risk range. If yes, determine that the metallized hole needs to be identified for risk;

[0079] Mark all the metallized holes that need to be identified as holes to be identified.

[0080] The graphic design information of the circuit board contains the hole shape information and aperture information of all metallized holes. Since the reliability risk of hole wall peeling is usually related to the hole shape and aperture of the metallized hole, all the metallized holes in the circuit board are identified through the graphic design information to obtain the hole shape and aperture of each metallized hole. The hole shape of each metallized hole is matched with the high-risk condition to obtain the aperture risk range corresponding to each hole shape. The aperture of each metallized hole is compared with the aperture risk range. If the aperture of the corresponding metallized hole is within the aperture risk range, it means that the metallized hole needs to be identified for risk, so the metallized hole is marked as a hole to be identified.

[0081] Optionally, the step of acquiring the layer through which the hole ring of each hole to be identified passes, and obtaining the layer information corresponding to each hole to be identified, includes:

[0082] Identify the layers that the hole rings of the holes to be identified pass through according to the graphic design information;

[0083] Each hole to be identified is marked according to the layer through which the hole ring of each hole to be identified passes, so as to obtain the layer information of each hole to be identified.

[0084] The graphic design information records the layers that each metallized hole passes through. The layers that each hole to be identified passes through can be determined based on the number or position of each hole to be identified combined with the graphic design information. The layers that each hole to be identified passes through are marked to obtain the layer information of each hole to be identified.

[0085] For example, there are four metallized holes in the aperture risk range in the graphic design information. These four metallized holes are named hole 1, hole 2, hole 3 and hole 4 respectively. Then hole 1, hole 2, hole 3 and hole 4 are holes to be identified. In the graphic design information, the layers that hole 1, hole 2, hole 3 and hole 4 pass through are identified, and the following table is obtained:

[0086]

[0087]

[0088] Optionally, the calculating the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information includes:

[0089] Obtain the stacking design information of the circuit board;

[0090] Calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of the corresponding hole to be identified;

[0091] The distances of all pads in the hole to be identified are compared to obtain the maximum inter-layer pad distance of the hole to be identified.

[0092] The stacking design information of the circuit board includes the materials and thicknesses used between the layers. Therefore, through the stacking design information of the circuit board and the layer information corresponding to the hole to be identified, the pad distances between all the layers passed through in the hole to be identified can be calculated, and all the pad distances of the hole to be identified can be compared to obtain the maximum inter-layer pad distance of the hole to be identified.

[0093] Optionally, the calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of each hole to be identified includes:

[0094] Matching the layer information of each hole to be identified with the stacking design information to obtain the interlayer information of each hole to be identified;

[0095] According to the inter-layer information of each hole to be identified, the layer type between two adjacent layers of each hole to be identified is obtained;

[0096] Obtain the ply thickness of each ply type in the stack design information;

[0097] The pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness.

[0098] According to the stacking design information of the circuit board, the materials and corresponding thickness of each layer in the circuit board are obtained, and the stacking design information is matched according to the layer information of each hole to be identified, so that the materials and corresponding thicknesses stacked between two adjacent layers in each hole to be identified can be determined, and the interlayer information of each hole to be identified can be obtained. Then, according to the interlayer information of each hole to be identified, the types of layers and the corresponding number of layers between two adjacent layers in the corresponding hole to be identified are counted. Combined with the thickness of the layer in the stacking design information, the pad distance between two adjacent layers in the corresponding hole to be identified can be calculated.

[0099] Optionally, the pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness, and the calculation is performed using the following formula:

[0100] L=L pp +L core +L cu ;

[0101] Where, L is the pad distance, L pp L is the total thickness of the prepreg between two adjacent layers; core is the total thickness of the core plate between two adjacent layers, L cu It is the total copper layer thickness between two adjacent layers excluding the associated copper layer.

[0102] Since the types of layers in a circuit board usually include a copper layer, one or more prepregs (PP) between two copper layers, and a copper-clad core board (Core) with copper films on the top and bottom; therefore, when calculating the thickness of two adjacent layers in the identification hole, it is necessary to calculate the total thickness of all prepregs between the two layers, the total thickness of the core board without copper thickness in the copper-clad core board, and the total copper layer thickness excluding the copper layers corresponding to the two layers.

[0103] Specifically, based on the above table and stacked structure design information, it can be obtained that, taking hole 1 as an example, L 1-5 =L pp +L core +L cu , where L pp =2.932+5.492=8.424mil; L core =4×2=8mil; L cu =1.2×3=3.6mil, so L 1-5 =8.796+8+3.6=20.024mil; Similarly, we can calculate L 5-10 =51.464mil, L 10-14 = 20.024mil, so the maximum inter-layer pad distance in hole 1 is L 5-10 =51.464mil.

[0104] Optionally, the high-risk conditions include:

[0105] When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within a first preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the first preset distance;

[0106] When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within the second preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the second preset distance;

[0107] The hole shape of the metallized hole is elliptical, and when the hole diameter of the metallized hole is within a third preset range, the maximum interlayer pad distance of the metallized hole is greater than or equal to the third preset distance.

[0108] Since the hole wall peeling of the metallized hole is not only related to the pad distance, but also related to the hole shape and aperture of the metallized hole, generally speaking, different hole shapes result in different maximum pad distances for hole wall peeling, and the larger the aperture, the smaller the maximum pad distance for hole wall peeling. Therefore, it is necessary to use the pre-stated maximum pad distance for hole wall peeling of metallized holes with different hole shapes and apertures as a high-risk condition.

[0109] Generally speaking, for a circular metallized hole, when its aperture X satisfies 2mm≤X≤3mm, the first preset distance is 1.27mm; when its aperture X satisfies X≥3mm, the second preset distance is 0.75mm; for an elliptical metallized hole, when its aperture X satisfies X≥3mm, the third preset distance is 0.6mm.

[0110] Optionally, judging whether there is a hole wall peeling risk for the corresponding hole to be identified according to the high-risk condition and the maximum inter-layer pad distance of each hole to be identified includes:

[0111] Matching corresponding high-risk conditions according to the hole shape and hole diameter of the hole to be identified;

[0112] The maximum inter-layer pad distance of the hole to be identified is compared with the corresponding high-risk condition. If the maximum inter-layer pad distance of the hole to be identified meets the corresponding high-risk condition, it is determined that the hole to be identified has a risk of hole wall peeling.

[0113] After obtaining the maximum interlayer pad distance of the hole to be identified, the hole shape and aperture of the hole to be identified are matched with the corresponding high-risk conditions. For example, if the hole to be identified is circular and the aperture is within a first preset range, the maximum interlayer pad distance of the hole to be identified is compared with the first preset distance. If the maximum interlayer pad distance of the hole to be identified is greater than the first preset distance, it means that there is a risk of hole wall peeling in the hole to be identified.

[0114] This embodiment identifies all the metallized holes in the graphic design information, and marks the metallized holes that need to be identified as holes to be identified. The layers passing through the hole rings in each hole to be identified are identified and the distances between adjacent layers are calculated in combination with the stacking design information to obtain the maximum inter-layer pad distance, which is then compared with the preset high-risk conditions to determine whether there is a risk of hole wall peeling in each hole to be identified.

[0115] Areas with hole wall peeling risks are identified before processing, so that inner hole rings can be added in time at the front end to avoid the reliability risk of hole wall peeling in subsequent products.

[0116] Embodiment 2

[0117] This embodiment provides a circuit board hole wall peeling risk identification method, such as Figure 1-3 As shown, including: pre-setting high-risk conditions;

[0118] Mark all the metallized holes on the circuit board that need to be identified for risk, and obtain the corresponding holes to be identified;

[0119] Obtain the layer level that the hole ring of each hole to be identified passes through, and obtain the layer level information corresponding to each hole to be identified;

[0120] Calculate the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information;

[0121] According to the high-risk condition and the maximum inter-layer pad distance of each hole to be identified, it is judged whether there is a risk of hole wall peeling corresponding to the hole to be identified. If yes, an alarm is issued.

[0122] High-risk conditions are related to the pre-collected hole wall peeling data. Usually, the corresponding high-risk conditions are set according to the hole diameter, hole shape, and distance between hole pads of each hole in the hole wall peeling data. After setting the high-risk conditions, it is determined whether the holes on the circuit board need to be identified for risk. Since hole wall peeling usually occurs in metallized holes with a hole diameter greater than a certain size, metallized holes with a hole diameter greater than a certain size are identified as metallized holes that need to be identified for risk, and these metallized holes are marked as holes to be identified.

[0123] Then, the layers that the hole rings of each hole to be identified pass through are identified, and all the layers connected by the hole rings of each hole to be identified are marked to obtain the layer information corresponding to each hole to be identified. Since hole wall peeling only occurs between adjacent layers of hole rings, the distance between adjacent layers that the hole rings in each hole to be identified pass through is calculated based on the layer information corresponding to each hole to be identified, and all the obtained layer distances are compared to obtain the maximum interlayer pad distance. The pre-set high-risk condition is then compared with the maximum interlayer pad distance. If the maximum interlayer pad distance of the hole to be identified meets the high-risk condition, it means that there is a risk of hole wall peeling at the position corresponding to the maximum interlayer pad distance in the hole to be identified.

[0124] Areas with hole wall peeling risks are identified before processing, so that inner hole rings can be added in time at the front end to avoid the reliability risk of hole wall peeling in subsequent products.

[0125] Optionally, marking all metallized holes on the circuit board that need to be risk identified to obtain corresponding holes to be identified includes:

[0126] Get the graphic design information of the circuit board;

[0127] Identifying hole shapes of all metallized holes on the circuit board according to the graphic design information;

[0128] Obtaining the aperture risk range of the corresponding metallized holes according to the hole shapes of the metallized holes;

[0129] Determine whether the aperture of each metallized hole is within the corresponding aperture risk range. If yes, determine that the metallized hole needs to be identified for risk;

[0130] Mark all the metallized holes that need to be identified as holes to be identified.

[0131] The graphic design information of the circuit board contains the hole shape information and aperture information of all metallized holes. Since the reliability risk of hole wall peeling is usually related to the hole shape and aperture of the metallized hole, all the metallized holes in the circuit board are identified through the graphic design information to obtain the hole shape and aperture of each metallized hole. The hole shape of each metallized hole is matched with the high-risk condition to obtain the aperture risk range corresponding to each hole shape. The aperture of each metallized hole is compared with the aperture risk range. If the aperture of the corresponding metallized hole is within the aperture risk range, it means that the metallized hole needs to be identified for risk, so the metallized hole is marked as a hole to be identified.

[0132] Optionally, the step of acquiring the layer through which the hole ring of each hole to be identified passes, and obtaining the layer information corresponding to each hole to be identified, includes:

[0133] Identify the layers that the hole rings of the holes to be identified pass through according to the graphic design information;

[0134] Each hole to be identified is marked according to the layer through which the hole ring of each hole to be identified passes, so as to obtain the layer information of each hole to be identified.

[0135] The graphic design information records the layers that each metallized hole passes through. The layers that each hole to be identified passes through can be determined based on the number or position of each hole to be identified combined with the graphic design information. The layers that each hole to be identified passes through are marked to obtain the layer information of each hole to be identified.

[0136] For example, there are four metallized holes in the aperture risk range in the graphic design information. These four metallized holes are named hole 1, hole 2, hole 3 and hole 4 respectively. Then hole 1, hole 2, hole 3 and hole 4 are holes to be identified. In the graphic design information, the layers that hole 1, hole 2, hole 3 and hole 4 pass through are identified, and the following table is obtained:

[0137] Hole number Kong Yi Kong Er Kong San Kong Si Through the layers 1 1 1 1 5 3 3 5 10 5 5 10 14 10 7 14 12 8 14 10 12 14

[0138] Optionally, the calculating the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information includes:

[0139] Obtain the stacking design information of the circuit board;

[0140] Calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of the corresponding hole to be identified;

[0141] The distances of all pads in the hole to be identified are compared to obtain the maximum inter-layer pad distance of the hole to be identified.

[0142] The stacking design information of the circuit board includes the materials and thicknesses used between the layers. Therefore, through the stacking design information of the circuit board and the layer information corresponding to the hole to be identified, the pad distances between all the layers passed through in the hole to be identified can be calculated, and all the pad distances of the hole to be identified can be compared to obtain the maximum inter-layer pad distance of the hole to be identified.

[0143] Optionally, the calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of each hole to be identified includes:

[0144] Matching the layer information of each hole to be identified with the stacking design information to obtain the interlayer information of each hole to be identified;

[0145] According to the inter-layer information of each hole to be identified, the layer type between two adjacent layers of each hole to be identified is obtained;

[0146] Obtain the ply thickness of each ply type in the stack design information;

[0147] The pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness.

[0148] According to the stacking design information of the circuit board, the materials and corresponding thickness of each layer in the circuit board are obtained, and the stacking design information is matched according to the layer information of each hole to be identified, so that the materials and corresponding thicknesses stacked between two adjacent layers in each hole to be identified can be determined, and the interlayer information of each hole to be identified can be obtained. Then, according to the interlayer information of each hole to be identified, the types of layers and the corresponding number of layers between two adjacent layers in the corresponding hole to be identified are counted. Combined with the thickness of the layer in the stacking design information, the pad distance between two adjacent layers in the corresponding hole to be identified can be calculated.

[0149] Optionally, the pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness, and the calculation is performed using the following formula:

[0150] L=L pp +L core +L cu;

[0151] Where, L is the pad distance, L pp L is the total thickness of the prepreg between two adjacent layers; core is the total thickness of the core plate between two adjacent layers, L cu It is the total copper layer thickness between two adjacent layers excluding the associated copper layer.

[0152] Since the types of layers in a circuit board usually include a copper layer, one or more prepregs (PP) between two copper layers, and a copper-clad core board (Core) with copper films on the top and bottom; therefore, when calculating the thickness of two adjacent layers in the identification hole, it is necessary to calculate the total thickness of all prepregs between the two layers, the total thickness of the core board without copper thickness in the copper-clad core board, and the total copper layer thickness excluding the copper layers corresponding to the two layers.

[0153] Specifically, based on the above table and stacked structure design information, it can be obtained that, taking hole 1 as an example, L 1-5 =L pp +L core +L cu , where L pp =2.932+5.492=8.424mil; L core =4×2=8mil; L cu =1.2×3=3.6mil, so L 1-5 =8.796+8+3.6=20.024mil; Similarly, we can calculate L 5-10 =51.464mil, L 10-14 = 20.024mil, so the maximum inter-layer pad distance in hole 1 is L 5-10 =51.464mil.

[0154] Optionally, the high-risk conditions include:

[0155] When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within a first preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the first preset distance;

[0156] When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within the second preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the second preset distance;

[0157] The hole shape of the metallized hole is elliptical, and when the hole diameter of the metallized hole is within a third preset range, the maximum interlayer pad distance of the metallized hole is greater than or equal to the third preset distance.

[0158] Since the hole wall peeling of the metallized hole is not only related to the pad distance, but also related to the hole shape and aperture of the metallized hole, generally speaking, different hole shapes result in different maximum pad distances for hole wall peeling, and the larger the aperture, the smaller the maximum pad distance for hole wall peeling. Therefore, it is necessary to use the pre-stated maximum pad distance for hole wall peeling of metallized holes with different hole shapes and apertures as a high-risk condition.

[0159] Generally speaking, for a circular metallized hole, when its aperture X satisfies 2mm≤X≤3mm, the first preset distance is 1.27mm; when its aperture X satisfies X≥3mm, the second preset distance is 0.75mm; for an elliptical metallized hole, when its aperture X satisfies X≥3mm, the third preset distance is 0.6mm.

[0160] Optionally, judging whether there is a hole wall peeling risk for the corresponding hole to be identified according to the high-risk condition and the maximum inter-layer pad distance of each hole to be identified includes:

[0161] Matching corresponding high-risk conditions according to the hole shape and hole diameter of the hole to be identified;

[0162] The maximum inter-layer pad distance of the hole to be identified is compared with the corresponding high-risk condition. If the maximum inter-layer pad distance of the hole to be identified meets the corresponding high-risk condition, it is determined that the hole to be identified has a risk of hole wall peeling.

[0163] After obtaining the maximum interlayer pad distance of the hole to be identified, the hole shape and aperture of the hole to be identified are matched with the corresponding high-risk conditions. For example, if the hole to be identified is circular and the aperture is within a first preset range, the maximum interlayer pad distance of the hole to be identified is compared with the first preset distance. If the maximum interlayer pad distance of the hole to be identified is greater than the first preset distance, it means that there is a risk of hole wall peeling in the hole to be identified.

[0164] Optionally, after determining that the hole to be identified has a risk of hole wall peeling, the method further includes:

[0165] Mark the layer corresponding to the maximum inter-layer pad distance of the hole to be identified.

[0166] After determining that there is a risk of hole wall peeling in the hole to be identified, in order to facilitate the subsequent addition of an inner hole ring in the hole to be identified, it is necessary to mark the hole to be identified in the graphic design information and mark the two layers corresponding to the maximum inter-layer pad distance of the hole to be identified.

[0167] Taking hole 1 as an example, since the maximum inter-layer pad distance in hole 1 is L 5-10 =51.464mil, which is greater than the first preset distance of 1.27mm, so L5 and L in hole 1 are 10Mark it out so that it is convenient to add an inner hole ring in the hole to be identified later.

[0168] Optionally, after marking the layer corresponding to the maximum inter-layer pad distance of the hole to be identified, the method further includes:

[0169] According to the layer corresponding to the maximum inter-layer pad distance of the hole to be identified and the corresponding high-risk condition, a layer recommendation for adding a non-functional ring is output.

[0170] Since the maximum inter-layer pad distance is too large, it is necessary to combine the corresponding high-risk conditions so that after adding the non-functional ring, the distance between the layer corresponding to the non-functional ring and the two layers corresponding to the maximum inter-layer pad distance is not greater than the distance corresponding to the high-risk conditions.

[0171] Taking hole 1 as an example, since the maximum inter-layer pad distance in hole 1 is L 5-10 =51.464mil, which is greater than the first preset distance of 1.27mm, and L 5-9 =45.316mil, which is smaller than the first preset distance of 1.27mm, but still relatively large. It is recommended to add a non-functional ring at L7 or L8.

[0172] This embodiment marks the layer corresponding to the maximum inter-layer pad distance of the hole to be identified with the risk of hole wall peeling, and proposes a layer suggestion for adding a non-functional ring. It can more accurately identify the specific location of the high-risk metallized hole, and facilitate the timely addition of inner hole rings at the front end to avoid the reliability risk of hole wall peeling caused by subsequent products.

[0173] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A circuit board hole wall peeling risk identification method, characterized in that: include: Set high-risk conditions in advance; Mark all the metallized holes on the circuit board that need to be identified for risk, and obtain the corresponding holes to be identified; Obtain the layer level that the hole ring of each hole to be identified passes through, and obtain the layer level information corresponding to each hole to be identified; Calculate the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information; According to the high-risk condition and the maximum inter-layer pad distance of each hole to be identified, it is judged whether there is a risk of hole wall peeling corresponding to the hole to be identified. If yes, an alarm is issued.

2. A circuit board hole wall peeling risk identification method according to claim 1, characterized in that: The marking of all metallized holes on the circuit board that need to be risk identified to obtain corresponding holes to be identified includes: Get the graphic design information of the circuit board; Identifying hole shapes of all metallized holes on the circuit board according to the graphic design information; Obtaining the aperture risk range of the corresponding metallized holes according to the hole shapes of the metallized holes; Determine whether the aperture of each metallized hole is within the corresponding aperture risk range. If yes, determine that the metallized hole needs to be identified for risk; Mark all the metallized holes that need to be identified as holes to be identified.

3. A circuit board hole wall peeling risk identification method according to claim 1, characterized in that: The step of obtaining the layer level that the hole ring of each hole to be identified passes through, and obtaining the layer level information corresponding to each hole to be identified, includes: Identify the layers that the hole rings of the holes to be identified pass through according to the graphic design information; Each hole to be identified is marked according to the layer through which the hole ring of each hole to be identified passes, so as to obtain the layer information of each hole to be identified.

4. A circuit board hole wall peeling risk identification method according to claim 1, characterized in that: The calculating the maximum inter-layer pad distance corresponding to the hole to be identified based on the layer information includes: Obtain the stacking design information of the circuit board; Calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of the corresponding hole to be identified; The distances of all pads in the hole to be identified are compared to obtain the maximum inter-layer pad distance of the hole to be identified.

5. A circuit board hole wall peeling risk identification method according to claim 4, characterized in that: The calculating the pad distance between two adjacent layers in the corresponding hole to be identified according to the stacking design information and the layer information of each hole to be identified includes: Matching the layer information of each hole to be identified with the stacking design information to obtain the interlayer information of each hole to be identified; According to the inter-layer information of each hole to be identified, the layer type between two adjacent layers of each hole to be identified is obtained; Obtain the ply thickness of each ply type in the stack design information; The pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness.

6. A circuit board hole wall peeling risk identification method according to claim 5, characterized in that: The pad distance between two adjacent layers in the corresponding hole to be identified is calculated according to the layer type and layer thickness, and the calculation is performed using the following formula: L=L pp +L core +L cu ; Where, L is the pad distance, L pp L is the total thickness of the prepreg between two adjacent layers; core is the total thickness of the core plate between two adjacent layers, L cu It is the total copper layer thickness between two adjacent layers excluding the associated copper layer.

7. A circuit board hole wall peeling risk identification method according to claim 1, characterized in that: High-risk conditions include: When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within a first preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the first preset distance; When the hole shape of the metallized hole is circular and the hole diameter of the metallized hole is within the second preset range, the maximum inter-layer pad distance of the metallized hole is greater than or equal to the second preset distance; The hole shape of the metallized hole is elliptical, and when the hole diameter of the metallized hole is within a third preset range, the maximum interlayer pad distance of the metallized hole is greater than or equal to the third preset distance.

8. A circuit board hole wall peeling risk identification method according to claim 1, characterized in that: The determining whether there is a hole wall peeling risk for the corresponding hole to be identified based on the high risk condition and the maximum inter-layer pad distance of each hole to be identified includes: Matching corresponding high-risk conditions according to the hole shape and hole diameter of the hole to be identified; The maximum inter-layer pad distance of the hole to be identified is compared with the corresponding high-risk condition. If the maximum inter-layer pad distance of the hole to be identified meets the corresponding high-risk condition, it is determined that the hole to be identified has a risk of hole wall peeling.

9. A circuit board hole wall peeling risk identification method according to claim 1, characterized in that: After determining that the hole to be identified has a risk of hole wall peeling, the method further includes: Mark the layer corresponding to the maximum inter-layer pad distance of the hole to be identified.

10. A circuit board hole wall peeling risk identification method according to claim 9, characterized in that: After marking the layer corresponding to the maximum inter-layer pad distance of the hole to be identified, it also includes: According to the layer corresponding to the maximum inter-layer pad distance of the hole to be identified and the corresponding high-risk condition, a layer recommendation for adding a non-functional ring is output.

Images