A digital intelligent bus fault analysis method and system

Abstract

The present invention relates to a digital intelligent bus fault analysis method and system, and relates to the field of electrical fault detection, comprising: obtaining a power node output voltage, a power node output current, a load node control parameter, a line voltage monitoring value, and a line current monitoring value of a first bus circuit, inputting a circuit state prediction model, and obtaining a line standard current prediction value and a line standard voltage prediction value; constructing a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value; constructing a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value; analyzing the line voltage deviation vector matrix and the line current deviation vector matrix through a bus fault probability prediction model to obtain a bus fault probability prediction value; when the bus fault probability prediction value is greater than or equal to a bus fault probability threshold, generating a bus fault early warning signal and sending it to a user end.

Description

Technical Field

[0001] The present invention relates to the field of electrical fault detection, and in particular to a digital intelligent bus fault analysis method and system. Background Art

[0002] As a vital component of the power system, the state of the busbar directly affects the stability of the entire power grid. Busbar faults, especially those under high load and complex load conditions, are often difficult to detect and handle in the early stages, which may cause large-scale power outages in the power grid and have a significant impact on social production and daily life. Traditional busbar faults are usually monitored directly, but direct monitoring can only achieve relatively obvious abnormal monitoring and cannot achieve subtle deviation fluctuation analysis. There are technical problems such as insufficient fault detection accuracy, weak real-time response capabilities, and impact on refined management. Summary of the invention

[0003] The present invention aims to solve the technical problems in the prior art such as insufficient fault detection accuracy, weak real-time response capability and influence on refined management, and provides a digital intelligent bus fault analysis method and system to solve the problems.

[0004] The technical solution of the present invention to solve the above technical problems is as follows:

[0005] In a first aspect, the present invention provides a digital intelligent bus fault analysis method.

[0006] Obtaining a power node output voltage, a power node output current, a load node control parameter, a line voltage monitoring value, and a line current monitoring value of a first bus circuit;

[0007] Input the power node output voltage, the power node output current, and the load node control parameter into a circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value;

[0008] Constructing a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value;

[0009] Constructing a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value;

[0010] By using a bus fault probability prediction model, the line voltage deviation vector matrix and the line current deviation vector matrix are analyzed to obtain a bus fault probability prediction value;

[0011] When the bus fault probability prediction value is greater than or equal to the bus fault probability threshold, a bus fault warning signal is generated and sent to the user end.

[0012] In a second aspect, the present invention provides a digital intelligent bus fault analysis system.

[0013] A circuit state monitoring module, used to obtain a power node output voltage, a power node output current, a load node control parameter, a line voltage monitoring value, and a line current monitoring value of the first bus circuit;

[0014] A circuit state prediction module, used for inputting the power node output voltage, the power node output current, and the load node control parameter into a circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value;

[0015] A voltage deviation vector construction module, used to construct a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value;

[0016] A current deviation vector construction module, used to construct a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value;

[0017] A bus fault probability prediction module, used to analyze the line voltage deviation vector matrix and the line current deviation vector matrix through a bus fault probability prediction model to obtain a bus fault probability prediction value;

[0018] The fault warning generation module is used to generate a bus fault warning signal and send it to the user end when the bus fault probability prediction value is greater than or equal to the bus fault probability threshold.

[0019] The beneficial effects of the present invention are as follows: by obtaining the power node output voltage, power node output current, load node control parameters, line voltage monitoring value and line current monitoring value of the first bus circuit, inputting the circuit state prediction model, obtaining the line standard current prediction value and the line standard voltage prediction value; constructing the line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value; constructing the line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value; analyzing the line voltage deviation vector matrix and the line current deviation vector matrix through the bus fault probability prediction model to obtain the bus fault probability prediction value; when the bus fault probability prediction value is greater than or equal to the bus fault probability threshold, generating a bus fault warning signal and sending it to the user end, thereby achieving the technical effect of improving fault detection accuracy and response capability and facilitating refined management. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a digital intelligent bus fault analysis method provided by the present invention;

[0021] Figure 2A structural schematic diagram of a digital intelligent bus fault analysis system provided by the present invention;

[0022] Figure 3 A schematic diagram of the structure of an electronic device provided by the present invention;

[0023] Figure 4 A schematic diagram of the structure of a computer-readable storage medium provided by the present invention.

[0024] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0025] Circuit state monitoring module 11, circuit state prediction module 12, voltage deviation vector construction module 13, current deviation vector construction module 14, bus fault probability prediction module 15, fault warning generation module 16, electronic device 500, memory 510, processor 520, computer program 511, computer readable storage medium 600. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0028] In the description of the present invention, the term "for example" is used to mean "used as an example, illustration or explanation". Any embodiment described as "for example" in the present invention is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is given to enable any technician in the field to implement and use the present invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present invention can be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in the present invention.

[0029] Embodiment 1: Figure 1 As shown, an embodiment of the present invention provides a digital intelligent bus fault analysis method.

[0030] Obtaining a power node output voltage, a power node output current, a load node control parameter, a line voltage monitoring value, and a line current monitoring value of a first bus circuit;

[0031] Specifically, first, the following key electrical parameters are collected from the first bus circuit: power node output voltage, that is, the output voltage value of the power supply end of the bus circuit, which is used to reflect the power supply stability of the power supply end; power node output current, that is, the output current value of the power supply end of the bus circuit, which is used to evaluate the load condition of the power supply end; load node control parameters, which are used to reflect the operating status and control strategy of the bus load end, such as load power factor, load power demand, etc.; line voltage monitoring value, which refers to the real-time voltage value on each line of the bus, which is used to monitor voltage distribution and its changes; line current monitoring value, which refers to the real-time current value on each line of the bus, which is used to monitor current distribution and its changes.

[0032] By collecting bus circuit parameters including power node output voltage, power node output current, load node control parameters, line voltage monitoring values ​​and line current monitoring values, the state of the target bus circuit can be accurately and intuitively reflected, providing an accurate data basis for subsequent analysis.

[0033] Input the power node output voltage, the power node output current, and the load node control parameter into a circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value;

[0034] Specifically, the collected electrical parameters are input into the circuit state prediction model to calculate the standard operating state of the bus, which involves the standard current prediction value and the standard voltage prediction value of the bus line. The standard current prediction value of the line refers to the standard current value of the bus line under ideal conditions calculated based on the circuit state prediction model, combined with the output voltage and current of the power node and the control parameters of the load node; similarly, the standard voltage prediction value of the line is the standard voltage value of the bus line under ideal conditions calculated by the prediction model.

[0035] Optionally, the circuit state prediction model is trained and optimized based on the physical circuit model, load characteristics and historical operation data through a machine learning algorithm or a numerical simulation method. The training process enables the circuit state prediction model to learn the mapping relationship between the power node output voltage, the power node output current, the load node control parameters, the line voltage monitoring value and the line current monitoring value and the line standard state (i.e., the line standard current prediction value and the line standard voltage prediction value), thereby ensuring that the predicted value can accurately reflect the normal operating state of the bus.

[0036] Constructing a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value;

[0037] Specifically, by comparing the real-time monitoring values ​​with the standard prediction values, a deviation vector matrix is ​​constructed, which is used to quantify the abnormality of the busbar operation status. Among them, the line voltage deviation vector matrix is ​​obtained by calculating the line voltage monitoring values ​​and the line standard voltage prediction values ​​at multiple points in the line and performing structured processing.

[0038] Optionally, the line voltage deviation vector matrix includes deviation information of multiple points of multiple lines, corresponding to elements at different positions in the line voltage deviation vector matrix.

[0039] By constructing a line voltage deviation vector matrix, the voltage anomaly degree of each bus line can be quantified in real time, providing data support for fault analysis and prediction, and laying the foundation for subsequent fault probability assessment and early warning signal generation.

[0040] Constructing a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value;

[0041] Specifically, the same method and principle as the above-mentioned construction of the line voltage deviation vector matrix is ​​adopted to calculate multiple deviations between the line current monitoring values ​​and the line standard current prediction values ​​at multiple points in the line, and the multiple deviations are converted into a matrix form according to a predefined matrix structure to generate a line current deviation vector matrix.

[0042] By using a bus fault probability prediction model, the line voltage deviation vector matrix and the line current deviation vector matrix are analyzed to obtain a bus fault probability prediction value;

[0043] Furthermore, the line voltage deviation vector matrix and the line current deviation vector matrix are used as the analysis input of the bus fault probability prediction model, and the bus fault probability prediction model is activated to perform fault probability prediction to obtain the bus fault probability prediction value. The bus fault probability prediction model is a mapping model constructed based on supervised learning, machine learning or regression analysis model, which is used to map the characteristic vectors in the line voltage deviation vector matrix and the line current deviation vector matrix into the predicted value of the bus fault probability.

[0044] Through the bus fault probability prediction model, it is convenient to establish a direct load mapping relationship between the vector matrix and the fault probability, and efficiently and accurately analyze the voltage and current deviation from the vector matrix, effectively predict the fault risk of the bus, help improve the accuracy and timeliness of fault identification, and provide protection for the safe operation of the power system.

[0045] When the bus fault probability prediction value is greater than or equal to the bus fault probability threshold, a bus fault warning signal is generated and sent to the user end.

[0046] Specifically, the core logic of the bus fault warning mechanism is to determine whether there is a bus fault risk by comparing the bus fault probability prediction value with the set bus fault probability threshold. If the fault risk exceeds the threshold, a warning signal is triggered to remind the user to take corresponding measures. Otherwise, if the condition is not met, the bus is considered to be operating normally and no warning signal needs to be generated.

[0047] Specifically, the fault probability threshold is a critical value for measuring the risk of bus failure. The fault probability threshold can be set based on various factors such as system operation requirements, historical data analysis, and user needs. For example, for a bus with higher importance, the threshold can be set lower (e.g., P 阈值 =0.7), so that an early warning is triggered when the risk of failure is small; for buses with lower importance, the threshold can be set higher (such as P 阈值 =0.9) to reduce false alarms; at the same time, users can adjust the threshold according to their own needs to balance the sensitivity and accuracy of the warning.

[0048] In some embodiments, the step of constructing the circuit state prediction model includes:

[0049] Obtain an equivalent circuit diagram of the first bus circuit; construct a graph neural network topology based on the equivalent circuit diagram, wherein the graph neural network topology is the same as the topological structure of the equivalent circuit diagram, the input nodes of the graph neural network topology are power nodes and load nodes, and the output nodes are line nodes; using the equivalent circuit diagram as a background constraint, collect the same circuit health sample data, wherein the same circuit health sample data includes power node output voltage recording data, power node output current recording data, load node control parameter recording data, line node monitoring voltage identification data, and line node monitoring current identification data; use the line node monitoring voltage identification data and the line node monitoring current identification data as the output supervision data of the line node, use the power node output voltage recording data and the power node output current recording data as the input data of the power node, use the load node control parameter recording data as the input data of the load node, train the graph neural network topology, and generate a circuit state prediction model and store it in association with the first bus circuit.

[0050] Specifically, firstly, an equivalent circuit diagram of the first bus circuit is obtained. The equivalent circuit diagram is the basis of the circuit state prediction model and is used to simplify and abstract the actual physical structure of the bus circuit while retaining key electrical characteristics. Exemplarily, firstly, the actual topology of the bus circuit is analyzed to determine the positions and connection relationships of the power nodes, load nodes and line nodes, and the electrical parameters of each line (such as resistance, inductance, capacitance, etc.); then, an equivalent circuit diagram is drawn manually using electrical engineering tools (such as MATLAB, PSCAD, etc.) or manually. The equivalent circuit diagram includes the topological structure and parameters of the power supply, load and line.

[0051] Specifically, the topological structure of the equivalent circuit diagram is mapped into the graph neural network (GNN), that is, the power nodes, load nodes and line nodes in the equivalent circuit diagram are mapped to the nodes of the GNN, and the connection relationship (edge) between the nodes is defined to be consistent with the topology of the equivalent circuit diagram, so that the GNN can learn the state characteristics of the circuit.

[0052] Optionally, the node types of GNN include: power node (input: output voltage and current data of the power node; output: passing its state vector to the connected line node), load node (input: control parameters of the load node, such as load power, load impedance, etc.; output: passing its state vector to the connected line node), line node (input: state vectors from the power node and the load node; output: predicting the voltage and current state of the line).

[0053] Specifically, background constraints mean that all collected data must be consistent with the topological structure and parameters of the equivalent circuit diagram, ensuring that the collected data can accurately reflect the health status of the circuit. Background constraints based on the equivalent circuit diagram can ensure the pertinence and accuracy of data collection, avoid collecting data that is not related to circuit operation, and improve the validity of the data.

[0054] Specifically, healthy sample data refers to electrical parameter data collected when the circuit is in normal operation (no faults, no abnormalities), which is used to train the model so that it can learn the normal operating characteristics of the circuit. Among them, healthy sample data is collected through sensor equipment, distributed control systems (DCS), supervisory control and data acquisition systems (SCADA), etc.; by collecting healthy sample data, high-quality training data can be provided for the model, so that the model can accurately learn the normal operating characteristics of the circuit, laying the foundation for fault prediction and diagnosis.

[0055] Furthermore, data input and supervised learning objectives are defined, wherein the input data is defined to include: the power supply node uses the output voltage recording data and the output current recording data of the power supply node as input features; the load node uses the control parameter recording data (such as load power, load impedance, etc.) of the load node as input features; the line node uses the state vector from the power supply node and the load node as the input feature of the line node; at the same time, the monitoring voltage identification data and the monitoring current identification data of the line node are used as the target output of supervised learning.

[0056] Specifically, according to the defined data input and supervised learning objectives, the collected healthy sample data are divided into training set, validation set and test set, and mapped to the corresponding GNN nodes. The voltage and current states of the line nodes are predicted through the propagation calculation of the graph neural network. The model parameters are optimized according to the loss function and the gradient descent algorithm (such as Adam, SGD), and the prediction accuracy is gradually improved. The supervised training of the graph neural network (GNN) is performed so that it can predict the voltage and current states of the line nodes based on the input data (data of the power node and the load node). Finally, the model performance is evaluated on the validation set, the hyperparameters (such as learning rate, hidden layer size, etc.) are adjusted, and the generalization ability of the model is verified on the test set. The trained model is obtained for real-time monitoring of the circuit status, rapid detection of anomalies, and providing guarantee for the safe operation of the power system.

[0057] In some implementations, the equivalent circuit diagram is used as a background constraint to collect the same circuit health sample data, wherein the same circuit health sample data includes power node output voltage record data, power node output current record data, load node control parameter record data, line node monitoring voltage identification data and line node monitoring current identification data, including:

[0058] Taking the equivalent circuit diagram as the background constraint, collect the same circuit health sample data, wherein the same circuit health sample data includes power node output voltage record data, power node output current record data, load node control parameter record data, line node monitoring voltage record data and line node monitoring current record data; taking the equivalent circuit diagram, the power node output voltage record data, the power node output current record data and the load node control parameter record data as the background constraint, collect the line node monitoring voltage increment record data and the line node monitoring current increment record data; perform central trend fitting on the line node monitoring voltage increment record data and the line node monitoring voltage record data to obtain the line node monitoring voltage identification data; perform central trend fitting on the line node monitoring current increment record data and the line node monitoring current identification data to obtain the line node monitoring current identification data.

[0059] Specifically, the equivalent circuit diagram is used as the background constraint to ensure that the node topology and electrical parameters of the equivalent circuit diagram are strictly followed when collecting data, ensure the integrity and consistency of the collected data, provide high-quality basic data for subsequent model training, and enable the model to accurately learn the normal operating characteristics of the circuit.

[0060] Specifically, the line node monitoring voltage incremental recording data and current incremental recording data are collected. The incremental recording data refers to the data of the line node voltage and current within the neighborhood time range, which is used to reflect the dynamic characteristics of the line. When collecting incremental data, the equivalent circuit diagram, power node data (voltage, current), and load node control parameters are required as background constraints to ensure that the collection range and characteristics of the incremental data are consistent with the actual operating status of the circuit. The incremental recording data provides dynamic characteristic information of the line nodes, which provides basic data for subsequent centralized trend fitting and identification data generation.

[0061] Specifically, central tendency fitting refers to statistical or mathematical processing of a set of data (such as incremental data and original record data) to extract the central tendency characteristics of the data. Optional central tendency fitting methods include mean fitting, weighted average fitting, least squares fitting, etc., where the central tendency is a characteristic that reflects the overall trend in the data distribution, such as the mean, weighted average, etc. Through central tendency fitting, the noise and random fluctuations in the data can be effectively removed, and stable identification data can be generated to provide high-quality input for subsequent circuit state prediction.

[0062] In the above steps, by collecting healthy sample data and incremental record data, the static and dynamic operating characteristics of the circuit are fully covered, so that the system can capture the dynamic change characteristics of the line nodes, and enhance the real-time monitoring and fault prediction capabilities of the circuit operation status; through central trend fitting, the generated monitoring voltage identification data and monitoring current identification data can accurately reflect the electrical state of the line nodes, remove noise and random fluctuations, and thus provide high-quality input for the subsequent training of the circuit state prediction model, which helps to improve the prediction accuracy and robustness of the model.

[0063] In some embodiments, the bus failure probability prediction model building step includes:

[0064] The equivalent circuit diagram of the first bus circuit is used as a background constraint, and a line voltage deviation vector record matrix and a line current deviation vector record matrix are configured; fault samples are collected according to the line voltage deviation vector record matrix and the line current deviation vector record matrix to obtain fault sample data; the ratio of the number of bus fault samples to the total number of samples in the fault sample data is counted and set as bus fault probability identification data; the bus fault probability identification data is used as supervision data, and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as input data to train the bus fault probability prediction model.

[0065] Specifically, according to the equivalent circuit diagram of the first bus circuit, a line voltage deviation vector recording matrix and a line current deviation vector recording matrix are defined, wherein the line voltage deviation vector recording matrix defines and records the voltage deviation of the bus and surrounding circuits, and the line current deviation vector recording matrix records the deviation data of the current in the line, which can reveal abnormal conditions such as bus current overload or short circuit.

[0066] Specifically, the above-mentioned voltage deviation vector recording matrix and current deviation vector recording matrix are used to collect fault samples based on historical data to obtain relevant electrical data when the bus fails. That is, each time a fault occurs, the specific values ​​of the voltage and current deviations and the identification of whether the bus corresponding to these data has a fault are recorded, and they are marked as fault data.

[0067] Specifically, statistical analysis is performed on the fault sample data to calculate the ratio of the number of bus fault samples to the total number of samples. This ratio represents the probability of a fault, that is, the frequency of bus faults in each set of data, and can be used as the target data of the fault prediction model (bus fault probability identification data). For example, if 15 samples out of 100 samples have bus faults, the bus fault probability identification data is 15 / 100=0.15.

[0068] Furthermore, a machine learning model is trained to predict the bus fault probability using the bus fault probability identification data as supervision data, wherein the input data of the model includes the line voltage deviation vector record matrix and the line current deviation vector record matrix, which are the characteristic data of the model; and the output is the bus fault probability identification data, which is the predicted bus fault probability.

[0069] Specifically, the busbar fault probability prediction model is supervised and trained based on the same method as mentioned above, including dividing the sample data into a training set and a validation set, selecting an appropriate loss function (such as mean square error), adjusting hyperparameters (such as learning rate, regularization coefficient, etc.), evaluating the model through indicators such as precision, recall rate, and F1 value, and determining that the model that meets the requirements is the busbar fault probability prediction model.

[0070] In some implementations, the bus fault probability identification data is used as supervision data, and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as input data to train the bus fault probability prediction model, including:

[0071] The bus fault probability identification data is used as the supervision data, and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as the input data to construct a bus fault probability prediction model construction data set; the bus fault probability prediction model construction data set is divided into k equal parts to obtain k groups of bus fault probability prediction model construction data; the k groups of bus fault probability prediction model construction data are sampled with replacement k times to obtain a first bus fault probability prediction model construction data set, a decision tree is trained, and a first bus fault probability prediction model is generated; until the k groups of bus fault probability prediction model construction data are sampled with replacement k times to obtain an N-th bus fault probability prediction model construction data set, a decision tree is trained, and an N-th bus fault probability prediction model is generated; based on the bus fault probability prediction model construction data set, the first bus fault probability prediction model to the N-th bus fault probability prediction model are combined and trained to obtain the bus fault probability prediction model.

[0072] Specifically, first, the bus fault probability identification data is used as the supervision data (i.e., the target variable), and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as the input data (i.e., the feature variables) to construct a bus fault probability prediction model to construct a data set; then, the constructed data set is divided into k equal parts, each of which is used as an independent subset corresponding to a part of the data used for training and validating the model.

[0073] Specifically, k groups of bus fault probability prediction model construction data are sampled k times with replacement, that is, the data are resampled to generate different training subsets. Exemplarily, this process can be completed by bootstrap. Each sampling randomly selects a group of data samples from the k groups of bus fault probability prediction model construction data, and the same data sample is allowed to be repeatedly selected, and the output is the first bus fault probability prediction model construction data set.

[0074] Furthermore, the above sampling operation is repeated until N first bus fault probability prediction models are obtained to construct data sets, and the decision tree models are trained with the obtained N data sets respectively to learn the relationship between voltage and current deviation data and bus fault probability, obtain N bus fault probability prediction models, and then merge the obtained k decision tree models for training, and finally obtain the bus fault probability prediction model.

[0075] Optionally, the Bagging method in ensemble learning is used to integrate the output results of N trained decision tree models to obtain the final fault probability prediction value. After the above-mentioned combined training, the final bus fault probability prediction model is obtained. The fault probability prediction is performed based on the integrated results of multiple decision tree models, which can more accurately predict the bus fault probability.

[0076] In some implementations, constructing a data set based on the bus failure probability prediction model and merging and training the first bus failure probability prediction model to the Nth bus failure probability prediction model to obtain the bus failure probability prediction model includes:

[0077] Construct the merged training objective function: in, Characterizes the output value of the busbar fault probability prediction model, until Characterize the outputs of the first busbar fault probability prediction model to the Nth busbar fault probability prediction model, until represents the merge weight, Characterize the merge function;

[0078] Construct the combined loss function:

[0079] in, Represents the output loss under a certain set of combined weights, Characterize supervision loss;

[0080] Based on the combined training objective function and the combined loss function, a weight parameter whose output is less than or equal to the combined loss threshold for a preset number of consecutive times is selected, and combined training is performed on the first bus fault probability prediction model to the Nth bus fault probability prediction model to obtain the bus fault probability prediction model.

[0081] Specifically, the merged training objective function is used to describe how the output values ​​of multiple bus fault probability prediction models are merged in a weighted manner to form the final bus fault probability prediction model output value y, wherein the merging function can be a linear weighted merging or a nonlinear merging (such as Sigmoid, ReLU, etc.).

[0082] Specifically, the combined loss function is used to evaluate the output value y of the combined training objective function and the supervision target value In the expression of the loss function, by taking the logarithm of the error, we can avoid numerical explosion when the error is too large, and emphasize the optimization of small errors. In other words, when the error is small, the logarithmic function can amplify the impact of the error and improve the optimization ability of the model in the small error range; when the error is large, the logarithmic function can reduce the impact of the error and avoid unstable training caused by excessive gradients.

[0083] Specifically, if the current loss value is less than or equal to the loss threshold, the count is +1; if the count value is greater than the preset number of times, the training is stopped and the final weight parameters are output; if the count value does not meet the conditions, it returns to iterative training.

[0084] Through the above-mentioned combined training method, an efficient, stable and accurate bus fault probability prediction model can be constructed, providing important technical support for the safe operation and intelligent management of the power system.

[0085] In some embodiments, the method further includes: when the bus fault probability prediction value is less than the bus fault probability threshold, returning to the process to start executing a loop.

[0086] Specifically, when the predicted value is less than the preset bus failure probability threshold, it indicates that the bus is in a relatively safe state. At this time, no further fault warning or intervention measures are required. The system can return to the initial process and continue to monitor the bus operation status, thereby achieving continuous optimization and real-time monitoring. Through this cycle mechanism, unnecessary resource consumption can be avoided, while ensuring that the system can continue to operate when the risk of failure is low, and update data and models in real time.

[0087] A digital intelligent bus fault analysis method provided by an embodiment of the present invention has at least the following technical effects:

[0088] By obtaining the power node output voltage, power node output current, load node control parameters, line voltage monitoring value and line current monitoring value of the first bus circuit, the circuit state prediction model is input to obtain the line standard current prediction value and the line standard voltage prediction value; according to the line voltage monitoring value and the line standard voltage prediction value, a line voltage deviation vector matrix is ​​constructed; according to the line current monitoring value and the line standard current prediction value, a line current deviation vector matrix is ​​constructed; through the bus fault probability prediction model, the line voltage deviation vector matrix and the line current deviation vector matrix are analyzed to obtain the bus fault probability prediction value; when the bus fault probability prediction value is greater than or equal to the bus fault probability threshold, a bus fault early warning signal is generated and sent to the user end, thereby achieving the technical effect of improving the accuracy and response capability of fault detection and facilitating refined management.

[0089] Embodiment 2: Figure 2As shown, based on the same inventive concept as the digital intelligent bus fault analysis method provided in Example 1, the embodiment of the present invention also provides a digital intelligent bus fault analysis system.

[0090] The circuit state monitoring module 11 is used to obtain the power node output voltage, power node output current, load node control parameters, line voltage monitoring value and line current monitoring value of the first bus circuit.

[0091] The circuit state prediction module 12 is used to input the power node output voltage, the power node output current, and the load node control parameter into the circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value.

[0092] The voltage deviation vector construction module 13 is used to construct a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value.

[0093] The current deviation vector construction module 14 is used to construct a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value.

[0094] The bus fault probability prediction module 15 is used to analyze the line voltage deviation vector matrix and the line current deviation vector matrix through a bus fault probability prediction model to obtain a bus fault probability prediction value.

[0095] The fault warning generation module 16 is used to generate a bus fault warning signal and send it to the user end when the bus fault probability prediction value is greater than or equal to the bus fault probability threshold.

[0096] In some embodiments, the execution steps of the circuit state prediction module 12 include:

[0097] An equivalent circuit diagram of the first bus circuit is obtained.

[0098] Based on the equivalent circuit diagram, a graph neural network topology is constructed, wherein the graph neural network topology is the same as the topological structure of the equivalent circuit diagram, the input nodes of the graph neural network topology are power nodes and load nodes, and the output nodes are line nodes.

[0099] Taking the equivalent circuit diagram as the background constraint, the same circuit health sample data is collected, wherein the same circuit health sample data includes power node output voltage recording data, power node output current recording data, load node control parameter recording data, line node monitoring voltage identification data and line node monitoring current identification data.

[0100] The line node monitoring voltage identification data and the line node monitoring current identification data are used as the output supervision data of the line node, the power node output voltage recording data and the power node output current recording data are used as the input data of the power node, and the load node control parameter recording data is used as the input data of the load node, the graph neural network topology is trained, and a circuit state prediction model is generated and stored in association with the first bus circuit.

[0101] In some embodiments, the execution steps of the circuit state prediction module 12 further include:

[0102] Taking the equivalent circuit diagram as the background constraint, the same circuit health sample data is collected, wherein the same circuit health sample data includes power node output voltage recording data, power node output current recording data, load node control parameter recording data, line node monitoring voltage recording data and line node monitoring current recording data.

[0103] With the equivalent circuit diagram, the power node output voltage recording data, the power node output current recording data, and the load node control parameter recording data as background constraints, line node monitoring voltage increment recording data and line node monitoring current increment recording data are collected.

[0104] Central trend fitting is performed on the line node monitoring voltage increment record data and the line node monitoring voltage record data to obtain the line node monitoring voltage identification data.

[0105] Central trend fitting is performed on the line node monitoring current increment record data and the line node monitoring current identification data to obtain the line node monitoring current identification data.

[0106] In some embodiments, the execution steps of the bus fault probability prediction module 15 include:

[0107] The equivalent circuit diagram of the first bus circuit is used as a background constraint, and a line voltage deviation vector recording matrix and a line current deviation vector recording matrix are configured.

[0108] Fault sample collection is performed according to the line voltage deviation vector record matrix and the line current deviation vector record matrix to obtain fault sample data.

[0109] The ratio of the number of bus fault samples to the total number of samples in the fault sample data is counted and set as bus fault probability identification data.

[0110] The bus fault probability identification data is used as supervision data, and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as input data to train the bus fault probability prediction model.

[0111] In some embodiments, the execution steps of the bus fault probability prediction module 15 further include:

[0112] The bus fault probability identification data is used as supervision data, and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as input data to construct a bus fault probability prediction model and a data set.

[0113] The bus fault probability prediction model construction data set is divided into k equal parts to obtain k groups of bus fault probability prediction model construction data.

[0114] The k groups of bus failure probability prediction model construction data are sampled k times with replacement to obtain a first bus failure probability prediction model construction data set, train a decision tree, and generate a first bus failure probability prediction model.

[0115] Until the k groups of bus failure probability prediction model construction data are sampled with replacement k times, the N-th bus failure probability prediction model construction data set is obtained, the decision tree is trained, and the N-th bus failure probability prediction model is generated.

[0116] Based on the bus fault probability prediction model, a data set is constructed to merge and train the first bus fault probability prediction model to the Nth bus fault probability prediction model to obtain the bus fault probability prediction model.

[0117] In some implementations, the execution steps of the bus fault probability prediction module 15 further include:

[0118] Construct the merged training objective function:

[0119] in, Characterizes the output value of the busbar fault probability prediction model, until Characterize the outputs of the first busbar fault probability prediction model to the Nth busbar fault probability prediction model, until represents the merge weight, Characterize the merge function;

[0120] Construct the combined loss function:

[0121] in, Represents the output loss under a certain set of combined weights, Characterizing the supervision loss.

[0122] Based on the combined training objective function and the combined loss function, a weight parameter whose output is less than or equal to the combined loss threshold for a preset number of consecutive times is selected, and combined training is performed on the first bus fault probability prediction model to the Nth bus fault probability prediction model to obtain the bus fault probability prediction model.

[0123] In some embodiments, the execution steps of the system further include:

[0124] When the bus fault probability prediction value is less than the bus fault probability threshold, the process returns to the beginning of the execution loop.

[0125] Example 3: Please refer to Figure 3 , Figure 3 Schematic diagram of an electronic device provided by an embodiment of the present invention. Figure 3 As shown, an embodiment of the present invention provides an electronic device 500, including a memory 510, a processor 520 and a computer program 511 stored in the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 511, the following steps are implemented: obtaining the power node output voltage, power node output current, load node control parameters, line voltage monitoring value and line current monitoring value of the first bus circuit; inputting the power node output voltage, the power node output current and the load node control parameters into a circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value; constructing a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value; constructing a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value; analyzing the line voltage deviation vector matrix and the line current deviation vector matrix through a bus fault probability prediction model to obtain a bus fault probability prediction value; when the bus fault probability prediction value is greater than or equal to a bus fault probability threshold, generating a bus fault warning signal and sending it to the user end.

[0126] Example 4: Please refer to Figure 4 , Figure 4 A schematic diagram of an embodiment of a computer-readable storage medium provided in an embodiment of the present invention. Figure 4As shown, this embodiment provides a computer-readable storage medium 600, on which a computer program 511 is stored. When the computer program 511 is executed by a processor, the following steps are implemented: obtaining the power node output voltage, power node output current, load node control parameters, line voltage monitoring value and line current monitoring value of the first bus circuit; inputting the power node output voltage, the power node output current and the load node control parameters into a circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value; constructing a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value; constructing a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value; analyzing the line voltage deviation vector matrix and the line current deviation vector matrix through a bus fault probability prediction model to obtain a bus fault probability prediction value; when the bus fault probability prediction value is greater than or equal to a bus fault probability threshold, generating a bus fault warning signal and sending it to the user end.

[0127] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0128] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0129] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0130] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0131] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0132] Although preferred embodiments of the present invention have been described, additional changes and modifications may occur to these embodiments once those skilled in the art understand the basic inventive concepts.

[0133] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention belong to the scope of the present invention and its equivalent technologies, the present invention is also intended to include these changes and variations.

Claims

1. A digital intelligent bus fault analysis method, characterized in that: include: Obtaining a power node output voltage, a power node output current, a load node control parameter, a line voltage monitoring value, and a line current monitoring value of a first bus circuit; Input the power node output voltage, the power node output current, and the load node control parameter into a circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value; Constructing a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value; Constructing a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value; By using a bus fault probability prediction model, the line voltage deviation vector matrix and the line current deviation vector matrix are analyzed to obtain a bus fault probability prediction value; When the bus fault probability prediction value is greater than or equal to the bus fault probability threshold, a bus fault warning signal is generated and sent to the user end; The steps of constructing the circuit state prediction model include: Obtaining an equivalent circuit diagram of the first bus circuit; Based on the equivalent circuit diagram, construct a graph neural network topology, wherein the graph neural network topology is the same as the topological structure of the equivalent circuit diagram, the input nodes of the graph neural network topology are power nodes and load nodes, and the output nodes are line nodes; Taking the equivalent circuit diagram as a background constraint, collecting the same circuit health sample data, wherein the same circuit health sample data includes power node output voltage record data, power node output current record data, load node control parameter record data, line node monitoring voltage identification data and line node monitoring current identification data; The line node monitoring voltage identification data and the line node monitoring current identification data are used as the output supervision data of the line node, the power node output voltage recording data and the power node output current recording data are used as the input data of the power node, and the load node control parameter recording data is used as the input data of the load node, the graph neural network topology is trained, and a circuit state prediction model is generated and stored in association with the first bus circuit.

2. The method according to claim 1, characterized in that Taking the equivalent circuit diagram as a background constraint, collect the same circuit health sample data, wherein the same circuit health sample data includes power node output voltage record data, power node output current record data, load node control parameter record data, line node monitoring voltage identification data and line node monitoring current identification data, including: Taking the equivalent circuit diagram as a background constraint, collecting the same circuit health sample data, wherein the same circuit health sample data includes power node output voltage record data, power node output current record data, load node control parameter record data, line node monitoring voltage record data and line node monitoring current record data; Taking the equivalent circuit diagram, the power node output voltage record data, the power node output current record data, and the load node control parameter record data as background constraints, collecting line node monitoring voltage increment record data and line node monitoring current increment record data; Performing central trend fitting on the line node monitoring voltage increment record data and the line node monitoring voltage record data to obtain the line node monitoring voltage identification data; Central trend fitting is performed on the line node monitoring current increment record data and the line node monitoring current identification data to obtain the line node monitoring current identification data.

3. The method according to claim 1, characterized in that The busbar fault probability prediction model construction step includes: Using the equivalent circuit diagram of the first bus circuit as a background constraint, configuring a line voltage deviation vector record matrix and a line current deviation vector record matrix; Fault sample collection is performed according to the line voltage deviation vector record matrix and the line current deviation vector record matrix to obtain fault sample data; Counting the ratio of the number of bus fault samples to the total number of samples in the fault sample data, and setting it as bus fault probability identification data; The bus fault probability identification data is used as supervision data, and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as input data to train the bus fault probability prediction model.

4. The method according to claim 3, characterized in that The bus fault probability identification data is used as supervision data, and the line voltage deviation vector record matrix and the line current deviation vector record matrix are used as input data to train the bus fault probability prediction model, including: Using the bus fault probability identification data as supervision data, and using the line voltage deviation vector record matrix and the line current deviation vector record matrix as input data, a bus fault probability prediction model is constructed to construct a data set; Dividing the bus fault probability prediction model construction data set into k equal parts to obtain k groups of bus fault probability prediction model construction data; Perform k sampling with replacement on the k groups of bus failure probability prediction model construction data to obtain a first bus failure probability prediction model construction data set, train a decision tree, and generate a first bus failure probability prediction model; Until the k groups of bus failure probability prediction model construction data are sampled k times with replacement, an N-th bus failure probability prediction model construction data set is obtained, a decision tree is trained, and an N-th bus failure probability prediction model is generated; Based on the bus fault probability prediction model, a data set is constructed to merge and train the first bus fault probability prediction model to the Nth bus fault probability prediction model to obtain the bus fault probability prediction model.

5. The method according to claim 4, characterized in that Based on the bus fault probability prediction model, a data set is constructed to merge and train the first bus fault probability prediction model to the Nth bus fault probability prediction model to obtain the bus fault probability prediction model, including: Construct the merged training objective function: in, Characterizes the output value of the busbar fault probability prediction model, until Characterize the outputs of the first busbar fault probability prediction model to the Nth busbar fault probability prediction model, until represents the merge weight, Characterize the merge function; Construct the combined loss function: in, Represents the output loss under a certain set of combined weights, Characterize supervision loss; Based on the combined training objective function and the combined loss function, a weight parameter whose output is less than or equal to the combined loss threshold for a preset number of consecutive times is selected, and combined training is performed on the first bus fault probability prediction model to the Nth bus fault probability prediction model to obtain the bus fault probability prediction model.

6. The method according to claim 1, characterized in that Also includes: When the bus fault probability prediction value is less than the bus fault probability threshold, the process returns to the beginning of the execution loop.

7. A digital intelligent bus fault analysis system, characterized in that: The system is used to execute a digital intelligent bus fault analysis method according to any one of claims 1 to 6, and the system comprises: A circuit state monitoring module, used to obtain a power node output voltage, a power node output current, a load node control parameter, a line voltage monitoring value, and a line current monitoring value of the first bus circuit; A circuit state prediction module, used for inputting the power node output voltage, the power node output current, and the load node control parameter into a circuit state prediction model to obtain a line standard current prediction value and a line standard voltage prediction value; A voltage deviation vector construction module, used to construct a line voltage deviation vector matrix according to the line voltage monitoring value and the line standard voltage prediction value; A current deviation vector construction module, used to construct a line current deviation vector matrix according to the line current monitoring value and the line standard current prediction value; A bus fault probability prediction module, used to analyze the line voltage deviation vector matrix and the line current deviation vector matrix through a bus fault probability prediction model to obtain a bus fault probability prediction value; The fault warning generation module is used to generate a bus fault warning signal and send it to the user end when the bus fault probability prediction value is greater than or equal to the bus fault probability threshold.

8. An electronic device, characterized in that: include: Memory for storing computer software programs; A processor is used to read and execute the computer software program, thereby implementing a digital intelligent bus fault analysis method as described in any one of claims 1-7.

9. A non-transitory computer-readable storage medium, characterized in that: The storage medium stores a computer software program, and when the computer software program is executed by the processor, it implements a digital intelligent bus fault analysis method as described in any one of claims 1 to 7.

Images