Voltage regulator
By using diodes and capacitors to replace large resistors in voltage regulators, the current mirror circuit and output circuit are designed, and the problem of excessive circuit area of traditional voltage regulators is solved, and the circuit area saving and chip size reduction is achieved, which improves the product Competitiveness.
Patent Information
- Application Number
- CN202411657277.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-01-07
AI Technical Summary
The large resistors used in traditional voltage regulators lead to an increase in circuit area, affecting the chip size reduction and product competitiveness.
Small-area electronic components such as diodes and capacitors are used to replace large resistors, and current mirror circuits and output circuits are designed to achieve voltage regulation and reduce circuit area.
Effectively save the circuit area of the voltage regulator, improve product competitiveness, and continue to provide the working voltage by storing electricity through capacitors after the chip enters the shutdown state.
Smart Images
Figure CN119270980A_ABST
Abstract
Description
[0001] This application is a divisional application of the invention patent application with application number 202411424836.4. The filing date of the original application is October 12, 2024. Technical Field
[0002] The invention relates to a voltage regulator, in particular to a voltage regulator capable of saving circuit area. Background Art
[0003] See also Figure 1 and Figure 2 They are the block diagram of a traditional chip and its signal waveform diagram. Figure 1 As shown, the chip 100 can also be a level shifter (LVSH) chip, which includes multiple input terminals 11, multiple output terminals 12 and two power supply terminals 13 and 14. One of the input terminals 11 is used to input the STVI signal, which is a periodic pulse signal (PulseSignal). One of the output terminals 12 is used to output the STVO signal. The STVO signal is preset to a low level (Low Level) state. One of the power supply terminals 13 is connected to the first voltage source VIN, and the other power supply terminal 14 is connected to the second voltage source VGH. The first voltage source VIN is a low voltage power supply, and its voltage range is 2.5V to 5V. The second voltage source VGH is a high voltage power supply, and its voltage range is 20V to 45V.
[0004] like Figure 1 and Figure 2 As shown, when the first voltage source VIN and the second voltage source VGH are provided to the chip 100 and the first voltage source VIN and the second voltage source VGH begin to rise, the chip 100 is in the power-on state. When the first voltage source VIN and the second voltage source VGH rise to a high voltage state respectively, the chip 100 begins to detect whether the input STVI signal has a rising edge. If the rising edge of the STVI signal is detected, the chip 100 enters the normal operation mode, and the output STVO signal is in phase with the STVI signal, such as when the STVI signal is H, the STVO signal also follows H; or when the STVI signal is L, the STVO signal also follows L.
[0005] Next, when the first voltage source VIN starts to drop and is lower than the voltage threshold, the chip 100 enters the power-off state (Power Off), and the STVO signal changes to a high level and remains at a high level. Furthermore, before the chip 100 completely stops shutting down, some work is still to be completed, so the logic circuit inside the chip 100 still needs a period of operation time. In order to provide the operating voltage required for this period of operation time, a voltage regulator can be set inside the chip 100. When the chip 100 just enters the power-off state, the second voltage source VGH will still maintain a high voltage state for a period of time. Therefore, the voltage regulator will adjust the second voltage source VGH to generate the operating voltage VCC required for the logic circuit inside the chip 100 to continue to operate.
[0006] See also Figure 3 and Figure 4 They are the block diagram and circuit diagram of the traditional voltage regulator. Figure 3 As shown, the voltage regulator 200 uses the second voltage source VGH as a power supply, and generates an operating voltage VCC through the second voltage source VGH. The operating voltage VCC is usually designed to be 3V or 1.8V.
[0007] Since the potential of the second voltage source VGH is very high and the chip 100 hopes to reduce the power consumption of the second voltage source VGH, a resistor with a relatively large resistance is usually set inside the voltage regulator 200, such as a resistor with a resistance of Mohm (Megaohms) or more.
[0008] Figure 4 As shown, the voltage regulator 200 includes a front-end circuit 30, a current mirror circuit assembly 40 and an output circuit 50. The front-end circuit 30 includes a first transistor M1, a second transistor M2, a third transistor M3 and a resistor R1. The first transistor M1, the second transistor M2 and the third transistor M3 are respectively NMOS transistors and are connected in the form of diodes, such as the gates of the transistors M1, M2 and M3 are connected to the drains. The first transistor M1, the second transistor M2 and the third transistor M3 are connected in series between the resistor R1 and the ground in sequence. One end of the resistor R1 is connected to the first transistor M1, and the other end is connected to the second voltage source VGH. Furthermore, the first transistor M1 and the resistor R1 are connected to a first node 301 formed with a first voltage VA.
[0009] The current mirror circuit assembly 40 includes a first high-voltage transistor HVM1, a second high-voltage transistor HVM2, a third high-voltage transistor HVM3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6. The first high-voltage transistor HVM1 and the second high-voltage transistor HVM2 are PMOS transistors, respectively, and the third high-voltage transistor HVM3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are NMOS transistors, respectively. The first high-voltage transistor HVM1 and the second high-voltage transistor HVM2 form a current mirror. The gate of the third high-voltage transistor M3 is connected to the first node 301, the drain is connected to the drain and the gate of the first high-voltage transistor HVM1 and the gate of the second high-voltage transistor HVM2, and the source is grounded. The fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are NMOS transistors and are connected in the form of diodes, such as the gates of the M4, M5 and M6 transistors are connected to the drain. The fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are connected in series between the drain of the second high-voltage transistor HVM2 and the ground. Furthermore, the fourth transistor M4 and the second high-voltage transistor HVM2 are connected to a second node 401 where a second voltage VB is formed.
[0010] The output circuit 50 is a fourth high-voltage transistor HVM4 , wherein the drain of the fourth high-voltage transistor HVM4 is connected to the second voltage source VGH, the gate is connected to the second node 401 , and the source is grounded.
[0011] When the second voltage source VGH supplies power to the resistor R1 and the first, second, and third transistors M1, M2, and M3, a front-end current I flows between the resistor R1 and the first, second, and third transistors M1, M2, and M3. A , and a first voltage VA is generated on the first node 211. When the first voltage VA is greater than or equal to the VTH of the third high-voltage transistor HVM3, the third high-voltage transistor HVM3 is driven to be turned on, so that a first current I1 is formed on the first high-voltage transistor HVM1 and the third high-voltage transistor HVM3. Through the circuit design of the current mirror, the second high-voltage transistor HVM2 maps the first current I1 on the first high-voltage transistor HVM1, so that the first current I1 flows through the fourth, fifth, and sixth transistors M4, M5, and M6, and a second voltage VB is generated on the second node 231. When the second voltage VB is greater than or equal to the VTH of the fourth high-voltage transistor HVM4, the fourth high-voltage transistor HVM4 forms a second current I2 and generates an operating voltage VCC at its source.
[0012] As mentioned above, the conventional voltage regulator 200 uses a resistor R1 and three transistors M1, M2, and M3 to design the front-end circuit 30. The front-end current flowing through the resistor R1 is I A=(VGH-VGS*3) / R1, where VGS is the voltage between the gate and source of the transistor. Assuming VGS = 1V, VGH = 45V, if you want to set the front-end current to I A If the current is limited to 5uA, the required resistor R1 is (45-1*3) / 5u=8.4Mohm. In a process without HR mask (High Resistance), the resistor R1 with a large resistance value must have a certain area, thereby increasing the circuit area of the voltage regulator 200. Therefore, if the chip 100 adopts the voltage regulator 200 with a larger circuit area, the size of the chip 100 cannot be effectively reduced, thereby reducing the product competitiveness. Summary of the invention
[0013] In the past, voltage regulators used Mohm resistors to design part of the circuit. However, Mohm resistors have a certain area and increase the overall circuit area. Therefore, the purpose of the voltage regulator of the present invention is to replace the Mohm resistors with electronic components with smaller areas such as diodes and / or capacitors while maintaining the original voltage regulation function. By designing the circuit in this way, the circuit area of the voltage regulator can be effectively saved, so as to enhance the competitiveness of the product.
[0014] In order to achieve the above object, the present invention adopts the following technical solutions:
[0015] To achieve the above-mentioned purpose, the present invention provides a voltage regulator, characterized in that it includes: a front-end circuit, including a first diode and a first capacitor, the positive electrode of the first diode is connected to a first voltage source, and the negative electrode and the first capacitor are connected to a first node; a current mirror circuit assembly, including a first high-voltage transistor, a second high-voltage transistor, a third high-voltage transistor and three transistors connected in the form of diodes; the first high-voltage transistor and the second high-voltage transistor form a current mirror, the source of the first high-voltage transistor and the source of the second high-voltage transistor are respectively connected to a second voltage source; the gate of the third high-voltage transistor is connected to the first node, the drain is connected to the drain and gate of the first high-voltage transistor and the gate of the second high-voltage transistor, and the source is grounded; the three transistors connected in the form of diodes are connected in series between the drain of the second high-voltage transistor and the ground in sequence, The output circuit includes a fourth high-voltage transistor, the drain of the fourth high-voltage transistor is connected to the second voltage source, the gate is connected to the second node, and the source is grounded; wherein the first voltage source supplies power to the first node through the first diode, the first capacitor is used to store electrical energy, and the first node forms a first voltage; the third high-voltage transistor is driven to conduct with the first voltage, and a first current flows through the first high-voltage transistor and the third high-voltage transistor; through the design of the current mirror, the second high-voltage transistor reflects the first current on the first high-voltage transistor, so that the first current flows through the three transistors connected in the form of diodes, and a second voltage is generated on the second node; the fourth high-voltage transistor is driven to conduct with the second voltage, and an operating voltage is generated on the source of the fourth high-voltage transistor. Preferably, the voltage regulator is designed in a chip and becomes an internal circuit of the chip, and the voltage regulator is used to adjust the operating voltage required for the operation of the logic circuit inside the chip.
[0016] Preferably, the chip is a level shifter, the first voltage source is a low voltage power source of the chip, and the second voltage source is a high voltage power source of the chip.
[0017] Preferably, when the chip is in the shutdown state, the first voltage source stops supplying power, and the first voltage generated on the first node continues to be maintained at a high potential state for a period of time through the electric energy stored in the first capacitor.
[0018] Preferably, the time length for which the voltage regulator provides the operating voltage after the chip enters the shutdown state is determined by the capacitance value of the first capacitor and the leakage current on the first node.
[0019] In addition, the present invention provides a voltage regulator, characterized in that it includes: a front-end circuit, including a first diode and a second diode, the anode of the first diode is connected to a first voltage source, the anode of the second diode is connected to an operating voltage, and the cathode and the cathode of the first diode are connected to a first node; a current mirror circuit assembly, including a first high-voltage transistor, a second high-voltage transistor, a third high-voltage transistor and three transistors connected in the form of diodes; the first high-voltage transistor and the second high-voltage transistor form a current mirror, the source of the first high-voltage transistor and the source of the second high-voltage transistor are respectively connected to a second voltage source; the gate of the third high-voltage transistor is connected to the first node, the drain is connected to the drain and gate of the first high-voltage transistor and the gate of the second high-voltage transistor, and the source is grounded; the three transistors connected in the form of diodes are connected in series between the drain of the second high-voltage transistor and the ground in sequence, and The drain of the second high-voltage transistor is connected to a second node where a second voltage is formed; and the output circuit includes a fourth high-voltage transistor, the drain of the fourth high-voltage transistor is connected to the second voltage source, the gate is connected to the second node, and the source is grounded and connected to the positive electrode of the second diode; wherein the first voltage source supplies power to the first node through the first diode or the working voltage supplies power to the first node through the second diode, and the first node forms a first voltage; the third high-voltage transistor is driven to conduct with the first voltage, and a first current flows through the first high-voltage transistor and the third high-voltage transistor; through the design of the current mirror, the second high-voltage transistor reflects the first current on the first high-voltage transistor, so that the first current flows through the three transistors connected in the form of diodes and a second voltage is generated at the second node; the fourth high-voltage transistor is driven to conduct with the second voltage, and the working voltage is generated at the source of the fourth high-voltage transistor.
[0020] Preferably, when the chip is in the shutdown state, the first voltage source stops supplying power. If the second voltage source is still maintained in a high voltage state, an operating voltage is generated at the source of the fourth high-voltage transistor. The operating voltage is fed back to the second diode and continues to supply power to the first node through the second diode, thereby generating a first voltage at the first node.
[0021] Due to the adoption of the above scheme, the beneficial effects of the present invention are:
[0022] The voltage regulator of the present invention can maintain the original voltage regulation function while replacing the original Mohm large resistor with electronic components with smaller areas such as diodes and / or capacitors. By designing the circuit in this way, the circuit area of the voltage regulator can be effectively saved, so as to enhance the competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is a block diagram of a traditional chip.
[0024] Figure 2This is the signal waveform diagram of the traditional chip.
[0025] Figure 3 Figure 2 is a block diagram of a conventional voltage regulator.
[0026] Figure 4 A circuit diagram of a conventional voltage regulator.
[0027] Figure 5 FIG. 1 is a block diagram of a chip according to an embodiment of the present invention.
[0028] Figure 6 FIG. 4 is a block diagram of a voltage regulator according to an embodiment of the present invention.
[0029] Figure 7 FIG. 4 is a circuit diagram of a voltage regulator according to an embodiment of the present invention.
[0030] Figure 8 A block diagram of another embodiment of the chip of the present invention.
[0031] Fig. 9 FIG. 4 is a block diagram of another embodiment of a voltage regulator of the present invention.
[0032] Fig.10 FIG. 4 is a circuit diagram of another embodiment of a voltage regulator of the present invention.
[0033] Description of Reference Numerals
[0034] 11: Input terminal
[0035] 12: Output terminal
[0036] 13, 14: Power supply end
[0037] 100: Chip
[0038] 200, 201, 202: Voltage regulator
[0039] 30, 31, 32: Front-end circuit
[0040] 301, 311, 321: first node
[0041] 40: Current mirror circuit assembly
[0042] 401: Second Node
[0043] 50: Output circuit
[0044] VIN: First voltage source
[0045] VGH: Second voltage source
[0046] VCC: Operating voltage DETAILED DESCRIPTION
[0047] In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the present application is further described in detail below in conjunction with drawings and specific implementation methods.
[0048] First, see Figure 5 , Figure 6 and Figure 7 The block diagram of the chip of the present invention and the block diagram and circuit diagram of the voltage regulator of the present invention are respectively Figure 2 .like Figure 5 and Figure 6 As shown, the voltage regulator 201 of this embodiment is designed in the chip 100 and becomes the internal circuit of the chip 100. The chip 100 adjusts the working voltage VCC required for the operation of its internal logic circuit through the voltage regulator 201. The voltage regulator 201 is connected to two voltage sources, one is the first voltage source VIN, and the other is the second voltage source VGH. The first voltage source VIN is a low voltage power source, and the second voltage source VGH is a high voltage power source. Specifically, the voltage regulator 201 of this embodiment adjusts and generates the working voltage VCC through the first voltage source VIN and the second voltage source VGH.
[0049] like Figure 7 As shown, the voltage regulator 201 includes a front-end circuit 31, a current mirror circuit assembly 40 and an output circuit 50. The front-end circuit 31 includes a first diode D1 and a first capacitor C1. The first capacitor C1 can also be a decoupling capacitor. One end (such as the positive end) of the first diode D1 is connected to the first voltage source VIN, and the other end (such as the negative end) and the first capacitor C1 are connected to the first node 311.
[0050] The current mirror circuit assembly 40 includes a first high-voltage transistor HVM1, a second high-voltage transistor HVM2, a third high-voltage transistor HVM3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6. The first high-voltage transistor HVM1 and the second high-voltage transistor HVM2 are PMOS transistors, respectively, while the third high-voltage transistor HVM3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are NMOS transistors, respectively. In the present invention, the high-voltage transistors HVM1, HVM2, HVM3 and HVM4 are all 45V LD (Laterally Diffused) MOS, whose VGS withstand voltage is 5V and VDS withstand voltage is 45V. The first high-voltage transistor HVM1 and the second high-voltage transistor HVM2 form a current mirror, and the sources of the two transistors HVM1 and HVM2 are respectively connected to the second voltage source VGH. The gate of the third high-voltage transistor M3 is connected to the first node 311, the drain is connected to the drain and gate of the first high-voltage transistor HVM1 and the gate of the second high-voltage transistor HVM2, and the source is grounded. The fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are respectively NMOS transistors and are connected in the form of diodes. The fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are connected in series between the drain of the second high-voltage transistor HVM2 and the ground. Furthermore, the fourth transistor M4 and the second high-voltage transistor HVM2 are connected to a second node 401 formed with a second voltage VB. The output circuit 50 is a fourth high-voltage transistor HVM4. The drain of the fourth high-voltage transistor HVM4 is connected to the second voltage source VGH, the gate is connected to the second node 401, and the source is grounded.
[0051] The first voltage source VIN transfers electric energy to the first node 311 through the first diode D1 to store the electric energy in the first capacitor C1, and a first voltage VA is formed on the first node 311. The first voltage VA generated by the energy storage of the first capacitor C1 is designed to be greater than the voltage VOV (overdrive voltage) of the third high-voltage transistor HVM3 plus the first current I1 to work normally, and VTH+VOV is about 1V. Assuming that the first voltage source VIN is 3.3V, the first voltage VA is about 2.6V, such as the first voltage source VIN minus the cross-voltage of the first diode D1 (0.7V). The first voltage VA drives the third high-voltage transistor HVM3 to turn on, and the source voltage of the third high-voltage transistor HVM3 is high enough to allow the first current I1 to work normally, so that a first current I1 flows through the first high-voltage transistor HVM1 and the third high-voltage transistor HVM3. Through the circuit design of the current mirror, the second high-voltage transistor HVM2 maps the first current I1 on the first high-voltage transistor HVM1, so that the first current I1 flows through the fourth, fifth, and sixth transistors M4, M5, and M6, and a second voltage VB is generated at the second node 231. When the second voltage VB is greater than or equal to the VTH of the fourth high-voltage transistor HVM4, the fourth high-voltage transistor HVM4 is turned on, and the fourth high-voltage transistor HVM4 forms a second current I2 and generates a working voltage VCC at its source.
[0052] Further, see also Figure 2 , Figure 5 , Figure 6 and Figure 7When the chip 100 is in the power-on state, since the first voltage source VIN is established earlier than the second voltage source VGH, when the second voltage source VGH is powered on, the front-end circuit 31 of the voltage regulator 201 can provide the first voltage VA. When the chip 100 is in the normal operation mode, the first voltage source VIN still exists, so the front-end circuit 31 of the voltage regulator 201 can continue to provide the VA voltage. When the chip 100 enters the power-off state, although the first voltage source VIN stops supplying power, because the first diode D1 is unidirectionally conductive, the first voltage VA on the first node 311 will not be discharged, and the first voltage VA will continue to maintain a high potential state for a period of time (such as a potential state that can drive the third high-voltage transistor to turn on) by relying on the electric energy stored in the first capacitor C1, so that the front-end circuit 31 of the voltage regulator 201 can continue to provide the first voltage VA. In summary, no matter the chip 100 is in the power-on state, the normal operation mode or the power-off state, as long as the front-end circuit 31 of the voltage regulator 201 can continue to provide the first voltage VA, the back-end current mirror circuit assembly 40 and the output circuit 50 can regulate the working voltage VCC required for the operation of the logic circuit of the chip 100 through the driving of the first voltage VA. In addition, the length of time that the voltage regulator 201 can provide the working voltage VCC after the chip 100 enters the power-off state will be determined by the capacitance value of the first capacitor C1 and the leakage current on the first node 311.
[0053] Then, a part of the circuit of the voltage regulator 201 (such as the front-end circuit 31) replaces the resistor R1 and the three MOSs M1, M2, and M3 with a smaller area by the first diode D1 and the first capacitor C1, which can effectively save the circuit area of the voltage regulator 201, so that the size of the chip 100 used can be reduced, thereby increasing the competitiveness of the product.
[0054] Furthermore, the voltage regulator 201 of this embodiment is explained by taking the LVSH chip 100 as an example. However, in actual application, it can also be designed on other chips with specific functions that require the working voltage VCC as the power supply for circuit operation.
[0055] See also Figure 8 , Fig. 9 and Fig.10 The block diagram of another embodiment of the chip of the present invention and the block diagram and circuit diagram of another embodiment of the voltage regulator of the present invention are respectively shown in FIG. Figure 2 .like Figure 8 and Fig. 9As shown, the voltage regulator 202 of the present embodiment is designed in the chip 100 and becomes the internal circuit of the chip 100. The chip 100 adjusts the working voltage VCC required for the operation of its internal logic circuit through the voltage regulator 202. The voltage regulator 202 is connected to two voltage sources, one is the first voltage source VIN, and the other is the second voltage source VGH. In addition, in the present embodiment, the working voltage VCC is fed back to the input end of the voltage regulator 202 as an input voltage. Specifically, the voltage regulator 202 of the present embodiment adjusts and generates the working voltage VCC through the first voltage source VIN, the fed-back input working voltage VCC and the second voltage source VGH.
[0056] The circuit architecture of the voltage regulator 202 of this embodiment is similar to that of the voltage regulator 201 of the above embodiment, and the difference between the two is only in the design of the front-end circuit. Fig.10 As shown, the voltage regulator 201 includes a front-end circuit 32, a current mirror circuit assembly 40 and an output circuit 50. The front-end circuit 32 includes a first diode D1 and a second diode D2. One end (such as the positive end) of the first diode D1 is connected to the first voltage source VIN. One end (such as the positive end) of the second diode D2 is connected to the working voltage VCC, and the other end (such as the negative end) and the other end (such as the negative end) of the first diode D1 are connected to the first node 321. In addition, the circuit architecture of the current mirror circuit assembly 40 and the output circuit 50 of the voltage regulator 202 of this embodiment is exactly the same as the circuit architecture of the current mirror circuit assembly 40 and the output circuit 50 of the voltage regulator 201 of the above embodiment, and will not be repeated here.
[0057] Further, see also Figure 2 , Figure 8 , Fig. 9 and Fig.10When the chip 100 is in the power-on state, since the first voltage source VIN is established earlier than the second voltage source VGH, when the second voltage source VGH is powered on, the front-end circuit 32 of the voltage regulator 202 can provide the first voltage VA. When the chip 100 is in the normal operation mode, the first voltage source VIN still exists, so the front-end circuit 32 of the voltage regulator 201 can continue to provide the VA voltage. When the chip 100 enters the power-off state, although the first voltage source VIN stops supplying power, as long as the second voltage source VGH is still maintained at a high voltage state, the output circuit 50 will still generate the operating voltage VCC; and the operating voltage VCC is fed back to the second diode D2 of the front-end circuit 32, and the voltage is transmitted to the first node 321 through the second diode D2 to continue to provide the first voltage VA. In short, no matter the chip 100 is in the power-on state, the normal operation mode or the power-off state, as long as the front-end circuit 32 of the voltage regulator 202 can continue to provide the first voltage VA, the back-end current mirror circuit assembly 40 and the output circuit 50 can adjust the operating voltage VCC required for the operation of the logic circuit of the chip 100 according to the driving of the first voltage VA.
[0058] Then, part of the circuit of the voltage regulator 202 (such as the front-end circuit 32) replaces the resistor R1 with a larger area and the three MOSs M1, M2, and M3 with two diodes D1 and D2 with a smaller area, which can effectively save the circuit area of the voltage regulator 202, so that the size of the chip 100 used can be reduced, thereby increasing the competitiveness of the product.
[0059] Likewise, the voltage regulator 202 of this embodiment is explained using the LVSH chip 100 as an example. However, in actual applications, it can also be used in other chips with specific functions that require the working voltage VCC as a circuit operation power source.
[0060] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.
Claims
1. A voltage regulator, characterized in that: include: The front-end circuit includes a first diode and a second diode, wherein the anode of the first diode is connected to a first voltage source, the anode of the second diode is connected to an operating voltage and the cathode of the second diode is connected to a first node together with the cathode of the first diode; A current mirror circuit assembly, comprising a first high-voltage transistor, a second high-voltage transistor, a third high-voltage transistor and three transistors connected in the form of diodes; the first high-voltage transistor and the second high-voltage transistor form a current mirror, the source of the first high-voltage transistor and the source of the second high-voltage transistor are respectively connected to a second voltage source; the gate of the third high-voltage transistor is connected to the first node, the drain is connected to the drain and gate of the first high-voltage transistor and the gate of the second high-voltage transistor, and the source is grounded; the three transistors connected in the form of diodes are connected in series between the drain of the second high-voltage transistor and the ground in sequence, and are connected to a second node formed with a second voltage with the drain of the second high-voltage transistor; and The output circuit includes a fourth high-voltage transistor, a drain of the fourth high-voltage transistor is connected to the second voltage source, a gate is connected to the second node, and a source is grounded and connected to the anode of the second diode; The first voltage source supplies power to the first node through the first diode or the working voltage supplies power to the first node through the second diode, and a first voltage is formed at the first node; the first voltage drives the third high-voltage transistor to be turned on, and a first current flows through the first high-voltage transistor and the third high-voltage transistor; through the design of a current mirror, the second high-voltage transistor reflects the first current on the first high-voltage transistor, so that the first current flows through three transistors connected in the form of diodes, and a second voltage is generated at the second node; the second voltage drives the fourth high-voltage transistor to be turned on, and the working voltage is generated at the source of the fourth high-voltage transistor.
2. The voltage regulator according to claim 1, wherein: The voltage regulator is designed in a chip and becomes the internal circuit of the chip. The voltage regulator is used to adjust the working voltage required for the operation of the logic circuit inside the chip.
3. The voltage regulator according to claim 1, wherein: The chip is a level shifter, the first voltage source is a low voltage power source of the chip, and the second voltage source is a high voltage power source of the chip.
4. The voltage regulator according to claim 1, wherein: When the chip is in the shutdown state, the first voltage source stops supplying power. If the second voltage source is still maintained in a high voltage state, the operating voltage is generated at the source of the fourth high-voltage transistor. The operating voltage is fed back to the second diode and continues to supply power to the first node through the second diode, thereby generating the first voltage at the first node.