Ternary addressable memory array and preparation method and test method thereof

Abstract

The invention discloses a ternary addressable memory array and a preparation method and a test method thereof, and relates to the technical field of transistor manufacturing. Comprising a plurality of ternary addressable memories which are arranged and interconnected in an array mode; each ternary addressable memory is composed of two reconfigurable double-gate field effect transistors which are connected with each other; a plurality of matching lines and grounding lines; the matching lines of the ternary addressable memories in the same row are connected with the same line, and the grounding lines are connected with the same line; a plurality of search lines; the search lines of the ternary addressable memories in the same column are connected with the same line; a plurality of first write lines and second write lines; the first write-in lines of the ternary addressable memories in the same column are connected with the same line, and the second write-in lines are connected with the same line. The memory array disclosed by the invention has the advantages of compact structure, strong reconfigurability, good compatibility and the like, obviously reduces the circuit area and power consumption, and is suitable for a high-energy-efficiency storage and calculation integrated system and a next-generation adaptive logic integrated circuit.

Description

A ternary addressable memory array and its fabrication and testing methods Technical Field

[0001] This invention relates to the field of transistor manufacturing technology, and in particular to a ternary addressable memory array and its fabrication and testing methods. Background Technology

[0002] As integrated circuits enter the sub-10 nanometer node, traditional silicon-based devices face size miniaturization bottlenecks due to the short-channel effect. Simultaneously, the "memory wall" problem caused by the separation of memory and computation in the von Neumann architecture severely restricts system performance improvements. To overcome these limitations, introducing novel semiconductor materials and innovative device structures, combined with energy-efficient in-memory computing architectures, has become an important development trend. Emerging in-memory computing typically requires hardware support for dynamic logic reconfiguration and high-throughput parallel search. Highly efficient reconfigurable circuits and ternary content-addressable memory (TCAM) are key hardware foundations for achieving this goal.

[0003] Reconfigurable field-effect transistors (FETs), based on novel materials and structures for their memory functional layers, enable non-volatile control of channel polarity within a single device. Their programmable polarity allows the same circuit to execute multiple Boolean logic functions, and compact TCAM cells can be constructed through device pairing. Traditional CMOS-based TCAM cells require at least 16 transistors, severely limiting area and energy efficiency advantages; however, TCAMs based on novel reconfigurable transistors utilize their programmable polarity to directly generate matched responses, requiring only two transistors to encode and parallelly search for the "1," "0," and "X" states, greatly simplifying the circuit structure. However, current reconfigurable transistors based on novel materials and structures still face integration process challenges in practical application, especially compatibility issues with silicon-based processes. Top-gate integration is often constrained by thermal budget and dielectric-induced doping, affecting device uniformity and reliability, making it difficult to achieve high-density, large-scale TCAM arrays. Therefore, developing a novel design and fabrication scheme that is compatible with existing silicon processes, possesses scalable integration capabilities, realizes high-performance reconfigurable field-effect transistors, and supports efficient TCAM architectures is of great significance for promoting the development of next-generation in-memory computing hardware. Summary of the Invention

[0004] The purpose of this invention is to provide a ternary addressable memory array and its fabrication and testing methods to solve the problems mentioned in the background art. The invention designs a ternary addressable memory array based on reconfigurable dual-gate field-effect transistors, which overcomes the technical difficulties of traditional CMOS-based TCAM cell transistors having a large number of transistors, large area, and incompatibility with the integration process of new reconfigurable devices. It has the advantages of high density and low power consumption.

[0005] To achieve the above objectives, the present invention provides the following solution: In one aspect, a ternary addressable memory array is provided, comprising: multiple ternary addressable memories interconnected in an array arrangement; each ternary addressable memory is composed of two reconfigurable dual-gate field-effect transistors interconnected; multiple matching lines and ground lines; the matching lines of the ternary addressable memories in the same row are connected to the same trace, and the ground lines are connected to the same trace; multiple search lines; the search lines of the ternary addressable memories in the same column are connected to the same trace; multiple first write lines and second write lines; the first write lines of the ternary addressable memories in the same column are connected to the same trace, and the second write lines are connected to the same trace.

[0006] Preferably, the ternary addressable memory is a NAND or NOR type ternary addressable memory.

[0007] Preferably, the reconfigurable dual-gate field-effect transistor includes: a substrate; an insulating layer disposed on the substrate; a bottom-gate programming gate disposed on the insulating layer; a storage function layer disposed on the bottom-gate programming gate; a channel layer disposed on the storage function layer, the channel layer being a bipolar semiconductor thin film; a source and a drain disposed on the left and right sides above the channel layer; a seed layer disposed on the source, drain, and channel layer; a top-gate dielectric layer and a top-gate control gate disposed on the seed layer; the bottom-gate programming gate completely covers the channel layer, and the top-gate control gate covers the middle region of the channel layer.

[0008] Preferably, the reconfigurable dual-gate field-effect transistor is interconnected in such a way that the source and drain are interconnected in series or in parallel, the top control gate is interconnected, and the bottom programming gate is independent.

[0009] Preferably, the storage functional layer is a floating gate structure layer, a multi-gate dielectric stack, or a ferroelectric material layer; wherein, the floating gate structure layer includes Al2O3 / Pt / Al2O3, HfO2 / Pt / HfO2, SiO2 / Gr / h-BN, and HfO2 / GR / HfO2; the multi-gate dielectric stack includes Al2O3 / HfO2 / Al2O3, h-BN / HfO2 / Al2O3, and h-BN / SiO2; and the ferroelectric material layer includes AlScN and HfZrO. X HfAlO X HfSiO X HfTiO X and HfYO X Any one of them.

[0010] Preferably, the bipolar semiconductor thin film includes any one of WS2, Wse2, MoTe2, and ReSe2 thin films, with a thickness of 3~10 nm.

[0011] Preferably, the seed layer is selected from any one of alumina, silicon oxide, yttrium oxide, molybdenum oxide, and silicon; the top gate dielectric layer is selected from any one of hafnium oxide, alumina, silicon oxide, and silicon nitride; and the thickness of the top gate dielectric layer is 10~30 nm.

[0012] Preferably, the materials of the bottom gate programming gate and the top gate control gate are selected from any one or more of gold, tungsten, titanium, copper, aluminum, platinum, iridium, nickel, chromium, palladium, ruthenium, tungsten nitride, and titanium nitride; the area of ​​the bottom gate programming gate is larger than that of the channel layer.

[0013] On the other hand, a method for fabricating a ternary addressable memory array is provided, the specific steps of which include the following: after photolithography and development on an insulating substrate, a bottom gate programming gate layer is prepared; a storage functional layer is deposited on the bottom gate programming gate layer using atomic layer deposition; a bipolar semiconductor thin film material is transferred to the storage functional layer to form a channel layer; after photolithography and development on the semiconductor material layer, metal electrodes are grown on both sides of the channel layer by thermal evaporation, electron beam evaporation, or magnetron sputtering to obtain the source and drain electrodes; a seed layer is prepared on the channel layer, source, and drain electrodes by electron beam evaporation or plasma-enhanced chemical vapor deposition; a top gate dielectric layer is deposited on the seed layer by atomic layer deposition; after photolithography, a top gate control gate is prepared on the top gate dielectric layer by thermal evaporation, electron beam evaporation, or magnetron sputtering.

[0014] Finally, a testing method for a ternary addressable memory array is provided, the specific steps of which include: acquiring the sampling signal of the matching line of the ternary addressable memory array; determining whether the search / matching operation has been completed based on the sampling signal; for a NAND type ternary addressable memory array, after one round of test signal input, determining whether the search / matching operation has been completed by comparing the highest current level of the sampling signal; for a NOR type ternary addressable memory array, after one round of test signal input, determining whether the search / matching operation has been completed by comparing the lowest current level of the sampling signal.

[0015] According to the present invention, a ternary addressable memory array and its fabrication and testing methods are disclosed. The present invention achieves the following technical advantages: A ternary addressable memory array constructed based on reconfigurable dual-gate field-effect transistors (FETs) offers comprehensive advantages such as compact structure, strong reconfigurability, and good process compatibility. Through the coordinated control of the bottom-gate programming gate and the top-gate control gate, combined with the non-volatile continuous storage mechanism of the storage functional layer, the transistors achieve non-volatile dynamic reconfiguration of the channel carrier type, enabling the same hardware unit to flexibly execute multiple logic functions and storage state configurations.

[0016] The constructed TCAM unit only requires two transistors interconnected by NAND or NOR to support encoding and parallel searching of the three states "1", "0" and "X", which significantly reduces the number of transistors and circuit area, and overcomes the problems of low integration and high power consumption caused by the traditional CMOS architecture TCAM unit requiring 16 transistors.

[0017] Ternary addressable memory arrays can collaborate with software systems to support in-memory computing tasks, making them suitable for high-efficiency in-memory computing systems and next-generation adaptive integrated circuits. They possess excellent scalability and promising practical application prospects. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a schematic diagram of the structure of the ternary addressable memory array of the present invention; Figure 2 is a schematic diagram of the structure of the NAND-type TCAM of the present invention; Figure 3 is a schematic diagram of the structure of the NOR-type TCAM of the present invention; Figure 4 is a schematic diagram of the structure of the reconfigurable dual-gate field-effect transistor of the present invention; Figure 5 is a graph showing the change of the bottom gate programming gate transfer characteristic curve of the reconfigurable dual-gate field-effect transistor prepared in Example 1 with the storage state of the storage functional layer; Figure 6 is a graph showing the change of the top gate control gate transfer characteristic curve of the reconfigurable dual-gate field-effect transistor prepared in Example 1 with the storage state of the storage functional layer; Figure 7 is a graph showing the search / matching operation of the NAND-type TCAM of the present invention; Figure 8 is a schematic diagram of the search / matching operation of the NOR-type TCAM of the present invention.

[0020] Among them, 1. First write line, 2. Second write line, 3. Search line, 4. Ground line, 5. Matching line, 6. Ternary addressable memory, 7. Reconfigurable dual-gate field-effect transistor, 8. Substrate, 9. Insulating layer, 10. Bottom gate programming gate, 11. Storage function layer, 12. Channel layer, 13. Source and drain, 14. Seed layer, 15. Top gate dielectric layer, 16. Top gate control gate. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] As shown in Figure 1, this invention discloses a ternary addressable memory array, comprising: multiple ternary addressable memories 6 interconnected in an N*M array arrangement, where M and N are positive integers greater than 1; each ternary addressable memory 6 is composed of two reconfigurable dual-gate field-effect transistors interconnected; multiple matching lines 5 and ground lines 4; the matching lines and ground lines of ternary addressable memories in the same row are connected to the same trace; multiple search lines 3; the search lines of ternary addressable memories in the same column are connected to the same trace; multiple first write lines 1 and second write lines 2; the first write lines and second write lines of ternary addressable memories in the same column are connected to the same trace.

[0023] The ternary addressable memory 6 is composed of two reconfigurable dual-gate field-effect transistors 7 interconnected in NAND or NOR type, as shown in Figures 2 and 3. The ternary addressable memory 6 is preferably a NOR type ternary addressable memory, but can be any type of NAND type ternary addressable memory. The specific type can be selected according to actual needs.

[0024] As shown in Figure 4, the reconfigurable dual-gate field-effect transistor 7 of the present invention includes: a substrate 8; an insulating layer 9 disposed on the substrate; a bottom-gate programming gate 10 disposed on the insulating layer 9; a storage function layer 11 disposed on the bottom-gate programming gate 10; a channel layer 12 disposed on the storage function layer 11, the channel layer 12 being a bipolar semiconductor thin film; a source and a drain 13 disposed on the left and right sides above the channel layer 12; a seed layer 14 disposed on the source, drain 13, and channel layer 12; a top-gate dielectric layer 15 and a top-gate control gate 16 disposed on the seed layer 14; the bottom-gate programming gate 11 completely covers the channel layer 12, and the top-gate control gate 16 covers the middle region of the channel layer 12.

[0025] In this invention, the reconfigurable dual-gate field-effect transistor 7 is preferably any one of the following: floating-gate reconfigurable dual-gate field-effect transistor 7, charge-trapping reconfigurable dual-gate field-effect transistor 7, and ferroelectric reconfigurable dual-gate field-effect transistor 7. The specific type can be selected according to actual needs.

[0026] In this invention, the substrate 8 is preferably a highly doped silicon substrate, such as a silicon wafer; an insulating layer 9 is disposed on the substrate 8, and the two constitute an insulating substrate; the insulating layer 9 is preferably a silicon oxide insulating layer, and the thickness is preferably 100 nm to 300 nm, which facilitates subsequent preparation.

[0027] The bottom-gate programming gate 10 is deposited on top of the insulating layer 9, and the material includes any one or more of the following: gold, tungsten, titanium, copper, aluminum, platinum, iridium, nickel, chromium, palladium, ruthenium, tungsten nitride, and titanium nitride. In this embodiment of the invention, the bottom-gate programming gate 10 is selected as titanium / gold, and the thickness is selected to be 5~30 nm.

[0028] The memory functional layer 11 is deposited above the bottom-gate programming gate 10. The memory functional layer 11 is a floating gate structure layer, a multi-gate dielectric stack, or a ferroelectric material layer. The floating gate structure layer includes Al2O3 / Pt / Al2O3, HfO2 / Pt / HfO2, SiO2 / Gr / h-BN, and HfO2 / GR / HfO2. The multi-gate dielectric stack includes Al2O3 / HfO2 / Al2O3, h-BN / HfO2 / Al2O3, and h-BN / SiO2. The ferroelectric material layer includes AlScN and HfZrO2. X HfAlO X HfSiO X HfTiO X and HfYO X Any one of them.

[0029] In this invention, the thickness of the barrier layer in the floating gate structure layer and the multi-gate dielectric stack is 20~40 nm, the thickness of the floating gate layer / charge trapping layer is 5~15 nm, the thickness of the tunneling layer is 5~15 nm, the thickness of the AlScN ferroelectric dielectric layer is 10~60 nm, and the thickness of the Hf-based ferroelectric dielectric layer is 10~20 nm.

[0030] A channel layer 12 is disposed above the storage functional layer 11, wherein the bipolar semiconductor thin film of the channel layer 12 is preferably any one of WS2, Wse2, MoTe2, and ReSe2 thin films, with a thickness of 3~10 nm. In one embodiment of the present invention, the channel layer is selected as Wse2, and the thickness is selected as 6.5 nm.

[0031] Source and drain electrodes 13 are deposited above the channel layer 12. The source and drain electrodes 13 are preferably made of any one of the following materials: gold, tungsten, titanium, copper, aluminum, platinum, iridium, nickel, chromium, palladium, ruthenium, tungsten nitride, and titanium nitride. In one embodiment of the invention, the source and drain electrodes 13 are selected as titanium / gold.

[0032] A seed layer 14 is deposited above the source and drain electrodes 13. The seed layer 14 is selected from any one of alumina, silicon oxide, yttrium oxide, molybdenum oxide, and silicon. In one embodiment of the present invention, the seed layer 14 is selected as silicon oxide.

[0033] A top gate dielectric layer 15 is deposited on the seed layer 14. The top gate dielectric layer 15 is preferably any one of hafnium oxide, aluminum oxide, silicon oxide, and silicon nitride, with a thickness of 10 nm to 30 nm and an area of ​​(10~30)*(60~80) μm. In one embodiment of the present invention, the top gate dielectric layer 15 is selected as hafnium oxide, with a thickness of 20 nm and an area of ​​20*60 μm.

[0034] A top-gate control gate 16 is deposited on the top-gate dielectric layer 15. The material of the top-gate control gate 16 is preferably any one or more of gold, tungsten, titanium, copper, aluminum, platinum, iridium, nickel, chromium, palladium, ruthenium, tungsten nitride, and titanium nitride. The thickness of the top-gate control gate 16 is 20-50 nm, and the width is 3-10 μm. In one embodiment of the present invention, the top-gate control gate 16 is selected as titanium / gold, with a thickness of 5 / 30 nm and a gate width of 5 nm.

[0035] This invention also provides a method for fabricating a ternary addressable memory array, the specific steps of which include: after photolithography on an insulating substrate, a bottom gate programming gate layer is prepared by thermal evaporation, electron beam evaporation, or magnetron sputtering; a storage functional layer is deposited on the bottom gate programming gate layer using atomic layer deposition; a bipolar semiconductor thin film material is transferred to the storage functional layer to form a channel layer; after photolithography on the semiconductor material layer, metal electrodes are grown on both sides by thermal evaporation, electron beam evaporation, or magnetron sputtering to obtain the source and drain electrodes; a seed layer is prepared on the channel layer, source, and drain electrodes by electron beam evaporation or plasma-enhanced chemical vapor deposition; a top gate dielectric layer is deposited on the seed layer by atomic layer deposition; after photolithography, a top gate control gate is prepared on the top gate dielectric layer by thermal evaporation, electron beam evaporation, or magnetron sputtering.

[0036] The following is a specific embodiment 1, which describes the fabrication of a ternary addressable memory array using a specific method: Step 1: After photolithography and development on an insulating substrate, a bottom-gate programming gate layer is prepared by thermal evaporation, electron beam evaporation, or magnetron sputtering. On an insulating silicon substrate with 300 nm silicon oxide on its surface, ultrasonic cleaning is performed sequentially using acetone, isopropanol, and deionized water, followed by nitrogen drying. Subsequently, LOR10A and AZ5214E ​​photoresists are coated sequentially by spin coating and baked separately. Next, exposure is performed using a contact ultraviolet lithography machine, followed by development with SUN-238D developer, cleaning with deionized water, and drying. Afterward, a 5 / 30 nm thick Ti / Au metal layer is deposited on the developed pattern using magnetron sputtering. Finally, lift-off is performed using N-methylpyrrolidone (NMP) solution to remove excess photoresist and its metal, followed by cleaning with deionized water and nitrogen drying to form the bottom-gate programming gate structure.

[0037] Step 2: Deposit the memory functional layer on the bottom-gate programming gate layer using atomic layer deposition (ALD). Place the substrate with the bottom gate in an ALD apparatus. First, deposit a 30 nm thick Al₂O₃ layer using an aluminum-oxygen source. Next, adjust the precursor to hafnium and deposit a 10 nm thick HfO₂ layer using an oxygen source. Then, adjust the precursor to aluminum and deposit a 10 nm thick Al₂O₃ layer to complete the fabrication of the memory functional layer.

[0038] Step 3: Transfer bipolar semiconductor thin film material over the storage functional layer to form a channel layer; prepare a two-dimensional semiconductor thin film using a mechanical exfoliation method: repeatedly peel off the layered WSe2 and MoTe2 crystals with adhesive tape until their thickness is reduced to 3-10 nm, then attach and transfer them onto the PDMS gel film. Select a film of suitable size (15-20 μm in length) and uniform surface under an optical microscope. Subsequently, using a two-dimensional material transfer system, precisely transfer the semiconductor thin film on the PDMS film onto the substrate that has undergone the above process, so that it is completely attached to the bottom gate and the storage functional layer to form the channel layer of the transistor.

[0039] Step 4: After photolithography to develop the semiconductor material layer, metal electrodes are grown on both sides by thermal evaporation, electron beam evaporation, or magnetron sputtering to obtain the source and drain electrodes. Electron beam photoresist MMA and PMMA are spin-coated onto the sample forming the channel layer, and both are baked. Then, alignment and exposure are performed using an electron beam lithography system. After exposure, development is performed using a developer, followed by cleaning with isopropanol and drying with nitrogen. Next, a 30 nm thick layer of Au is deposited using vacuum thermal evaporation. Finally, the photoresist and excess metal are removed by stripping in acetone to form the source and drain electrodes, resulting in a prototype transistor with a bottom gate and source / drain electrodes.

[0040] Step 5: Prepare a seed layer on the channel layer, source, and drain using electron beam evaporation or plasma-enhanced chemical vapor deposition; place the transistor obtained in the previous step in an electron beam evaporation device and deposit a silicon oxide film of about 2 nm thick on the source, drain, and channel regions as a seed layer for subsequent atomic layer deposition.

[0041] Step 6: Place the sample covered with the seed layer in the atomic layer deposition equipment, adjust the precursor to hafnium and oxygen source, set an appropriate pulse time, and after multiple deposition cycles, grow a hafnium oxide layer of about 10 nm thickness on the seed layer as the top gate dielectric layer. After completion, remove the sample and cool it for later use.

[0042] Step 7: After photolithography, the top gate control gate is prepared on the top gate dielectric layer by thermal evaporation, electron beam evaporation, or magnetron sputtering.

[0043] On a sample with a top-gate dielectric layer, electron beam photoresist MMA and PMMA were spin-coated sequentially and baked. Subsequently, electron beam lithography exposure and development were performed. After development, a 5 / 30 nm thick Ti / A metal was deposited as the gate using thermal evaporation. Finally, excess photoresist and metal were removed by acetone stripping, completing the fabrication of the top-gate control gate. This resulted in a fully functional reconfigurable dual-gate field-effect transistor with a bottom-gate programming gate, a top-gate control gate, a source, and a drain. The detailed structure is shown in Figure 4.

[0044] As shown in Figure 5, after different programming pulses are applied to the programming gate of the reconfigurable dual-gate field-effect transistor prepared in Example 1, the corresponding charge is stored in the storage function layer, which non-volatilely affects the channel conduction polarity and switches the conduction state of the transistor.

[0045] As shown in Figure 6, the reconfigurable dual-gate field-effect transistor prepared in Example 1 exhibits standard P / N transfer characteristics in the top gate control gate transfer effect under different charge storage states, and also shows a low subthreshold swing. This is because the incompletely covered control gate can realize a PNP / NPN rectification structure in the same channel, further improving the device's electrical performance and optimizing its non-volatility.

[0046] As shown in Figures 7 and 8, the two types of ternary addressable memories based on reconfigurable dual-gate field-effect transistors prepared in Example 1 achieve storage of three states: "1", "0", and "X" under the programming operation of the write line. Under different voltage excitations on the search line, the matching line exhibits corresponding responses, completing standard search and matching operations. Specifically, the "1", "0", and "X" states of the NAND ternary addressable memory cell correspond to the programming polarities of the two transistors being "NN", "PP", and "PN", respectively, with a high matching current. Similarly, the "1", "0", and "X" states of the NOR ternary addressable memory cell correspond to the programming polarities of the two transistors being "PP", "NN", and "PN", respectively, with a low matching current. The ternary addressable memory array based on reconfigurable dual-gate field-effect transistors prepared in this invention exhibits different matching current responses depending on the number of matching cells in a single row under a set of search line voltage excitations.

[0047] Finally, a testing method for ternary addressable memory arrays is provided, the specific steps of which include: acquiring the sampling signal of the matching line of the ternary addressable memory array; determining whether the search / matching operation has been completed based on the sampling signal; for NAND-type ternary addressable memory arrays, after one round of test signal input, determining whether the search / matching operation has been completed by comparing the highest current level of the sampling signal; for NOR-type ternary addressable memory arrays, after one round of test signal input, determining whether the search / matching operation has been completed by comparing the lowest current level of the sampling signal.

[0048] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A ternary addressable memory array, characterized in that, include: Multiple ternary addressable memories interconnected in an array; Each of the ternary addressable memories consists of two reconfigurable dual-gate field-effect transistors interconnected. Multiple matching lines and ground lines; the matching lines of the ternary addressable memory in the same row are connected to the same trace, and the ground lines are connected to the same trace; Multiple search lines; the search lines of the ternary addressable memory in the same column are connected to the same trace; multiple first write lines and second write lines; the first write lines of the ternary addressable memory in the same column are connected to the same trace, and the second write lines are connected to the same trace.

2. The ternary addressable memory array according to claim 1, characterized in that, The ternary addressable memory is a NAND or NOR type ternary addressable memory.

3. A ternary addressable memory array according to claim 1, characterized in that, The reconfigurable dual-gate field-effect transistor includes: a substrate; an insulating layer disposed on the substrate; a bottom-gate programming gate disposed on the insulating layer; a storage function layer disposed on the bottom-gate programming gate; a channel layer disposed on the storage function layer, the channel layer being a bipolar semiconductor thin film; a source and a drain disposed on the left and right sides above the channel layer; a seed layer disposed on the source, drain, and channel layer; a top-gate dielectric layer and a top-gate control gate disposed on the seed layer; the bottom-gate programming gate completely covers the channel layer, and the top-gate control gate covers the middle region of the channel layer.

4. A ternary addressable memory array according to claim 1, characterized in that, The reconfigurable dual-gate field-effect transistor is interconnected in the form of a source and drain connected in series or parallel, with the top control gate interconnected and the bottom programming gate independent.

5. A ternary addressable memory array according to claim 3, characterized in that, The storage functional layer is a floating gate structure layer, a multi-gate dielectric stack, or a ferroelectric material layer; wherein, the floating gate structure layer includes Al2O3 / Pt / Al2O3, HfO2 / Pt / HfO2, SiO2 / Gr / h-BN, and HfO2 / GR / HfO2; the multi-gate dielectric stack includes Al2O3 / HfO2 / Al2O3, h-BN / HfO2 / Al2O3, and h-BN / SiO2; and the ferroelectric material layer includes AlScN and HfZrO. X HfAlO X HfSiO X HfTiO X and HfYO X Any one of them.

6. A ternary addressable memory array according to claim 3, characterized in that, The bipolar semiconductor thin film includes any one of WS2, Wse2, MoTe2, and ReSe2 thin films, with a thickness of 3~10 nm.

7. A ternary addressable memory array according to claim 3, characterized in that, The seed layer is selected from any one of alumina, silicon oxide, yttrium oxide, molybdenum oxide, and silicon; the top gate dielectric layer is selected from any one of hafnium oxide, alumina, silicon oxide, and silicon nitride, and the thickness of the top gate dielectric layer is 10~30 nm.

8. A ternary addressable memory array according to claim 3, characterized in that, The materials of the bottom gate programming gate and the top gate control gate are selected from any one or more of gold, tungsten, titanium, copper, aluminum, platinum, iridium, nickel, chromium, palladium, ruthenium, tungsten nitride, and titanium nitride; the area of ​​the bottom gate programming gate is larger than that of the channel layer.

9. A method for fabricating a ternary addressable memory array, characterized in that, The specific steps include the following: after photolithography and development on an insulating substrate, a bottom-gate programming gate layer is prepared; a storage functional layer is deposited on the bottom-gate programming gate layer using atomic layer deposition; and a bipolar semiconductor thin film material is transferred over the storage functional layer to form a channel layer. After photolithography is performed on the semiconductor material layer, metal electrodes are grown on both sides of the channel layer by thermal evaporation, electron beam evaporation, or magnetron sputtering to obtain the source and drain electrodes. Seed layers are prepared above the channel layer, source, and drain electrodes by electron beam evaporation or plasma-enhanced chemical vapor deposition. A top gate dielectric layer is deposited on the seed layer by atomic layer deposition. After photolithography, the top gate control gate is prepared above the top gate dielectric layer by thermal evaporation, electron beam evaporation, or magnetron sputtering.

10. A test method for a ternary addressable memory array, characterized in that, The specific steps include the following: acquiring the sampling signal of the matching line of the ternary addressable memory array; determining whether the search / matching operation has been completed based on the sampling signal; for NAND ternary addressable memory arrays, after one round of test signal input, determining whether the search / matching operation has been completed by comparing the highest current level of the sampling signal; for NOR ternary addressable memory arrays, after one round of test signal input, determining whether the search / matching operation has been completed by comparing the lowest current level of the sampling signal.

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