A state management circuit architecture for USB devices

Abstract

This disclosure relates to the field of USB 2.0 protocol implementation, specifically to a state management circuit architecture for a USB device, comprising: a state detection unit, configured to receive and determine a state signal based on a differential signal pair, and determine the target state of the USB based on the state signal; the differential signal pair includes a differential signal D+ and a differential signal D-; the state signal is any one of SE0, J, and K; the target state is any one of a suspended state, a wake-up state, a reset state, a general working state, and a wake-up request state; a high-speed handshake unit, configured to control the USB to perform high-speed handshake detection after the reset state, and to close the high-speed handshake unit after the high-speed handshake detection, so that the USB re-enters the general working state; and a state transition control unit, configured to manage the current state of the USB and transition the current state of the USB to the target state.

Description

Technical Field

[0001] This disclosure relates to the field of USB 2.0 (Universal Serial Bus 2.0) protocol implementation, specifically to a state management circuit architecture for USB devices. This disclosure can be used for operating state management and detection in USB 2.0 devices and slave circuits. Background Technology

[0002] USB (Universal Serial Bus) is a widely used connection standard between personal computers and external devices. It defines the data transfer rate, cable specifications, and connection and communication methods. It not only provides an efficient data transfer mechanism but also supports various types of peripherals to access computer systems through its flexible device architecture. While the USB protocol has evolved to versions like USB 3.2 and USB 4.0, USB 2.0 remains widely used in various electronic devices, especially embedded and IoT mobile devices, due to its simplicity, ease of use, and low cost.

[0003] According to the definition of the USB 2.0 protocol, USB 2.0 has normal operating state, suspended state, wake-up state, and reset state. While sending and receiving data, the current protocol state is determined by checking the status of the D+ and D- data transmission signal lines of the USB 2.0. After the USB is in reset state, the current operating speed is first determined, thus entering different operating speed modes. USB 2.0 has three data rate modes: low speed (1.5MHz), full speed (12MHz), and high speed (480MHz). After the device is connected to the host, the D+ and D- signals are used to determine the low-speed or full-speed operating mode. If the D- signal is pulled up, it operates in low-speed mode; if the D+ signal is pulled up, it operates in full-speed mode. Then, the high-speed state is detected according to the corresponding protocol.

[0004] USB 2.0 generally consists of a host, a hub, and slave devices. However, existing USB 2.0 device controller circuits, which use state machines to transition between operating states and counters and corresponding control circuits to determine the current operating state, often suffer from the following drawbacks: (1). Regarding the speed detection and state transition of USB 2.0, existing circuit designs for implementing state machines are often complex in structure, difficult to implement, and have a large circuit area.

[0005] (2). USB 2.0 device controllers are now mostly used in IoT, embedded and other mobile devices, and there is a need to continuously reduce the power consumption of the circuit.

[0006] (3) Existing small embedded devices generally support USB 2.0 low-speed 1.5MHz and full-speed 12MHz transmission protocols, but there are fewer protocols that support high-speed 480MHz transmission. Summary of the Invention

[0007] To address the problems existing in the prior art, this disclosure proposes a state management circuit architecture for USB devices, aiming to resolve at least one of the aforementioned technical problems. The technical solution adopted in this disclosure is as follows: A state management circuit architecture for a USB device includes: A status detection unit is used to receive differential signal pairs, determine the received status signal based on the differential signal pairs, and determine the target state that the USB should enter based on the status signal; wherein, the differential signal pairs include differential signal D+ and differential signal D-; the status signal is any one of SE0, J, and K; the target state is any one of suspended state, wake-up state, reset state, general working state, and wake-up request state; The high-speed handshake unit is used to control the USB to perform high-speed handshake detection after the reset state, and to shut down the high-speed handshake unit after the high-speed handshake detection, so that the USB can return to the general working state. A state transition control unit is used to manage the current state of the USB and to transition the current state of the USB to the target state.

[0008] Preferably, the state management circuit communicates with the front-end physical layer circuit of the USB device through the UTMI interface.

[0009] Preferably, the state management circuit transmits the received and / or output data, drives, differential signal pairs, USB current state, target state, and state signals to the protocol layer and register group of the USB device for processing.

[0010] Preferably, the state detection unit, the high-speed handshake unit, and the state transition control unit are interconnected in pairs.

[0011] Preferably, the USB device is a USB 2.0 device.

[0012] Preferably, the state detection unit may be configured with a state detection state machine.

[0013] Furthermore, the duration of the frequency division clock is preferably 50µs.

[0014] Preferably, the high-speed handshake unit may be configured with a high-speed handshake control state machine.

[0015] Preferably, the state transition control unit may be configured with: A general-purpose delay counter is used to generate delay assertions corresponding to the delay time, which are used to assist the operation of the state transition control unit; the delay time is <= 100ms; A state transition control state machine is used to manage the current state of the USB based on the delay assertion, and to control the transition of the current state of the USB to the target state.

[0016] The beneficial effects of this disclosure are as follows: This disclosure provides a state management circuit architecture for USB devices, which can be used for state management in USB 2.0 device controller circuits. It can also be used to identify the current operating state of USB 2.0 (general operating state, suspended state, reset state, wake-up state, etc.), and to detect the current operating speed of the USB 2.0 device after the USB 2.0 reset state (supporting full-speed and high-speed detection). It has good versatility in integrated circuit design. This disclosure can be used for the design of operating state detection circuits in USB 2.0 device slave circuits, and can also be used as a means of implementing protocols such as USB 2.0 (Universal Serial Bus 2.0) in integrated circuit design.

[0017] Compared with the prior art, this disclosure has the following advantages: (1). This disclosure proposes a novel state management circuit architecture for USB devices, which can reduce the complexity and circuit area of ​​USB 2.0 speed detection circuits.

[0018] (2). In addition to supporting USB 2.0 low-speed and full-speed operating rates, this disclosure also supports full-speed and high-speed detection.

[0019] (3) The present disclosure has optimized the circuit structure for low power consumption, thereby reducing the overall power consumption of the circuit. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is an architecture diagram of the state management circuit architecture for USB devices described in this disclosure.

[0022] Figure 2 This is a schematic diagram of the operation of the state detection unit described in this disclosure.

[0023] Figure 3 This is a schematic diagram of the high-speed handshake control state machine described in this disclosure.

[0024] Figure 4 This is a schematic diagram of the state transition control state machine described in this disclosure. Detailed Implementation

[0025] The present disclosure will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in the present application can be combined with each other.

[0026] The following detailed descriptions are exemplary and intended to provide further detailed explanation of this disclosure. Unless otherwise specified, all technical terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure.

[0027] like Figure 1 As shown, a state management circuit architecture for a USB device includes: The status detection unit 100 is used to receive differential signal pairs, determine the received status signal based on the differential signal pairs, and determine the target state that the USB should enter based on the status signal; wherein, the differential signal pairs include differential signal D+ and differential signal D-; the status signal is any one of SE0, J, and K; the target state is any one of suspended state, wake-up state, reset state, general working state, and wake-up request state; The high-speed handshake unit 200 is used to control the USB to perform high-speed handshake detection after the reset state, and to shut down the high-speed handshake unit 200 after the high-speed handshake detection, so that the USB can return to the general working state. The state transition control unit 300 is used to manage the current state of the USB and to transition the current state of the USB to the target state.

[0028] In implementation, the state detection unit 100 determines the received state signal based on the differential signal D+ and the differential signal D-, and generates state assertions corresponding to suspended state, wake-up state, reset state, general working state, and wake-up request state, respectively, based on the state signal. It is understood that the state assertions can be suspended assertions, wake-up assertions, reset assertions, general working assertions, and wake-up request assertions, etc.

[0029] The state assertion can be used to determine the target state that the USB should enter. For example, if the state assertion is a suspend assertion, the target state is a suspend state; if the state assertion is a reset assertion, the target state is a reset state. Through the state assertion, the state detection unit 100 can determine the target state that the USB should enter based on the state signal.

[0030] The state detection unit 100 controls the validity of the clocks of the high-speed handshake unit 200 and the state transition control unit 300 based on state assertions, and turns off the clocks of the corresponding units when in a suspended state or when high-speed handshake detection is not performed, thereby reducing overall power consumption.

[0031] The state transition control unit 300 is responsible for managing the current state of the USB and, based on state assertions, controls the transition from the current state of the USB to the corresponding suspended state, wake-up state, reset state, general working state, and wake-up request state.

[0032] In one feasible implementation, the state management circuit communicates with the front-end physical layer circuit of the USB device via the UTMI interface.

[0033] In one feasible implementation, the state management circuit transmits the data, drives, differential signal pairs, USB current state, target state, and status signals it receives and / or outputs to the protocol layer and register group of the USB device for processing.

[0034] In one feasible implementation, the state detection unit 100, the high-speed handshake unit 200, and the state transition control unit 300 are interconnected in pairs.

[0035] In one feasible implementation, the state detection unit 100 may be configured with a state detection state machine.

[0036] Furthermore, such as Figure 2 As shown, the state detection state machine can be configured with: Step S101: Generate a frequency-divided clock, and perform SE0 hold time counting and J hold time counting based on the frequency-divided clock to obtain SE0 hold time and J hold time; Step S102: Based on whether the SEO holding time and J holding time have reached the corresponding preset time threshold, generate a reset assertion or a suspension assertion; Step S103: Based on the generated reset assertion or suspend assertion, the state transition control unit 300 controls the USB to enter the reset state or suspend state accordingly, and counts the USB's reset state holding time or suspend state holding time accordingly.

[0037] Furthermore, the duration of the frequency division clock is preferably 50µs.

[0038] Furthermore, such as Figure 2 As shown, the state detection state machine can also be configured with: Step S104: When the USB is in full-speed mode, if the SEO hold time is greater than 2.5us, the corresponding reset assertion is generated; if the J hold time is greater than 3ms, the corresponding suspend assertion is generated.

[0039] Furthermore, the state detection state machine may also be configured with: Step S105: When the USB is in high-speed mode, if the SEO hold time is longer than 3ms, a state assertion is generated. The USB is then switched to full-speed mode by the state assertion. After that, the SEO hold time or the J hold time is detected. The state transition control unit 300 controls the USB to switch between different states according to the SEO hold time or the J hold time.

[0040] In implementation, it can also be configured such that USB 2.0 only performs high-speed handshake detection after entering the reset state. Therefore, the clock of the high-speed handshake unit 200 is turned on only when the USB is currently in the reset state, and turned off at other times. When the USB is in the suspended state, the clock of the state transition control unit 300 is turned off. When the wake-up state or reset state is detected, the clock of the state transition control unit 300 is turned on. The state transition control unit 300 manages the current state of the USB and / or transitions the current state of the USB to the target state.

[0041] In one feasible implementation, the high-speed handshake unit 200 may be configured with a high-speed handshake control state machine.

[0042] Furthermore, such as Figure 3 As shown, the high-speed handshake control state machine can be configured with: Step S201: When the USB enters the high-speed handshake detection state from the general working state, a 1ms chirp K status signal is sent to the host or hub. Step S202: After sending a 1ms chirp K status signal to the host or hub, wait for the host or hub to send continuous status transition signals; the status transition signals are the chirp K status signal and / or the chirp J status signal; Step S203: If an SEO state signal is received before the cumulative receipt of 6 consecutive state transition signals, the USB reset state ends and the USB continues to communicate in full-speed mode—that is, the USB does not enter high-speed mode. Step S204: In response to receiving the state transition signal 6 times consecutively, the USB enters high-speed mode.

[0043] Furthermore, once the USB enters high-speed mode, high-speed interface communication can be performed by controlling the UTMI interface.

[0044] Furthermore, a Chirp K state signal counter and a Chirp J state signal counter can be configured to count the received consecutive Chirp K state signals or Chirp J state signals respectively. It is worth noting that the determination of whether 6 consecutive state transition signals have been received does not distinguish between Chirp K state signals and / or Chirp J state signals.

[0045] In one feasible implementation, the state transition control unit 300 may be configured with: A general-purpose delay counter is used to generate delay assertions corresponding to the delay time, which are used to assist the operation of the state transition control unit 300; the delay time is <= 100ms. A state transition control state machine is used to manage the current state of the USB based on the delay assertion, and to control the transition of the current state of the USB to the target state.

[0046] Furthermore, the delay assertion corresponds one-to-one with the delay time, and there are multiple of both.

[0047] Furthermore, such as Figure 4 As shown, the state transition control state machine can also be configured with: Step S301: In response to detecting that the USB is connected to the host or hub, delay for 100ms to wait for the USB to stabilize; Step S302: After the USB stabilizes, the USB enters the general working state and communicates in full-speed mode. When the USB detects a suspend assertion or a reset assertion in full-speed mode, the USB enters the suspend state or the reset state accordingly. Step S303: In high-speed mode, when the SE0 hold time is detected to be more than 3ms, the USB will switch to full-speed mode. Step S304: In full-speed mode, the USB continues to detect the differential signal D+ and differential signal D-, and controls the USB to enter the reset state or the suspend state from the current state.

[0048] Furthermore, the state transition control state machine may also be configured with: Step S305: In response to the determination that the USB has entered the reset state, the USB enters the high-speed handshake detection and starts the high-speed handshake detection to determine whether the USB supports high-speed transmission. If yes, the USB enters high-speed transmission mode; otherwise, the USB operates in full-speed mode and remains in a reset state until it receives a signal from the host to cancel the reset state and then enters the general operating state. Step S306: In response to determining that the USB has entered a suspended state, the clock of the state transition control unit 300 is turned off, so that the state transition control unit 300 enters a low-power state. Step S307: In response to detecting a wake-up state request sent by the host, the USB enters the wake-up state; Step S308: In response to detecting that the host has finished sending the wake-up status request, the USB enters the general working state after a preset delay time.

[0049] Furthermore, the preset delay time is 1ms.

[0050] Furthermore, the step of responding to the detection of a wake-up state request sent by the host and then the USB entering the wake-up state specifically includes: after receiving the wake-up state request signal sent by the host, the USB sends a K state signal for 1ms (a preset delay time), and then the USB enters the wake-up state, waiting to be woken up by the host.

[0051] In summary, through the aforementioned unique technical solution, this disclosure provides a state management circuit architecture for USB devices. It can be used for state management in USB 2.0 device controller circuits, and also for identifying the current operating state of USB 2.0 (general operating state, suspended state, reset state, wake-up state, etc.), and detecting the current operating speed of the USB 2.0 device after the USB 2.0 reset state (supporting full-speed and high-speed detection). It has good versatility in integrated circuit design. This disclosure can be used as a design for operating state detection circuits in USB 2.0 device slave circuits, and also as a means of implementing protocols such as USB 2.0 (Universal Serial Bus 2.0) in integrated circuit design.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure and not to limit them. Although this disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this disclosure. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this disclosure should be covered within the protection scope of the claims of this disclosure.

Claims

1. A state management circuit architecture for a USB device, characterized in that, include: A status detection unit (100) is configured to receive differential signal pairs, determine the received status signal based on the differential signal pairs, and determine the target state that the USB should enter based on the status signal; wherein, the differential signal pairs include differential signal D+ and differential signal D-; the status signal is any one of SE0, J, and K; and the target state is any one of suspended state, wake-up state, reset state, general working state, and wake-up request state. The high-speed handshake unit (200) is used to control the USB to perform high-speed handshake detection after the reset state, and to shut down the high-speed handshake unit (200) after the high-speed handshake detection so that the USB can return to the general working state. A state transition control unit (300) is used to manage the current state of the USB and to transition the current state of the USB to the target state.

2. The state management circuit architecture for a USB device as described in claim 1, characterized in that, The state management circuit communicates with the front-end physical layer circuit of the USB device through the UTMI interface.

3. The state management circuit architecture for a USB device as described in claim 1, characterized in that, The state management circuit transmits the received and / or output data, drive signals, differential signal pairs, USB current state, target state, and state signals to the protocol layer and register group of the USB device for processing.

4. The state management circuit architecture for a USB device as described in claim 1, characterized in that, The state detection unit (100), the high-speed handshake unit (200), and the state transition control unit (300) are interconnected in pairs; The USB device is a USB 2.0 device.

5. The state management circuit architecture for a USB device as described in claim 1, characterized in that, The state detection unit (100) is equipped with a state detection state machine; The state detection state machine is configured with: Generate a frequency-divided clock, and perform SE0 hold time and J hold time counting based on the frequency-divided clock to obtain the SE0 hold time and J hold time; Based on whether the SEO hold time and J hold time reach the corresponding preset time threshold, a reset assertion or a suspension assertion is generated. Based on the generated reset assertion or suspend assertion, the state transition control unit (300) controls the USB to enter the reset state or suspend state accordingly, and counts the USB's reset state holding time or suspend state holding time accordingly.

6. The state management circuit architecture for a USB device as described in claim 5, characterized in that, The state detection state machine is also configured with: When the USB is in full-speed mode, if the SEO hold time is greater than 2.5µs, the reset assertion is generated accordingly; if the J hold time is greater than 3ms, the suspend assertion is generated accordingly. When the USB is in high-speed mode, if the SEO hold time is longer than 3ms, a state assertion is generated. The USB is then switched to full-speed mode by the state assertion. After that, the SEO hold time or the J hold time is detected. The state transition control unit (300) controls the USB to switch between different states according to the SEO hold time or the J hold time.

7. The state management circuit architecture for a USB device as described in claim 1, characterized in that, The high-speed handshake unit (200) is equipped with a high-speed handshake control state machine; The high-speed handshake control state machine is configured with: When USB transitions from general operation to high-speed handshake detection, it sends a 1ms chirp K status signal to the host or hub. After sending a 1ms chirp K status signal to the host or hub, wait to receive continuous status transition signals from the host or hub; the status transition signals are the chirp K status signal and / or the chirp J status signal. If an SEO state signal is received before six consecutive state transition signals are received, the USB reset state ends and the USB continues to communicate in full-speed mode—that is, the USB does not enter high-speed mode. The USB enters high-speed mode in response to receiving the state transition signal a total of 6 times consecutively.

8. The state management circuit architecture for a USB device as described in claim 1, characterized in that, The state transition control unit (300) is configured with: A general-purpose delay counter is used to generate delay assertions corresponding to a delay time, which assists the operation of the state transition control unit (300); the delay time is <= 100ms. A state transition control state machine is used to manage the current state of the USB based on the delay assertion, and to control the transition of the current state of the USB to the target state.

9. The state management circuit architecture for a USB device as described in claim 8, characterized in that, The state transition control state machine is configured with: In response to detecting a USB connection to a host or hub, a 100ms delay is performed to allow the USB connection to stabilize. Once the USB is stable, it enters a general working state and communicates in full-speed mode. When the USB detects a suspend assertion or a reset assertion in full-speed mode, it enters the suspend state or reset state accordingly. When the USB is in high-speed mode, it will switch to full-speed mode after detecting that the SE0 hold time is more than 3ms. In full-speed mode, the USB continues to detect the differential signal D+ and differential signal D-, controlling the USB to enter a reset state or a suspended state from the current state.

10. The state management circuit architecture for a USB device as described in claim 1, characterized in that, The state transition control state machine is also configured with: In response to the determination that the USB has entered the reset state, the USB enters the high-speed handshake detection and starts the high-speed handshake detection to determine whether the USB supports high-speed transmission. If yes, the USB enters high-speed transmission mode; otherwise, the USB operates in full-speed mode and remains in a reset state until it receives a signal from the host to cancel the reset state and then enters the general operating state. In response to the determination that the USB has entered a suspended state, the clock of the state transition control unit (300) is turned off, so that the state transition control unit (300) enters a low power state. Upon detecting a wake-up request from the host, the USB enters wake-up state; In response to the detection that the host has finished sending the wake-up status request, the USB enters the general working state after a preset delay time.

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