FPGA-based high-speed hybrid multiplier and integrated circuit chip
By using a high-speed hybrid multiplier based on FPGA and combining it with different carry adders, the multiplier structure is optimized, which solves the shortcomings of existing multipliers in terms of speed, area and power consumption, and achieves more efficient computing and lightweight design.
Patent Information
- Application Number
- CN202411335301.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-01-07
AI Technical Summary
Existing multipliers have room for improvement in terms of speed, area, and power consumption, especially when dealing with complex calculations, making them difficult to meet the needs of electronic devices.
A high-speed hybrid multiplier based on FPGA is adopted, which optimizes the multiplier structure by using four 8-bit select-carry adders, two 12-bit select-carry adders and one 16-bit select-carry adder, combined with Hancarlson, Weinberger and Ling adders, to improve computation speed and reduce area.
It achieves reduced multiplier latency, improved computational efficiency, reduced device size, and lower power consumption, making it suitable for various scenarios such as image processing, cryptography, and artificial intelligence.
Smart Images
Figure CN119271171A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of multiplication operation units, and in particular to a high-speed hybrid multiplier and an integrated circuit chip based on FPGA. Background Art
[0002] At present, with the development and iteration of smart products, electronic devices are rapidly updating in the direction of small size, low power consumption and high speed. For electronic products, their speed depends on arithmetic operations. At the same time, in the current intelligent era, the application of multimedia, artificial intelligence, machine learning, deep learning, Internet of Things and other technologies also involves huge basic arithmetic calculations. Multiplication operation is an important computing unit in the processor, which determines the overall performance. Designing the processing module of any electronic device requires a high-speed multiplier.
[0003] For multipliers, their speed, area and power consumption are the main indicators of application. Speed determines the computing efficiency of devices and models. High speed means low latency and increased efficiency. Area determines the size and cost of chips and devices, limiting their development in compact devices. Power consumption affects the energy consumption and heat generation of devices. Currently, existing multipliers are based on traditional algorithms and structures, and there is still much room for improvement in the above indicators when processing complex operations. Summary of the invention
[0004] In order to overcome the deficiencies of the above technologies, the present invention provides a high-speed hybrid multiplier and integrated circuit chip based on FPGA, which uses a hybrid adder to simultaneously add the partial products generated by every two consecutive multiplier bits to calculate the final product of the multiplier, thereby improving the calculation speed and reducing the size of the device.
[0005] The technical solution adopted by the present invention to overcome the technical problems is: to provide a high-speed hybrid multiplier based on FPGA, comprising:
[0006] 4 8-bit carry-select adders, each 8-bit carry-select adder consists of two stages, each stage is 4 bits, and the output of the first stage of the 8-bit carry-select adder is the input of its second stage;
[0007] 2 12-bit carry-select adders, each 12-bit carry-select adder consists of three stages, each stage is 4 bits, the output of the first stage of the 12-bit carry-select adder is the input of its second stage, the output of the second stage of the 12-bit carry-select adder is the input of its third stage, the output of the second stage of the first 8-bit carry-select adder and the output of the second stage of the second 8-bit carry-select adder are used as the input of the first stage of the first 12-bit carry-select adder, the output of the second stage of the third 8-bit carry-select adder and the output of the second stage of the fourth 8-bit carry-select adder are used as the input of the first stage of the second 12-bit carry-select adder;
[0008] A 16-bit carry-select adder is composed of four stages, each stage is 4 bits, the output of the first stage of the 16-bit carry-select adder is the input of its second stage, the output of the second stage of the 16-bit carry-select adder is the input of its third stage, the output of the third stage of the 16-bit carry-select adder is the input of its fourth stage, the output of the third stage of the first 12-bit carry-select adder and the output of the third stage of the second 12-bit carry-select adder are the input of the first stage of the 16-bit carry-select adder.
[0009] Furthermore, the first stage of the 8-bit carry select adder is a Hancarlson adder.
[0010] Furthermore, the second stage of the 8-bit carry select adder is a Weinberger adder.
[0011] Furthermore, the first stage of the 12-bit carry select adder is a Hancarlson adder.
[0012] Furthermore, the second stage of the 12-bit carry select adder is a Weinberger adder.
[0013] Furthermore, the third stage of the 12-bit carry select adder is a Ling adder.
[0014] Furthermore, the first stage of the 16-bit carry select adder is a Hancarlson adder.
[0015] Furthermore, the second stage and the third stage of the 16-bit carry select adder are both Weinberger adders.
[0016] Furthermore, the fourth stage of the 16-bit carry select adder is a Hancarlson adder with BEC.
[0017] On the other hand, the present invention also relates to an integrated circuit chip, comprising the aforementioned FPGA-based high-speed hybrid multiplier.
[0018] The beneficial effects of the present invention are:
[0019] (1) Through the reasonable mixed use and structure of adders, the multiplier delay is reduced and the efficiency is improved, and the performance is improved compared to the existing multipliers.
[0020] (2) Compared with the existing multiplier, the volume is reduced and lightweight can be achieved.
[0021] (3) It has broad application prospects and can be applied to multipliers with different inputs. It can be applied to image processing, cryptography, artificial intelligence, the Internet of Things, and many other scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a structural diagram of an 8-bit mixed adder of the present invention;
[0023] Figure 2 It is a structural diagram of a 12-bit mixed adder of the present invention;
[0024] Figure 3 It is a structural diagram of a 16-bit mixed adder of the present invention;
[0025] Figure 4 is a structural diagram of a hybrid multiplier of the present invention;
[0026] Figure 5 Structural diagram generated for the partial product of the present invention. DETAILED DESCRIPTION
[0027] The following is combined with Figure 1 To Attachment Figure 5 The preferred embodiments of the present invention are described in detail so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.
[0028] In the description of the present invention, it should be noted that the embodiments described in the present invention are only part of the embodiments of the present invention, rather than all of the embodiments; based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention.
[0029] The terms "first", "second", etc. in the specification and claims of this article and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of this article described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.
[0030] Example 1
[0031] As attached Figure 4 As shown, a high-speed hybrid multiplier based on FPGA includes:
[0032] 4 8-bit carry-select adders, each 8-bit carry-select adder consists of two stages, each stage is 4 bits, and the output of the first stage of the 8-bit carry-select adder is the input of its second stage.
[0033] Two 12-bit carry-select adders, each 12-bit carry-select adder consists of three stages, each stage is 4 bits, the output of the first stage of the 12-bit carry-select adder is the input of its second stage, the output of the second stage of the 12-bit carry-select adder is the input of its third stage, the output of the second stage of the first 8-bit carry-select adder and the output of the second stage of the second 8-bit carry-select adder are used as the input of the first stage of the first 12-bit carry-select adder, the output of the second stage of the third 8-bit carry-select adder and the output of the second stage of the fourth 8-bit carry-select adder are used as the input of the first stage of the second 12-bit carry-select adder.
[0034] A 16-bit carry-select adder is composed of four stages, each stage is 4 bits, the output of the first stage of the 16-bit carry-select adder is the input of its second stage, the output of the second stage of the 16-bit carry-select adder is the input of its third stage, the output of the third stage of the 16-bit carry-select adder is the input of its fourth stage, the output of the third stage of the first 12-bit carry-select adder and the output of the third stage of the second 12-bit carry-select adder are the input of the first stage of the 16-bit carry-select adder.
[0035] Mixed adders of different sizes are used to simultaneously add the partial products generated by every two consecutive multiplier bits to calculate the final product of the multiplier. By simulating and verifying the multiplier proposed in the present invention and comparing it with other excellent multipliers currently available, the speed of the multiplier can be increased by 7%-35%, and the area is also reduced to a certain extent, thereby reducing the critical path delay and can be used for high-performance computing.
[0036] As attached Figure 1 , Attachment Figure 2 , Attachment Figure 3 As shown, in this embodiment, the first stage of the 8-bit carry-select adder is a Hancarlson adder. The second stage of the 8-bit carry-select adder is a Weinberger adder. The first stage of the 12-bit carry-select adder is a Hancarlson adder. The second stage of the 12-bit carry-select adder is a Weinberger adder. The third stage of the 12-bit carry-select adder is a Ling adder. The first stage of the 16-bit carry-select adder is a Hancarlson adder. The second and third stages of the 16-bit carry-select adder are both Weinberger adders. The fourth stage of the 16-bit carry-select adder is a Hancarlson adder with BEC.
[0037] The feasible values of the input carry (i.e., 0 or 1) of each stage of the carry select adder are determined in advance, and the sum is calculated in advance. The addition results of two possible carries (0 and 1) are calculated simultaneously, and then the final result is selected based on the actual carry. It divides the addition process into multiple blocks, and two results are calculated simultaneously in each block (one assuming the carry is 0 and the other assuming the carry is 1), and then a selection is made at the end of the block based on the actual carry. It is generally constructed using a dual-path ripple carry adder and a multiplexer to select the final carry and sum output. This adder reduces the carry propagation time and improves the operating speed.
[0038] The Hancarlson adder is designed using the principle of parallel prefix addition and is a combination of the KoggeStone and BrentKung adders. The KoggeStone adder can provide less delay, while the BrentKung adder occupies less area. The adder formed by the combination of the two has obvious advantages over other adders.
[0039] In the carry select adder, the ripple carry adder is changed to a Ling adder, which can achieve lower latency and smaller area than the ripple carry adder. The modified adder is called a Ling-carry select adder.
[0040] The Weinberger adder is an adder based on the algorithm and circuit design proposed by Weinberger. It uses the Weinberger recursive algorithm to reduce the delay of the adder. The BK adder is replaced by the Weinberger adder to form a Weinberger-carry select adder. It can take into account power consumption, efficiency and area at the same time.
[0041] The structure of the adder of the present invention is created by using a hybrid adder, i.e., multiple logic circuits. It includes input signals, intermediate modules, and outputs. Different adder technologies are used in the intermediate modules to generate sum and carry outputs. The above-mentioned adders each have their own advantages. In order to improve the speed and area utilization of the multiplier, the above-mentioned adders are incorporated into different modules and levels of the multiplier. Under the premise of ensuring area and power consumption, the delay of the adder is focused on, and a new hybrid selection carry adder is proposed.
[0042] The structure of the multiplier proposed by the present invention is an 8*8 multiplier. In this structure, partial products are generated through a series of AND gates. Partial product generation is the first process of multiplication. A logical AND operation is performed on each bit of the multiplier to obtain a partial product. For example, an 8*8 multiplier has an 8-bit multiplier A (A0 to A7) and a multiplier B (B0 to B7). In partial product generation, the first step involves a logical AND operation of each bit of multiplier A and the multiplication number B0 (LSB), and the result is stored in C0 (8 bits), which is mathematically expressed as C0[0]=B0 AND A0, C0[1]=B0 AND A1..., C0[7]=B0AND A7. Similarly, the B1 multiplication number and each bit of multiplier A and the result are stored in C1 (8 bits), and so on.
[0043] The proposed hybrid multiplier consists of 3 stages. In each stage, hybrid adders of different sizes are used. That is, the first stage uses 8-bit carry select adders (4-bit each for Hancarlson adder and Weinberger adder), the second stage uses 12-bit carry select adders (4-bit each for Hancarlson adder, Weinberger adder and Ling adder), and the third stage uses 16-bit carry select adders (4-bit each for Hancarlson, Weinberger adder and Hancarlson with BEC circuit).
[0044] The first stage consists of 8-bit carry select adders for 4 numbers. In this stage, the bits of every two consecutive partial products are added simultaneously. The output of each adder is passed to the input of the next adder. The second stage adder consists of two 12-bit adders. In this stage, the outputs of the first stage are added simultaneously and the result is passed to the last stage 16-bit carry select adder. This 16-bit adder output is the final result of the 8*8 multiplier.
[0045] By comparing the multiplier proposed in the present invention with other excellent multipliers currently available through simulation and verification, the speed of the multiplier can be increased by 7%-35%, and the area is also reduced to a certain extent, thereby reducing the critical path delay and can be used for high-performance computing.
[0046] Example 2
[0047] An integrated circuit chip includes the FPGA-based high-speed hybrid multiplier described in Example 1.
[0048] It should be understood that in the embodiments of this document, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects before and after are in an "or" relationship.
[0049] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this article.
[0050] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0051] In the several embodiments provided herein, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.
[0052] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of this article.
[0053] In addition, each functional unit in each embodiment of this invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
[0054] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this article is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of this article. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.
[0055] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A high-speed hybrid multiplier based on FPGA, characterized in that: include: 4 8-bit carry-select adders, each 8-bit carry-select adder consists of two stages, each stage is 4 bits, and the output of the first stage of the 8-bit carry-select adder is the input of its second stage; 2 12-bit carry-select adders, each 12-bit carry-select adder consists of three stages, each stage is 4 bits, the output of the first stage of the 12-bit carry-select adder is the input of its second stage, the output of the second stage of the 12-bit carry-select adder is the input of its third stage, the output of the second stage of the first 8-bit carry-select adder and the output of the second stage of the second 8-bit carry-select adder are used as the input of the first stage of the first 12-bit carry-select adder, the output of the second stage of the third 8-bit carry-select adder and the output of the second stage of the fourth 8-bit carry-select adder are used as the input of the first stage of the second 12-bit carry-select adder; A 16-bit carry-select adder is composed of four stages, each stage is 4 bits, the output of the first stage of the 16-bit carry-select adder is the input of its second stage, the output of the second stage of the 16-bit carry-select adder is the input of its third stage, the output of the third stage of the 16-bit carry-select adder is the input of its fourth stage, the output of the third stage of the first 12-bit carry-select adder and the output of the third stage of the second 12-bit carry-select adder are the input of the first stage of the 16-bit carry-select adder.
2. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The first stage of the 8-bit carry select adder is the Hancarlson adder.
3. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The second stage of the 8-bit carry select adder is the Weinberger adder.
4. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The first stage of the 12-bit carry-select adder is the Hancarlson adder.
5. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The second stage of the 12-bit carry select adder is the Weinberger adder.
6. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The third stage of the 12-bit carry select adder is the Ling adder.
7. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The first stage of the 16-bit carry select adder is the Hancarlson adder.
8. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The second and third stages of the 16-bit carry-select adder are Weinberger adders.
9. The high-speed hybrid multiplier based on FPGA according to claim 1, characterized in that: The fourth stage of the 16-bit carry select adder is a Hancarlson adder with BEC.
10. An integrated circuit chip, characterized in that: The invention comprises the FPGA-based high-speed hybrid multiplier as described in any one of claims 1 to 9.