A QSPI serial port transfer method, system and storage medium thereof

Abstract

The present application provides a QSPI serial port transfer method, system and storage medium thereof. By responding to the serial port signal sent by the QSPI serial port host, identifying the target instruction according to the serial port signal, and determining the total data interaction direction of the internal communication interface according to the target instruction; then, reading the first configuration information of the instruction register and determining the target flash memory among multiple flash memories according to the first configuration information; then, reading the second configuration information of the instruction register and determining the target partition bit in the target flash memory according to the second configuration information, and setting the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions; finally, when the number of target flash memories is multiple, according to the total data interaction direction, controlling the target storage partitions in the multiple target flash memories to synchronously perform data transfer with the QSPI serial port host in a triple modular redundancy manner, so that the QSPI serial port host can easily implement the triple modular redundancy transmission function during the process of reading flash memory data.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular, to a QSPI serial port transfer method, system, and storage medium thereof. Background Art

[0002] In a space environment, data in a memory chip is prone to error flipping due to interference from cosmic radiation. Therefore, in the application of spacecraft, triple modular redundancy technology is often required to back up and correct stored data.

[0003] In an aerospace application scenario, a traditional QSPI serial port host controls multiple flash chips through multiple chip select signal lines. However, during the process of reading multiple flash chips, it does not support the triple modular redundancy transmission function. In order to add the triple modular redundancy function, it is necessary to modify the circuit design code inside QSPI serial port hosts of different manufacturers, which makes it very cumbersome to implement the triple modular redundancy function in the QSPI serial port host. Moreover, in an aerospace application scenario, the QSPI serial port host often requires two different startup programs, and two startup programs need to be equipped with two flash chips, which greatly increases the data storage cost of the QSPI serial port host. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose a QSPI serial port transfer method, system, and storage medium thereof. By changing the overall data interaction direction inside the transfer controller, the QSPI serial port host can easily implement the triple modular redundancy transmission function during the process of reading flash data, and during the data exchange process, the partition bit of the flash storage address is set to one, thereby dividing the flash storage address into two, so that the QSPI serial port host can burn two different startup programs based on the same flash, reducing the data storage cost of the QSPI serial port host.

[0005] To achieve the above object, a first aspect of the embodiments of this application proposes a QSPI serial port transfer method, which is applied to a serial port transfer system. The serial port transfer system includes a transfer controller, an instruction register, a QSPI serial port host, and multiple flash memories. The transfer controller is communicatively connected to the instruction register, the QSPI serial port host, and the flash memories respectively. The QSPI serial port transfer method includes:

[0006] The transfer controller responds to a serial port signal sent by the QSPI serial port host, identifies a target instruction according to the serial port signal, and determines the overall data interaction direction of the internal communication interface according to the target instruction;

[0007] The transfer controller reads first configuration information of the instruction register and determines a target flash memory that needs data interaction among multiple flash memories according to the first configuration information;

[0008] The transfer controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions, and the target storage partitions are located on both sides of the target partition bit;

[0009] When the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories to synchronously perform data transfer with the QSPI serial port host in a triple modular redundancy manner according to the total data interaction direction.

[0010] Further, in some embodiments, the QSPI serial port transfer method further includes:

[0011] When the number of target flash memories is one, the transfer controller controls the target storage partition in the target flash memory to perform data transfer with the QSPI serial port host according to the total data interaction direction.

[0012] Further, in some embodiments, the transfer controller is provided with a timing counter, and in response to the serial port signal sent by the QSPI serial port host, the target instruction is identified according to the serial port signal, including:

[0013] In response to the serial port signal sent by the QSPI serial port host, continuously read and detect the clock signal sent by the QSPI serial port host, and set the timing count value of the timing counter to the initial count value;

[0014] Whenever the clock signal enters the falling edge state, increment the timing count value by 1 until the timing count value is equal to the first preset value, lock and identify the instruction code of the instruction register in the current rotation to obtain the target instruction, and reset the timing count value to the initial count value.

[0015] Further, in some embodiments, in response to the serial port signal sent by the QSPI serial port host, identifying the target instruction according to the serial port signal further includes:

[0016] Whenever the clock signal enters the rising edge state, save the data transmitted by the QSPI serial port host to the instruction register.

[0017] Further, in some embodiments, determining the total data interaction direction in the serial port data transfer process according to the target instruction includes:

[0018] According to the target instruction, query and determine multiple to-be-executed time-sharing transfer tasks in the preset instruction table;

[0019] Obtain the first status mapping table, and query the working status corresponding to the transfer controller when executing each time-sharing transfer task in the first status mapping table to obtain multiple target working statuses that are asynchronous to each other;

[0020] Obtain the second state mapping table, and query the data interaction sub-directions of the transfer controller in each target working state in the second state mapping table;

[0021] Combine each data interaction sub-direction according to the time-sharing sequence of each time-sharing transfer task to obtain the total data interaction direction.

[0022] Further, in some embodiments, setting the value of the target partition bit to one includes:

[0023] When the target working state of the transfer controller is the address state, continuously detect the timing count value of the timing counter;

[0024] When the timing count value of the counter is equal to the second preset value, determine the current moment as the partition moment, where the partition moment is the moment when the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit;

[0025] At the partition moment, send partition data with a value of one to the target flash memory to set the value of the target partition bit to one.

[0026] Further, in some embodiments, the serial port transfer system further includes an error flag register, which is communicatively connected to the transfer controller. During the process of controlling the data transfer between the target storage partition in multiple target flash memories and the QSPI serial port host in a triple modular redundancy manner, the serial port transfer method further includes the following steps:

[0027] When the target working state of the transfer controller is the read state, respectively read the flash output parameters output from the target storage partition of each target flash memory to the transfer controller;

[0028] Align the bit positions of each flash output parameter, and compare whether the values on the same bit position in each flash output parameter are the same;

[0029] When the values on the same bit position in each flash output parameter are different, determine the bit position with different values as the error bit, correct the value of the error bit, and send an error signal to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory corresponding to the error bit according to the error signal.

[0030] Further, in some embodiments, the types of the error signal include a high-level signal type and a low-level signal type. After sending the error signal to the error flag register, the serial port transfer method further includes the following steps:

[0031] Continuously detect whether the value of the error bit has been corrected;

[0032] When the value of the error bit has been corrected, determine whether the type of the error signal is a high-level signal type;

[0033] When the type of the error signal is a high-level signal type, send an error clearing signal to the error flag register to clear the comparison error flag.

[0034] To achieve the above object, a second aspect of the embodiments of the present application provides a serial port transfer system, including:

[0035] A transfer controller, an instruction register, a QSPI serial port host, an error flag register, and multiple flash memories. The transfer controller is communicatively connected to the instruction register, the QSPI serial port host, the flash memories, and the error flag register respectively;

[0036] The transfer controller is configured to, in response to a serial port signal sent by the QSPI serial port host, identify a target instruction according to the serial port signal, and determine the total data interaction direction during the data transfer process according to the target instruction;

[0037] The transfer controller is further configured to read the first configuration information of the instruction register and determine a target flash memory that needs data interaction from multiple flash memories according to the first configuration information;

[0038] The transfer controller is further configured to read the second configuration information of the instruction register, and determine a target partition bit of the physical storage address in the target flash memory according to the second configuration information, and set the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions, and the target storage partitions are located on both sides of the target partition bit;

[0039] The transfer controller is further configured to, when the number of target flash memories is multiple, control the target storage partitions in the multiple target flash memories and the QSPI serial port host to perform data transfer in a triple modular redundancy manner according to the total data interaction direction.

[0040] To achieve the above object, a third aspect of the embodiments of the present application provides a storage medium, which is a computer-readable storage medium, and the storage medium stores a computer program. When the computer program is executed by a processor, the serial port transfer method in the first aspect of the embodiments is implemented.

[0041] In the embodiments of the present application, the following beneficial effects are achieved: The present application enables the transfer controller to respond to the serial port signal sent by the QSPI serial port host, identify the target instruction according to the serial port signal, and determine the overall data interaction direction of the internal communication interface according to the target instruction. Then, the transfer controller reads the first configuration information of the instruction register and determines the target flash memory that requires data interaction among multiple flash memories according to the first configuration information. Next, the transfer controller reads the second configuration information of the instruction register and determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions, with the target storage partitions located on both sides of the target partition bit. Finally, when the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories to synchronously perform data transfer with the QSPI serial port host in a triple modular redundancy manner based on the overall data interaction direction. Furthermore, based on the overall data interaction direction inside the transfer controller, the QSPI serial port host can easily implement the triple modular redundancy transmission function during the process of reading flash memory data, and set the partition bit of the flash memory storage address to one during the data exchange process to divide the flash memory storage address into two, enabling the QSPI serial port host to burn two different boot programs based on the same flash memory, thereby reducing the data storage cost of the QSPI serial port host. Description of the Drawings

[0042] Figure 1 is a flowchart of the QSPI serial port transfer method provided by some embodiments of the present application;

[0043] Figure 2 is a schematic diagram of the jump of the working state of the transfer controller provided by some embodiments of the present application;

[0044] Figure 3 is a flowchart of the QSPI serial port transfer method provided by some other embodiments of the present application;

[0045] Figure 4 is a flowchart of identifying the target instruction according to the serial port signal provided by some embodiments of the present application;

[0046] Figure 5 is a flowchart of identifying the target instruction according to the serial port signal provided by some other embodiments of the present application;

[0047] Figure 6 is a flowchart of determining the overall data interaction direction according to the target instruction provided by some embodiments of the present application;

[0048] Figure 7 is a flowchart of setting the value of the target partition bit to one provided by some embodiments of the present application;

[0049] Figure 8 and9 It is a flowchart after sending an error signal to an error flag register provided by some embodiments of the present application;

[0050] Figure 10 It is a flowchart of data transfer synchronization between a target flash memory and a QSPI serial host in a triple modular redundancy manner provided by some embodiments of the present application;

[0051] Figure 11 It is a schematic diagram of the hardware structure of an electronic device provided by some embodiments of the present application. Detailed implementation manners

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0053] In the description of the present application, it should be understood that for orientation descriptions, such as up, down, front, back, left, right, etc., the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application.

[0054] It should also be noted that in the description of the present application, the meaning of several is more than one, the meaning of multiple is more than two, greater than, less than, exceeding, etc. are understood as not including the recited number, and above, below, within, etc. are understood as including the recited number. If there is a description of first and second, it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0056] In the description of the present application, the descriptions with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0057] First, several terms involved in this application are parsed as follows:

[0058] Triple Modular Redundancy (TMR) means that the same data is pre - stored in three memories. When the circuit works, the controller reads these three memories simultaneously. If the data from these three memories is not completely consistent, then the same data among them is selected, commonly known as "two - out - of - three". Among them, this data specifically refers to binary data. The binary data of a single bit has only two states, 0 and 1. Therefore, there is no situation where the data of the same bit in the three memories is completely inconsistent.

[0059] In the aerospace application scenario, the traditional QSPI serial host controls multiple flash chips through multiple chip - select signal lines. However, during the process of reading multiple flash chips, it does not support the triple - modular - redundancy transmission function. In order to add the triple - modular - redundancy function, it is necessary to modify the circuit - design code inside the QSPI serial hosts of different manufacturers, which makes it very cumbersome to implement the triple - modular - redundancy function for the QSPI serial host. Moreover, in the aerospace application scenario, the QSPI serial host often requires two different boot programs, and two boot programs need to be equipped with two flash chips, which greatly increases the data - storage cost of the QSPI serial host.

[0060] Based on this, in response to the serial signal sent by the QSPI serial host, the transfer controller of this application identifies the target instruction according to the serial signal, and determines the total direction of data interaction of the internal communication interface according to the target instruction. Then, the transfer controller reads the first configuration information of the instruction register, and determines the target flash for data interaction among multiple flashes according to the first configuration information. Next, the transfer controller reads the second configuration information of the instruction register, and determines the target partition bit of the physical storage address in the target flash according to the second configuration information, and sets the value of the target partition bit to one to divide the target flash into multiple target storage partitions, and the target storage partitions are located on both sides of the target partition bit. Finally, when the number of target flashes is multiple, the transfer controller controls the target storage partitions in the multiple target flashes to synchronously perform data transfer with the QSPI serial host in a triple - modular - redundancy manner according to the total direction of data interaction. Thus, based on the total direction of data interaction inside the transfer controller, the QSPI serial host can easily implement the triple - modular - redundancy transmission function during the process of reading flash data, and set the partition bit of the flash storage address to one during the data - exchange process to divide the storage address of the flash into two parts, so that the QSPI serial host can burn two different boot programs based on the same flash, reducing the data - storage cost of the QSPI serial host.

[0061] A QSPI serial port conversion method, system and storage medium provided by an embodiment of the present application will be specifically described through the following embodiments.

[0062] In a first aspect, a QSPI serial port conversion method in an embodiment of the present application will be first described. The QSPI serial port conversion method is applied to a serial port conversion system, and the serial port conversion system includes a conversion controller, an instruction register, a QSPI serial port host, and multiple flash memories. The conversion controller is communicatively connected to the instruction register, the QSPI serial port host, and the flash memories respectively.

[0063] Refer to Figure 1 shown in Figure 1 is a flowchart of the QSPI serial port conversion method provided by some embodiments of the present application. The QSPI serial port conversion method may include but is not limited to steps S101 to S105.

[0064] Step S101: The conversion controller responds to the serial port signal sent by the QSPI serial port host, identifies the target instruction according to the serial port signal, and determines the total data interaction direction of the internal communication interface according to the target instruction.

[0065] Among them, the serial port signal sent by the QSPI serial port host is the chip select signal qspi_slv_csn, and data interaction between the QSPI serial port host and the conversion controller is performed through a slave interface.

[0066] Specifically, the conversion controller responds to the chip select signal qspi_slv_csn sent by the QSPI serial port host. At this time, the slave interface of the conversion controller detects that the current chip select signal is active low, and the conversion controller jumps from the idle type of working state to the instruction type of working state. Then the conversion controller identifies the target instruction according to the serial port signal, and determines the total data interaction direction of the internal communication interface according to the target instruction.

[0067] It should be noted that the working states of the conversion controller include: idle state (IDLE), instruction state (INSTR), address state (ADDR), opcode state (MODE), dummy cycle state (DUNNY), read state (READ), program state (PRGRM), and unknown state (X). Among them, the asynchronous jump relationship between each working state is as Figure 2 shown in Figure 2It is a schematic diagram of the state jump of the transfer controller provided by some embodiments of the present application. When the transfer controller is in the idle state, it can jump to the instruction state; when the transfer controller is in the instruction state, it can jump to the address state or the unknown state; when the transfer controller is in the unknown state, it can jump to the idle state; when the transfer controller is in the address state, it can jump to the opcode state, the idle cycle state, the read state, or the write state; when the transfer controller is in the opcode state, it can jump to the idle cycle state or the read state; when the transfer controller is in the idle cycle state, it can jump to the read state; when the transfer controller is in the read state, it can jump to the idle state; when the transfer controller is in the write state, it can jump to the idle state.

[0068] Step S102: The transfer controller reads the first configuration information of the instruction register and determines the target flash memory that needs data interaction among multiple flash memories according to the first configuration information.

[0069] Among them, the multiple flash memories include the first flash memory (Flash0), the second flash memory (Flash1), and the third flash memory (Flash2). The instruction register is preset with the first configuration information, and the first configuration information includes the first configuration signal qspi_cs_sel. The bit width of the first configuration signal qspi_cs_sel is 2. When the value of the first configuration signal qspi_cs_sel is 0, it means that the transfer controller needs to control the first flash memory to perform data interaction with the QSPI serial port host; when the value of the first configuration signal qspi_cs_sel is 1, it means that the transfer controller needs to control the second flash memory to perform data interaction with the QSPI serial port host; when the value of the first configuration signal qspi_cs_sel is 2, it means that the transfer controller needs to control the third flash memory to perform data interaction with the QSPI serial port host; when the value of the first configuration signal qspi_cs_sel is 3, it means that the transfer controller needs to control the first flash memory, the second flash memory, and the third flash memory to perform data interaction with the QSPI serial port host.

[0070] In an optional embodiment, the transfer controller reads the first configuration information of the instruction register and obtains that the value of the corresponding first configuration signal qspi_cs_sel is 3. Then, according to the value of the first configuration signal qspi_cs_sel being 3, it determines the target flash memory that needs data interaction among multiple flash memories, that is, the target flash memories include the first flash memory (Flash0), the second flash memory (Flash1), and the third flash memory (Flash2).

[0071] In an alternative embodiment, the transfer controller reads the first configuration information of the instruction register and obtains that the value corresponding to the first configuration signal qspi_cs_sel is 0. Then, according to the value of 0 of the first configuration signal qspi_cs_sel, the target flash memory that needs data interaction is determined among multiple flash memories, that is, the target flash memory includes the first flash memory (Flash0).

[0072] Step S103: The transfer controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions.

[0073] Among them, the instruction register is also preset with second configuration information. The first configuration information includes the second configuration signal qspi_half_enable and the third configuration signal qspi_cs_sel. The second configuration signal qspi_half_enable is used to select which bit of the storage address of the target flash memory as the target partition bit, and the third configuration signal qspi_cs_sel is used to divide the storage address of the target flash memory into two, so that the target partition bit of the target flash memory is fixed at 1.

[0074] Specifically, the transfer controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration signal in the second configuration information, and sets the value of the target partition bit to one according to the third configuration signal in the second configuration information to divide the target flash memory into multiple target storage partitions.

[0075] It should be noted that the target storage partitions are located on both sides of the target partition bit.

[0076] Step S104: When the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories to synchronously perform data transfer with the QSPI serial port host in a triple modular redundancy manner according to the total data interaction direction.

[0077] In an alternative embodiment, when the target flash memory includes the first flash memory (Flash0), the second flash memory (Flash1), and the third flash memory (Flash2), that is, when the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories to synchronously perform data transfer with the QSPI serial port host in a triple modular redundancy manner according to the total data interaction direction.

[0078] Further, referring to Figure 3 shown Figure 3 is a flowchart of a QSPI serial port transfer method provided by some other embodiments of the present application. The QSPI serial port transfer method may include but is not limited to step S301.

[0079] Step S301: When the number of target flash memories is one, the transfer controller controls data transfer between the target storage partition in the target flash memory and the QSPI serial port host according to the total data interaction direction.

[0080] In an alternative embodiment, when the target flash memory includes the first flash memory (Flash0), that is, when the number of target flash memories is one, the transfer controller controls data transfer between the target storage partition in the target flash memory and the QSPI serial port host according to the total data interaction direction.

[0081] Furthermore, the transfer controller is provided with a timing counter, and a timing count value is set in the timing counter.

[0082] Refer to Figure 4 as shown Figure 4 is a flowchart for identifying a target instruction according to a serial port signal provided by some embodiments of the present application. The method for identifying a target instruction according to a serial port signal may include, but is not limited to, steps S401 to S402.

[0083] Step S401: In response to the serial port signal sent by the QSPI serial port host, continuously read and detect the clock signal sent by the QSPI serial port host, and set the timing count value of the timing counter to the initial count value.

[0084] In a possible implementation manner, the transfer controller, in response to the serial port signal sent by the QSPI serial port host, continuously reads and detects the clock signal qspi_slv_sclk sent by the QSPI serial port host, and sets the timing count value of the timing counter to 0.

[0085] Wherein, the initial count value can be 0, or 1, or 10, and the present application does not make specific limitations.

[0086] Step S402: Whenever the clock signal enters the falling edge state, increment the timing count value by 1 until the timing count value is equal to the first preset value, lock and identify the instruction code rotated by the instruction register in the current cycle to obtain the target instruction, and reset the timing count value to the initial count value.

[0087] In a possible implementation manner, whenever the transfer controller detects that the clock signal qspi_slv_sclk enters the falling edge state, increment the timing count value by 1 until the timing count value is equal to the first preset value of 7, lock and identify the instruction code rotated by the instruction register in the current cycle to obtain the target instruction, and reset the timing count value to 0.

[0088] It should be noted that the instruction codes rotated by the instruction register are shown in the following table:

[0089]

[0090] Referring to Figure 5 as shown Figure 5 is a flowchart for identifying a target instruction according to a serial port signal provided by some other embodiments of the present application. The QSPI serial port transfer method may include, but is not limited to, step S501.

[0091] Step S501: Whenever the clock signal enters the rising edge state, save the data transmitted by the QSPI serial port host to the instruction register.

[0092] Among them, whenever the transfer controller detects that the clock signal qspi_slv_sclk enters the rising edge state, save the data transmitted by the QSPI serial port host (i.e., the data on the slave interface) to the instruction register.

[0093] Referring to Figure 6 as shown Figure 6 is a flowchart for determining the total data interaction direction according to the target instruction provided by some embodiments of the present application. The method for determining the total data interaction direction according to the target instruction may include, but is not limited to, steps S601 to S604.

[0094] Step S601: According to the target instruction, query and determine multiple pending time-sharing transfer tasks in a preset instruction table.

[0095] In a possible implementation manner, for a target instruction of the read ID type, multiple pending time-sharing transfer tasks queried in the preset instruction table are as follows: The first time-sharing transfer task is that the transfer controller receives an 8-bit instruction code from the QSPI serial port host, the second time-sharing transfer task is to receive 24-bit or 32-bit address data in the QSPI serial port host, the third time-sharing transfer task is to receive an 8-bit operation code (dual-line I / O mode and four-line I / O mode) from the QSPI serial port host, the fourth time-sharing transfer task is to receive 4 empty cycles from the QSPI serial port host (four-line mode), and the fifth time-sharing transfer task is that the transfer controller circularly sends the read ID transmitted from the target flash to the QSPI serial port host.

[0096] In a possible implementation, for instructions of the read data type, multiple pending time-sharing transfer tasks are queried in a preset instruction table as follows: The first time-sharing transfer task is that the transfer controller receives an 8-bit instruction code from the QSPI serial port host; the second time-sharing transfer task is to receive 24-bit or 32-bit address data from the QSPI serial port host; the third time-sharing transfer task is to receive an 8-bit operation code (dual-line I / O mode and four-line I / O mode) from the QSPI serial port host; the fourth time-sharing transfer task is to receive 8 or 4 or 2 or 0 idle cycles from the QSPI serial port host (each instruction is different); the fifth time-sharing transfer task is that the transfer controller circularly sends the read data transferred from the target flash to the QSPI serial port host.

[0097] In a possible implementation, for instructions of the write data type, multiple pending time-sharing transfer tasks are queried in a preset instruction table as follows: The first time-sharing transfer task is that the transfer controller first receives an 8-bit instruction code from the QSPI serial port host; the second time-sharing transfer task is to receive 24-bit or 32-bit address data from the QSPI serial port host; the third time-sharing transfer task is that the transfer controller continuously receives the write data from the QSPI serial port host.

[0098] Step S602: Obtain the first status mapping table, and query the working status corresponding to the transfer controller when executing each time-sharing transfer task in the first status mapping table to obtain multiple target working statuses that are asynchronous to each other.

[0099] In a possible implementation, for instructions of the read data type, the working status corresponding to the time-sharing transfer task "the transfer controller receives an 8-bit instruction code from the QSPI serial port host" queried in the first status mapping table is the instruction status; the working status corresponding to the time-sharing transfer task "receive 24-bit or 32-bit address data from the QSPI serial port host" is the address status; the working status corresponding to the time-sharing transfer task "receive an 8-bit operation code in the QSPI serial port host" is the operation code status; the working status corresponding to the time-sharing transfer task "receive 8 or 4 or 2 or 0 idle cycles from the QSPI serial port host" is the idle cycle status; the working status corresponding to the time-sharing transfer task "the transfer controller circularly sends the read data transferred from the target flash to the QSPI serial port host" is the read status.

[0100] In a possible implementation, for instructions of the programming data type, the working state corresponding to the time-sharing transfer task "the transfer controller receives an 8-bit instruction code from the QSPI serial port host" is queried in the first state mapping table as the instruction state; the working state corresponding to the time-sharing transfer task "receives 24-bit or 32-bit address data from the QSPI serial port host" is the address state; the working state corresponding to the time-sharing transfer task "the transfer controller continuously receives programming data from the QSPI serial port host" is the programming state

[0101] Step S603: Obtain a second state mapping table and query the data interaction sub-directions of the transfer controller in each target working state in the second state mapping table.

[0102] In a possible implementation, when the target flash memory includes the first flash memory (Flash0) and the target working state is the instruction state, the data interaction sub-direction is as follows: The data of the QSPI serial port host is transmitted to the transfer controller (i.e., the slave interface of the transfer controller is in the input state), and the data of the transfer controller is transmitted to the target flash memory (i.e., the host interface of the transfer controller is in the output state).

[0103] In a possible implementation, when the target flash memory includes the third flash memory (Flash2) and the target working state is the instruction state, the data interaction sub-direction is as follows: The data of the QSPI serial port host is transmitted to the transfer controller (i.e., the slave interface of the transfer controller is in the input state), and the data of the transfer controller is transmitted to the target flash memory (i.e., the host interface of the transfer controller is in the output state).

[0104] In a possible implementation, when the target flash memory includes the first flash memory (Flash0), the second flash memory (Flash1), and the third flash memory (Flash2) and the target working state is the instruction state, the data interaction sub-direction is as follows: The data of the QSPI serial port host is transmitted to the transfer controller (i.e., the slave interface of the transfer controller is in the input state), and the data of the transfer controller is transmitted to the target flash memory (i.e., the host interface of the transfer controller is in the output state).

[0105] In a possible implementation, when the target flash memory includes the second flash memory (Flash1) and the target working state is the instruction state, the data interaction sub-direction is as follows: The data of the transfer controller is transmitted to the QSPI serial port host (i.e., the slave interface of the transfer controller is in the output state), and the data of the target flash memory is transmitted to the transfer controller (i.e., the host interface of the transfer controller is in the input state).

[0106] In a possible implementation, for a target instruction being a Fast Read Quad I / O instruction, the data interaction sub-directions in the address state and the opcode state are as follows: The data of the QSPI serial host is transmitted to the transfer controller (i.e., the slave interface of the transfer controller is in the input state), and the data of the transfer controller is transmitted to the target flash memory (i.e., the host interface of the transfer controller is in the output state); the data of the transfer controller is transmitted to the QSPI serial host (i.e., the slave interface of the transfer controller is in the output state), and the data of the target flash memory is transmitted to the transfer controller (i.e., the host interface of the transfer controller is in the input state).

[0107] Step S604: Combine each data interaction sub-direction according to the time-sharing sequence of each time-sharing transfer task to obtain the total data interaction direction.

[0108] Specifically, combine each data interaction sub-direction according to the time-sharing sequence of each time-sharing transfer task to obtain the total data interaction direction.

[0109] Refer to Figure 7 shown Figure 7 is a flowchart for setting the value of the target partition bit to one provided by some embodiments of the present application. The setting the value of the target partition bit to one may include but is not limited to steps S701 to S703.

[0110] Step S701: When the target working state of the transfer controller is the address state, continuously detect the timing count value of the timing counter.

[0111] Specifically, when the target working state of the transfer controller is the address state, continuously detect the timing count value of the timing counter.

[0112] Step S702: When the timing count value of the counter is equal to the second preset value, determine the current moment as the partitioning moment.

[0113] Wherein, the partitioning moment is the moment when the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit.

[0114] It should be noted that the second preset value is used to confirm that at the current moment, the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit.

[0115] Step S703: At the partitioning moment, send partition data with a value of one to the target flash memory to set the value of the target partition bit to one.

[0116] Specifically, at the partitioning moment, send partition data with a value of one to the target flash memory to set the value of the target partition bit to one.

[0117] Furthermore, the serial port conversion system further includes an error flag register, and the error flag register is communicatively connected to the conversion controller.

[0118] Refer to Figure 8 as shown in Figure 8 FIG. 8 is a flowchart of synchronously performing data conversion between a target flash memory and a QSPI serial port host in a triple modular redundancy manner according to some embodiments of the present application. The method may include, but is not limited to, steps S801 to S803.

[0119] Step S801: When the target working state of the conversion controller is the read state, read the flash output parameters output from the target storage partitions of each target flash memory to the conversion controller.

[0120] In a possible implementation, when the target flash memory includes a first flash memory (Flash0), a second flash memory (Flash1), and a third flash memory (Flash2), and the target working state of the conversion controller is the read state, read the flash output parameters output from the target storage partitions of the first flash memory, the second flash memory, and the third flash memory to the conversion controller (i.e., the first flash output parameter, the second flash output parameter, and the third flash output parameter).

[0121] Step S802: Align the bit positions of each flash output parameter, and compare whether the values of the same bit position in each flash output parameter are the same.

[0122] In a possible implementation, when the target flash memory includes a first flash memory (Flash0), a second flash memory (Flash1), and a third flash memory (Flash2), align the bit positions of the first flash output parameter, the second flash output parameter, and the third flash output parameter, and compare whether the values of the same bit position in each flash output parameter are the same.

[0123] Step S803: When the values of the same bit position in each flash output parameter are different, determine the bit position with different values as the error bit, correct the value of the error bit, and send an error signal to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory corresponding to the error bit according to the error signal.

[0124] In a possible implementation, when the value of the first bit in the first flash output parameter is 0, while the values of the first bits in the second flash output parameter and the third flash output parameter are both 1, it is confirmed that the value of the first bit in the first flash output parameter is inconsistent with the values of the first bits in other flash output parameters. Then, the first bit in the first flash output parameter is confirmed as an error bit, and the value of this error bit is corrected from 0 to 1 (i.e., the value of the first bit in the first flash output parameter is consistent with the values of the first bits in other flash output parameters). Then, an error signal qspi_slv_tmr_err_cs0 is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash corresponding to the error bit (i.e., the first flash) according to the error signal qspi_slv_tmr_err_cs0 or the error signal qspi_slv_tmr_err_tgl.

[0125] In a possible implementation, when the value of the second bit in the second flash output parameter is 1, while the values of the second bits in the first flash output parameter and the third flash output parameter are both 0, it is confirmed that the value of the second bit in the second flash output parameter is inconsistent with the values of the second bits in other flash output parameters. Then, the second bit in the second flash output parameter is confirmed as an error bit, and the value of this error bit is corrected from 1 to 0 (i.e., the value of the second bit in the second flash output parameter is consistent with the values of the second bits in other flash output parameters). Then, an error signal qspi_slv_tmr_err_cs1 is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash corresponding to the error bit (i.e., the second flash) according to the error signal qspi_slv_tmr_err_cs1 or the error signal qspi_slv_tmr_err_tgl.

[0126] In a possible implementation, when the value of the third bit in the third flash output parameter is 0, while the values of the third bits in the first flash output parameter and the second flash output parameter are both 1, it is confirmed that the value of the third bit in the third flash output parameter is inconsistent with the values of the third bits in other flash output parameters. Then, the third bit in the third flash output parameter is confirmed as an error bit, and the value of this error bit is corrected from 0 to 1 (i.e., the value of the third bit in the third flash output parameter is consistent with the values of the third bits in other flash output parameters). Then, an error signal qspi_slv_tmr_err_c2 is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash (i.e., the third flash) corresponding to the error bit according to the error signal qspi_slv_tmr_err_cs2 or the error signal qspi_slv_tmr_err_tgl.

[0127] Among them, the types of error signals include high-level signal types and low-level signal types. The types of the error signals qspi_slv_tmr_err_cs0, qspi_slv_tmr_err_cs1, and qspi_slv_tmr_err_cs2 are all high-level signal types, and the error signal qspi_slv_tmr_err_tgl is a low-level signal type.

[0128] Refer to Figure 9 as shown Figure 9 is a flowchart after sending an error signal to the error flag register provided by some embodiments of the present application. The method may include, but is not limited to, steps S901 to S903.

[0129] Step S901: Continuously detect whether the value of the error bit has been corrected.

[0130] Step S902: When the value of the error bit has been corrected, determine whether the type of the error signal is a high-level signal type.

[0131] Specifically, when the value of the error bit has been corrected, determine whether the type of the error signal is a high-level signal type.

[0132] Step S903: When the type of the error signal is a high-level signal type, send an error clearing signal to the error flag register so that the comparison error flag is cleared.

[0133] Specifically, when the type of the error signal is a high-level signal type (i.e., the error signal qspi_slv_tmr_err_cs0 or the error signal qspi_slv_tmr_err_cs1 or the error signal qspi_slv_tmr_err_cs2), an error clearing signal qspi_slv_tmr_err_clr is sent to the error flag register to clear the comparison error flag.

[0134] It should be noted that the reset value of the error signal qspi_slv_tmr_err_tgl is low level, and the level flips every time an error occurs. When the level flips, the comparison error flag is automatically cleared.

[0135] In a second aspect, an embodiment of the present application further provides a serial port transfer system. Refer to Figure 10 , Figure 10 which is a schematic structural diagram of the serial port transfer system provided by some embodiments of the present application. The serial port transfer system 1000 includes:

[0136] A transfer controller 1001, an instruction register 1002, a QSPI serial port host 1003, an error flag register 1004, and a plurality of flash memories 1005. The transfer controller 1001 is communicatively connected to the instruction register 1002, the QSPI serial port host 1003, the flash memories 1005, and the error flag register 1004 respectively;

[0137] The transfer controller 1001 is configured to, in response to a serial port signal sent by the QSPI serial port host 1003, identify a target instruction according to the serial port signal, and determine the total data interaction direction during the data transfer process according to the target instruction;

[0138] The transfer controller 1001 is further configured to read first configuration information of the instruction register 1002 and determine a target flash memory 1005 that needs data interaction among the plurality of flash memories 1005 according to the first configuration information;

[0139] The transfer controller 1001 is further configured to read second configuration information of the instruction register 1002, and determine a target partition bit of the physical storage address in the target flash memory 1005 according to the second configuration information, and set the value of the target partition bit to one to divide the target flash memory 1005 into a plurality of target storage partitions, and the target storage partitions are located on both sides of the target partition bit;

[0140] The transfer controller 1001 is further configured to, when the number of target flash memories 1005 is multiple, control the target storage partitions in the plurality of target flash memories 1005 to perform data transfer with the QSPI serial port host 1003 in a triple modular redundancy manner according to the total data interaction direction.

[0141] The above serial port transfer system 1000 and the above QSPI serial port transfer method are based on the same inventive concept. The above process describes the serial port transfer system 900 of the embodiments of the present application. By the transfer controller responding to the serial port signal sent by the QSPI serial port host, identifying the target instruction according to the serial port signal, and determining the general data interaction direction of the internal communication interface according to the target instruction; then, the transfer controller reads the first configuration information of the instruction register, and determines the target flash memory that needs data interaction among multiple flash memories according to the first configuration information; next, the transfer controller reads the second configuration information of the instruction register, and determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one to divide the target flash memory into multiple target storage partitions, and the target storage partitions are located on both sides of the target partition bit; finally, when the number of target flash memories is multiple, the transfer controller controls the target storage partitions in the multiple target flash memories to synchronously perform data transfer with the QSPI serial port host in a triple modular redundancy manner according to the general data interaction direction, thereby enabling the QSPI serial port host to simply implement the triple modular redundancy transmission function during the process of reading flash memory data based on the general data interaction direction inside the transfer controller, and setting the partition bit of the flash memory storage address to one during the data exchange process to divide the storage address of the flash memory into two, so that the QSPI serial port host can burn two different startup programs based on the same flash memory, reducing the data storage cost of the QSPI serial port host.

[0142] The embodiments of the present application also provide an electronic device. The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the above QSPI serial port transfer method and / or cache data reading method. The electronic device can be any intelligent terminal including a mobile phone, a tablet computer, an in-vehicle computer, etc.

[0143] Please refer to Figure 11 , Figure 11 which is a schematic diagram of the hardware structure of the electronic device provided by some embodiments of the present application. The electronic device includes:

[0144] A processor 1101, which can be implemented by using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., and is used to execute relevant programs to implement the QSPI serial port transfer method and / or cache data reading method provided by the embodiments of the present application;

[0145] The memory 1102 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM), etc. The memory 1102 can store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 1102, and are called by the processor 1101 to execute the QSPI serial port conversion method and / or the cache data reading method provided in the embodiments of this application;

[0146] The input / output interface 1103 is used to implement information input and output;

[0147] The communication interface 1104 is used to implement communication and interaction between this device and other devices. It can communicate through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0148] The bus 1105 transmits information between the various components of the device (such as the processor 1101, the memory 1102, the input / output interface 1103, and the communication interface 1104);

[0149] Among them, the processor 1101, the memory 1102, the input / output interface 1103, and the communication interface 1104 are communicatively connected to each other inside the device through the bus 1105.

[0150] The embodiments of this application also provide a computer-readable storage medium. This computer-readable storage medium stores a computer program. When this computer program is executed by a processor, the QSPI serial port conversion method and / or the cache data reading method provided in the embodiments of this application are executed.

[0151] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory can optionally include memories that are remotely arranged relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0152] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0153] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than those shown, or combine certain steps, or different steps.

[0154] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0155] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations.

[0156] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0157] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item) of the following" or its similar expression refers to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0158] In several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the above division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0159] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0160] In addition, each functional unit in various embodiments of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0161] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on such understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media that can store programs such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0162] The preferred embodiments of the embodiments of this application have been described above with reference to the accompanying drawings, which does not limit the scope of the rights of the embodiments of this application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of this application shall be within the scope of the rights of the embodiments of this application.

Claims

1. A QSPI serial port transfer method, characterized in that: Applied to a serial port transfer system, the serial port transfer system includes a transfer controller, an instruction register, a QSPI serial port host and multiple flash memories, the transfer controller is respectively connected to the instruction register, the QSPI serial port host and the flash memories for communication, and the QSPI serial port transfer method includes: The transfer controller responds to the serial port signal sent by the QSPI serial port host, identifies the target instruction according to the serial port signal, and determines the overall direction of data interaction of the internal communication interface according to the target instruction; The transfer controller reads the first configuration information of the instruction register, and determines a target flash memory requiring data interaction among the plurality of flash memories according to the first configuration information; The transfer controller reads the second configuration information of the instruction register, determines the target partition bit of the physical storage address in the target flash memory according to the second configuration information, and sets the value of the target partition bit to one, so as to divide the target flash memory into a plurality of target storage partitions, the target storage partitions being located on both sides of the target partition bit; When there are multiple target flash memories, the transfer controller controls the target storage partitions in the multiple target flash memories to transfer data synchronously with the QSPI serial port host in a triple-mode redundant manner according to the general direction of data interaction; Wherein, determining the overall direction of data interaction of the internal communication interface according to the target instruction comprises the following steps: According to the target instruction, searching and determining a plurality of time-sharing transfer tasks to be executed in a preset instruction table; Acquire a first state mapping table, and query the first state mapping table for the corresponding working state of the switching controller when executing each of the time-sharing switching tasks, to obtain a plurality of target working states that are asynchronous to each other; Acquire a second state mapping table, and query the second state mapping table for the data interaction sub-direction of the transfer controller in each of the target working states; The data interaction sub-directions are combined according to the time-sharing sequence of the time-sharing switching tasks to obtain the overall data interaction direction.

2. The QSPI serial port transfer method according to claim 1, wherein: The QSPI serial port transfer method also includes: When the number of the target flash memory is one, the transfer controller transfers data between the target storage partition in the target flash memory and the QSPI serial port host according to the general direction of data interaction.

3. The QSPI serial port transfer method according to claim 1, wherein: The transfer controller is provided with a timing counter, which responds to the serial port signal sent by the QSPI serial port host and identifies the target instruction according to the serial port signal, including: In response to the serial port signal sent by the QSPI serial port host, continuously read and detect the clock signal sent by the QSPI serial port host, and set the timing count value of the timing counter to an initial count value; Whenever the clock signal enters a falling edge state, the timing count value is incremented by 1 until the timing count value is equal to a first pre-designed value, the instruction code of the instruction register in the current rotation is locked and identified, the target instruction is obtained, and the timing count value is reset to the initial count value.

4. The QSPI serial port transfer method according to claim 3, wherein: The method of responding to the serial port signal sent by the QSPI serial port host and identifying the target instruction according to the serial port signal also includes: Whenever the clock signal enters a rising edge state, the data transmitted by the QSPI serial port host is saved in the instruction register.

5. The serial port switching method according to claim 3, characterized in that: The step of setting the value of the target partition bit to one includes: When the target working state of the transfer controller is the address state, continuously detecting the timing count value of the timing counter; When the timing count value of the timing counter is equal to the second pre-designed value, the current moment is determined as the partition moment, and the partition moment is the moment when the bit address of the data sent by the transfer controller to the target flash memory overlaps with the target partition bit; At the partition time, partition data with a value of one is sent to the target flash memory to set the value of the target partition bit to one.

6. The serial port switching method according to claim 1, characterized in that: The serial port transfer system further includes an error flag register, which is in communication with the transfer controller. In the process of controlling the target storage partitions in the plurality of target flash memories to transfer data with the QSPI serial port host in a triple-mode redundant manner, the serial port transfer method further includes the following steps: When the target working state of the switching controller is a reading state, respectively reading the flash memory output parameters outputted from the target storage partitions of each target flash memory to the switching controller; Aligning the bits of the flash memory output parameters, and comparing whether the values ​​of the same bit in the flash memory output parameters are consistent; When the values ​​on the same bit in each of the flash memory output parameters are inconsistent, the bit with the inconsistent value is determined as an error bit, the value of the error bit is corrected, and an error signal is sent to the error flag register, so that the error flag register marks a comparison error flag in the target flash memory corresponding to the error bit according to the error signal.

7. The serial port switching method according to claim 6, characterized in that: The types of the error signal include a high level signal type and a low level signal type. After sending the error signal to the error flag register, the serial port switching method further includes the following steps: Continuously detecting whether the erroneous value has been corrected; When the value of the error bit has been corrected, determining whether the type of the error signal is a high level signal type; When the type of the error signal is a high level signal type, an error clearing signal is sent to the error flag register so that the comparison error flag is cleared.

8. A serial port switching system, characterized in that: include: A transfer controller, an instruction register, a QSPI serial port host, an error flag register and a plurality of flash memories, wherein the transfer controller is communicatively connected with the instruction register, the QSPI serial port host, the flash memory and the error flag register respectively; The transfer controller is configured to, in response to a serial port signal sent by the QSPI serial port host, identify a target instruction according to the serial port signal, and determine a general direction of data interaction in a data transfer process according to the target instruction; The switching controller is further configured to read the first configuration information of the instruction register, and determine the target flash memory requiring data interaction among the plurality of flash memories according to the first configuration information; The switching controller is further configured to read second configuration information of the instruction register, and determine a target partition bit of a physical storage address in the target flash memory according to the second configuration information, and set a value of the target partition bit to one, so as to divide the target flash memory into a plurality of target storage partitions, the target storage partitions being located on both sides of the target partition bit; The transfer controller is further configured to, when there are multiple target flash memories, control multiple target storage partitions of one of the multiple target flash memories to transfer data with the QSPI serial port host in a triple-mode redundant manner according to the general direction of data interaction; Wherein, determining the overall direction of data interaction of the internal communication interface according to the target instruction comprises the following steps: According to the target instruction, searching and determining a plurality of time-sharing transfer tasks to be executed in a preset instruction table; Acquire a first state mapping table, and query the first state mapping table for the corresponding working state of the switching controller when executing each of the time-sharing switching tasks, to obtain a plurality of target working states that are asynchronous to each other; Acquire a second state mapping table, and query the second state mapping table for the data interaction sub-direction of the transfer controller in each of the target working states; The data interaction sub-directions are combined according to the time-sharing sequence of the time-sharing switching tasks to obtain the overall data interaction direction.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the serial port switching method according to any one of claims 1 to 7 is implemented.

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