A method and system for aligning the delay of clock signals in a circuit reverse labeling simulation environment

Abstract

The present invention discloses a method and system for aligning the delay of clock signals in a circuit back-labeling simulation environment. The present invention includes the following steps: determining the clock signal delay requirement of the input port of the module to be tested in the circuit back-labeling simulation environment; determining the clock signal delay requirement of the output port of the module to be tested in the circuit back-labeling simulation environment; combining the two clock signal delay requirements to obtain the required clock signal delay range; and performing delay alignment on the clock signals in the circuit back-labeling simulation environment according to the required clock signal delay range. The present invention aims to improve the efficiency of circuit back-labeling simulation and accelerate the progress of back-labeling simulation. The present invention innovatively obtains the delay alignment time of the clock signal through delay calculation, avoiding multiple iterative simulations in the back-labeling simulation environment in the traditional method, and effectively accelerating the simulation progress.

Description

Technical Field

[0001] The present invention relates to a circuit function simulation technology in a digital circuit, and in particular to a method and system for aligning a clock signal delay in a circuit reverse labeling simulation environment. Background Art

[0002] Digital sequential circuit design generally requires functional simulation before hardware implementation to confirm that the designed functions are correct. The simulation environment should be able to meet the requirements of each stage of circuit design, including the requirements of the non-delay simulation stage and the requirements of the delayed back-labeling simulation stage.

[0003] In digital sequential circuits, all sequential logics exchange data uniformly at the moment when the clock signal arrives. In functional simulation without considering circuit delay, the delay of the clock signal from the generation point to the timing device using the clock signal is negligible, and the clock signal-related circuits are all zero delay. In the digital sequential circuit simulation environment, in addition to the module under test using the clock signal, other circuits connected to the module under test will also use the same clock signal, so the clock signal from the generation point to these circuits is also zero delay. However, when the physical design of the circuit under test is completed and the delay back-annotation simulation is performed, the delay from the clock input point in the circuit under test to the timing device using the clock signal is no longer zero delay, but the actual delay of the circuit. However, the clock signal used by other circuits connected to the module under test in the original simulation environment is still zero delay, which does not match the delay of the clock signal in the circuit under test. The interface timing that originally meets the requirements of the module under test may cause timing violations due to this mismatch, resulting in simulation failure. At this time, the clock signal needs to be delayed for a period of time to align with the clock delay of the module under test and then transmitted separately to the timing device outside the module under test. In this way, the interface of the module under test can meet the timing requirements in the simulation environment and the back-labeling simulation can proceed normally.

[0004] The traditional solution to clock signal delay alignment is to observe the waveform, find the delay range of the clock signal of the module under test in the simulation waveform where the timing violation occurs, and mark it in the interface-related circuit of the simulation environment for alignment to solve the timing violation problem of the interface of the module under test in the simulation environment. This method can generally solve the problem of interface timing violation after multiple iterative checks. Since the clock signal usually controls the input and output signals of the module under test at the same time, the waveforms of a large number of interface signals in complex logic circuits need to be recorded and searched to try to solve the interface timing violation, and the circuit back-annotation simulation speed is very slow, so the traditional method is very inefficient. Summary of the invention

[0005] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a method and system for delay alignment of clock signals in a circuit back-labeling simulation environment are provided. The present invention aims to improve the efficiency of circuit back-labeling simulation and accelerate the progress of back-labeling simulation.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A method for aligning the delay of a clock signal in a circuit back-annotation simulation environment comprises the following steps:

[0008] Determine the clock signal delay requirements of the input port of the module under test in the circuit back-annotation simulation environment;

[0009] Determine the clock signal delay requirements of the output port of the module under test in the circuit back-annotation simulation environment;

[0010] The two clock signal delay requirements are combined to obtain the required clock signal delay range;

[0011] The clock signal in the circuit back-annotation simulation environment is delayed and aligned according to the required clock signal delay range.

[0012] Optionally, determining the clock signal delay requirement of the input port of the module to be tested in the circuit back-annotation simulation environment includes:

[0013] Select any input port of the module to be tested, and determine the hold time constraint and setup time constraint of the input port according to the circuit structure of the input port in the circuit back-annotation simulation environment;

[0014] For the hold time constraint and setup time constraint of the input port, the delay of the circuit other than the module to be tested in the circuit back-annotation simulation environment is set to zero, so as to obtain the simplified hold time constraint and setup time constraint of the input port;

[0015] According to the need for the input port to simultaneously satisfy the simplified hold time constraint and setup time constraint, the relevant clock signal delay maximum value and minimum value that the input port simultaneously satisfies the simplified hold time constraint and setup time constraint are determined as the clock signal delay requirement of the input port of the module to be tested.

[0016] Optionally, the step of determining a clock signal delay requirement of an output port of a module to be tested in a circuit reverse-annotation simulation environment includes:

[0017] Select any output port of the module to be tested, and determine the hold time constraint and setup time constraint of the output port according to the circuit structure of the output port in the circuit back-annotation simulation environment;

[0018] For the hold time constraint and setup time constraint of the output port, the delay of the circuit other than the module to be tested in the circuit back-annotation simulation environment is set to zero, so as to obtain the simplified hold time constraint and setup time constraint of the output port;

[0019] According to the need for the output port to simultaneously satisfy the simplified hold time constraint and setup time constraint, the relevant clock signal delay maximum value and minimum value that the output port simultaneously satisfies the simplified hold time constraint and setup time constraint are determined as the clock signal delay requirement of the output port of the module to be tested.

[0020] Optionally, the merging of the two clock signal delay requirements to obtain the required clock signal delay range includes: selecting a larger minimum delay value between the minimum delay value of the clock signal delay requirement of each input port of the module to be tested and the minimum delay value of the clock signal delay requirement of each output port of the module to be tested as the combined minimum delay value; selecting a smaller maximum delay value between the maximum delay value of the clock signal delay requirement of each input port of the module to be tested and the maximum delay value of the clock signal delay requirement of each output port of the module to be tested as the combined maximum delay value, thereby obtaining the required clock signal delay range consisting of the combined minimum delay value and the combined maximum delay value.

[0021] Optionally, the delay alignment of the clock signal in the circuit back-labeling simulation environment according to the required clock signal delay range includes: selecting a delay value within the required clock signal delay range as a target delay value; delaying the clock signal of the non-back-labeled circuit connected to the module to be tested by the target delay value, thereby achieving delay alignment to meet the timing requirements of the hold time and setup time of all circuits.

[0022] Optionally, delaying the clock signal of the non-inverted circuit connected to the module under test by the target delay value refers to inserting a target delay value into the clock signal of the non-inverted circuit connected to the module under test using a hardware description language to perform delay alignment.

[0023] In addition, the present invention also provides a delay alignment system for clock signals in a circuit back-marking simulation environment, comprising:

[0024] An input port delay requirement determination program unit is used to determine the clock signal delay requirement of the input port of the module to be tested in the circuit back-annotation simulation environment;

[0025] An output port delay requirement determination program unit is used to determine the clock signal delay requirement of the output port of the module to be tested in the circuit back-annotation simulation environment;

[0026] A delay requirement merging program unit is used to merge the two clock signal delay requirements to obtain the required clock signal delay range;

[0027] The delay alignment execution program unit is used to perform delay alignment on the clock signal in the circuit back-annotation simulation environment according to the required clock signal delay range.

[0028] In addition, the present invention also provides a delay alignment system for clock signals in a circuit back-marking simulation environment, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the delay alignment method for clock signals in the circuit back-marking simulation environment.

[0029] In addition, the present invention also provides a computer-readable storage medium, which stores a computer program or instruction, and the computer program or instruction is programmed or configured to execute the delay alignment method of the clock signal in the circuit back-labeling simulation environment through a processor.

[0030] In addition, the present invention also provides a computer program product, including a computer program or an instruction, wherein the computer program or the instruction is programmed or configured to execute the delay alignment method of the clock signal in the circuit back-annotation simulation environment through a processor.

[0031] Compared with the prior art, the present invention mainly has the following advantages: in order to improve the efficiency of circuit back-labeling simulation and accelerate the progress of back-labeling simulation, the present invention includes the following steps: determining the clock signal delay requirement of the input port of the module to be tested in the circuit back-labeling simulation environment; determining the clock signal delay requirement of the output port of the module to be tested in the circuit back-labeling simulation environment; combining the two clock signal delay requirements to obtain the required clock signal delay range; and performing delay alignment on the clock signal in the circuit back-labeling simulation environment according to the required clock signal delay range. The present invention innovatively obtains the delay alignment time of the clock signal through delay calculation, thereby avoiding multiple iterative simulations in the back-labeling simulation environment in the traditional method and effectively accelerating the simulation progress. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention.

[0033] Figure 2 Schematic diagram of the clock and data path delay of the input port of the module under test in an embodiment of the present invention.

[0034] Figure 3 Schematic diagram of the clock and data path delay of the output port of the module under test in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] like Figure 1 As shown, the method for aligning the delay of the clock signal in the circuit back-annotation simulation environment of this embodiment includes the following steps:

[0036] Determine the clock signal delay requirements of the input port of the module under test in the circuit back-annotation simulation environment;

[0037] Determine the clock signal delay requirements of the output port of the module under test in the circuit back-annotation simulation environment;

[0038] The two clock signal delay requirements are combined to obtain the required clock signal delay range;

[0039] The clock signal in the circuit back-annotation simulation environment is delayed and aligned according to the required clock signal delay range.

[0040] In this embodiment, determining the clock signal delay requirement of the input port of the module to be tested in the circuit back-annotation simulation environment includes:

[0041] Select any input port of the module to be tested, and determine the hold time constraint and setup time constraint of the input port according to the circuit structure of the input port in the circuit back-annotation simulation environment;

[0042] For the hold time constraint and setup time constraint of the input port, the delay of the circuit other than the module to be tested in the circuit back-annotation simulation environment is set to zero, so as to obtain the simplified hold time constraint and setup time constraint of the input port;

[0043] According to the need for the input port to simultaneously satisfy the simplified hold time constraint and setup time constraint, the relevant clock signal delay maximum value and minimum value that the input port simultaneously satisfies the simplified hold time constraint and setup time constraint are determined as the clock signal delay requirement of the input port of the module to be tested.

[0044] Figure 2 Schematic diagram of the clock and data path delay of the input port of the module to be tested in this embodiment. The module to be tested is within the dotted line in the figure, and the circuit outside the dotted line is connected to the module to be tested in the reverse-label simulation environment. Clock is the clock signal, and the register in the example can be represented as any timing device. Figure 2 In the figure, Cin1 is the delay from the clock signal clock to the register CK in the reverse-annotated simulation environment; Cin2 is the delay from the clock signal to the clock signal input port of the module under test; Cin3 is the delay from the clock signal input port of the module under test to the CK of the internal register of the module; Din1 is the delay from the data output Q of the external register to the data input port of the module under test; Din2 is the delay from the data input port of the module under test to the data input D of the internal register. In addition, let Tj be the delay from the clock input terminal CK of the register to the data output terminal Q, Tc be the period of the clock, Thold be the hold time of the register, and Tsetup be the setup time of the register. Figure 2 As shown, select any input port of the module to be tested, determine the hold time constraint of the input port according to the circuit structure of the input port in the circuit back-annotation simulation environment, and when establishing the time constraint, the hold time constraint should meet the following conditions:

[0045] Cin1+Tj+Din1+Din2>Cin2+Cin3+Thold (1)

[0046] The following conditions should be met to establish time constraints:

[0047] Cin1+Tj+Din1+Din2 <Tc+Cin2+Cin3–Tsetup (2)

[0048] Because the circuit outside the module under test in the simulation environment is a zero-delay functional simulation circuit, Cin2=0, Din1=0, Tj=0, and Cin1 is the clock path that needs to be delayed aligned. Therefore, by simplifying formula (1), we can get:

[0049] Cin1>Cin3+Thold-Din2 (3)

[0050] By simplifying formula (2), we can get:

[0051] Cin1 <Tc+Cin3–Tsetup–Din2 (4)

[0052] Formula (3) and Formula (4) are simplified hold time constraints and setup time constraints of the input port. Formula (3) and Formula (4) are the timing requirements of a single input port path of the module under test. The parameter values ​​on the right side of Formula (3) and Formula (4) are fixed values ​​after the physical design of the module under test is completed, so the value range of Cin1 is also fixed. The setup time constraint requirements and hold time constraint requirements of all input port related paths should be met at the same time, so from Formula (3) and Formula (4), the value range of Cin1 for all input port related paths of the module under test is as follows:

[0053] Cin1_min>max(Cin3 + Thold - Din2) (5)

[0054] Cin1_max <min(Tc + Cin3 – Tsetup – Din2) (6)

[0055] In formula (5) and formula (6), Cin1_max and Cin1_min are the maximum and minimum delay values ​​of the relevant clock signal for all input ports that simultaneously meet the simplified hold time constraint and setup time constraint. The max and min on the right side of the equation represent the functions of taking the maximum and minimum values ​​of the calculation results of all input ports, respectively. Therefore, formula (5) and formula (6) are the clock signal delay requirements of the input ports of the module under test.

[0056] In this embodiment, determining the clock signal delay requirement of the output port of the module under test in the circuit back-annotation simulation environment includes:

[0057] Select any output port of the module to be tested, and determine the hold time constraint and setup time constraint of the output port according to the circuit structure of the output port in the circuit back-annotation simulation environment;

[0058] For the hold time constraint and setup time constraint of the output port, the delay of the circuit other than the module to be tested in the circuit back-annotation simulation environment is set to zero, so as to obtain the simplified hold time constraint and setup time constraint of the output port;

[0059] According to the need for the output port to simultaneously satisfy the simplified hold time constraint and setup time constraint, the relevant clock signal delay maximum value and minimum value that the output port simultaneously satisfies the simplified hold time constraint and setup time constraint are determined as the clock signal delay requirement of the output port of the module to be tested.

[0060] Figure 3 The schematic diagram of the clock and data path delay of the output port of the module under test is shown in Figure 1. The module under test is inside the dotted line, and the circuit connected to the module under test in the reverse-label simulation environment is outside the dotted line. The clock is Figure 2 With the same clock signal, the registers in the example can be represented as any sequential device. Figure 3 In the example, Cout1 is the delay from the clock signal input port of the module under test to the CK end of the internal register of the module; Cout2 is the delay from the clock signal clock to the clock input port of the module under test; Cout3 is the delay from the clock signal clock to the CK end of the register in the simulation environment; Dout1 is the delay from the Q end of the internal register data output of the module under test to the data output port of the module under test; Dout2 is the delay from the data output port of the module under test to the D end of the external register data input; the definitions of Tj, Tc, Thold and Tsetup are the same as before. Figure 3 As shown, select any output port of the module to be tested, determine the hold time constraint of the output port according to the circuit structure of the output port in the circuit back-annotation simulation environment, and when establishing the time constraint, the hold time constraint should meet the following conditions:

[0061] Cout2+Cout1+Tj+Dout1+Dout2>Cout3+Thold (7)

[0062] The following conditions should be met to establish time constraints:

[0063] Cout2+Cout1+Tj+Dout1+Dout2 <Tc+Cout3–Tsetup (8)

[0064] Because the circuit outside the module under test is a zero-delay functional simulation circuit, Cout2 = 0, Dout2 = 0, and Cout3 is the clock path that needs to be delayed aligned. Therefore, by simplifying formula (7), we can get:

[0065] Cout3 <Cout1+Tj+Dout1-Thold (9)

[0066] By simplifying formula (8), we can get:

[0067] Cout3>Cout1+Tj+Dout1-Tc+Tsetup (10)

[0068] Formulas (9) and (10) are simplified hold time constraints and setup time constraints for the output port. The parameter values ​​on the right side of formulas (9) and (10) are fixed values ​​after the physical design of the module under test is completed, so the value range of Cout3 is also fixed. The setup time constraint requirements and hold time constraint requirements of all output port related paths should be met at the same time, so the value range of Cout3 for all output port related paths of the module under test can be obtained from formulas (9) and (10):

[0069] Cout3_max <min(Cout1+Tj+Dout1-Thold)(11)

[0070] Cout3_min>max(Cout1+Tj+Dout1-Tc+Tsetup) (12)

[0071] In formula (11) and formula (12), Cout3_max and Cout3_min are the maximum and minimum delay values ​​of the relevant clock signal for all output ports that simultaneously meet the simplified hold time constraint and setup time constraint. The max and min on the right side of the equation represent the functions of taking the maximum and minimum values ​​of the calculation results of all output ports, respectively. Therefore, formula (11) and formula (12) are the clock signal delay requirements of the output ports of the module under test.

[0072] In this embodiment, the two clock signal delay requirements are combined to obtain the required clock signal delay range, including: selecting the larger minimum delay value as the combined minimum delay value between the minimum delay value of the clock signal delay requirement of the input port of the module to be tested and the minimum delay value of the clock signal delay requirement of the output port of the module to be tested; selecting the smaller maximum delay value as the combined maximum delay value between the maximum delay value of the clock signal delay requirement of the input port of the module to be tested and the maximum delay value of the clock signal delay requirement of the output port of the module to be tested, thereby obtaining the required clock signal delay range consisting of the combined minimum delay value and the combined maximum delay value. In the reverse-label simulation environment, the clock signal generally only needs to be delayed aligned once before it is connected to the relevant timing device. Assuming the delay time is Tf, it can be seen from the above discussion that Tf should be able to simultaneously satisfy the above-mentioned formulas (5), (6), (11) and (12), that is:

[0073] Tf_max <min(Cin1_max,Cout3_max) (13)

[0074] Tf_min>max(Cin1_min,Cout3_min) (14)

[0075] In equations (13) and (14), Tf_max and Tf_min are the maximum and minimum values ​​of Tf that meet the requirements. Therefore, as long as the four values ​​of Cin1_max, Cout3_max, Cin1_min and Cout3_min are calculated, the range of clock signal delay can be determined.

[0076] It should be noted that this calculation method only includes the main delay items in the timing path calculation. Other factors affecting the delay, such as OCV and noise, are not included in the formula due to their smaller impact, but the scope of use of this embodiment also covers these aspects.

[0077] In this embodiment, the delay alignment of the clock signal in the circuit reverse-labeling simulation environment according to the required clock signal delay range includes: selecting a delay value within the required clock signal delay range as the target delay value; delaying the clock signal of the non-reverse-labeled circuit connected to the module to be tested by the target delay value, thereby achieving delay alignment to meet the timing requirements of the hold time and setup time of all circuits. Specifically, any value within the delay range that satisfies both equations (13) and (14) is taken as the delay value of the clock signal in the reverse-labeling simulation environment. After the clock signal of the non-reverse-labeled circuit connected to the module to be tested is delayed by this time value for alignment, the interface circuit related to the module to be tested can meet the timing requirements.

[0078] As an optional implementation, in this embodiment, delaying the clock signal of the non-inverted circuit connected to the module under test by the target delay value means inserting a target delay value into the clock signal of the non-inverted circuit connected to the module under test using a hardware description language to perform delay alignment. Since the non-inverted circuit is used for behavioral level function simulation, there is no need to insert a buffer for delay.

[0079] In summary, in order to improve the efficiency of reverse labeling simulation, the present embodiment proposes a clock signal delay alignment method in a circuit reverse labeling simulation environment. This method does not need to confirm the effective range of clock signal delay by checking the waveform in the simulation environment, but finds the delay range of the clock signal by timing analysis and calculation. The timing of each input port signal of the module to be tested must meet the requirements of setup time and hold time. The present embodiment can obtain the arrival time window range of the clock signal relative to all input port related timing devices through analysis and calculation. Similarly, all output ports must also meet the requirements of setup time and hold time. The present embodiment can also obtain the arrival time window range of the clock signal relative to all output port related timing devices through calculation. For a circuit that uses the same clock signal to control input signal and output signal related timing devices, the overlapping part of the above two clock arrival time window ranges is the clock signal delay range that meets both the input signal timing requirements and the output signal timing requirements. In this delay range, take any value and mark it on other circuits that use this clock signal connected to the module to be tested in the reverse labeling environment for timing alignment, and you can quickly build a reverse labeling simulation environment that can meet the timing requirements. In this embodiment, it is not necessary to iteratively confirm the effective range of the clock signal by looking at the waveform multiple times, but to directly find the delay range of the clock signal through analysis and calculation, and feed the result back to the reverse-annotation simulation environment. Therefore, the reverse-annotation simulation does not need multiple iterations, and the simulation progress can be greatly accelerated.

[0080] In addition, this embodiment also provides a delay alignment system for clock signals in a circuit back-annotation simulation environment, including:

[0081] An input port delay requirement determination program unit is used to determine the clock signal delay requirement of the input port of the module to be tested in the circuit back-annotation simulation environment;

[0082] An output port delay requirement determination program unit is used to determine the clock signal delay requirement of the output port of the module to be tested in the circuit back-annotation simulation environment;

[0083] A delay requirement merging program unit is used to merge the two clock signal delay requirements to obtain the required clock signal delay range;

[0084] The delay alignment execution program unit is used to perform delay alignment on the clock signal in the circuit back-annotation simulation environment according to the required clock signal delay range.

[0085] In addition, this embodiment also provides a delay alignment system for clock signals in a circuit back-annotation simulation environment, including a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the delay alignment method for clock signals in the circuit back-annotation simulation environment.

[0086] In addition, this embodiment also provides a computer-readable storage medium, which stores a computer program or instruction, and the computer program or instruction is programmed or configured to execute the delay alignment method of the clock signal in the circuit back-annotation simulation environment through a processor.

[0087] In addition, this embodiment also provides a computer program product, including a computer program or instructions, which are programmed or configured to execute the delay alignment method of the clock signal in the circuit back-annotation simulation environment through a processor.

[0088] Those skilled in the art should understand that the technical solutions provided by the embodiments of the present application may be in the form of methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0089] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for aligning the delay of a clock signal in a circuit back-annotation simulation environment, characterized in that: The steps include: Determine the clock signal delay requirements of the input port of the module under test in the circuit back-annotation simulation environment; Determine the clock signal delay requirements of the output port of the module under test in the circuit back-annotation simulation environment; The two clock signal delay requirements are combined to obtain the required clock signal delay range; The combining of the two clock signal delay requirements to obtain the required clock signal delay range includes: selecting a larger minimum delay value between the minimum delay value of the clock signal delay requirement of each input port of the module to be tested and the minimum delay value of the clock signal delay requirement of each output port of the module to be tested as the combined minimum delay value; Selecting a smaller maximum delay value between the maximum delay value required for the clock signal delay of each input port of the module to be tested and the maximum delay value required for the clock signal delay of each output port of the module to be tested as the combined maximum delay value, thereby obtaining a required clock signal delay range consisting of the combined minimum delay value and the combined maximum delay value; The clock signal in the circuit back-annotation simulation environment is delayed and aligned according to the required clock signal delay range.

2. The method for delay alignment of clock signals in a circuit back-annotation simulation environment according to claim 1, characterized in that: Determining the clock signal delay requirement of the input port of the module to be tested in the circuit reverse-annotation simulation environment includes: Select any input port of the module to be tested, and determine the hold time constraint and setup time constraint of the input port according to the circuit structure of the input port in the circuit back-annotation simulation environment; For the hold time constraint and setup time constraint of the input port, the delay of the circuit other than the module to be tested in the circuit back-annotation simulation environment is set to zero, so as to obtain the simplified hold time constraint and setup time constraint of the input port; According to the need for the input port to simultaneously satisfy the simplified hold time constraint and setup time constraint, the relevant clock signal delay maximum value and minimum value that the input port simultaneously satisfies the simplified hold time constraint and setup time constraint are determined as the clock signal delay requirement of the input port of the module to be tested.

3. The method for aligning the delay of a clock signal in a circuit back-annotation simulation environment according to claim 1, characterized in that: Determining the clock signal delay requirement of the output port of the module to be tested in the circuit reverse labeling simulation environment includes: Select any output port of the module to be tested, and determine the hold time constraint and setup time constraint of the output port according to the circuit structure of the output port in the circuit back-annotation simulation environment; For the hold time constraint and setup time constraint of the output port, the delay of the circuit other than the module to be tested in the circuit back-annotation simulation environment is set to zero, so as to obtain the simplified hold time constraint and setup time constraint of the output port; According to the need for the output port to simultaneously satisfy the simplified hold time constraint and setup time constraint, the relevant clock signal delay maximum value and minimum value that the output port simultaneously satisfies the simplified hold time constraint and setup time constraint are determined as the clock signal delay requirement of the output port of the module to be tested.

4. The method for delay alignment of clock signals in a circuit back-annotation simulation environment according to claim 1, characterized in that: The method of delay aligning the clock signal in the circuit back-labeling simulation environment according to the required clock signal delay range includes: selecting a delay value as a target delay value within the required clock signal delay range; delaying the clock signal of the non-back-labeled circuit connected to the module to be tested by the target delay value, thereby achieving delay alignment to meet the timing requirements of the hold time and setup time of all circuits.

5. The method for delay alignment of clock signals in a circuit back-annotation simulation environment according to claim 4, characterized in that: Delaying the clock signal of the non-inverted circuit connected to the module under test by the target delay value refers to inserting a target delay value into the clock signal of the non-inverted circuit connected to the module under test by hardware description language to perform delay alignment.

6. A system for aligning the delay of clock signals in a circuit back-annotation simulation environment, characterized in that: include: An input port delay requirement determination program unit is used to determine the clock signal delay requirement of the input port of the module to be tested in the circuit back-annotation simulation environment; An output port delay requirement determination program unit is used to determine the clock signal delay requirement of the output port of the module to be tested in the circuit back-annotation simulation environment; A delay requirement merging program unit is used to merge the two clock signal delay requirements to obtain the required clock signal delay range; The combining of the two clock signal delay requirements to obtain the required clock signal delay range includes: selecting a larger minimum delay value between the minimum delay value of the clock signal delay requirement of each input port of the module to be tested and the minimum delay value of the clock signal delay requirement of each output port of the module to be tested as the combined minimum delay value; Selecting a smaller maximum delay value between the maximum delay value required for the clock signal delay of each input port of the module to be tested and the maximum delay value required for the clock signal delay of each output port of the module to be tested as the combined maximum delay value, thereby obtaining a required clock signal delay range consisting of the combined minimum delay value and the combined maximum delay value; The delay alignment execution program unit is used to perform delay alignment on the clock signal in the circuit back-annotation simulation environment according to the required clock signal delay range.

7. A system for aligning a clock signal delay in a circuit back-annotation simulation environment, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for delay alignment of clock signals in a circuit back-annotation simulation environment as claimed in any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program or instruction stored therein, characterized in that: The computer program or instruction is programmed or configured to execute the method for delay alignment of clock signals in a circuit back-annotation simulation environment according to any one of claims 1 to 5 through a processor.

9. A computer program product comprising a computer program or instructions, characterized in that The computer program or instruction is programmed or configured to execute the method for delay alignment of clock signals in a circuit back-annotation simulation environment according to any one of claims 1 to 5 through a processor.

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