Integrated circuit and metal layer ECO method thereof

Abstract

The invention discloses an integrated circuit and a metal layer ECO method thereof, redundant logic units are arranged in the integrated circuit for metal layer ECO, and the method comprises the following steps: S1, in a chip layout stage, redundant logic unit arrays are arranged in a layout area according to a certain interval; s2, sequentially and logically connecting the redundant logic units of each redundant logic unit array in pairs; s3, in the wiring stage, wires connected with the input ends and the output ends of the redundant logic units float to an ME2 layer and an ME3 layer; s4, in the ECO stage of the metal layer, if a certain redundant logic unit needs to be used, only the metal wires of the ME2 layer and / or the ME3 layer connected with the input end and the output end of the redundant logic unit need to be modified. By adopting the technical scheme of the invention, the period and the cost required by the Metal ECO stage are greatly reduced, and the working efficiency of chip design is favorably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an integrated circuit and a metal layer ECO method thereof. Background Art

[0002] With the advancement of integration technology, the size of thin-film transistors and metal wiring has continued to shrink, and the scale and integration of chips have significantly increased, which has gradually reduced the reliability and controllability of the process in the chip manufacturing process. Therefore, in the chip design process, the strategy of improving manufacturing reliability by improving the design has become an important link that cannot be ignored. At the same time, with the increase in integration, the cost and expense of chip tape-out have increased rapidly, and cost has become an increasingly important consideration in the chip design process.

[0003] In the digital IC back-end design implementation, it is often necessary to do Function ECO on the chip. Common Function ECO can be divided into two types: Pre-Mask ECO and Post-Mask ECO. Pre-Mask ECO, the full name is Pre-Mask Engineering Change Order, that is, ECO between Freeze and Tape out, refers to the engineering change order before the manufacture of photolithography mask in the integrated circuit (IC) design process. The ECO at this stage is highly flexible, allowing the design team to make relatively extensive modifications to various aspects of the design without being restricted by the difficulty and cost of modification after the mask is made. Post-Mask ECO, the full name is Post-Mask Engineering Change Order, that is, ECO after Tape out, is an engineering change order made in the later stage of integrated circuit (IC) design, when the photolithography mask has been made, but the final metal layer wiring processing has not yet been carried out. Due to the limitations of physical implementation, the ECO at this stage can only make relatively limited modifications that do not involve changes to the base layer. The difference between the two is that the transistors and wiring layers of Pre-Mask ECO have not yet started to make masks, and cells can be added to the Netlist at this time. The transistor layer of Post-MaskECO has already been processed, but the wiring layer has not yet been processed and can still be modified. You can use the pre-reserved redundant logic cells (Spare Cell or ECO Cell) to make logic modifications and change the connection relationship of various existing cells. If you find that there is a problem with the timing later (or want to modify the function), you can use the nearby Spare Cell or ECO Cell with the upper metal connection to modify the circuit structure. However, new cells cannot be added at this stage, which has certain limitations.

[0004] Spare Cell is a spare Cell, that is, a redundant logic unit, which needs to be inserted in advance in the Pre-Place stage (or instantiated in the RTL stage) (it is already in the netlist given by the front end). When there are some design defects that require Post Mask ECO (after Tape out), Spare Cell is used to modify the logic unit, without modifying the Base Layer or Metal Layer to modify the logic relationship. In order to ensure that there are enough logic function Cells available when doing Function ECO, we generally recommend using several types of Cells that can build most of the logic functions. Generally, it will include basic Standard Cells, such as DFF, NAND, AND, XOR, INV, etc. Spare Cell has no logic function when not in use, similar to Filler, and its input and output Pins are not connected to any logic. Therefore, generally speaking, the input Pin of Spare Cell needs to be connected to VDD or VSS through Tie Cell, and the output Pin can be left floating. When the logic needs to be modified, disconnect the input Pin and then re-ECO.

[0005] Metal ECO (metal engineering change order) is a specific type of Post-Mask ECO (post-mask engineering change order), which focuses on the later stage of the integrated circuit (IC) design process. When the photolithography mask has been produced, Metal ECO cannot change the content of the base layer (well, active area, field area, etc.), and can only modify the metal interconnect layer. The modification at this stage is extremely critical because it requires adjusting or redoing the metal connection to fix timing problems, correct design errors or meet new design requirements without changing the underlying transistor structure.

[0006] With the development of Moore's Law, the process of integrated circuits is becoming more and more advanced, but for integrated circuit designers, the cost of tape-out is getting higher and higher. Therefore, after the chip is taped out, in order to save costs, the ECO of the Metal layer is particularly important. The cost of Metal ECO is much lower than the full modification cost of remaking the mask, but it still requires a lot of engineering time and resources. Therefore, its cost-effectiveness lies in the ability to quickly respond to urgent design needs without significantly delaying the project schedule and increasing costs. Correct decision-making and efficient implementation processes are crucial to the successful implementation of Metal ECO.

[0007] Generally speaking, under 28nm process conditions, the price of modifying CONT, ME1, and VI1 is $150,000 per layer, while the price of modifying ME2, VI2, ME3, and ME4 is $50,000 per layer. Generally speaking, since there will be criss-crossing power networks above ME5, the logic routing will be concentrated in the metal layers below ME5, that is, IC design companies will modify CONT, ME1, VI1, ME2, VI2, ME3, and ME4 in the Metal ECO stage. This method costs $500,000 to perform a Metal ECO, which is relatively expensive. If it is possible to control that only two metal layers, ME2 and ME3, and the through-hole layer VI2, are modified in the Metal ECO stage, that is, using relatively cheaper layers to implement the modifications required in the Metal ECO stage, it will only cost $150,000, greatly reducing the cost of Metal ECO.

[0008] Therefore, in view of the defects of the prior art, it is necessary to propose a technical solution to solve the technical problems existing in the prior art. Summary of the invention

[0009] In view of this, it is indeed necessary to provide an integrated circuit and its metal layer ECO method. By setting a redundant logic unit array and logically connecting the redundant logic units of each redundant logic unit array in pairs in turn, it is only necessary to modify the fixed metal layers ME2, ME3 and through-hole layer V2 as needed, which greatly reduces the cycle and cost required for the Metal ECO stage, helps to improve the efficiency of chip design work and reduce ineffective work.

[0010] In order to solve the technical problems existing in the prior art, the technical solution of the present invention is as follows:

[0011] An integrated circuit metal layer ECO method is provided, in which a redundant logic unit is provided in the integrated circuit for use in the metal layer ECO, comprising the following steps:

[0012] Step S1: In the chip layout stage, a redundant logic unit array is arranged in a layout area at a certain interval, wherein the redundant logic unit array includes a plurality of redundant logic units of different types;

[0013] Step S2: logically connecting the redundant logic units of each redundant logic unit array in pairs in sequence;

[0014] Step S3: In the wiring stage, the wiring connecting the input end and the output end of the redundant logic unit is floated to the ME2 layer and the ME3 layer;

[0015] Step S4: In the metal layer ECO stage, if a certain redundant logic unit needs to be used, it is only necessary to modify the metal routing of the ME2 layer and / or ME3 layer connecting the input and output ends of the redundant logic unit.

[0016] As a further improvement, in step S2, some input terminals of the redundant logic unit are connected to "1" or "0" through a clamping unit.

[0017] As a further improvement, the redundant logic unit array is provided with at least seven types of redundant logic units, namely, AND, XOR, NAND, DFF, MUX, OR, and INV.

[0018] As a further improvement solution, only the metal routing of the ME2 layer and / or ME3 layer needs to be modified in the metal layer ECO stage.

[0019] As a further improvement, in step S4, metal routing of the ME2 layer and / or ME3 layer is modified automatically in the metal layer ECO stage, wherein logical and physical modifications are completed by tools to meet the Metal ECO requirements.

[0020] As a further improvement, the metal routing of the ME2 layer and / or ME3 layer is modified in an automatic manner, including the following steps:

[0021] The tool reads the ECO script and completes the logic modification;

[0022] Fixed the DRC violation of Short caused by the change of net name;

[0023] Solidify the metal layers except ME2 and ME3 layers and the via layers except VI2 to ensure that these solidified layers will not be modified during rewinding;

[0024] Set the routing rules for the Net modified in the ECO script, stipulating that it can only be routed in the ME2 and ME3 layers;

[0025] Use tools to perform ECO routing on the modified Net to change the physical connection of the Net according to the requirements of the logic change.

[0026] As a further improvement, the following steps are included to fix the DRC violation of Short caused by the net name change:

[0027] First, find out all the Shorts belonging to the ME1 layer among the DRC violations belonging to Short, and obtain the area of ​​the ME1 layer with Short DRC violations; then obtain the Owner1 of the Pin where the violation occurs in the area, the shape of the ME1 layer connected to it, and the Owner2 of the VIA of the VI1 layer; finally, change the shape where the violation occurs and the Owner2 of the VIA to be the same as the Owner1 of the Pin.

[0028] The present invention also discloses an integrated circuit, which is designed using the above-mentioned integrated circuit metal layer ECO method, and at least a plurality of redundant logic unit arrays are arranged, wherein the redundant logic unit array includes a plurality of redundant logic units of different types, and each redundant logic unit in the redundant logic unit array is logically connected to each other in pairs in sequence, so that the routing connecting the input and output ends of the redundant logic unit can float to the ME2 layer and the ME3 layer during the wiring stage.

[0029] As a further improvement solution, in the metal layer ECO stage, if a certain redundant logic unit needs to be used, it is only necessary to modify the metal routing of the ME2 layer and / or ME3 layer connecting the input and output ends of the redundant logic unit.

[0030] As a further improvement, the redundant logic unit array is provided with at least seven types of redundant logic units, namely, AND, XOR, NAND, DFF, MUX, OR, and INV.

[0031] Compared with the prior art, by setting a redundant logic unit array and logically connecting the redundant logic units of each redundant logic unit array in pairs in sequence, it is only necessary to modify the fixed metal layers ME2, ME3 and the through-hole layer V2 as required, which greatly reduces the cycle and cost required for the Metal ECO stage, helps to improve the efficiency of chip design work and reduce ineffective work; at the same time, the present invention adopts an automated method to allow the tool to complete logical and physical modifications to meet the requirements of Metal ECO, and ensure that the CONT layer, ME1, and VI1 are not modified, thereby controlling costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention is a flowchart of an integrated circuit metal layer ECO method.

[0033] Figure 2 FIG. 4 is a schematic diagram of a redundant logic unit array according to the present invention.

[0034] Figure 3 The figure is a layout effect diagram of a Spare Cell array in one embodiment of the present invention.

[0035] Figure 4Schematic diagram of the internal interconnection of the Spare Cell array in the present invention.

[0036] Figure 5 This is a schematic diagram of the physical connection of Spare Cells in the present invention, taking AND connection with XOR as an example.

[0037] Figure 6 The present invention is a flowchart of a preferred embodiment of the method.

[0038] Figure 7 This is a schematic diagram of an example of Metal ECO modification in the present invention.

[0039] Figure 8 This is a schematic diagram showing an example of the Metal ECO modification results in the present invention. DETAILED DESCRIPTION

[0040] The technical solution provided by the present invention will be further described below in conjunction with the accompanying drawings.

[0041] In the later stages of the IC design process, when the design has been completed and the photolithography mask has been manufactured, if it is found that modifications are needed, Post-Mask ECO can only be performed. In this case, the modifications are usually limited to the metal layer (Metal ECO) to avoid the huge cost of re-manufacturing the mask.

[0042] In order to solve the above technical problems, the present invention sets a redundant logic unit in the integrated circuit for use in the metal layer ECO, see Figure 1 , which is a flowchart of an integrated circuit metal layer ECO method of the present invention, comprising the following steps:

[0043] Step S1: In the chip layout stage, a redundant logic unit array is arranged in a layout area at a certain interval, wherein the redundant logic unit array includes a plurality of redundant logic units of different types;

[0044] Step S2: logically connecting the redundant logic units of each redundant logic unit array in pairs in sequence;

[0045] Step S3: In the wiring stage, the wiring connecting the input end and the output end of the redundant logic unit is floated to the ME2 layer and the ME3 layer;

[0046] Step S4: In the metal layer ECO stage, if a certain redundant logic unit needs to be used, it is only necessary to modify the metal routing of the ME2 layer and / or ME3 layer connecting the input and output ends of the redundant logic unit.

[0047] By adopting the above technical solution, only the ME2 layer, ME3 layer and their corresponding vias need to be modified in the metal layer ECO stage, so as to control the number of changed metal layers to the maximum extent, thereby reducing the cost caused by ECO.

[0048] In the above technical solution, at the beginning of the IC design process, it is necessary to place a series of redundant logic cells (Spare Cells) in the layout area in the Pre-Place stage (generally the Floorplan stage). Usually, a series of Spare Cells are evenly placed in the layout area at a certain interval. A group of Spare Cells of different types is called a redundant logic cell array. Figure 2 , shown is a schematic diagram of the redundant logic cell array of the present invention, a group of Spare Cells consisting of seven types of Spare Cells, namely AND, XOR, NAND, DFF, MUX, OR, and INV, is called a Spare Cell array, and the Spare Cell array is evenly placed in the layout area (avoiding the areas where Hard Macro, IP, Blockage, etc. are located) at a certain spacing (33um in both horizontal and vertical directions). This arrangement can ensure that there are Spare Cells around any Standard Cell, and in the Metal ECO stage, it can greatly reduce the situation where the distance between the Spare Cell and the Standard Cell leads to insufficient driving force of the Drive Cell, resulting in large Setup violations and Transition violations. At the same time, this arrangement can also ensure that the optional Spare Cells around any Standard Cell are rich in logic, and are more flexible to use in the metal eco stage. See. Figure 3 , which is a diagram showing the placement effect of a Spare Cell array in one embodiment of the present invention.

[0049] After all the Spare Cell arrays are evenly arranged in the above manner, each Spare Cell in a Spare Cell array is connected to each other. In a preferred embodiment, 7 different types of Spare Cells are arranged in the Spare Cell array. Figure 4, which is a schematic diagram of the internal interconnection of the Spare Cell array, wherein the seven Spare Cells in each SpareCell array are logically interconnected in pairs, wherein some input ends of the redundant logic cells are connected to "1" or "0" through the clamping unit Tie Cell, that is, the input end of the Spare Cell is connected to 1 (tie high) or 0 (tie low) through the Tie Cell. Therefore, the present invention provides a Metal ECO method for automatically modifying the fixed metal layer and the through-hole layer by using Spare Cell and Tie Cell (clamping unit, commonly there are two types of tie high and tie low, which provide power supply potential and ground potential respectively).

[0050] The above technical solution, by connecting the Spare Cells in a Spare Cell array in pairs, can float the routing lines connected to the input and output ends of the Spare Cells to the ME2 layer and the ME3 layer in the Route and Postroute stages (the interconnection between the two must be routed through the ME2 and ME3 layers. If only ME1 is used for routing, the signal line will be shorted with the original power line of ME1). Figure 5 As shown (taking the connection between AND and XOR as an example, the through-hole layer is omitted in the figure).

[0051] In this way, when doing Metal ECO, if you need to use a Spare Cell, you only need to disconnect the metal routing of ME2 or ME3 connected to the input and output of the SpareCell, and then make a physical connection according to the modified logical relationship. If this AND is needed to drive a Standard Cell in the Metal ECO stage, we can disconnect the routing of ME2 or ME3 in the figure, and then connect the routing of ME2 or ME3 led out from the input of the Standard Cell to meet the requirement. In summary, when doing Metal ECO, if you need to use a Spare Cell, you only need to disconnect the metal routing of ME2 or ME3 connected to the input and output of the Spare Cell, and then make a physical connection according to the modified logical relationship. The above series of operations on Spare Cell need to be completed in the early stage of IC design, which ensures that in the Metal ECO stage, the method of only modifying ME2, ME3 and VI2 without modifying CONT, ME1, VI1 is feasible.

[0052] In a technical solution that is relatively close to the prior art, the input and output of the spare cell are respectively connected to a metal line segment in at least one metal layer (a metal layer not occupied by a standard cell). However, the objects to which the input and output of the Spare Cell are interconnected are not disclosed. If the Spare Cell is connected to the surrounding Standard Cell, then the Spare Cell itself contains logical functions, and there are certain limitations when using the Spare Cell in Metal ECO. The present invention interconnects various Spare Cells contained in a Spare Cell array in pairs, thereby solving this shortcoming. Meanwhile, in the prior art design, the input and output ends of the Spare Cells are connected to the upper metal layer after the wiring. However, when the wiring resources are relatively few, even if the Spare Cell input and output are connected to the upper metal layer, they cannot pass through the surrounding logic wiring. The present invention logically connects the Spare Cells in a Spare Cell array to each other, and with the help of Tie Cells, the input and output ends of the Spare Cells are connected to the upper metal layers ME2 and ME3 during wiring. In addition, in the prior art, the input and output pins of the Spare Cells used are only connected to the upper metal layer. If only one layer of the upper metal is connected without being connected to other cells, this will cause the input pins of the Spare Cells to float. In principle, the floating input pin situation is not allowed. Therefore, when the design is finally checked, if there are a large number of Spare Cells, it will be easy to fail to find the logic unit with such a problem. In the prior art, the area of ​​Spare Cells reaches 2%-15% of the total design, but it is usually impossible to use so many Spare Cells in one metal ECO. In order to reduce the waste of a large amount of area caused by the layout of Spare Cells, the total number of Spare Cells in the present invention is 7, which includes 7 different logics sufficient for use in metal eco and saves area.

[0053] With the above technical solution, when the Metal ECO modification is minor, the designer can manually disconnect the original metal wires, and then manually connect them correctly according to the ECO requirements to implement the modification. However, when the Metal ECO modification is major, the workload of manual modification will increase accordingly. At this time, it is not realistic to implement the logic modification manually. In a preferred embodiment, the present invention proposes a new Metal ECO method, which uses an automated method to allow the tool to complete the logical and physical modifications to meet the Metal ECO requirements and ensure that the CONT layer, ME1, and VI1 are not modified, thereby controlling costs. See Figure 6 , which is a flowchart of the automated Metal ECO method of the present invention. In the Metal ECO stage, the metal routing of the ME2 layer and / or the ME3 layer is modified automatically, including the following steps:

[0054] The tool reads the ECO script and completes the logic modification;

[0055] Fixed the DRC violation of Short caused by the change of net name;

[0056] Solidify the metal layers except ME2 and ME3 layers and the via layers except VI2 to ensure that these solidified layers will not be modified during rewinding;

[0057] Set the routing rules for the Net modified in the ECO script, stipulating that it can only be routed in the ME2 and ME3 layers;

[0058] Use tools to perform ECO routing on the modified Net to change the physical connection of the Net according to the requirements of the logic change.

[0059] When the Metal ECO changes are large, the front-end staff is generally required to provide the ECO script first. The script contains the Net that needs to be modified due to the logic change.

[0060] See also Figure 7 , as shown in the Metal ECO modification diagram, a Standard Cell was originally connected to BUF1, and the name of the connected Net was Old Net, but because of the change in the front-end logic, this Standard Cell should now be connected to BUF2, and the name of the connection was changed to ECO Net. When the back-end reads the ECO script provided by the front-end personnel, the logic change has been completed. In the graphical interface of the design, the name of Old Net has been changed to ECO Net, but the physical connection has not changed with the change in logic. The metal routing that originally connected to BUF1 and belongs to Old Net still exists (indicated by solid lines in the figure), and the metal routing of ECO Net has not been generated (indicated by dotted lines in the figure). This requires rewinding these Nets to complete the changes in physical connections. The final effect that should be achieved in the graphical interface of the design is shown in the figure below. Figure 8 As shown, the metal routing that originally belonged to the Old Net and existed in the ME2 and ME3 layers needs to be deleted, and then the metal routing of the ECO Net needs to be generated so that the Standard Cell and BUF2 are also physically connected together.

[0061] However, before the wire is wound, the name of the Net is changed from OldNet to ECO Net because the ECO script provided by the front-end personnel is read in. However, the Owner of the input Pin of BUF1 is still Old Net, which will cause the ECO Net to be connected with the Pin belonging to Old Net, which will cause the Short DRC violation problem. Moreover, when the Metal ECO is changed significantly, the number of Short DRC violations caused by this is also large. It is not realistic to modify it manually, and an automated process is also needed to modify this type of violation. Similarly, because the ME1 layer and the VI1 layer cannot be modified, in order to solve this problem, the steps are as follows: first find out the Shorts belonging to the ME1 layer among all the DRC violations belonging to Short, and obtain the area of ​​the ME1 layer with Short DRC violations; then obtain the Owner1 of the Pin with violations in the area and the shape of the ME1 layer connected to it, and the Owner2 of the VIA of the VI1 layer (the two are different to cause Short); finally, change the shape of the violation and the Owner2 of the VIA to be the same as the Owner1 of the Pin, and the Short violation of the ME1 layer can be solved. After solving the violation problem of Short, you need to freeze the metal layers other than ME2 and ME3 and the through-hole layers other than VI2 first to ensure that these frozen layers will not be changed when rewinding. In addition, you need to set the winding rules for these Nets that are modified in the ECO script, stipulating that they can only be wound in the two layers of ME2 and ME3. After all settings are completed, the specified tool performs ECO routing on these modified Nets, so that the physical connection of the Net can be successfully changed according to the requirements of the logic change, and compared with before Metal ECO, only two metal layers ME2 and ME3 and the through-hole layer VI2 in the design graphical interface are changed. This automated Metal ECO method not only greatly reduces the workload and improves the efficiency of chip design work, but also greatly reduces the cycle and cost required in the Metal ECO stage.

[0062] The present invention also discloses an integrated circuit, which is designed using the above-mentioned integrated circuit metal layer ECO method, and at least a plurality of redundant logic unit arrays are arranged, wherein the redundant logic unit array includes a plurality of redundant logic units of different types, and each redundant logic unit in the redundant logic unit array is logically connected to each other in pairs in sequence, so that the routing connecting the input and output ends of the redundant logic unit can float to the ME2 layer and the ME3 layer during the wiring stage.

[0063] As a further improvement solution, in the metal layer ECO stage, if a certain redundant logic unit needs to be used, it is only necessary to modify the metal routing of the ME2 layer and / or ME3 layer connecting the input and output ends of the redundant logic unit.

[0064] As a further improvement, the redundant logic unit array is provided with at least seven types of redundant logic units, namely, AND, XOR, NAND, DFF, MUX, OR, and INV.

[0065] Compared with the prior art, by setting a redundant logic unit array and logically connecting the redundant logic units of each redundant logic unit array in pairs in sequence, it is only necessary to modify the fixed metal layers ME2, ME3 and the through-hole layer V2 as required, which greatly reduces the cycle and cost required for the Metal ECO stage, helps to improve the efficiency of chip design work and reduce ineffective work; at the same time, the present invention adopts an automated method to allow the tool to complete logical and physical modifications to meet the requirements of Metal ECO, and ensure that the CONT layer, ME1, and VI1 are not modified, thereby controlling costs.

[0066] The above embodiments are only used to help understand the method and core idea of ​​the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0067] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit metal layer ECO method, wherein a redundant logic unit is provided in the integrated circuit for use in the metal layer ECO, characterized in that: The steps include: Step S1: In the chip layout stage, a redundant logic unit array is arranged in a layout area at a certain interval, wherein the redundant logic unit array includes a plurality of redundant logic units of different types; Step S2: logically connecting the redundant logic units of each redundant logic unit array in pairs in sequence; Step S3: In the wiring stage, the wiring connecting the input end and the output end of the redundant logic unit is floated to the ME2 layer and the ME3 layer; Step S4: In the metal layer ECO stage, if a certain redundant logic unit needs to be used, it is only necessary to modify the metal routing of the ME2 layer and / or ME3 layer connecting the input and output ends of the redundant logic unit.

2. The integrated circuit metal layer ECO method according to claim 1, characterized in that: In step S2, some input terminals of the redundant logic unit are connected to "1" or "0" through the clamping unit.

3. The integrated circuit metal layer ECO method according to claim 2, characterized in that: The redundant logic cell array is provided with at least seven types of redundant logic cells, namely, AND, XOR, NAND, DFF, MUX, OR, and INV.

4. The integrated circuit metal layer ECO method according to claim 1, characterized in that: Step S4: In the metal layer ECO stage, only the metal routing of the ME2 layer and / or the ME3 layer needs to be modified.

5. The integrated circuit metal layer ECO method according to claim 1, characterized in that: Step S4, in the metal layer ECO stage, metal routing of the ME2 layer and / or ME3 layer is modified in an automatic manner, wherein logical and physical modifications are completed by tools to meet the requirements of Metal ECO.

6. The integrated circuit metal layer ECO method according to claim 5, characterized in that: The automatic method for modifying the metal routing of the ME2 layer and / or ME3 layer includes the following steps: The tool reads the ECO script and completes the logic modification; Fixed the DRC violation of Short caused by the change of net name; Solidify the metal layers except ME2 and ME3 layers and the via layers except VI2 to ensure that these solidified layers will not be modified during rewinding; Set the routing rules for the Net modified in the ECO script, stipulating that it can only be routed in the ME2 and ME3 layers; Use tools to perform ECO routing on the modified Net to change the physical connection of the Net according to the requirements of the logic change.

7. The integrated circuit metal layer ECO method according to claim 6, characterized in that: The steps to fix the Short DRC violation caused by the net name change include the following: First, find out the Short belonging to the ME1 layer among all the DRC violations belonging to Short, and obtain the area of ​​the ME1 layer with Short DRC violations; Then obtain the Owner1 of the Pin where the violation occurs in the area, the shape of the ME1 layer connected to it, and the Owner2 of the VIA of the VI1 layer; finally, change the shape where the violation occurs and the Owner2 of the VIA to be the same as the Owner1 of the Pin.

8. An integrated circuit, characterized in that: The integrated circuit is designed by the integrated circuit metal layer ECO method of any one of claims 1 to 7, and at least a plurality of redundant logic cell arrays are provided, wherein the redundant logic cell arrays include a plurality of redundant logic cells of different types, and each redundant logic cell in the redundant logic cell array is logically connected to each other in pairs in sequence, so that the routing lines connecting the input and output ends of the redundant logic cells can float to the ME2 layer and the ME3 layer during the wiring stage.

9. The integrated circuit according to claim 8, characterized in that In the metal layer ECO stage, if a redundant logic unit needs to be used, it is only necessary to modify the metal routing of the ME2 layer and / or ME3 layer connecting the input and output ends of the redundant logic unit.

10. The integrated circuit according to claim 8, characterized in that The redundant logic unit array is provided with at least seven types of redundant logic units, namely, AND, XOR, NAND, DFF, MUX, OR, and INV.

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