Gate driver, display panel and display device

Abstract

The invention provides a gate driver, a display panel and a display device. The gate driver comprises a plurality of stages, gate control signals are sequentially output through gate control lines, each stage comprises a driving circuit and a gating circuit, and the driving circuit comprises a pull-up module; and the gating circuit comprises a gating control signal write-in module, the gating control signal write-in module comprises a first switch, a grid electrode of the first switch in each stage except the first stage in the plurality of stages is connected with a first node of the driving circuit of the previous stage, and the voltage of the first node is used for driving the pull-up module. The driving voltage of the pull-up module is adopted to drive the grid electrode of the first switch, so that the defect of partition refreshing boundary split screen is overcome.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driver, a display panel and a display device. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver and a drive controller. The gate driver outputs gate control signals to the plurality of gate lines respectively. The data driver outputs data voltages to the plurality of data lines respectively. The emission driver outputs emission control signals to the plurality of emission lines respectively.

[0003] The gate driver for partition refresh includes a multi-level structure, and any level includes a driving circuit and a gating circuit. Generally, the gate of the switch unit to which the gating control signal of the gating circuit is written is connected to the output signal of the driving circuit. Since the output signal of the driving circuit is normally low, the gating control signal and the high voltage are coupled through a capacitor in most states. Since the coupling capacitor is large, when the gating control signal jumps at the partition refresh boundary, the gating control signal changes from high to low, and the high voltage outputted by the low-level output is pulled down through the capacitor coupling, resulting in insufficient high voltage of the pixel being compensated, resulting in a dark display. That is, the partition refresh boundary split screen phenomenon occurs. Summary of the invention

[0004] The main purpose of the present application is to provide a gate driver, a display panel and a display device to solve the problem that the multi-level driving structure of the gate driver in the prior art is prone to the phenomenon of partition refresh boundary split screen during partition driving.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a gate driver is provided, comprising multiple stages, which sequentially output gate control signals through gate control lines, each of the stages comprising a driving circuit and a gating circuit, wherein the driving circuit comprises a pull-up module; the gating circuit comprises a gating control signal writing module, the gating control signal writing module comprises a first switch, the gate of the first switch in each of the multiple stages except the first stage is connected to the first node of the driving circuit of the previous stage, and the voltage of the first node is used to drive the pull-up module.

[0006] Optionally, the selection control signal writing module also includes a capacitor and a second switch, the capacitor, the first switch and the second switch are connected in series, the first plate of the capacitor is connected to a first power supply, the gate of the second switch is connected to the output end of the driving circuit, and the signal input end of the second switch inputs the selection control signal.

[0007] Optionally, both the first switch and the second switch are P-type switch tubes.

[0008] Optionally, the gating circuit also includes a gating control module and a gating output module, the output end of the driving circuit is connected to the gates of some switches in the gating control module, and the gating output module outputs the gate control signal. Under the action of the gating control signal and the output signal of the driving circuit, the switches in the gating control module are controlled to be turned on or off so that the gate control signal is at a high level or a low level.

[0009] Optionally, the gating control module includes: a third switch, a fourth switch, a fifth switch and a sixth switch, the third switch and the fourth switch are coupled between the second node and the first power supply, the fifth switch and the sixth switch are coupled between the second node and the second power supply, and the gate of the third switch and the gate of the sixth switch are connected to the output end of the driving circuit, the gate of the fourth switch is connected to the second plate of the capacitor, and the gate of the fifth switch is connected to the first end of the first switch.

[0010] Optionally, the third switch and the fourth switch are both P-type switch tubes, and the fifth switch and the sixth switch are both N-type switch tubes.

[0011] Optionally, within a preset time after the enable control signal changes from a high level to a low level, the voltage of the first node maintains a low level, the voltage of the second node maintains a high level, the level of the third node changes from a high level to a low level synchronously with the enable control signal, the second plate of the capacitor is coupled to the third node, and within the preset time, the output signal of the next-level driving circuit maintains a low level, and the level of the gate control signal output by the enable output module is opposite to the level of the second node.

[0012] Optionally, after the preset time ends, the output signal of the next-level driving circuit changes to a high level, and during the time period when the output signal of the next-level driving circuit and the output signal of the previous-level driving circuit are both at high levels, the voltage of the first node maintains a low level, the voltage of the second node maintains a high level, and the third node maintains a low level.

[0013] Optionally, during the time period when the output signal of the driving circuit of the previous level changes to a low level and the output signal of the driving circuit of the next level is a high level, the level of the first node is a high level, the voltage of the second node maintains a high level, and the third node maintains a low level.

[0014] Optionally, the enable output module includes a seventh switch and an eighth switch, the first end of the seventh switch is connected to the first power supply, the gate of the seventh switch and the gate of the eighth switch are coupled to a second node, the second end of the seventh switch is connected to the second end of the eighth switch, the first end of the eighth switch is connected to the second power supply, and a control signal line is led out between the second end of the seventh switch and the second end of the eighth switch to output the gate control signal.

[0015] Optionally, the seventh switch is a P-type switch tube, and the eighth switch is an N-type switch tube.

[0016] Optionally, the driving circuit also includes a pull-down module, a pull-up control module and a pull-down control module, the pull-up control module is configured to generate a pull-up driving signal for driving the pull-up module, the pull-down control module is configured to generate a pull-down driving signal for driving the pull-down module, the pull-up module and the pull-down module are coupled between a first power supply and a second power supply, and a common node of the pull-up module and the pull-down module leads to a signal line to output the output signal of the driving circuit.

[0017] Optionally, both the pull-up module and the pull-down module are P-type switch tubes.

[0018] Optionally, the first stage among the multiple stages receives a start signal, a first clock signal, and a second clock signal, all stages receive the first clock signal and the second clock signal, and the first clock access terminals of two adjacent stages receive the first clock signal and the second clock signal, respectively, and the second clock access terminals of two adjacent stages receive the first clock signal and the second clock signal, respectively.

[0019] Optionally, the first clock signal and the second clock signal have the same frequency, and there is a phase difference between the second clock signal and the first clock signal.

[0020] Optionally, each of the plurality of stages drives at least one row of pixel units.

[0021] Optionally, the number of rows of pixel units driven by each stage determines the phase difference between the second clock signal and the first clock signal.

[0022] According to a second aspect of the present application, a display panel is provided, comprising: any one of the gate drivers described; a gate control signal generator configured to generate a gate control signal; an input signal generator configured to generate an input signal; a first clock signal generator configured to generate a first clock signal; and a second clock signal generator configured to generate a second clock signal.

[0023] Optionally, the display panel further comprises: a plurality of rows of pixel units, the gate driver is configured to provide a gate control signal to the pixel units; a data driver is configured to provide a data voltage to the pixel units; and

[0024] The emission driver is configured to provide an emission signal to the pixel unit.

[0025] According to a third aspect of the present application, a display device is provided, including a display panel.

[0026] By applying the technical solution of the present application, the gate of the first switch in each stage except the first stage among the multiple stages is connected to the first node of the driving circuit of the previous stage, that is, under this connection mode, a new first switch is added in the selection control signal writing module and driven by the voltage of the first node of the driving circuit. Since the first node is usually a high-level signal, the first switch is usually in the off state, thereby reducing the coupling between the signal input to the selection control signal writing module and VGH, thereby avoiding the partition refresh boundary split screen phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings constituting part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0028] Figure 1 A schematic diagram of a gate driver according to an embodiment of the present application is shown;

[0029] Figure 2 shows a schematic diagram of the nth stage in a gate driver according to an embodiment of the present application;

[0030] Figure 3 A schematic diagram of a border split screen according to an embodiment of the present application is shown;

[0031] Figure 4 A schematic diagram of a gating circuit according to an embodiment of the present application is shown;

[0032] Figure 5 A first driving circuit schematic diagram according to an embodiment of the present application is shown;

[0033] Figure 6 A second driving circuit schematic diagram according to an embodiment of the present application is shown;

[0034] Figure 7 A specific level schematic diagram according to an embodiment of the present application is shown;

[0035] Figure 81 shows a timing diagram of the gating control signal SN_ctrl jumping from a high level to a low level according to an embodiment of the present application;

[0036] Fig. 9 A timing diagram showing the conversion of high refresh to high refresh at the n+1th time according to an embodiment of the present application;

[0037] Fig.10 shows a working timing diagram of the high frequency region according to an embodiment of the present application;

[0038] Fig.11 shows a working timing diagram of the low frequency region according to an embodiment of the present application;

[0039] Fig.12 shows a timing diagram in a first partition refresh mode according to an embodiment of the present application;

[0040] Fig.13 shows a timing diagram in a second partition refresh mode according to an embodiment of the present application;

[0041] Fig.14 A schematic diagram of a multi-stage cascade relationship according to an embodiment of the present application is shown;

[0042] Fig.15 A schematic diagram showing a phase difference between a second clock signal and a first clock signal according to an embodiment of the present application is shown;

[0043] Fig.16 A schematic diagram of a first display panel according to an embodiment of the present application is shown;

[0044] Fig.17 A schematic diagram of a second display panel according to an embodiment of the present application is shown;

[0045] Fig.18 A schematic diagram of a first pixel driving circuit according to an embodiment of the present application is shown;

[0046] Fig.19 A second pixel driving circuit schematic diagram according to an embodiment of the present application is shown;

[0047] Fig. 20 A third pixel driving circuit schematic diagram according to an embodiment of the present application is shown.

[0048] Fig.21 A schematic diagram of a display device according to an embodiment of the present application is shown.

[0049] The above drawings include the following reference numerals:

[0050] 1. Gate driver; 2. Strobe control signal generator; 3. Input signal generator; 4. First clock signal generator; 5. Second clock signal generator; 6. Pixel unit; 7. Data driver; 8. Emission driver; 100. Display panel; 10. Stage; 11. Driving circuit; 12. Strobe circuit; 110. Pull-up module; 111. Pull-down module; 112. Pull-up control module; 113. Pull-down control module; 120. Strobe control signal writing module; 121. Strobe control module; 122. Strobe output module; 1201. First switch. DETAILED DESCRIPTION

[0051] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0052] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0053] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0054] As introduced in the background technology, the multi-level driving structure of the gate driver in the prior art is prone to the phenomenon of partition refresh boundary split screen during partition driving. In order to solve the problem that the multi-level driving structure of the gate driver as above is prone to the phenomenon of partition refresh boundary split screen during partition driving, the present application proposes a gate driver, a display panel and a display device.

[0055] The gate driver provided in the embodiment of the present application is as follows: Figure 1 As shown, the gate driver 1 includes a plurality of stages 10, and sequentially outputs a gate control signal SN_OUT through a gate control line. Each stage 10 includes a driving circuit 11 and a gating circuit 12, wherein:

[0056] The driving circuit 11 includes a pull-up module 110;

[0057] The gating circuit 12 includes a gating control signal writing module 120, which includes a first switch 1201. The gate of the first switch 1201 in each level 10 except the first level in the multiple levels 10 is connected to the first node of the driving circuit 11 of the previous level, and the voltage of the first node N1 is used to drive the pull-up module 110.

[0058] Figure 1 , it is shown that the voltage N1(n-2) of the first node of the n-2th stage drives the first switch 1201 in the n-1th stage, the voltage N1(n-1) of the first node of the n-1th stage drives the first switch 1201 in the nth stage, and the voltage N1(n) of the first node of the nth stage drives the first switch 1201 in the n+1th stage;

[0059] In the above-mentioned method, the gate of the first switch 1201 in each stage 10 except the first stage among the multiple stages 10 is connected to the first node of the driving circuit 11 of the previous stage, that is, under this connection mode, a new first switch is added in the selection control signal writing module and is driven by the voltage of the first node of the driving circuit. Since the first node is usually a high-level signal, the first switch 1201 is usually in the off state, thereby reducing the coupling between the signal SN_ctrl input to the selection control signal writing module and VGH, thereby avoiding the partition refresh boundary split screen phenomenon.

[0060] Furthermore, if Figure 2 As shown, the gating control signal writing module 120 also includes a capacitor C1 and a second switch M2. The capacitor C1 and the first switch M1 (equivalent to Figure 1 The first switch 1201) and the second switch M2 are connected in series, the first plate of the capacitor is connected to the first power supply, the gate of the second switch is connected to the output end of the driving circuit, and the signal input end of the second switch inputs the selection control signal SN_ctrl.

[0061] In the related scheme, the first switch is not set in the gating control signal writing module, the gating control signal is input to the signal input end of the second switch, the gate of the second switch is connected to the Next(n) signal, the Next signal is usually low, so in most states, SN_ctrl and VGH are connected through capacitor coupling, the SN_ctrl coupling capacitor is very large, when SN_ctrl jumps at the partition refresh boundary moment, SN_ctrl changes from high to low, and the VGH output by SN is pulled down through capacitor coupling, resulting in insufficient VGH of the pixel SN being compensated, resulting in dark display, that is, the phenomenon of boundary split screen appears. See Figure 3 .

[0062] The function of the gating circuit is to control whether the effective high level of Next is output to SN_OUT by writing the potential of the lower plate of capacitor C1 through the SN_ctrl signal;

[0063] By adopting the solution of the present application, the signal written by SN_ctrl is changed from being controlled by Next(n) to being jointly controlled by the N1 node signal of the previous level and Next(n), thereby ensuring that SN_ctrl is not connected to the lower plate of capacitor C1 most of the time, thereby reducing the coupling between SN_ctrl and VGH, effectively ensuring that the effective high level of Next is output to SN_OUT, and improving the boundary split screen.

[0064] Specifically, the first switch and the second switch are both P-type switch tubes.

[0065] Furthermore, the gating circuit also includes a gating control module and a gating output module. The output end of the driving circuit is connected to the gates of some switches in the gating control module. The gating output module outputs a gate control signal. Under the action of the gating control signal and the output signal of the driving circuit, the switch in the gating control module is controlled to be turned on or off so that the gate control signal is at a high level or a low level. Figure 4 1 shows the connection relationship between the gate control module 121, the gate control signal writing module 120 and the gate output module 122. The output signal Next(n) of the driving circuit is input to the gate control module 121 and the gate of the second switch M2.

[0066] More specifically, Figure 4 As shown, the gating control module 121 includes: a third switch M3, a fourth switch M4, a fifth switch M5 and a sixth switch M6, the third switch M3 and the fourth switch M4 are coupled between the second node N2 and the first power supply VGH, the fifth switch M5 and the sixth switch M6 are coupled between the second node and the second power supply VGL, and the gate of the third switch M3 and the gate of the sixth switch M6 are connected to the output terminal Next(n) of the driving circuit, the gate M4 of the fourth switch is connected to the second plate of the capacitor C1, and the gate of the fifth switch M5 is connected to the first end of the first switch M1.

[0067] like Figure 4 As shown, the third switch M3 and the fourth switch M4 are both P-type switch tubes, and the fifth switch M5 and the sixth switch M6 are both N-type switch tubes.

[0068] Specifically, Figure 4 As shown, the gate output module 122 includes a seventh switch M7 and an eighth switch M8.

[0069] A first end of the seventh switch M7 is connected to the first power source VGH, a gate of the seventh switch M7 and a gate of the eighth switch M8 are coupled to the second node N2,

[0070] A second end of the seventh switch M7 is connected to a second end of the eighth switch M8 , a first end of the eighth switch M8 is connected to the second power source VGL, and a control signal line is led between the second ends of the seventh switch M7 and the eighth switch M8 to output a gate control signal SN_OUT.

[0071] Furthermore, if Figure 4 As shown, the seventh switch M7 is a P-type switch tube, and the eighth switch M8 is an N-type switch tube.

[0072] It should be noted that this application Figure 4 The specific structure shown is only an optional implementation. Under the condition that the capacitor C1, the second switch M2 and the first switch M1 are included, the same structure as shown in FIG. Figure 4 Equivalent variant structures of various circuits.

[0073] like Figure 5 As shown, the driving circuit also includes a pull-down module 111, a pull-up control module 112 and a pull-down control module 113. The pull-up control module 112 is configured to generate a pull-up driving signal for driving the pull-up module, and the pull-down control module 113 is configured to generate a pull-down driving signal for driving the pull-down module 111. The pull-up module 110 and the pull-down module 111 are coupled between a first power supply VGH and a second power supply VGL, and a common node of the pull-up module 110 and the pull-down module 111 leads to a signal line to output the output signal of the driving circuit.

[0074] like Figure 6 As shown, the pull-up module M17 and the pull-down module M18 are both P-type switch tubes.

[0075] Of course, this application Figure 6 The driving circuit shown is only an optional solution. Other driving circuits can also be used in the solution of this application. It is only necessary to ensure that the other driving circuits are compatible with Figure 6 A node equivalent to the N1 node in the circuit can be connected to the gate of the first switch of the next stage.

[0076] Figure 7 A schematic diagram of a stage in a specific gate driver is shown.

[0077] Application Figure 7 The circuit shown and Figure 7In the equivalent circuit, within the preset time after the selection control signal SN_ctrl jumps from a high level to a low level, the voltage of the first node N1 maintains a low level, the voltage of the second node N2 maintains a high level, the level of the third node N3 jumps from a high level to a low level synchronously with the selection control signal SN_ctrl, the second plate of the capacitor C1 is coupled to the third node N3, the output signal of the next-level driving circuit maintains a low level within the preset time, and the level SN_OUT of the gate control signal SN_OUT output by the selection output module is opposite to the level of the second node N2. Further, after the preset time ends, the output signal of the next-stage driving circuit changes to a high level, and in the time period when the output signal of the next-stage driving circuit and the output signal of the previous-stage driving circuit are both at high levels, the voltage of the first node N1 maintains a low level, the voltage of the second node N2 maintains a high level, and the third node N3 maintains a low level; in addition, in the time period when the output signal of the previous-stage driving circuit changes to a low level and the output signal of the next-stage driving circuit is at a high level, the level of the first node N1 is a high level, the voltage of the second node N2 maintains a high level, and the third node N3 maintains a low level. Specifically, the timing diagram is as follows: Figure 8 As shown, combined Figure 7 and Figure 8 Analysis shows that, assuming that the high-brush to low-brush conversion is performed at the n+1th time, the level change of the strobe control signal SN_Ctrl from VGH to VGL between Next(n) and Next(n+1) is divided into the following stages:

[0078] In the T1 phase, the first node N1(n) jumps low, the first switch M1 is turned on, SN_ctrl is written into the third node N3, at which time the third switch M3 is turned on, the second node N2 is written into VGH, and OUT outputs VGL;

[0079] In the T2 phase, SN_ctrl jumps low, at which time the third node N3 is written low, Next(n) is written high, the third switch M3 is closed, the fourth switch M4 is opened, the second node N2 is still written to VGH, and OUT outputs VGL;

[0080] In the T3 phase, the second node N2 maintains VGH, and OUT outputs VGL;

[0081] In the T4 stage, the third switch M3 is closed. Due to the existence of the capacitor C1, the third node N3(n+1) maintains VGL, the fourth switch M4 is opened, the second node N2 is VGH, the output OUT is VGL, and thus SN_OUT(n+1) maintains the output VGL, entering the low-frequency maintenance state, realizing the conversion of high frequency to low frequency, and because the first node N1(n) is usually at a high level and cascaded progressively, after adding the first switch M1, at the same time, only SN_ctrl in level 1 writes the coupling VGH, and the coupling effect is small, thereby improving the display boundary.

[0082] Fig. 9 The timing diagram of the high refresh to high refresh conversion at the n+1th time is shown, SN_Ctrl maintains VGH, which specifically includes the following stages:

[0083] In the T1 phase, the first node N1(n) jumps low, the first switch M1 is turned on, SN_ctrl is written into the third node N3, at which time the third switch M3 is turned on, the second node N2 is written into VGH, and OUT outputs VGL;

[0084] In the T2 phase, SN_ctrl jumps low, at which time the third node N3 is written high, Next is written high, the third switch M3 is closed, the fourth switch M4 is closed, the fifth switch M5 and the sixth switch M6 are opened, the second node N2 is written to VGL, and OUT outputs VGH;

[0085] In the T3 phase, N2 maintains VGL and OUT outputs VGH;

[0086] In the T4 stage, the third switch M3 is turned off. Due to the existence of the capacitor C1, N3(n+1) maintains VGH, the fourth switch M4 is turned off, the second node N2 is VGL, the output OUT is VGH, and SN_OUT(n+1) maintains the output VGL, entering the low-frequency maintenance state, and realizing the conversion of high frequency to low frequency.

[0087] Phase T5: Next(n+1) jumps low, the sixth switch M6 is closed, the third switch M3 is opened, the second node N2 is written to VGH, and OUT outputs VGL, thereby achieving normal SN output.

[0088] Fig.10 The working sequence of the high frequency area is shown. OUT normally outputs Next. When the Ctrl signal is written to N3 at a high level, M4 is closed and M5 is open. At this time, when Next is at a high level, M3 is closed and M6 is open. VGL is written to the N2 node to output VGH. At this time, the OUT signal normally outputs the high level pulse of Next.

[0089] Fig.11 The working sequence of the low frequency area is shown. OUT maintains VGL. When Next is low, M4 is turned on and M5 is turned off. When Next is high, M3 is turned off and M6 is turned on. At this time, VGH is written into N2 through M4, and M8 is turned on to output a low level. At this time, the OUT signal maintains a low level, and the panel display enters a low frequency maintenance state.

[0090] Fig.12 The timing diagram in the first partition refresh mode is shown, and the high-frequency refresh → low-frequency maintenance conversion is performed between the nth to the n+1th level; the corresponding Ctrl signal completes the signal H→L jump between Next(n) and Next(n+1);

[0091] Fig.13 The timing diagram in the second partition refresh mode is shown, and the low-frequency maintenance → high-frequency refresh conversion is performed between the nth to the n+1th level; the Ctrl signal of the corresponding example completes the signal L→H jump between Next(n) and Next(n+1);

[0092] In the embodiment of the present application, the first stage of the multiple stages receives a start signal, a first clock signal, and a second clock signal, all stages receive the first clock signal and the second clock signal, and the first clock access terminals of two adjacent stages receive the first clock signal and the second clock signal, and the second clock access terminals of two adjacent stages receive the first clock signal and the second clock signal, respectively. Fig.14 As shown, the first stage receives the start signal IN, the first clock signal is CK, and the second clock signal is XCK.

[0093] Furthermore, the first clock signal and the second clock signal have the same frequency, and there is a phase difference between the second clock signal and the first clock signal.

[0094] Further, each of the multiple stages drives at least one row of pixel units.

[0095] Furthermore, the number of rows of pixel units driven at each level determines the phase difference between the second clock signal and the first clock signal. Fig.15 As shown, the H value is the row time of the panel scanning, and the timing diagram is an example of one driving two, that is, one circuit unit drives two rows of pixel units, and the waveform phase progresses according to 2H (that is, two rows of pixel units).

[0096] More specifically, all switches involved in the embodiments of the present application are transistors.

[0097] Based on the same inventive concept, the embodiment of the present application further provides a display panel, specifically as follows Fig.16 As shown, it includes: a gate driver 1; a gating control signal generator 2, configured to generate a gating control signal; an input signal generator 3, configured to generate an input signal; a first clock signal generator 4, configured to generate a first clock signal; and a second clock signal generator 5, configured to generate a second clock signal.

[0098] Furthermore, if Fig.17 As shown, the display panel also includes: multiple rows of pixel units 6, a gate driver 1 configured to provide gate control signals to the pixel units 6; a data driver 7 configured to provide data voltages to the pixel units 6; and an emission driver 8 configured to provide emission signals to the pixel units 6.

[0099] It should be noted that this application Fig.17 The multiple rows of pixel units 6 are for illustration only and do not limit the number of rows of pixel units in the solution of the present application.

[0100] Specifically, the pixel unit includes a pixel driving circuit such as Fig.18 , Fig.19 and Fig. 20 Three pixel driving circuits are shown. Of course, the pixel driving circuits other than those shown in the embodiment of the present application can also be selected. The SN_OUT gate control signal output by the gate driver is connected to Figures 18 to 20 In the scanning line S1 or scanning line S2, two gate drivers need to be configured for the scanning line S1 and the scanning line S2 in actual application, and the data voltage output by the data driver is connected to Fig.18 The data line Vdata in Fig.19 The data line DATA, and Fig. 20 The data line Vdata in the transmitter driver is connected to the transmitter signal output by the transmitter driver. Fig.18 The light-emitting control signal line EMIT in Fig.19 The light emitting control signal line E1, Fig. 20 The gate driver, data driver, and emission driver provide corresponding driving signals to the pixel driving circuit, and the pixel driving circuit drives the light-emitting element to emit light to finally realize display, wherein the light-emitting element can be selected from LED, OLED, miniLED, etc.

[0101] Furthermore, the display panel also includes a substrate structure, and multiple rows of pixel units, a gate driver, a data driver, an emission driver, an input signal generator, a first clock signal generator, and a second clock signal generator are all arranged on the substrate structure. In addition, the gate driver, the data driver, the emission driver, the input signal generator, the first clock signal generator, and the second clock signal generator in the present application are all modular structures that are conveniently arranged on the substrate structure, which is convenient for the preparation of the display panel.

[0102] Based on the same inventive concept, the embodiment of the present application further provides a display device, such as Fig.21 As shown, it includes a display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiment, and will not be repeated here. Fig.21 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0103] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0104] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A gate driver, characterized in that: It includes multiple stages, and sequentially outputs gate control signals through gate control lines. Each of the stages includes a driving circuit and a gating circuit, wherein: The driving circuit includes a pull-up module; A gating circuit includes a gating control signal writing module, wherein the gating control signal writing module includes a first switch, wherein the gate of the first switch in each stage except the first stage among the multiple stages is connected to the first node of the driving circuit of the previous stage, and the voltage of the first node is used to drive the pull-up module.

2. The gate driver according to claim 1, characterized in that: The gating control signal writing module also includes a capacitor and a second switch. The capacitor, the first switch and the second switch are connected in series, the first plate of the capacitor is connected to a first power supply, the gate of the second switch is connected to the output end of the drive circuit, and the signal input end of the second switch inputs a selection control signal.

3. The gate driver according to claim 2, characterized in that: The first switch and the second switch are both P-type switch tubes.

4. The gate driver according to claim 2, characterized in that: The gating circuit also includes a gating control module and a gating output module. The output end of the driving circuit is connected to the gates of some switches in the gating control module, and the gating output module outputs the gate control signal. Under the action of the gating control signal and the output signal of the driving circuit, the switches in the gating control module are controlled to be turned on or off so that the gate control signal is at a high level or a low level.

5. The gate driver according to claim 4, characterized in that: The gating control module includes: a third switch, a fourth switch, a fifth switch and a sixth switch, The third switch and the fourth switch are coupled between a second node and the first power source, the fifth switch and the sixth switch are coupled between the second node and a second power source, The gate of the third switch and the gate of the sixth switch are connected to the output end of the driving circuit, the gate of the fourth switch is connected to the second plate of the capacitor, and the gate of the fifth switch is connected to the first end of the first switch.

6. The gate driver according to claim 5, characterized in that: The third switch and the fourth switch are both P-type switch tubes, and the fifth switch and the sixth switch are both N-type switch tubes.

7. The gate driver according to claim 5, characterized in that: Within a preset time after the selection control signal changes from a high level to a low level, the voltage of the first node maintains a low level, the voltage of the second node maintains a high level, the level of the third node changes from a high level to a low level synchronously with the selection control signal, the second plate of the capacitor is coupled to the third node, and within the preset time, the output signal of the next-level driving circuit maintains a low level, and the level of the gate control signal output by the selection output module is opposite to the level of the second node.

8. The gate driver according to claim 7, characterized in that: After the preset time ends, the output signal of the next-level driving circuit changes to a high level, and during the time period when the output signal of the next-level driving circuit and the output signal of the previous-level driving circuit are both high levels, the voltage of the first node maintains a low level, the voltage of the second node maintains a high level, and the third node maintains a low level.

9. The gate driver according to claim 8, characterized in that: During the time period when the output signal of the driving circuit at the previous level changes to a low level and the output signal of the driving circuit at the next level is a high level, the level of the first node is a high level, the voltage of the second node maintains a high level, and the third node maintains a low level.

10. The gate driver according to claim 4, characterized in that: The strobe output module includes a seventh switch and an eighth switch, A first end of the seventh switch is connected to the first power source, a gate of the seventh switch and a gate of the eighth switch are coupled to a second node, The second end of the seventh switch is connected to the second end of the eighth switch, the first end of the eighth switch is connected to the second power supply, and a control signal line is led between the second end of the seventh switch and the second end of the eighth switch to output the gate control signal.

11. The gate driver according to claim 10, characterized in that: The seventh switch is a P-type switch tube, and the eighth switch is an N-type switch tube.

12. The gate driver according to claim 1, characterized in that: The driving circuit also includes a pull-down module, a pull-up control module and a pull-down control module. The pull-up control module is configured to generate a pull-up driving signal for driving the pull-up module, and the pull-down control module is configured to generate a pull-down driving signal for driving the pull-down module. The pull-up module and the pull-down module are coupled between a first power supply and a second power supply, and a signal line leads out from a common node of the pull-up module and the pull-down module to output an output signal of the driving circuit.

13. The gate driver according to claim 12, characterized in that: The pull-up module and the pull-down module are both P-type switch tubes.

14. The gate driver according to claim 1, characterized in that: The first stage of the multiple stages receives a start signal, a first clock signal, and a second clock signal, all stages receive the first clock signal and the second clock signal, and the first clock access terminals of two adjacent stages receive the first clock signal and the second clock signal, respectively, and the second clock access terminals of two adjacent stages receive the first clock signal and the second clock signal, respectively.

15. The gate driver according to claim 14, characterized in that: The first clock signal and the second clock signal have the same frequency, and there is a phase difference between the second clock signal and the first clock signal.

16. The gate driver according to claim 1, characterized in that: Each of the plurality of stages drives at least one row of pixel units.

17. The gate driver according to claim 15, characterized in that: The number of rows of pixel units driven by each stage determines the phase difference between the second clock signal and the first clock signal.

18. A display panel, characterized in that: include: The gate driver according to any one of claims 1 to 17; a gating control signal generator configured to generate a gating control signal; an input signal generator configured to generate an input signal; A first clock signal generator configured to generate a first clock signal; The second clock signal generator is configured to generate a second clock signal.

19. The display panel according to claim 18, characterized in that: The display panel further includes: a plurality of rows of pixel units, the gate driver being configured to provide gate control signals to the pixel units; a data driver configured to provide a data voltage to the pixel unit; and The emission driver is configured to provide an emission signal to the pixel unit.

20. A display device, characterized in that: Comprising the display panel as claimed in claim 18 or 19.

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