Display panel and electronic equipment

Abstract

The invention relates to a display panel and electronic equipment, the display panel comprises a display area and a non-display area, the display area comprises a plurality of rows of pixel circuits and a plurality of first shift circuits, each first shift circuit is connected with one row of pixel circuits, and the plurality of first shift circuits are in cascade connection; the non-display area comprises a plurality of second shifting circuits, each second shifting circuit is connected with at least one row of pixel circuits, and the second shifting circuits are connected in a cascade mode. According to the embodiment of the invention, the plurality of cascaded second shift circuits are arranged in the non-display area outside the display area, so that the voltage loads of the pixel circuits in different areas of the display panel during resetting tend to be consistent, transverse dark bands caused by voltage load differences are removed, the image quality of the display panel is improved, and the yield of display panel products is further improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and an electronic device. Background Art

[0002] The gate driver on array (GOA) technology is a technology that directly manufactures the gate drive circuit on the array substrate to replace the driver chip made by the external silicon chip. Through this technology, the gate drive array can be directly set around the panel, reducing the manufacturing process, which is conducive to the realization of the narrow frame design of the display screen and can also reduce the production cost. Therefore, it has been widely used and studied.

[0003] However, due to the timing limitation of the gate drive array, horizontal dark bands will appear on the screen of the display panel, and its image quality needs to be further improved. Summary of the invention

[0004] In view of this, the present disclosure provides a display panel and an electronic device.

[0005] According to one aspect of the present disclosure, a display panel is provided, the display panel comprising a display area and a non-display area, the display area comprising a plurality of rows of pixel circuits and a plurality of first shift circuits, each of which is connected to a row of pixel circuits, and the plurality of first shift circuits are cascade-connected; the non-display area comprises a plurality of second shift circuits, each of which is connected to at least one row of pixel circuits, the plurality of second shift circuits are cascade-connected, and the second shift circuits provide a voltage load for the pixel circuits. In this way, the plurality of second shift circuits can reduce the voltage load differences of pixel circuits in different areas of the display panel.

[0006] In one possible implementation, the display panel also includes a controller connected to the multiple second shift circuits, and the second shift circuit provides a voltage load for the pixel circuit, including: the controller determines whether the number of areas in the display area where the pixel circuits are reset simultaneously changes; when the controller determines that the number of areas in the display area where the pixel circuits are reset simultaneously decreases, the controller instructs the second shift circuit to provide a voltage load so that the voltage load when the pixel circuits are reset in the areas after the reduction is the same as the voltage load when the pixel circuits are reset in the areas before the reduction.

[0007] In a possible implementation manner, the pixel circuit includes a pixel compensation circuit and a light-emitting device, and the pixel compensation circuit is used to drive the light-emitting device.

[0008] In a possible implementation, the pixel compensation circuit includes a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor.

[0009] In a possible implementation, the first end of the capacitor and the first end of the fifth transistor are used to receive a power supply voltage, the second end of the capacitor is connected to the first end of the second transistor and the control end of the third transistor, the second end of the second transistor is connected to the first end of the first transistor, the second end of the third transistor, and the first end of the sixth transistor, the second end of the first transistor is used to receive a first input voltage, the second end of the sixth transistor is connected to the first end of the seventh transistor and the anode of the light-emitting device, the second end of the seventh transistor is used to receive a second input voltage, the second end of the fifth transistor is connected to the first end of the third transistor, the first end of the fourth transistor, and the first end of the eighth transistor, the second end of the fourth transistor is used to receive a data voltage corresponding to grayscale data, the second end of the eighth transistor is used to receive a third input voltage, the control end of the seventh transistor is connected to the control end of the eighth transistor for receiving a first reset signal, the control end of the first transistor receives a second reset signal, the control end of the fifth transistor is connected to the control end of the sixth transistor for receiving a first control signal, the control end of the second transistor receives a second control signal, and the control end of the fourth transistor receives a third control signal.

[0010] In one possible implementation, the second input voltage resets the anode of the light-emitting device through the seventh transistor, and the anodes of the light-emitting devices in the pixel circuits of multiple areas in the display area are reset at the same time. When the number of areas in the display area where the pixel circuits are reset at the same time is reduced, the second shift circuit is used to share the second input voltage so that the voltage load of the second input voltage remains unchanged.

[0011] In a possible implementation, the multiple first shift circuits are cascaded connected, including: the output end of the i-th first shift circuit is connected to the reset end of the i-1th first shift circuit and the input end of the i+1th first shift circuit, where i is an integer greater than or equal to 2; the multiple second shift circuits are cascaded connected, including: the output end of the j-th second shift circuit is connected to the reset end of the j-1th second shift circuit and the input end of the j+1th second shift circuit, where j is an integer greater than or equal to 2.

[0012] In a possible implementation manner, the number of the second shift circuits is determined according to the second input voltage.

[0013] In one possible implementation, the display panel is at least one of a low-temperature polycrystalline oxide panel, a liquid crystal display panel, a micro-LED display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small-pitch display panel.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising the display panel as described above.

[0015] The display panel of the disclosed embodiment includes a display area and a non-display area, the display area includes multiple rows of pixel circuits and multiple first shift circuits, each first shift circuit is connected to a row of pixel circuits, and multiple first shift circuits are cascaded; the non-display area includes multiple second shift circuits, each second shift circuit is connected to at least one row of pixel circuits, and multiple second shift circuits are cascaded, and multiple second shift circuits are used to reduce the voltage load difference of pixel circuits in different areas of the display panel. The disclosed embodiment arranges multiple cascaded second shift circuits in the non-display area outside the display area, so that the voltage load of pixel circuits in different areas of the display panel when reset tends to be consistent, removes the horizontal dark band caused by the voltage load difference, improves the image quality of the display panel, and further improves the yield of the display panel product.

[0016] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0018] Figure 1 A schematic diagram showing a display panel according to an embodiment of the present disclosure is shown.

[0019] Figure 2 A schematic diagram showing a connection relationship among a plurality of first shift circuits according to an embodiment of the present disclosure.

[0020] Figure 3 A schematic diagram showing the connection relationship of multiple second shift circuits according to an embodiment of the present disclosure.

[0021] Figure 4 A schematic diagram of a pixel circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram showing the presentation effect of a display panel in the related art is shown.

[0023] Figure 6 A schematic diagram showing the presentation effect of a display panel according to an embodiment of the present disclosure is shown.

[0024] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0026] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0028] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0029] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0030] It should be noted that the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switch transistors. Since the source and drain of the switch transistor used here are symmetrical, the source and drain are interchangeable, and the source is referred to as the first end and the drain is referred to as the second end, or the drain is referred to as the first end and the source is referred to as the second end. For example, the middle end of the transistor may be defined as the gate, the signal input end as the source, and the signal output end as the drain according to the form in the accompanying drawings. In addition, the switch transistors used in the embodiments of the present disclosure may include any one of a P-type transistor and an N-type transistor or a combination thereof. Among them, the P-type transistor is turned on when the gate is a low voltage and is turned off when the gate is a high voltage, and the N-type transistor is turned on when the gate is a high voltage and is turned off when the gate is a low voltage. In addition, multiple signals in each embodiment may correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not represent that the first potential or the second potential has a specific value.

[0031] Figure 1 FIG. 1 is a schematic diagram showing a display panel according to an embodiment of the present disclosure. Figure 1 As shown, the display panel includes a display area 1 and a non-display area 2, the display area 1 includes multiple rows of pixel circuits 3 and multiple first shift circuits 4, each first shift circuit 4 is connected to a row of pixel circuits 3, and multiple first shift circuits 4 are cascaded; the non-display area 2 includes multiple second shift circuits 5, each second shift circuit 5 is connected to at least one row of pixel circuits 3, multiple second shift circuits 5 are cascaded, and the second shift circuits 5 provide voltage loads for the pixel circuits 3. In this way, multiple second shift circuits 5 can reduce the voltage load differences of pixel circuits 3 in different areas of the display panel.

[0032] In one possible implementation, the display panel is at least one of a low-temperature polycrystalline oxide panel (LTPO, Low Temperature Polycrystalline Oxide), a liquid crystal display panel, a micro-LED display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small-pitch display panel, and the embodiments of the present disclosure are not limited to this.

[0033] Exemplarily, display area 1 is an active area (AA) of the display panel, which is used to display pictures. For example, an image can be called a frame, each frame is composed of multiple rows of pixels, and each row of pixels is composed of multiple pixels. The display panel can start from a preset position of display area 1 (for example, above the screen), obtain the data of each row of pixels line by line and display it, and when one row is displayed, jump to the next row to start displaying; when all rows are displayed, it can continue to jump to the next row to start displaying the next frame of the image, or it can jump to a preset position (for example, above the screen) to start displaying the next frame of the image, and the embodiments of the present disclosure are not limited to this.

[0034] Among them, multiple rows of pixel circuits 3 can be arranged in columns in the display area 1, and each row of pixel circuits 3 can be used to display a row of pixels in a frame of image. In addition, the display area 1 also includes multiple first shift circuits 4, and each row of pixel circuits 3 can correspond to one first shift circuit 4, so that the pixel circuits 3 are driven row by row in the display area 1 through the first shift circuits 4.

[0035] Exemplarily, the non-display area 2 can be set as a border area surrounding the outer periphery of the display area 1, or can be set in an adjacent area of ​​the display area 1, such as the top, bottom, left or right side of the display area 1. The embodiments of the present disclosure do not limit the specific position of the non-display area 2, and can be set according to actual application scenarios.

[0036] The non-display area 2 includes a plurality of second shift circuits 5, each of which is connected to one or more rows of pixel circuits 3, so as to reduce the voltage load difference of the pixel circuits 3 in different areas of the display panel.

[0037] Optionally, the first shift circuit 4 can constitute a GOA, the second shift circuit 5 can be regarded as a dummy GOA, and the first shift circuit 4 and the second shift circuit 5 can use the same components, such as a shift register. The connection method of the second shift circuit 5 and the pixel circuit 3 can be the same as that of the first shift circuit 4.

[0038] By setting up multiple cascaded second shift circuits 5 in the non-display area 2 outside the display area 1, the voltage load of the pixel circuits 3 in different areas of the display panel can be made consistent when they are reset, thereby removing the horizontal dark bands caused by the voltage load difference, improving the image quality of the display panel, and further improving the yield of the display panel product.

[0039] In a possible implementation, the display panel further includes a controller connected to the plurality of second shift circuits 5 ( Figure 1(not shown), the second shift circuit 5 provides a voltage load for the pixel circuit 3, including: the controller determines whether the number of areas in the display area where the pixel circuit 3 is reset simultaneously changes; when the controller determines that the number of areas in the display area 1 where the pixel circuit 3 is reset simultaneously is reduced, the controller instructs the second shift circuit 5 to provide a voltage load so that the voltage load when the pixel circuit 3 is reset tends to be consistent, that is, the voltage load when the pixel circuit 3 is reset in the area after the reduction is the same as the voltage load when the pixel circuit 3 is reset in the area before the reduction.

[0040] For example, assuming that there are N rows of pixel circuits 3 and N rows of first shift circuits 4 in the display area 1, the first shift circuit 4 of the first row is connected to the pixel circuit 3 of the first row, the first shift circuit 4 of the second row is connected to the pixel circuit 3 of the second row, and so on, the first shift circuit 4 of the Nth row is connected to the pixel circuit 3 of the Nth row.

[0041] Assume that at time T, there are P areas in the display area 1 (for example, area 1 to area P, each area may correspond to one or more rows of pixel circuits 3, for example, at time T, area 1 corresponds to the N / P×1th row of pixel circuits 3 in the display area 1, area 2 corresponds to the N / P×2th row of pixel circuits 3 in the display area 1, and so on, area P corresponds to the Nth row of pixel circuits 3 in the display area 1), and the pixel circuits 3 are reset at the same time. As time changes, at time T+△t, when Q (Q<P) areas among the P areas are in a blanking state (for example, at time T+1, area P will enter a blanking state), the display area 1 actually resets the pixel circuits 3 corresponding to PQ areas at the same time.

[0042] When the reset voltage remains unchanged, compared with the resetting of the pixel circuits 3 corresponding to the P areas at time T, at time T+△t, the PQ areas have fewer corresponding pixel circuits 3, and the voltage load of the pixel circuits 3 is smaller than that of the P areas. Therefore, the reset of the PQ areas will be more sufficient, which will cause dark horizontal bands to appear on the flat screen.

[0043] The display panel may also be provided with a controller (e.g., a timing controller), the output of which is connected to the input of each second shift circuit 5, and the controller may determine, based on the display code, whether the number of regions in the display area 1 where the pixel circuits 3 are simultaneously reset has changed; if the controller determines that the number of regions in the display area 1 where the pixel circuits 3 are simultaneously reset has decreased, for example, the controller determines, based on the display code, that the number of pixel circuits 3 corresponding to PQ regions at time T+△t is less than the number of pixel circuits 3 corresponding to P regions at time T, the controller may instruct the second shift circuits 5 corresponding to the pixel circuits 3 in Q regions to be turned on at time T+△t, thereby increasing the voltage load to compensate for the Q regions that are in a blanking state, so that the voltage load of the pixel circuits 3 corresponding to the PQ regions when they are reset is consistent with the voltage load of the pixel circuits 3 corresponding to the P regions when they are reset, thereby removing the horizontal dark band caused by the voltage load difference.

[0044] It should be understood that in order to enable the second shift circuit 5 to operate normally and remove the horizontal dark band caused by the voltage load difference, a controller (for example, a timing controller) is provided to provide some control signals for the second shift circuit 5. The controller can output multiple clock signals and other control signals (for example, a start signal) to the second shift circuit 5, so that when the number of areas in the display area 1 where the pixel circuits 3 are reset at the same time is reduced, at least one second shift circuit 5 is turned on to compensate for the load of this area in the blanking state. This is easy for those skilled in the art to understand, and the specific implementation method (for example, the number and timing of the second shift circuits 5 turned on) can be adjusted according to the actual application scenario, which will not be repeated here.

[0045] The blanking state of the display panel refers to a period of time and signal interval set during the display process in order to make the data reading more accurate and the display more stable. For example, for a single-frame image, the display panel can start from a preset position of the screen (such as the top), obtain the data of each pixel in the single-frame image line by line and display it. When one line is displayed, it can jump to the next line, until all lines are displayed, and then jump to the next frame. The display panel can jump line by line and frame by frame.

[0046] Correspondingly, before the display panel prepares to draw the next frame, the display panel will refresh at a preset frequency according to the vertical synchronization signal Vsync (Vertical synchronization). Therefore, there are some intervals between the two frames. The interval between the falling edge and the rising edge of the vertical synchronization signal Vsync can be recorded as VSW, the leading shoulder of the vertical synchronization signal Vsync can be recorded as the vertical leading shoulder VBP, and the trailing shoulder of the vertical synchronization signal Vsync can be recorded as the vertical trailing shoulder VFP. During the time period of VSW+VBP+VFP, the display panel no longer updates pixels, which can be called a blanking state.

[0047] By setting up multiple cascaded second shift circuits 5 in the non-display area 2, the second shift circuit 5 is used to make the voltage load of the pixel circuit 3 consistent when it is reset, remove the horizontal dark band caused by the voltage load difference, improve the image quality of the display panel, and further improve the yield of the display panel product.

[0048] Figure 2 FIG. 4 is a schematic diagram showing the connection relationship of a plurality of first shift circuits 4 according to an embodiment of the present disclosure. Figure 2 As shown, the multiple first shift circuits 4 are cascaded connected, including: the output end of the i-th first shift circuit 4 is connected to the reset end of the i-1th first shift circuit 4 and the input end of the i+1th first shift circuit 4, and i is an integer greater than or equal to 2.

[0049] In this way, the i-1th first shift circuit 4 can first open the i-th first shift circuit 4, and the i-th first shift circuit 4 then opens the i+1th first shift circuit 4, and each first shift circuit 4 is opened in sequence according to the cascade relationship of each first shift circuit 4.

[0050] It should be understood that in order to make the first shift circuit 4 work normally, a controller (such as a timing controller) can also be set to provide some control signals ( Figure 2 (not shown), the controller may output a plurality of clock signals and other control signals (such as a start signal) to the first shift circuit 4, which is easily understood by those skilled in the art and will not be described in detail here.

[0051] Figure 3 FIG. 5 is a schematic diagram showing the connection relationship of a plurality of second shift circuits 5 according to an embodiment of the present disclosure. Figure 2 As shown, the multiple second shift circuits 5 are cascaded connected, including: the output end of the jth second shift circuit 5 is connected to the reset end of the j-1th second shift circuit 5 and the input end of the j+1th second shift circuit 5, and j is an integer greater than or equal to 2.

[0052] In this way, the j-1th second shift circuit 5 can first open (turn on) the jth second shift circuit 5, and the jth second shift circuit 5 then opens the j+1th second shift circuit 5, and each second shift circuit 5 is opened in turn according to the cascade relationship of each second shift circuit 5.

[0053] It should be understood that in order to make the second shift circuit 5 work normally and remove the horizontal dark band caused by the voltage load difference, a controller (such as a timing controller) can also be set to provide some control signals ( Figure 3(not shown), the controller can output multiple clock signals and other control signals (such as a start signal) to the second shift circuit 5, so that when the number of areas in the display area 1 where the pixel circuits 3 are reset simultaneously is reduced, at least one second shift circuit 5 is turned on to compensate for the load of the area in the blanking state. This is easy to understand for those skilled in the art and will not be elaborated here.

[0054] In one possible implementation, Figure 4 A schematic diagram of a pixel circuit 3 according to an embodiment of the present disclosure is shown. Figure 4 As shown, the pixel circuit 3 includes a pixel compensation circuit 6 and a light-emitting device L, and the pixel compensation circuit 6 is used to drive the light-emitting device L.

[0055] Exemplarily, the light emitting device L has a turn-on voltage, and emits light when the voltage difference between the anode and cathode of the light emitting device L is greater than or equal to the turn-on voltage. In a specific implementation, the anode of the light emitting device L is electrically connected to the pixel compensation circuit 6. In an embodiment of the present disclosure, the light emitting device L may include: an electroluminescent diode, such as an organic light-emitting diode (OLED), a quantum dot light emitting diode (QLED), etc.

[0056] Exemplarily, the pixel compensation circuit 6 is a circuit system for adjusting the light emitting state of the light emitting device L. By adjusting the driving signal or circuit parameters of the pixel compensation circuit 6, the light emitting device L can be accurately compensated to achieve uniformity and stability of the display panel display image, reduce the light emission non-uniformity caused by factors such as device aging, environmental differences or driving voltage fluctuations, thereby improving the overall quality of the display panel display image.

[0057] In one possible implementation, Figure 4 As shown, the pixel compensation circuit 6 includes a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0058] Optionally, the third transistor T3 can be used as a driving transistor to provide a driving current for the light emitting device L, and the other first transistor T1, second transistor T2, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be used as switching transistors.

[0059] Optionally, the second transistor T2 is an N-channel thin film transistor, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-channel thin film transistors.

[0060] Among them, the gate of the third transistor T3 as a driving transistor can be used as a control terminal, the drain can be used as a first terminal, and the source can be used as a second terminal. For the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 as switch tubes, the control terminal of these switch tubes is the gate, the first terminal can be the source, and the second terminal can be the drain; or, the first terminal can be the drain, and the second terminal can be the source, and no specific distinction is made here. Further, in a specific implementation, the N-type switch tube is turned on under the action of a high-level signal and turned off under the action of a low-level signal. The P-type switch tube is turned off under the action of a high-level signal and turned on under the action of a low-level signal.

[0061] In one possible implementation, Figure 4As shown, the first end of the capacitor CST and the first end of the fifth transistor T5 are used to receive the power supply voltage ELVDD, the second end of the capacitor CST is connected to the first end of the second transistor T2 and the control end of the third transistor T3, the second end of the second transistor T2 is connected to the first end of the first transistor T1, the second end of the third transistor T3, and the first end of the sixth transistor T6, the second end of the first transistor T1 is used to receive the first input voltage Vinit1, the second end of the sixth transistor T6 is connected to the first end of the seventh transistor T7 and the anode of the light emitting device L, the second end of the seventh transistor T7 is used to receive the second input voltage Vinit2, the second end of the fifth transistor T5 is connected to the first end of the third transistor T3, the first end of the fourth transistor T4, and the anode of the eighth transistor T8 The first end is connected, the second end of the fourth transistor T4 is used to receive the data voltage Data corresponding to the grayscale data, the second end of the eighth transistor T8 is used to receive the third input voltage Vinit3, the control end of the seventh transistor T7 is connected to the control end of the eighth transistor T8 for receiving the first reset signal Reset-H, the control end of the first transistor T1 receives the second reset signal Reset-P, the control end of the fifth transistor T5 is connected to the control end of the sixth transistor T6 for receiving the first control signal EM, the control end of the second transistor T2 receives the second control signal Gate-N, the control end of the fourth transistor T4 receives the third control signal Gate-P, and the cathode of the light emitting device L receives the common ground voltage ELVSS, and the common ground voltage ELVSS is opposite to the level of the power supply voltage ELVDD. Among them, the control end receiving the second control signal Gate-N and the second control signal Gate-P can be connected to the output end of the first shift circuit 4.

[0062] The control end of each transistor in the pixel compensation circuit 6 can control the opening or closing of each transistor according to the high or low level of the received signal.

[0063] For example, the control end of the first transistor T1 is used to receive the second reset signal Reset-P. When the second reset signal Reset-P is at a high level, the first transistor T1 is turned off (cut off); when the second reset signal Reset-P is at a low level, the first transistor T1 is turned on (conducted).

[0064] For example, the control end of the second transistor T2 receives the second control signal Gate-N. When the second control signal Gate-N is at a high level, the second transistor T2 is turned on (conducted); when the second control signal Gate-N is at a low level, the second transistor T2 is turned off (cut off).

[0065] For example, the control end of the fourth transistor T4 receives the third control signal Gate-P. When the third control signal Gate-P is at a high level, the fourth transistor T4 is turned off (cut off); when the third control signal Gate-P is at a low level, the fourth transistor T4 is turned on (conducted).

[0066] For example, the control end of the fifth transistor T5 and the control end of the sixth transistor T6 are used to receive the first control signal EM. When the first control signal EM is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned off (cut off); when the first control signal EM is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on (conducted).

[0067] For example, the control end of the seventh transistor T7 and the control end of the eighth transistor T8 are used to receive the first reset signal Reset-H. When the first reset signal Reset-H is at a high level, the seventh transistor T7 and the eighth transistor T8 are turned off (cut off); when the first reset signal Reset-H is at a low level, the seventh transistor T7 and the eighth transistor T8 are turned on (conducted).

[0068] By controlling the high and low levels of the signals received by the control terminals of the transistors in the pixel compensation circuit 6, the working cycle of the pixel compensation circuit 6 can be divided into four stages, namely, a reset stage, a write stage, a compensation stage, and a light emitting stage.

[0069] For the reset phase as phase 1, the fifth transistor T5 and the sixth transistor T6 are turned off, the second transistor T2 is turned on first, and then the first transistor T1 is turned on. The first input voltage Vinit1 resets the lower substrate of the capacitor CST through the first transistor T1 and the second transistor T2, and turns off the first transistor T1.

[0070] For the writing phase as phase 2, the fourth transistor T4 is turned on, and the data voltage Data charges the capacitor CST lower substrate to Data+Vth voltage through the third transistor T3 and the fourth transistor T4, and the second transistor T2 and the fourth transistor T4 are turned off; wherein Vth is the threshold voltage of the third transistor T3.

[0071] For the compensation stage as stage 3, the seventh transistor T7 and the eighth transistor T8 are turned on, the third input voltage Vinit3 resets the first end of the third transistor T3 through the eighth transistor T8, the second input voltage Vinit2 resets the anode of the light emitting device L through the seventh transistor T7, and the seventh transistor T7 and the eighth transistor T8 are turned off. Among them, the first shift circuit 4 and the second shift circuit 5 can adjust the voltage load of the second input voltage Vinit2.

[0072] In the light emitting stage as stage 4, the fifth transistor T5 and the sixth transistor T6 are turned on, and the supply voltage ELVDD passes through the fifth transistor T5, the third transistor T3, and the sixth transistor T6 to the anode of the light emitting device L, so that the light emitting device L emits light.

[0073] The above is only an example to illustrate the specific structure of a pixel compensation circuit 6 provided in an embodiment of the present disclosure. In specific implementation, the specific structure of the above pixel compensation circuit 6 is not limited to the above structure provided in the embodiment of the present disclosure, and can be adjusted according to the actual application scenario, which is not limited here.

[0074] The pixel compensation circuit 6 can compensate the light emitting device L to achieve uniformity and stability of the display panel display image, reduce the light emission non-uniformity caused by device aging, environmental differences or driving voltage fluctuations, and thus improve the overall quality of the display panel display image.

[0075] The display panel of the embodiment of the present disclosure is introduced below by way of comparative illustration.

[0076] Figure 5 A schematic diagram showing the display effect of a display panel in the related art is shown. Figure 5 As shown in the left part, k (k is a positive integer) cascaded first shift circuits 4 are arranged in the display area 1 of the display panel, for example, the first shift circuit 4_1 to the first shift circuit 4_k. The first shift circuit 4_1 can be turned on first, and the first shift circuit 4_1 then turns on the first shift circuit 4_2, and so on, until the first shift circuit 4_k is turned on in sequence, and then enters the blanking state. Figure 5 The medium blanking state indicates that a certain area of ​​the display area 1 has entered a blanking period or state, rather than a physical area.

[0077] Among them, the blanking state can be determined based on the vertical front shoulder VFP and the vertical back shoulder VBP. The front part of the vertical synchronization signal Vsync is the vertical front shoulder VFP, for example, including vertical front shoulder VFP1~vertical front shoulder VFPm, and the rear part of the vertical synchronization signal Vsync is the vertical back shoulder VBP, for example, including vertical back shoulder VBP1~VBPn.

[0078] The vertical synchronization signal Vsync can indicate the beginning and end of a frame of image, and each frame of image can be displayed by multiple rows of pixel circuits 3. For example, when the vertical synchronization signal Vsync is at a high level, it indicates the end of a frame of image, and when the vertical synchronization signal Vsync is at a low level, it indicates the beginning of a frame of image. Alternatively, when the vertical synchronization signal Vsync is at a high level, it indicates the beginning of a frame of image, and when the vertical synchronization signal Vsync is at a low level, it indicates the end of a frame of image. The vertical front porch (VFP) indicates the time before the vertical synchronization signal Vsync, which is used to adjust the position of the image or refresh the display area 1, that is, within a period of time before the vertical synchronization signal Vsync, the display area 1 can be refreshed or adjusted; similarly, the vertical back porch (VBP) indicates the time after the vertical synchronization signal Vsync, which is used to adjust the position of the image or refresh the display area 1, that is, within a period of time after the vertical synchronization signal Vsync, the display area 1 can be refreshed or adjusted.

[0079] like Figure 5 As shown in the middle part, due to timing limitations, a horizontal dark band will appear on the display area 1 of the display panel, see Figure 5 The two horizontal dark bands shown in Area 1 and Area 2 in the middle part are caused by the following reasons:

[0080] like Figure 4 As shown, when the seventh transistor T7 is turned on by the first reset signal Reset-H, the second input voltage Vinit2 will reset the anode of the light-emitting device L through the seventh transistor T7. Since the k first shift circuits 4 are cascaded and turned on, there will be a situation where the multi-region multi-row pixel circuits 3 are reset at the same time; Figure 5 As shown in the right part, a total of three areas (eg, area 1 to area 3) are reset simultaneously.

[0081] As time changes, since the k first shift circuits 4 are cascaded and opened, the pixel rows in the display area 1 will be transferred upward one by one. At a certain moment, an area (for example, area three) may be in a blank state, and then the other two areas (for example, area one and area two) are in the display area 1.

[0082] This will result in a situation where the second input voltage Vinit2 has different loads, and the two regions (for example Figure 5 Because there are fewer pixel circuits 3 in the middle area (area 1 and area 2), the pixels will be smaller than those in the three areas (e.g. Figure 5 The load of area 1 to area 3 on the right side is small, so the reset of the two areas will be more sufficient. Because the anode of the light-emitting device L is a positive voltage, and the second input voltage Vinit2 is a negative voltage for the anode reset voltage, the anode voltage of the light-emitting device L will be lower in the two areas, and the brightness will be darker.

[0083] contrast Figure 5 The display panel in the related technology shown, in a possible implementation, can add multiple cascaded second shift circuits 5 in the non-display area 2. In this case, the second input voltage Vinit2 resets the anode of the light-emitting device L through the seventh transistor T7, and the anodes of the light-emitting devices L in the pixel circuits 3 in multiple areas of the display area 1 are reset at the same time. As time changes, when the number of areas where the pixel circuits 3 are reset at the same time decreases, the second shift circuit 5 is used to share the second input voltage Vinit2 so that the voltage load of the second input voltage Vinit2 remains unchanged, that is, the voltage load of the second input voltage Vinit2 received by the pixel circuit 3 in the area after the reduction is the same as the voltage load of the second input voltage Vinit2 received by the pixel circuit 3 in the area before the reduction.

[0084] Figure 6 A schematic diagram showing the display effect of a display panel according to an embodiment of the present disclosure is shown in FIG. Figure 6 As shown in the left part, in addition to k (k is a positive integer) cascaded first shift circuits 4, such as the first shift circuit 4_1 to the first shift circuit 4_k, provided in the display area 1 of the display panel, m+n cascaded second shift circuits 5, such as the second shift circuit 5_1 to the second shift circuit 5_m+n, are added in the non-display area 2 outside the display area 1.

[0085] Exemplarily, in the non-display area 2, in order to determine whether each area enters the blanking state, the non-display area 2 may have a signal interface of a vertical front shoulder VFP and a vertical back shoulder VBP, which is used to determine whether each part of the display area 1 enters the blanking state, wherein the front part of the vertical synchronization signal Vsync is a vertical front shoulder (VFP) area, for example, including vertical front shoulder VFP1 to vertical front shoulder VFPm, and the second shift circuit 5_1 to the second shift circuit 5_m can be added accordingly, and the rear part of the vertical synchronization signal Vsync is a vertical back shoulder area (VBP) area, for example, including vertical back shoulder VBP1 to VBPn, and the second shift circuit 5_m+1 to the second shift circuit 5_m+n can be added accordingly.

[0086] The vertical synchronization signal Vsync can indicate the beginning and end of a frame of image, and each frame of image can be displayed by multiple rows of pixel circuits 3. For example, when the vertical synchronization signal Vsync is at a high level, it indicates the end of a frame of image, and when the vertical synchronization signal Vsync is at a low level, it indicates the beginning of a frame of image. Alternatively, when the vertical synchronization signal Vsync is at a high level, it indicates the beginning of a frame of image, and when the vertical synchronization signal Vsync is at a low level, it indicates the end of a frame of image. The vertical front porch (VFP) indicates the time before the vertical synchronization signal Vsync, which is used to adjust the position of the image or refresh the display area 1, that is, within a period of time before the vertical synchronization signal Vsync, the display area 1 can be refreshed or adjusted; similarly, the vertical back porch (VBP) indicates the time after the vertical synchronization signal Vsync, which is used to adjust the position of the image or refresh the display area 1, that is, within a period of time after the vertical synchronization signal Vsync, the display area 1 can be refreshed or adjusted.

[0087] By adding a plurality of cascaded second shift circuits 5 in the non-display area 2, when the second input voltage Vinit2 is refreshed in the blanking state, the corresponding pixel circuit 3 can also draw the load of the second input voltage Vinit2, so that the second input voltage Vinit2 can keep the load consistent at any time, thereby eliminating Figure 6 The dark bands shown in areas 1 and 2 in the middle section.

[0088] In a possible implementation, the number of the second shift circuits 5 is determined according to the second input voltage Vinit2. If the driving capability of the second input voltage Vinit2 is stronger, the second input voltage Vinit2 is less susceptible to interference from other signals, and the number of the second shift circuits 5 is smaller; if the driving capability of the second input voltage Vinit2 is weaker, the second input voltage Vinit2 is more susceptible to interference from other signals, and the number of the second shift circuits 5 is greater.

[0089] In this way, the number of second shift circuits 5 can be reasonably set according to the driving capability of the second input voltage Vinit2, so that when the second input voltage Vinit2 is refreshed in the blanking state, the corresponding pixel circuit 3 can also draw the load of the second input voltage Vinit, so that the second input voltage Vinit2 can maintain a consistent load at any time, thereby reducing the occurrence of dark bands on the screen of the display panel.

[0090] In a possible implementation manner, an electronic device is provided, including the display panel as described above.

[0091] Figure 7A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 may be provided as a server or a terminal device.

[0092] Exemplarily, the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with large screens such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving.

[0093] Exemplarily, the electronic device may also be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: a display, a smart phone or a portable device, a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid (Smart Grid), a wireless terminal in transportation safety (Transportation Safety), a wireless terminal in smart city (Smart City), a wireless terminal in smart home (Smart Home), a wireless terminal in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.

[0094] Reference Figure 7 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0095] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0096] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0097] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

[0098] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0099] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0100] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0101] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area. The display area includes a plurality of rows of pixel circuits and a plurality of first shift circuits, each first shift circuit is connected to a row of pixel circuits, and the plurality of first shift circuits are cascade-connected; The non-display area includes a plurality of second shift circuits, each second shift circuit is connected to at least one row of pixel circuits, a plurality of second shift circuits are cascade-connected, and the second shift circuits provide voltage loads for the pixel circuits.

2. The display panel according to claim 1, characterized in that: The display panel further includes a controller connected to the plurality of second shift circuits, wherein the second shift circuits provide a voltage load for the pixel circuits, including: The controller determines whether the number of regions in the display area where pixel circuits are simultaneously reset changes; When the controller determines that the number of areas in the display area where pixel circuits are reset simultaneously is reduced, the controller instructs the second shift circuit to provide a voltage load so that the voltage load when the pixel circuits are reset in the reduced areas is the same as the voltage load when the pixel circuits are reset in the areas before the reduction.

3. The display panel according to claim 1 or 2, characterized in that: The pixel circuit includes a pixel compensation circuit and a light emitting device, and the pixel compensation circuit is used to drive the light emitting device.

4. The display panel according to claim 3, characterized in that: The pixel compensation circuit includes a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor.

5. The display panel according to claim 4, characterized in that: The first end of the capacitor and the first end of the fifth transistor are used to receive a power supply voltage, the second end of the capacitor is connected to the first end of the second transistor and the control end of the third transistor, the second end of the second transistor is connected to the first end of the first transistor, the second end of the third transistor, and the first end of the sixth transistor, the second end of the first transistor is used to receive a first input voltage, the second end of the sixth transistor is connected to the first end of the seventh transistor and the anode of the light-emitting device, and the second end of the seventh transistor is used to receive a second input voltage. The second end of the fifth transistor is connected to the first end of the third transistor, the first end of the fourth transistor, and the first end of the eighth transistor. The second end of the fourth transistor is used to receive a data voltage corresponding to the grayscale data. The second end of the eighth transistor is used to receive a third input voltage. The control end of the seventh transistor is connected to the control end of the eighth transistor for receiving a first reset signal. The control end of the first transistor receives a second reset signal. The control end of the fifth transistor is connected to the control end of the sixth transistor for receiving a first control signal. The control end of the second transistor receives a second control signal. The control end of the fourth transistor receives a third control signal.

6. The display panel according to claim 5, characterized in that: The second input voltage resets the anode of the light-emitting device through the seventh transistor, and the anodes of the light-emitting devices in the pixel circuits of multiple areas in the display area are reset at the same time. When the number of areas in the display area where the pixel circuits are reset at the same time is reduced, the second shift circuit is used to share the second input voltage so that the voltage load of the second input voltage remains unchanged.

7. The display panel according to claim 1 or 2, characterized in that: The plurality of first shift circuits are connected in cascade, comprising: The output terminal of the i-th first shift circuit is connected to the reset terminal of the i-1-th first shift circuit and the input terminal of the i+1-th first shift circuit, where i is an integer greater than or equal to 2; The plurality of second shift circuits are cascade-connected, comprising: The output end of the j-th second shift circuit is connected to the reset end of the j-1-th second shift circuit and the input end of the j+1-th second shift circuit, where j is an integer greater than or equal to 2.

8. The display panel according to claim 5, characterized in that: The number of the second shift circuits is determined according to the second input voltage.

9. The display panel according to claim 1 or 2, characterized in that: The display panel is at least one of a low-temperature polycrystalline oxide panel, a liquid crystal display panel, a micro-LED display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small-pitch display panel.

10. An electronic device, characterized in that: The invention comprises a display panel according to any one of claims 1 to 9.

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