Electronic device and electronic system

Abstract

The invention relates to an electronic device and an electronic system. The electronic device includes a capacitor connected to an output node of the receiving circuit. The receiving circuit includes an input unit that receives an input signal and an inverted input signal. The receive circuit further includes a current source including a first PMOS transistor between the supply voltage terminal and the first internal node and a first NMOS transistor between the ground voltage terminal and the second internal node, the current source configured to amplify a voltage difference of the input signal and the inverted input signal. The receiving circuit further includes an output unit that drives the output node according to the current supplied from the current source.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2023-0086686, filed on Jul. 4, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Some embodiments of the present disclosure relate to electronic devices and electronic systems that receive input signals having different voltages, sense and amplify a voltage difference between the input signals, and output an amplified signal. Background Art

[0004] Generally, an electronic device receives various signals input from an external device and performs internal operations using the received signals. The electronic device performs internal operations by adjusting the voltage of the received signal, or performs operations of adjusting the voltage of the received signal and outputting the adjusted signal to an external device.

[0005] In order to adjust the voltage of a signal, a differential amplifier circuit is generally used, which senses and amplifies the difference between input signals having different voltages and outputs the amplified input signal. Summary of the invention

[0006] According to an embodiment of the present disclosure, an electronic device includes a capacitor connected to an output node of a receiving circuit. The receiving circuit may include an input unit that receives an input signal and an inverted input signal. The receiving circuit may also include a current source that includes a first PMOS transistor between a power supply voltage terminal and a first internal node and a first NMOS transistor between a ground voltage terminal and a second internal node, the current source being configured to amplify a voltage difference between the input signal and the inverted input signal. The receiving circuit may also include an output unit that drives the output node according to a current supplied from the current source.

[0007] Also according to an embodiment of the present disclosure is an electronic device, which includes a transmission circuit configured to output an input signal and an inverted input signal having different voltages from each other. The electronic device may also include a receiving circuit configured to connect a first power supply node to a power supply voltage terminal via a first PMOS transistor turned on by a first control voltage, and to connect a second power supply node to a ground voltage terminal via a first NMOS transistor turned on by a second control voltage. The receiving circuit may be configured to: directly receive the power supply voltage via the first power supply node; directly receive the ground voltage via the second power supply node; control the current input and current output between the power supply voltage terminal and the ground voltage terminal and the internal node according to the voltage of the input signal and the inverted input signal; and sense and amplify the voltage difference between the input signal and the inverted input signal to generate an internal clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a configuration of an electronic system according to an embodiment of the present disclosure.

[0009] Figure 2 It shows that according to Figure 1 FIG. 2 is a block diagram of a configuration of an embodiment of an electronic device included in an electronic system shown.

[0010] Figure 3 It shows that according to Figure 2 A circuit diagram showing a configuration of an embodiment of a receiving circuit included in an electronic device shown.

[0011] Figure 4 It shows that according to Figure 2 A circuit diagram showing a configuration of another embodiment of a receiving circuit included in an electronic device.

[0012] Figure 5 and Figure 6 It shows that according to Figure 3 A circuit diagram of the operation of an embodiment of a receiving circuit is shown.

[0013] Figure 7 and Figure 8 It shows that according to Figure 4 A circuit diagram of the operation of another embodiment of a receiving circuit is shown.

[0014] Fig. 9 It is shown according to the application Figure 1 The electronic system shown is a schematic diagram of a configuration of an embodiment of an electronic system. DETAILED DESCRIPTION

[0015] In the following description of the embodiments, when a parameter is referred to as "predetermined", it may be intended to mean that the value of the parameter is determined before the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the period in which the process or algorithm is executed.

[0016] It should be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not intended to imply the order or quantity of the elements. Therefore, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0017] In addition, it should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0018] Logical "high" levels and logical "low" levels can be used to describe the logical levels of electrical signals. A signal with a logical "high" level can be distinguished from a signal with a logical "low" level. For example, when a signal with a first voltage corresponds to a signal with a logical "high" level, a signal with a second voltage corresponds to a signal with a logical "low" level. In an embodiment, the voltage level of the logical "high" level can be set to a voltage level higher than the voltage level of the logical "low" level. At the same time, the logic level of the signal can be set to be different or opposite according to the embodiment. For example, a signal with a logical "high" level in one embodiment can be set to have a logical "low" level in another embodiment.

[0019] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0020] Figure 1 1 is a block diagram showing the configuration of an electronic system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the electronic system 1 may include a controller 10 and an electronic device 20. The controller 10 may include a transmission circuit 110. The electronic device 20 may include a reception circuit 220.

[0021] The controller 10 may include a first control pin 11_1, a second control pin 11_2, a third control pin 11_3, and a fourth control pin 11_4. The electronic device 20 may include a first device pin 21_1, a second device pin 21_2, a third device pin 21_3, and a fourth device pin 21_4. The first transmission line L11 may be connected between the first control pin 11_1 and the first device pin 21_1. The second transmission line L12 may be connected between the second control pin 11_2 and the second device pin 21_2. The third transmission line L13 may be connected between the third control pin 11_3 and the third device pin 21_3. The fourth transmission line L14 may be connected between the fourth control pin 11_4 and the fourth device pin 21_4.

[0022] The transmission circuit 110 can output an input signal IN and an inverted input signal INB having different voltages. The transmission circuit 110 can output an input signal IN and an inverted input signal INB having different voltages. Figure 3 VDD) and ground voltage ( Figure 3 The input signal IN and the inverting input signal INB are switched between VSS in the circuit.

[0023] The controller 10 may transmit a command address CA for controlling the electronic device 20 to the electronic device 20 via the first transmission line L11. The controller 10 may transmit an input signal IN to the electronic device 20 via the second transmission line L12. The controller 10 may transmit an inverted input signal INB to the electronic device 20 via the third transmission line L13. The controller 10 may transmit data DATA to the electronic device 20 via the fourth transmission line L14. The controller 10 may receive data DATA from the electronic device 20 via the fourth transmission line L14. The command address CA may include a plurality of bits and may be set to a signal including a command and an address for controlling the operation of the electronic device 20. The input signal IN and the inverted input signal INB may be set to signals having different voltages. The input signal IN and the inverted input signal INB may be set to be at a power supply voltage ( Figure 3 VDD) and ground voltage ( Figure 3 The data DATA may include a plurality of bits, and the plurality of bits may be input and output serially.

[0024] The receiving circuit 220 can control the power supply voltage ( Figure 3 VDD) terminal and ground voltage ( Figure 3 The receiving circuit 220 can sense and amplify the voltage difference between the input signal IN and the inverted input signal INB to generate an internal clock ( Figure 2The receiving circuit 220 can connect the capacitor ( Figure 3 341_2 and 341_4 in, Figure 4 381_3 and 381_5) are connected to the internal clock output ( Figure 2 The output node of ICLK in Figure 3 nd341 in), and via a capacitor ( Figure 3 341_2 and 341_4 in, Figure 4 381_3 and 381_5) to stabilize the internal clock ( Figure 2 The frequency of ICLK in .

[0025] The electronic device 20 can control the power supply voltage ( Figure 3 VDD) terminal and ground voltage ( Figure 3 The electronic device 20 can sense and amplify the voltage difference between the input signal IN and the inverted input signal INB to generate an internal clock ( Figure 2 The electronic device 20 can latch and internal clock (ICLK in) based on the command address CA during the write operation. Figure 2 The electronic device 20 may align the latched data DATA during a write operation to store the internal data ( Figure 2 The electronic device 20 may read the internal data stored therein ( Figure 2 ID<1:N> in) and the internal clock ( Figure 2 The electronic device 20 can output the serialized internal data ( Figure 2 ID<1:N> in is used as data DATA.

[0026] Figure 2 It shows that according to Figure 1 FIG. 1 is a block diagram of a configuration of an embodiment of an electronic device 20 included in an electronic system. Figure 2 As shown, the electronic device 20 according to an embodiment of the present disclosure may include a voltage generating circuit (VOL GEN) 210, a receiving circuit (RX) 220, a command generating circuit (CMD GEN) 230, an internal address generating circuit (IADD GEN) 240, a data input / output circuit (DATA I / O) 250 and a memory circuit 260.

[0027] The voltage generating circuit 210 may generate a first control voltage VN for turning on an NMOS transistor included in the receiving circuit 220. The voltage generating circuit 210 may generate a second control voltage VP for turning on a PMOS transistor included in the receiving circuit 220. The first control voltage VN may be a voltage input to the gate of each of the NMOS transistors included in the receiving circuit 220, and may be generated as a high voltage to turn on the NMOS transistor. The second control voltage VP may be a voltage input to the gate of each of the PMOS transistors included in the receiving circuit 220, and may be generated as a low voltage to turn on the PMOS transistor. Here, high voltage and low voltage are relative concepts, and a high voltage means a voltage of a first voltage level sufficient to turn on an NMOS transistor included in the present disclosure, and a low voltage means a voltage of a second voltage level sufficient to turn on a PMOS transistor included in the present disclosure.

[0028] The receiving circuit 220 can control the power supply voltage ( Figure 3 VDD) terminal and ground voltage ( Figure 3 The receiving circuit 220 can sense and amplify the voltage difference between the input signal IN and the inverted input signal INB to generate an internal clock ( Figure 2 The receiving circuit 220 can connect the capacitor ( Figure 3 341_2 and 341_4 in, Figure 4 381_3 and 381_5) are connected to the internal clock output ( Figure 2 The output node of ICLK in Figure 3 nd341 in), and via a capacitor ( Figure 3 341_2 and 341_4 in, Figure 4 381_3 and 381_5) to stabilize the internal clock ( Figure 2 The frequency of ICLK in .

[0029] The command generation circuit 230 may generate a write command WT and a read command RD in synchronization with the internal clock ICLK based on the first command address to the "L"th command address CA<1:L>. The command generation circuit 230 may generate a write command WT that is enabled when the first command address to the "L"th command address CA<1:L> input in synchronization with the internal clock ICLK have a logic level combination for performing a write operation. The command generation circuit 230 may generate a read command RD that is enabled when the first command address to the "L"th command address CA<1:L> input in synchronization with the internal clock ICLK have a logic level combination for performing a read operation. The first command address to the "L"th command address CA<1:L> may include commands for controlling the write operation and the read operation of the electronic device 20 and addresses for selecting a storage unit in the write operation and the read operation. The number of bits of the first command address to the "L"th command address CA<1:L> may be set to a variety of bit numbers according to the embodiment. The number of bits of the first to 'L'th command addresses CA<1:L> may be set to a positive integer.

[0030] The internal address generation circuit 240 may generate the first internal address to the "M"th internal address IADD<1:M> in synchronization with the internal clock ICLK based on the first command address to the "L"th command address CA<1:L>. The internal address generation circuit 240 may decode the first internal address to the "L"th command address CA<1:L> in synchronization with the internal clock ICLK to generate the first internal address to the "M"th internal address IADD<1:M>. The number of bits of the first internal address to the "M"th internal address IADD<1:M> may be set to a variety of bit numbers according to embodiments. The number of bits "M" of the first internal address to the "M"th internal address IADD<1:M> may be set to a positive integer.

[0031] The data input / output circuit 250 may sequentially latch the first to "N"th data DATA<1:N> in synchronization with the rising and falling edges of the internal clock ICLK during a write operation. The data input / output circuit 250 may align the first to "N"th data DATA<1:N> latched in synchronization with the rising and falling edges of the internal clock ICLK during a write operation to generate the first to "N"th internal data ID<1:N>. The first to "N"th data DATA<1:N> may be input from the controller 10 in a write operation. The data input / output circuit 250 may latch the first to "N"th internal data ID<1:N> in synchronization with the rising and falling edges of the internal clock ICLK during a read operation. The data input / output circuit 250 may serialize the first to "N"th internal data ID<1:N> latched synchronously with the rising and falling edges of the internal clock ICLK to generate the first to "N"th data DATA<1:N> during the read operation. The first to "N"th data DATA<1:N> may be output to the controller 10 during the read operation. The first to "N"th data DATA<1:N> may be serially input / output. The first to "N"th internal data ID<1:N> may be generated in parallel. The number of bits of the first to "N"th data DATA<1:N> and the number of bits of the first to "N"th internal data ID<1:N> may be set to a variety of bit numbers according to the embodiment. The number of bits "N" of the first to "N"th data DATA<1:N> and the number of bits "N" of the first to "N"th internal data ID<1:N> may be set to a positive integer.

[0032] The memory circuit 260 may include a plurality of memory cells MC. The memory circuit 260 may store the first internal data to the "N"th internal data ID<1:N> in the memory cells MC selected by the first internal address to the "M"th internal address IADD<1:M> when the write command WT is enabled. The memory circuit 260 may output the first internal data to the "N"th internal data ID<1:N> stored in the memory cells MC selected by the first internal address to the "M"th internal address IADD<1:M> when the read command RD is enabled.

[0033] The electronic device 20 can control the power supply voltage ( Figure 3 VDD) terminal and ground voltage ( Figure 3 The electronic device 20 can sense and amplify the voltage difference between the input signal IN and the inverted input signal INB to generate an internal clock ( Figure 2 The electronic device 20 can latch and internal clock (ICLK in) based on the command address CA during the write operation. Figure 2 The electronic device 20 may align the latched data DATA during a write operation to store the internal data ( Figure 2 The electronic device 20 may read the internal data stored therein ( Figure 2 ID<1:N> in) and the internal clock ( Figure 2 The electronic device 20 can output the serialized internal data ( Figure 2 ID<1:N> in is used as data DATA.

[0034] Even when inputting to an input cell with a rail-to-rail structure ( Figure 3 310 and Figure 4 When the voltage of the input signal IN and the inverted input signal INB of the electronic device 20 is low, the receiving circuit 220 included in the electronic device 20 may also generate an internal clock ICLK having a voltage between the power supply voltage VDD and the ground voltage VSS. Therefore, the voltage range of the input signal IN and the inverted input signal INB may be maximized. The receiving circuit 220 included in the electronic device 20 may be configured to receive the input signal IN and the inverted input signal INB by applying the second current source ( Figure 3 330 of them, Figure 4 The transmission gate ( Figure 3 331_5 in Figure 4 The receiving circuit 220 included in the electronic device 20 may be implemented to have a single-ended structure in which the receiving circuit 220 senses and amplifies a voltage difference between two signals (input signal IN and inverted input signal INB) to generate one signal (internal clock ICLK).

[0035] Figure 3 It shows that according to Figure 2 The circuit diagram of the receiving circuit 220 a of the embodiment of the receiving circuit 220 included in the electronic device 20 is shown. The receiving circuit 220 a may include an input unit 310 , a first current source 320 , a second current source 330 , and an output unit 340 .

[0036] The input unit 310 may include: an NMOS transistor 311_1 located between a ground voltage VSS terminal and a power supply node nd311; an NMOS transistor 311_2 located between the power supply node nd311 and an internal node nd321; and an NMOS transistor 311_3 located between the power supply node nd311 and an internal node nd331. The NMOS transistor 311_1 may receive a first control voltage VN via a gate and be turned on to supply the ground voltage VSS to the power supply node nd311. The NMOS transistor 311_2 may be turned on when the voltage of the input signal IN is a high voltage (a first voltage level) to increase the current output from the internal node nd321 to the power supply node nd311. The current output from the internal node nd321 to the power supply node nd311 may be set to the product of the amplification factor gm of the NMOS transistor 311_2 and the voltage of the input signal IN. The NMOS transistor 311_3 can be turned on to increase the current output from the internal node nd331 to the power supply node nd311 when the voltage of the inverting input signal INB is a high voltage (a first voltage level). The current output from the internal node nd331 to the power supply node nd311 can be set to the product of the amplification factor gm of the NMOS transistor 311_3 and the voltage of the inverting input signal INB. The amplification factor gm represents the transconductance of the transistor, and the amplification factor gm represents the ratio of controlling the amount of current in the drain according to the voltage input to the gate.

[0037] In addition, the input unit 310 may include: a PMOS transistor 311_4 located between the power supply voltage VDD terminal and the power supply node nd312; a PMOS transistor 311_5 located between the power supply node nd312 and the internal node nd322; and a PMOS transistor 311_6 located between the power supply node nd312 and the internal node nd333. The PMOS transistor 311_4 may receive the second control voltage VP via the gate and be turned on to supply the power supply voltage VDD to the power supply node nd312. The PMOS transistor 311_5 may be turned on when the voltage of the input signal IN is a low voltage (second voltage level) to increase the current output from the power supply node nd312 to the internal node nd322. The current output from the power supply node nd312 to the internal node nd322 may be set to the product of the amplification factor gm of the PMOS transistor 311_5 and the voltage of the input signal IN. The PMOS transistor 311_6 can be turned on when the voltage of the inverting input signal INB is a low voltage (a second voltage level) to increase the current output from the power supply node nd312 to the internal node nd333. The current output from the power supply node nd312 to the internal node nd333 can be set to the product of the amplification factor gm of the PMOS transistor 311_6 and the voltage of the inverting input signal INB.

[0038] The input unit 310 may receive a ground voltage VSS via a power supply node nd311 according to a first control voltage VN. The input unit 310 may receive a power supply voltage VDD via a power supply node nd312 according to a second control voltage VP. The input unit 310 may control current input and current output between a power supply voltage VDD terminal and a ground voltage VSS terminal and internal nodes nd321, nd331, nd322, and nd333 according to voltages of an input signal IN and an inverted input signal INB. The operation of controlling current input and current output between a power supply voltage VDD terminal and a ground voltage VSS terminal and internal nodes nd321, nd331, nd322, and nd333 according to voltages of an input signal IN and an inverted input signal INB in ​​the input unit 310 will be described later with reference to Figure 5 and Figure 6 Let's describe it in more detail.

[0039] The input unit 310 may be implemented to have a rail-to-rail structure. The rail-to-rail structure may refer to a connection structure in which the input unit 310 may directly receive the power supply voltage VDD and the ground voltage VSS to generate a signal having a voltage between the power supply voltage VDD and the ground voltage VSS even when the voltage of the input signal is a low voltage.

[0040] The first current source 320 may include a PMOS transistor 321_1 located between a power supply voltage VDD terminal and an internal node nd321, and a PMOS transistor 321_2 located between the power supply voltage VDD terminal and an internal node nd333. A common gate of the PMOS transistor 321_1 and the PMOS transistor 321_2 may be connected to the internal node nd321. The PMOS transistor 321_1 may supply current from the power supply voltage VDD terminal to the internal node nd321. The PMOS transistor 321_2 may copy the current output from the internal node nd321 to the power supply node nd311, and supply the same current to the internal node nd333.

[0041] In addition, the first current source 320 may include an NMOS transistor 321_3 located between the internal node nd322 and the ground voltage VSS terminal, and an NMOS transistor 321_4 located between the internal node nd331 and the ground voltage VSS terminal. The common gate of the NMOS transistor 321_3 and the NMOS transistor 321_4 may be connected to the internal node nd322. The NMOS transistor 321_3 may output a current from the internal node nd322 to the ground voltage VSS terminal. The NMOS transistor 321_4 may copy the current output from the power supply node nd312 to the internal node nd322, and output the same current from the internal node nd331 to the ground voltage VSS terminal.

[0042] The second current source 330 may include a PMOS transistor 331_1 located between the power supply voltage VDD terminal and the internal node nd331, and a PMOS transistor 331_2 located between the power supply voltage VDD terminal and the internal node nd332. The common gate of the PMOS transistor 331_1 and the PMOS transistor 331_2 may be connected to the internal node nd331. The PMOS transistor 331_1 may supply the following current to the internal node nd331 from the power supply voltage VDD terminal: a current obtained by copying the sum of the current output from the internal node nd331 to the power supply node nd311 by the input unit 310 and the current output from the internal node nd331 to the ground voltage VSS terminal by the first current source 320. The PMOS transistor 331_2 may copy the current supplied by the PMOS transistor 331_1 to the internal node nd331 to supply the same current from the power supply voltage VDD terminal to the internal node nd332.

[0043] In addition, the second current source 330 may include an NMOS transistor 331_3 located between the internal node nd333 and the ground voltage VSS terminal, and an NMOS transistor 331_4 located between the internal node nd334 and the ground voltage VSS terminal. The common gate of the NMOS transistor 331_3 and the NMOS transistor 331_4 may be connected to the internal node nd333. The NMOS transistor 331_3 may supply the ground voltage VSS terminal with a current obtained by copying the sum of the current supplied from the power supply voltage VDD terminal to the internal node nd333 by the input unit 310 and the current supplied from the power supply voltage VDD terminal to the internal node nd333 by the first current source 320. The NMOS transistor 331_4 may copy the current output by the NMOS transistor 331_3 to the ground voltage VSS terminal to output the same current from the internal node nd334 to the ground voltage VSS terminal.

[0044] The second current source 330 may further include a transmission gate 331_5 located between the internal node nd332 and the internal node nd334 and turned on by the first control voltage VN and the second control voltage VP. The transmission gate 331_5 may control the voltage difference between the internal node nd332 and the internal node nd334. The transmission gate 331_5 may control the voltage difference between the internal node nd332 and the internal node nd334 by outputting a current from the PMOS transistor 331_2 to the ground voltage VSS terminal via the NMOS transistor 331_4. When the current output from the PMOS transistor 331_2 to the ground voltage VSS terminal via the NMOS transistor 331_4 increases, the transmission gate 331_5 may increase the voltage difference between the internal node nd332 and the internal node nd334. When the current output from the PMOS transistor 331_2 to the ground voltage VSS terminal via the NMOS transistor 331_4 decreases, the transmission gate 331_5 may reduce the voltage difference between the internal node nd332 and the internal node nd334.

[0045] The output unit 340 may include a PMOS transistor 341_1 located between a power supply voltage VDD terminal and an output node nd341, and an NMOS transistor 341_3 located between the output node nd341 and a ground voltage VSS terminal. When the PMOS transistor 341_1 receives a voltage of an internal node nd332 via a gate and is turned on, the PMOS transistor 341_1 may supply a current from the power supply voltage VDD terminal to the output node nd341 to generate an internal clock ICLK. When the NMOS transistor 341_3 receives a voltage of an internal node nd334 via a gate and is turned on, the NMOS transistor 341_3 may output a current from the output node nd341 to the ground voltage VSS terminal to generate an internal clock ICLK.

[0046] In addition, the output unit 340 may include a capacitor 341_2 located between the internal node nd332 and the output node nd341, and a capacitor 341_4 located between the internal node nd334 and the output node nd341. The capacitor 341_2 can prevent the voltage of the output node nd341 from oscillating operation rapidly changing due to the operation of the second current source 330 and the output unit 340, thereby stabilizing the frequency of the internal clock ICLK. The capacitor 341_4 can prevent the voltage of the output node nd341 from oscillating operation rapidly changing due to the operation of the second current source 330 and the output unit 340, thereby stabilizing the frequency of the internal clock ICLK.

[0047] Figure 4 It shows that according to Figure 2FIG. 2 is a circuit diagram of a receiving circuit 220b of another embodiment of the receiving circuit 220 included in the electronic device 20. Figure 4 As shown, the receiving circuit 220 b may include an input unit 350 , a first current source 360 ​​, a second current source 370 , and an output unit 380 .

[0048] The input unit 350 may include: an NMOS transistor 351_1 located between a ground voltage VSS terminal and a power supply node nd351; an NMOS transistor 351_2 located between the power supply node nd351 and an internal node nd361; and an NMOS transistor 351_3 located between the power supply node nd351 and an internal node nd371. The NMOS transistor 351_1 may receive a first control voltage VN via a gate and be turned on to supply the ground voltage VSS to the power supply node nd351. The NMOS transistor 351_2 may be turned on when the voltage of the input signal IN is a high voltage to increase the current output from the internal node nd361 to the power supply node nd351. The current output from the internal node nd361 to the power supply node nd351 may be set to the product of the amplification factor gm of the NMOS transistor 351_2 and the voltage of the input signal IN. The NMOS transistor 351_3 may be turned on when the voltage of the inverted input signal INB is a high voltage to increase the current output from the internal node nd371 to the power supply node nd351. The current output from the internal node nd371 to the power supply node nd351 can be set to the product of the amplification factor gm of the NMOS transistor 351_3 and the voltage of the inverting input signal INB. The amplification factor gm can represent the transconductance of the transistor, and the amplification factor gm can represent the ratio of adjusting the current amount in the drain according to the voltage input to the gate.

[0049] In addition, the input unit 350 may include: a PMOS transistor 351_4 located between the power supply voltage VDD terminal and the power supply node nd352; a PMOS transistor 351_5 located between the power supply node nd352 and the internal node nd362; and a PMOS transistor 351_6 located between the power supply node nd352 and the internal node nd373. The PMOS transistor 351_4 may receive the second control voltage VP via the gate and be turned on to supply the power supply voltage VDD to the power supply node nd352. The PMOS transistor 351_5 may be turned on when the voltage of the input signal IN is a low voltage to increase the current output from the power supply node nd352 to the internal node nd362. The current output from the power supply node nd352 to the internal node nd362 may be set to the product of the amplification factor gm of the PMOS transistor 351_5 and the voltage of the input signal IN. The PMOS transistor 351_6 may be turned on when the voltage of the inverted input signal INB is a low voltage to increase the current output from the power supply node nd352 to the internal node nd373. The current output from the power supply node nd352 to the internal node nd373 may be set to the product of the amplification factor gm of the PMOS transistor 351_6 and the voltage of the inverted input signal INB.

[0050] The input unit 350 may receive the ground voltage VSS via the power supply node nd351 according to the first control voltage VN. The input unit 350 may receive the power supply voltage VDD via the power supply node nd352 according to the second control voltage VP. The input unit 350 may control the current input and current output between the power supply voltage VDD terminal and the ground voltage VSS terminal and the internal nodes nd361, nd371, nd362, and nd373 according to the voltages of the input signal IN and the inverted input signal INB. The operation of controlling the current input and current output between the power supply voltage VDD terminal and the ground voltage VSS terminal and the internal nodes nd361, nd371, nd362, and nd373 according to the voltages of the input signal IN and the inverted input signal INB will be described with reference to the following description. Figure 7 and Figure 8 Let's describe it in more detail.

[0051] The input unit 350 may be implemented to have a rail-to-rail structure. The rail-to-rail structure may refer to a connection structure in which the input unit 350 may directly receive the power supply voltage VDD and the ground voltage VSS to generate a signal having a voltage between the power supply voltage VDD and the ground voltage VSS even when the voltage of the input signal is a low voltage.

[0052] The first current source 360 ​​may include a PMOS transistor 361_1 located between the power supply voltage VDD terminal and the internal node nd361, and a PMOS transistor 361_2 located between the power supply voltage VDD terminal and the internal node nd373. The common gate of the PMOS transistor 361_1 and the PMOS transistor 361_2 may be connected to the internal node nd361. The PMOS transistor 361_1 may supply current from the power supply voltage VDD terminal to the internal node nd361. The PMOS transistor 361_2 may copy the current output from the internal node nd361 to the power supply node nd351 to supply the same current to the internal node nd373.

[0053] In addition, the first current source 360 ​​may include an NMOS transistor 361_3 located between the internal node nd362 and the ground voltage VSS terminal, and an NMOS transistor 361_4 located between the internal node nd371 and the ground voltage VSS terminal. The common gate of the NMOS transistor 361_3 and the NMOS transistor 361_4 may be connected to the internal node nd362. The NMOS transistor 361_3 may output a current from the internal node nd362 to the ground voltage VSS terminal. The NMOS transistor 361_4 may replicate the current output from the power supply node nd352 to the internal node nd362 to output the same current from the internal node nd371 to the ground voltage VSS terminal.

[0054] The second current source 370 may include a PMOS transistor 371_1 located between the power supply voltage VDD terminal and the internal node nd371, and a PMOS transistor 371_2 located between the power supply voltage VDD terminal and the internal node nd372. The common gate of the PMOS transistor 371_1 and the PMOS transistor 371_2 may be connected to the internal node nd371. The PMOS transistor 371_1 may supply the internal node nd371 with a current obtained by replicating the sum of a current output from the internal node nd371 to the power supply node nd351 by the input unit 350 and a current output from the internal node nd371 to the ground voltage VSS terminal by the first current source 360. The PMOS transistor 371_2 may replicate the current supplied by the PMOS transistor 371_1 to the internal node nd371 to supply the same current from the power supply voltage VDD terminal to the internal node nd372.

[0055] In addition, the second current source 370 may include an NMOS transistor 371_3 located between the internal node nd373 and the ground voltage VSS terminal, and an NMOS transistor 371_4 located between the internal node nd374 and the ground voltage VSS terminal. The common gate of the NMOS transistor 371_3 and the NMOS transistor 371_4 may be connected to the internal node nd373. The NMOS transistor 371_3 may output the following current to the ground voltage VSS terminal: a current obtained by copying the sum of the current supplied from the power supply voltage VDD terminal to the internal node nd373 by the input unit 350 and the current supplied from the power supply voltage VDD terminal to the internal node nd373 by the first current source 360. The NMOS transistor 371_4 may copy the current output by the NMOS transistor 371_3 to the ground voltage VSS terminal to output the same current from the internal node nd374 to the ground voltage VSS terminal.

[0056] In addition, the second current source 370 may include a transmission gate 371_5 located between the internal node nd372 and the internal node nd374 and turned on by the first control voltage VN and the second control voltage VP. The transmission gate 371_5 can control the voltage difference between the internal node nd372 and the internal node nd374. The transmission gate 371_5 can control the voltage difference between the internal node nd372 and the internal node nd374 by outputting the current from the PMOS transistor 371_2 to the ground voltage VSS terminal via the NMOS transistor 371_4. When the current output from the PMOS transistor 371_2 to the ground voltage VSS terminal via the NMOS transistor 371_4 increases, the transmission gate 371_5 can increase the voltage difference between the internal node nd372 and the internal node nd374. When the current output from the PMOS transistor 371_2 to the ground voltage VSS terminal via the NMOS transistor 371_4 decreases, the transmission gate 371_5 can reduce the voltage difference between the internal node nd372 and the internal node nd374.

[0057] The output unit 380 may include a PMOS transistor 381_1 located between a power supply voltage VDD terminal and an output node nd381, and an NMOS transistor 381_4 located between the output node nd381 and a ground voltage VSS terminal. When the PMOS transistor 381_1 receives a voltage of an internal node nd372 via a gate and is turned on, the PMOS transistor 381_1 may supply current from the power supply voltage VDD terminal to the output node nd381 to generate an internal clock ICLK. When the NMOS transistor 381_4 receives a voltage of an internal node nd374 and is turned on, the NMOS transistor 381_4 may output current from the output node nd381 to the ground voltage VSS terminal to generate an internal clock ICLK.

[0058] In addition, the output unit 380 may include: a resistor 381_2 located between the internal node nd372 and the internal node nd382; a capacitor 381_3 located between the internal node nd382 and the output node nd381; a resistor 381_5 located between the internal node nd374 and the internal node nd383; and a capacitor 381_6 located between the internal node nd383 and the output node nd381. The resistor 381_2 and the capacitor 381_3 can prevent the voltage of the output node nd381 from oscillating operation that changes rapidly due to the operation of the second current source 370 and the output unit 380, thereby stabilizing the frequency of the internal clock ICLK. The resistor 381_5 and the capacitor 381_6 can prevent the voltage of the output node nd381 from oscillating operation that changes rapidly due to the operation of the second current source 370 and the output unit 380, thereby stabilizing the frequency of the internal clock ICLK.

[0059] Figure 5 and Figure 6 is a circuit diagram showing the operation of the receiving circuit of the present disclosure. Figure 5 The operation of the receiving circuit 220a according to the embodiment of the present disclosure is described below. The operation of generating the internal clock ICLK when the input signal IN has a high voltage (first voltage level = +ΔV) and the inverted input signal INB has a low voltage (second voltage level = -ΔV) will be described below.

[0060] The NMOS transistor 311_1 of the input unit 310 may receive the first control voltage VN through a gate and be turned on to supply the ground voltage VSS to the power supply node nd311. The PMOS transistor 311_4 may receive the second control voltage VP through a gate and be turned on to supply the power supply voltage VDD to the power supply node nd312.

[0061] The NMOS transistor 311_2 of the input unit 310 can be turned on when the voltage of the input signal IN is a high voltage (first voltage level) to increase the current I11 output from the internal node nd321 to the power supply node nd311. The current I11 output from the internal node nd321 to the power supply node nd311 can be set to the product of the amplification factor gm of the NMOS transistor 311_2 and the voltage of the input signal IN. The NMOS transistor 311_3 can be turned off when the voltage of the inverted input signal INB is a low voltage (second voltage level = -ΔV).

[0062] The PMOS transistor 311_6 of the input unit 310 can be turned on to increase the current I12 output from the power supply node nd312 to the internal node nd333 when the voltage of the inverting input signal INB is a low voltage (a second voltage level). The current I12 output from the power supply node nd312 to the internal node nd333 can be set to the product of the amplification factor gm of the PMOS transistor 311_6 and the voltage of the inverting input signal INB. The PMOS transistor 311_5 can be turned off when the voltage of the input signal IN is a high voltage (a first voltage level).

[0063] The PMOS transistor 321_1 of the first current source 320 may supply current from the power supply voltage VDD terminal to the internal node nd321. The PMOS transistor 321_2 of the first current source 320 may copy the current output from the internal node nd321 to the power supply node nd311 to supply the same current I11 to the internal node nd333.

[0064] The NMOS transistor 331_3 of the second current source 330 may output a current I13 to the ground voltage VSS terminal, the current I13 being obtained by replicating the sum of the current I12 supplied from the power supply voltage VDD terminal to the internal node nd333 by the input unit 310 and the current I11 supplied from the power supply voltage VDD terminal to the internal node nd333 by the first current source 320. The NMOS transistor 331_4 may replicate the current I13 outputted to the ground voltage VSS terminal by the NMOS transistor 331_3 to output the same current I13 from the internal node nd334 to the ground voltage VSS terminal.

[0065] The transmission gate 331_5 of the second current source 330 may be turned on by the first control voltage VN and the second control voltage VP. Since the current I13 is output from the PMOS transistor 331_2 of the second current source 330 to the ground voltage VSS terminal via the NMOS transistor 331_4, the voltage at the internal node nd332 may be generated as a low voltage.

[0066] The PMOS transistor 341_1 of the output unit 340 may receive the voltage of the internal node nd332 via the gate and be turned on to supply the current I14 from the power supply voltage VDD terminal to the output node nd341 and increase the internal clock ICLK to a high voltage. The capacitor 341_2 of the output unit 340 may prevent the oscillation operation in which the voltage of the output node nd341 changes rapidly due to the operation of the second current source 330 and the output unit 340, thereby stabilizing the frequency of the internal clock ICLK. When the internal clock ICLK is generated to have a high voltage, it means that the internal clock ICLK is generated at the power supply voltage VDD level.

[0067] Even when the voltage of the input signal IN and the inverted input signal INB input to the input unit 310 having a rail-to-rail structure is a low voltage, the above-mentioned receiving circuit 220a can generate an internal clock ICLK having a voltage between the power supply voltage VDD and the ground voltage VSS, thereby maximizing the voltage range of the input signal IN and the inverted input signal INB. The receiving circuit 220a can reduce current consumption by applying the transmission gate 331_5 included in the second current source 330. The receiving circuit 220a can be implemented in a single-ended structure, in which the receiving circuit 220a senses and amplifies the voltage difference between two signals (the input signal IN and the inverted input signal INB) to generate one signal (the internal clock ICLK).

[0068] Will refer to Figure 6 The operation of the receiving circuit 220a according to the embodiment of the present disclosure is described below. The operation of generating the internal clock ICLK when the input signal IN has a low voltage (second voltage level = -ΔV) and the inverted input signal INB has a high voltage (first voltage level = +ΔV) will be described below.

[0069] The NMOS transistor 311_1 of the input unit 310 may receive the first control voltage VN through a gate and be turned on to supply the ground voltage VSS to the power supply node nd311. The PMOS transistor 311_4 of the input unit 310 may receive the second control voltage VP through a gate and be turned on to supply the power supply voltage VDD to the power supply node nd312.

[0070] The NMOS transistor 311_3 of the input unit 310 can be turned on to increase the current I21 output from the internal node nd331 to the power supply node nd311 when the voltage of the inverting input signal INB is a high voltage (a first voltage level). The current I21 output from the internal node nd331 to the power supply node nd311 can be set to the product of the amplification factor gm of the NMOS transistor 311_3 and the voltage of the inverting input signal INB. The NMOS transistor 311_2 can be turned off when the voltage of the input signal IN is a low voltage (a second voltage level).

[0071] The PMOS transistor 311_5 of the input unit 310 can be turned on when the voltage of the input signal IN is a low voltage (a second voltage level) to increase the current I22 output from the power supply node nd312 to the internal node nd322. The current I22 output from the power supply node nd312 to the internal node nd322 can be set to the product of the amplification factor gm of the PMOS transistor 311_5 and the voltage of the input signal IN. The PMOS transistor 311_6 can be turned off when the voltage of the inverted input signal INB is a high voltage (a first voltage level = +ΔV).

[0072] The NMOS transistor 321_3 of the first current source 320 may output the current I22 from the internal node nd322 to the ground voltage VSS terminal. The NMOS transistor 321_4 of the first current source 320 may replicate the current I22 output from the power supply node nd312 to the internal node nd322 to output the same current I22 from the internal node nd331 to the ground voltage VSS terminal.

[0073] The PMOS transistor 331_1 of the second current source 330 may supply a current I23 to the internal node nd331, the current I23 being obtained by replicating the sum of the current I21 output from the internal node nd331 to the power supply node nd311 by the input unit 310 and the current I22 output from the internal node nd331 to the ground voltage VSS terminal by the first current source 320. The PMOS transistor 331_2 of the second current source 330 may replicate the current I23 supplied by the PMOS transistor 331_1 to the internal node nd331 to supply the same current I23 from the power supply voltage VDD terminal to the internal node nd332.

[0074] The transmission gate 331_5 of the second current source 330 may be turned on by the first control voltage VN and the second control voltage VP. Since the current I23 is not output from the PMOS transistor 331_2 of the second current source 330 to the ground voltage VSS terminal via the NMOS transistor 331_4, the voltage of the internal node nd334 may be generated as a high voltage.

[0075] The NMOS transistor 341_3 of the output unit 340 can receive the voltage of the internal node nd334 via the gate to be turned on and output the current I24 to the ground voltage VSS terminal to reduce the voltage of the internal clock ICLK to a low voltage. The capacitor 341_4 of the output unit 340 can prevent the oscillation operation in which the voltage of the output node nd341 changes rapidly due to the operation of the second current source 330 and the output unit 340, thereby stabilizing the frequency of the internal clock ICLK. When the voltage of the internal clock ICLK is reduced to a low voltage and generated, it means that the internal clock ICLK is generated at the ground voltage VSS level.

[0076] Even when the voltage of the input signal IN and the inverted input signal INB input to the input unit 310 having a rail-to-rail structure is a low voltage, the above-mentioned receiving circuit 220a can generate an internal clock ICLK having a voltage between the power supply voltage VDD and the ground voltage VSS, thereby maximizing the voltage range of the input signal IN and the inverted input signal INB. The receiving circuit 220a can reduce current consumption by applying the transmission gate 331_5 included in the second current source 330. The receiving circuit 220a can be implemented in a single-ended structure, in which the receiving circuit 220a senses and amplifies the voltage difference between two signals (the input signal IN and the inverted input signal INB) to generate one signal (the internal clock ICLK).

[0077] Figure 7 and Figure 8 is a circuit diagram showing the operation of the receiving circuit of the present disclosure. Figure 7 The operation of the receiving circuit 220b according to the embodiment of the present disclosure is described below. The operation of generating the internal clock ICLK when the input signal IN has a high voltage (first voltage level = +ΔV) and the inverted input signal INB has a low voltage (second voltage level = -ΔV) will be described below.

[0078] The NMOS transistor 351_1 of the input unit 350 may receive the first control voltage VN through a gate and be turned on to supply the ground voltage VSS to the power supply node nd351. The PMOS transistor 351_4 of the input unit 350 may receive the second control voltage VP through a gate and be turned on to supply the power supply voltage VDD to the power supply node nd352.

[0079] The NMOS transistor 351_2 of the input unit 350 can be turned on when the voltage of the input signal IN is a high voltage (first voltage level) to increase the current I31 output from the internal node nd361 to the power supply node nd351. The current I31 output from the internal node nd361 to the power supply node nd351 can be set to the product of the amplification factor gm of the NMOS transistor 351_2 and the voltage of the input signal IN. The NMOS transistor 351_3 can be turned off when the voltage of the inverted input signal INB is a low voltage (second voltage level = -ΔV).

[0080] The PMOS transistor 351_6 of the input unit 350 can be turned on to increase the current I32 output from the power supply node nd352 to the internal node nd373 when the voltage of the inverting input signal INB is a low voltage (a second voltage level). The current I32 output from the power supply node nd352 to the internal node nd373 can be set to the product of the amplification factor gm of the PMOS transistor 351_6 and the voltage of the inverting input signal INB. The PMOS transistor 351_5 can be turned off when the voltage of the input signal IN is a high voltage (a first voltage level).

[0081] The PMOS transistor 361_1 of the first current source 360 ​​may supply current from the power supply voltage VDD terminal to the internal node nd361. The PMOS transistor 361_2 of the first current source 360 ​​may copy the current I31 supplied from the internal node nd361 to the power supply node nd351 to supply the same current I31 to the internal node nd373.

[0082] The NMOS transistor 371_3 of the second current source 370 may output a current I33 obtained by replicating the sum of a current I32 supplied from the power supply voltage VDD terminal to the internal node nd373 by the input unit 350 and a current I31 supplied from the power supply voltage VDD terminal to the internal node nd373 by the first current source 360 ​​to the ground voltage VSS terminal. The NMOS transistor 371_4 may replicate the current I33 output from the ground voltage VSS terminal by the NMOS transistor 371_3 to output the same current I33 from the internal node nd374 to the ground voltage VSS terminal.

[0083] The transmission gate 371_5 of the second current source 370 may be turned on by the first control voltage VN and the second control voltage VP. Since the current I33 is output from the PMOS transistor 371_2 of the second current source 370 to the ground voltage VSS terminal via the NMOS transistor 371_4, the voltage of the internal node nd372 may be generated as a low voltage.

[0084] The PMOS transistor 381_1 of the output unit 380 can receive the voltage of the internal node nd372 via the gate to be turned on, and supply the current I34 from the power supply voltage VDD terminal to the output node nd381 to increase the voltage of the internal clock ICLK to a high voltage. The resistor 381_2 and the capacitor 381_3 of the output unit 380 can prevent the oscillation operation in which the voltage of the output node nd381 changes rapidly due to the operation of the second current source 370 and the output unit 380, thereby stabilizing the frequency of the internal clock ICLK. When the internal clock ICLK is generated to have a high voltage, it means that the internal clock ICLK is generated at the power supply voltage VDD level.

[0085] Even when the voltage of the input signal IN and the inverted input signal INB input to the input unit 350 having a rail-to-rail structure is a low voltage, the above-mentioned receiving circuit 220b can generate an internal clock ICLK having a voltage between the power supply voltage VDD and the ground voltage VSS, thereby maximizing the voltage range of the input signal IN and the inverted input signal INB. The receiving circuit 220b can reduce current consumption by applying the transmission gate 371_5 included in the second current source 370. The receiving circuit 220b can be implemented in a single-ended structure, in which the receiving circuit 220b senses and amplifies the voltage difference between two signals (the input signal IN and the inverted input signal INB) to generate one signal (the internal clock ICLK).

[0086] Will refer to Figure 8 The operation of the receiving circuit 220b according to the embodiment of the present disclosure is described below. The operation of generating the internal clock ICLK when the input signal IN has a low voltage (second voltage level = -ΔV) and the inverted input signal INB has a high voltage (first voltage level = +ΔV) will be described below.

[0087] The NMOS transistor 351_1 of the input unit 350 may receive the first control voltage VN through a gate and be turned on to supply the ground voltage VSS to the power supply node nd351. The PMOS transistor 351_4 of the input unit 350 may receive the second control voltage VP through a gate and be turned on to supply the power supply voltage VDD to the power supply node nd352.

[0088] The NMOS transistor 351_3 of the input unit 350 can be turned on to increase the current I41 output from the internal node nd371 to the power supply node nd351 when the voltage of the inverting input signal INB is a high voltage. The current I41 output from the internal node nd371 to the power supply node nd351 can be set to the product of the amplification factor gm of the NMOS transistor 351_3 and the voltage of the inverting input signal INB. The NMOS transistor 351_2 can be turned off when the voltage of the input signal IN is a low voltage (a second voltage level).

[0089] The PMOS transistor 351_5 of the input unit 350 can be turned on when the voltage of the input signal IN is a low voltage (a second voltage level) to increase the current I42 output from the power supply node nd352 to the internal node nd362. The current I42 output from the power supply node nd352 to the internal node nd362 can be set to the product of the amplification factor gm of the PMOS transistor 351_5 and the voltage of the input signal IN. The PMOS transistor 351_6 can be turned off when the voltage of the inverted input signal INB is a high voltage (a first voltage level = +ΔV).

[0090] The NMOS transistor 361_3 of the first current source 360 ​​may output the current I42 from the internal node nd362 to the ground voltage VSS terminal. The NMOS transistor 361_4 of the first current source 360 ​​may replicate the current I42 output from the power supply node nd352 to the internal node nd362 to output the same current I42 from the internal node nd371 to the ground voltage VSS terminal.

[0091] The PMOS transistor 371_1 of the second current source 370 may supply a current I43 to the internal node nd371, which is obtained by replicating the sum of the current I41 output from the internal node nd371 to the power supply node 351 by the input unit 350 and the current I42 output from the internal node nd371 to the ground voltage VSS terminal by the first current source 360. The PMOS transistor 371_2 of the second current source 370 may replicate the current I43 supplied by the PMOS transistor 371_1 to the internal node nd371 to supply the same current I43 from the power supply voltage VDD terminal to the internal node nd372.

[0092] The transmission gate 371_5 of the second current source 370 may be turned on by the first control voltage VN and the second control voltage VP. Since the current I43 is not output from the PMOS transistor 371_2 of the second current source 370 to the ground voltage VSS terminal via the NMOS transistor 371_4, the voltage at the internal node nd374 may be generated as a high voltage.

[0093] The NMOS transistor 381_4 of the output unit 380 can receive the voltage of the internal node nd374 to be turned on, and output the current I44 from the output node nd381 to the ground voltage VSS terminal to reduce the voltage of the internal clock ICLK to a low voltage. The resistor 381_5 and the capacitor 381_6 of the output unit 380 can prevent the oscillation operation in which the voltage of the output node nd381 changes rapidly due to the operation of the second current source 370 and the output unit 380, thereby stabilizing the frequency of the internal clock ICLK. When the voltage of the internal clock ICLK is reduced to a low voltage and generated, it means that the internal clock ICLK is generated at the ground voltage VSS level.

[0094] Even when the voltage of the input signal IN and the inverted input signal INB input to the input unit 350 having a rail-to-rail structure is a low voltage, the above-mentioned receiving circuit 220b can generate an internal clock ICLK having a voltage between the power supply voltage VDD and the ground voltage VSS, thereby maximizing the voltage range of the input signal IN and the inverted input signal INB. The receiving circuit 220b can reduce current consumption by applying the transmission gate 371_5 included in the second current source 370. The receiving circuit 220b can be implemented in a single-ended structure, in which the receiving circuit 220b senses and amplifies the voltage difference between two signals (the input signal IN and the inverted input signal INB) to generate one signal (the internal clock ICLK).

[0095] Fig. 9 1 is a block diagram showing a configuration of an electronic system 1000 according to an embodiment of the present disclosure. Fig. 9 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200 .

[0096] The host 1100 and the semiconductor system 1200 may use an interface protocol to transmit signals to each other. The interface protocol used between the host 1100 and the semiconductor system 1200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), a universal serial bus (USB), etc.

[0097] The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400 (1: K). The controller 1300 may control the semiconductor device 1400 (1: K) to perform a write operation and a read operation. Even when the voltage of the input signal IN and the inverted input signal INB input to the input unit having a rail-to-rail structure is a low voltage, each of the semiconductor devices 1400 (1: K) may generate an internal clock ICLK having a voltage between a power supply voltage VDD and a ground voltage VSS, thereby maximizing the voltage range of the input signal IN and the inverted input signal INB. Each of the semiconductor devices 1400 (K: 1) may reduce current consumption by applying a transmission gate included in a current source of a receiving circuit included therein. Each of the semiconductor devices 1400 (K: 1) may generate an internal clock having a stable frequency via a capacitor connected to an output node of a receiving circuit included therein. Each of the semiconductor devices 1400 (K: 1) can be implemented to have a single-ended structure, in which each of the semiconductor devices 1400 (K: 1) senses and amplifies the voltage difference between two signals (input signal IN and inverted input signal INB) to generate a signal (internal clock ICLK).

[0098] The controller 1300 may be implemented as Figure 1 The controller 10 shown. Each of the semiconductor devices 1400 (K: 1) can be implemented as Figure 2 The semiconductor device 20 is shown. According to an embodiment, each of the semiconductor devices 1400(1:K) can be implemented with one of a dynamic random access memory (DRAM) device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device.

[0099] Concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will recognize that various modifications, additions and / or substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive perspective, but rather from an illustrative perspective. The scope of the concepts is not limited to the above description, but is defined by the appended claims, and all significant features within the scope of equivalents should be interpreted as included in the concepts.

Claims

1. An electronic device, comprising: Receiving circuit; as well as a capacitor connected to an output node of the receiving circuit; Wherein, the receiving circuit comprises: An input unit receiving an input signal and an inverted input signal; a current source including a first PMOS transistor and a first NMOS transistor, the first PMOS transistor being located between a power supply voltage terminal and a first internal node, and the first NMOS transistor being located between a ground voltage terminal and a second internal node, the current source amplifying a voltage difference between the input signal and the inverted input signal; and An output unit drives the output node according to the current supplied from the current source.

2. The electronic device according to claim 1, wherein: The input unit comprises: a second NMOS transistor located between the ground voltage terminal and a first power supply node, the second NMOS transistor being turned on by a first control voltage to directly supply a ground voltage to the first power supply node; and A second PMOS transistor is located between the power supply voltage terminal and a second power supply node, wherein the second PMOS transistor is turned on by a second control voltage to directly supply a power supply voltage to the second power supply node.

3. The electronic device according to claim 1, wherein: The input unit: Directly accepts ground and supply voltages, and Current input and current output between the ground voltage terminal and the power supply voltage terminal and the first and second internal nodes are controlled according to voltages of the input signal and the inverted input signal.

4. The electronic device as claimed in claim 1, in, The current source comprises a first current source, Wherein, the first current source includes the first PMOS transistor and the first NMOS transistor, and The first current source: supplies current to the first internal node via the first PMOS transistor; and releases current of the second internal node via the first NMOS transistor.

5. The electronic device as claimed in claim 4, in, The current source further includes a second current source, Wherein, the second current source includes a third PMOS transistor and a fourth PMOS transistor and a third NMOS transistor and a fourth NMOS transistor; wherein the second current source: supplies current to a third internal node via the third PMOS transistor; and supplies current to a fifth internal node via the fourth PMOS transistor, and The second current source: releases the current of the fourth internal node via the third NMOS transistor; and releases the current of the sixth internal node via the fourth NMOS transistor.

6. The electronic device as claimed in claim 5, in, The second current source further includes a transmission gate, and The transmission gate is turned on by the first control voltage and the second control voltage to control the voltage difference between the fifth internal node and the sixth internal node.

7. The electronic device as claimed in claim 1, wherein: The output unit comprises: a fifth PMOS transistor connected between the power supply voltage terminal and the output node, the fifth PMOS transistor driving the output node by a voltage of the fifth internal node; and A fifth NMOS transistor is connected between the output node and the ground voltage terminal, and the fifth NMOS transistor drives the output node by the voltage of the sixth internal node.

8. The electronic device as claimed in claim 1, wherein: The output unit comprises: a first capacitor connected between the fifth internal node and the output node; and A second capacitor is connected between the sixth internal node and the output node.

9. The electronic device as claimed in claim 1, wherein: The output unit comprises: a first resistor connected between the fifth internal node and a seventh internal node; a first capacitor connected between the seventh internal node and the output node; a second resistor connected between the sixth internal node and an eighth internal node; and A second capacitor is connected between the eighth internal node and the output node.

10. The electronic device according to claim 1, wherein: The receiving circuit drives the output node according to voltages of the input signal and the inverted input signal to generate an internal clock.

11. The electronic device according to claim 10, wherein: The receiving circuit generates the internal clock when the voltages of the input signal and the inverted input signal are voltages between the power supply voltage and the ground voltage.

12. The electronic device according to claim 10, wherein: The receiving circuit stabilizes the frequency of the internal clock via the capacitor connected to the output node.

13. The electronic device according to claim 1, wherein: The receiving circuit comprises: an input unit, which: directly receives a power supply voltage and a ground voltage through a first control voltage and a second control voltage; outputs a first current from the first internal node to the ground voltage terminal when the input signal is at a first voltage level; and supplies a second current from the power supply voltage terminal to a fourth internal node when the inverted input signal is at a second voltage level; a first current source supplying the first current to the fourth internal node; a second current source that supplies a third current to a fifth internal node and a sixth internal node, the third current being a sum of the first current and the second current; and An output unit supplies a current to the output node to generate an internal clock according to the third current supplied to the fifth internal node and the sixth internal node.

14. The electronic device according to claim 1, wherein: The receiving circuit comprises: an input unit, which: directly receives a power supply voltage and a ground voltage through a first control voltage and a second control voltage; outputs a first current from a third internal node to the ground voltage terminal when the inverted input signal is at a first voltage level; and supplies a second current from the power supply voltage terminal to the second internal node when the input signal is at a second voltage level; a first current source that outputs the second current from the third internal node to the ground voltage terminal; a second current source that supplies a third current to a fifth internal node and a sixth internal node, the third current being a sum of the first current and the second current; and An output unit supplies a current to the output node to generate an internal clock according to the third current supplied to the fifth internal node and the sixth internal node.

15. An electronic device comprising: a transmission circuit that outputs an input signal and an inverted input signal having voltages different from each other; as well as A receiving circuit that: connects a first power supply node to a power supply voltage terminal via a first PMOS transistor turned on by a first control voltage; and connects a second power supply node to a ground voltage terminal via a first NMOS transistor turned on by a second control voltage; Wherein, the receiving circuit: directly receives the power supply voltage via the first power supply node; directly receives the ground voltage via the second power supply node; controls the current input and current output between the power supply voltage terminal and the ground voltage terminal and the internal node according to the voltage of the input signal and the inverted input signal; and senses and amplifies the voltage difference between the input signal and the inverted input signal to generate an internal clock.

16. The electronic device as claimed in claim 15, wherein: The receiving circuit includes a rail-to-rail structure in which the receiving circuit directly receives the power supply voltage and the ground voltage via the first PMOS transistor and the first NMOS transistor.

17. The electronic device as claimed in claim 15, wherein: The receiving circuit includes a single-ended structure in which the receiving circuit senses and amplifies the voltage difference between the input signal and the inverted input signal to generate the internal clock.

18. The electronic device as claimed in claim 15, wherein: The receiving circuit stabilizes the frequency of the internal clock via a first capacitor and a second capacitor connected to an output node generating the internal clock.

19. The electronic device according to claim 15, wherein: The receiving circuit comprises: an input unit, which: directly receives the power supply voltage and the ground voltage through the first control voltage and the second control voltage; and controls current input and current output between the power supply voltage terminal and the ground voltage terminal and the first to fourth internal nodes according to the voltages of the input signal and the inverted input signal; a first current source that supplies current to the first internal node and the second internal node; a second current source that: supplies current to the third internal node and the fourth internal node; and supplies current to a fifth internal node and a sixth internal node according to the current supplied to the third internal node and the fourth internal node; and An output unit supplies or outputs a current to an output node according to the current supplied to the fifth internal node and the sixth internal node to generate the internal clock.

20. The electronic device as claimed in claim 19, wherein: The output unit comprises: a first capacitor connected between the fifth internal node and the output node; and a second capacitor connected between the sixth internal node and the output node, and The frequency of the internal clock is stabilized via the first capacitor and the second capacitor.

21. The electronic device as claimed in claim 19, wherein: The output unit comprises: a first resistor connected between the fifth internal node and a seventh internal node; a first capacitor connected between the seventh internal node and the output node; a second resistor connected between the sixth internal node and an eighth internal node; and a second capacitor connected between the eighth internal node and the output node, and The frequency of the internal clock is stabilized via the first capacitor and the second capacitor.

22. The electronic device as claimed in claim 15, wherein: The receiving circuit comprises: an input unit, which: directly receives the power supply voltage and the ground voltage through the first control voltage and the second control voltage; outputs a first current from a first internal node to the ground voltage terminal when the input signal is at a first voltage level; and supplies a second current from the power supply voltage terminal to a fourth internal node when the inverted input signal is at a second voltage level; a first current source supplying the first current to the fourth internal node; a second current source that supplies a third current to a fifth internal node and a sixth internal node, the third current being a sum of the first current and the second current; and An output unit supplies a current to the output node according to the third current supplied to the fifth internal node and the sixth internal node to generate the internal clock.

23. The electronic device of claim 15, wherein: The receiving circuit comprises: an input unit, which: directly receives the power supply voltage and the ground voltage through the first control voltage and the second control voltage; outputs a first current from a third internal node to the ground voltage terminal when the inverted input signal is at a first voltage level; and supplies a second current from the power supply voltage terminal to the second internal node when the input signal is at a second voltage level; a first current source that outputs the second current from the third internal node to the ground voltage terminal; a second current source that supplies a third current to a fifth internal node and a sixth internal node, the third current being a sum of the first current and the second current; and An output unit supplies a current to the output node according to the third current supplied to the fifth internal node and the sixth internal node to generate the internal clock.

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