Method of operating memory device and memory device

Abstract

The invention discloses a method of operating a memory device and the memory device. The memory device includes a memory controller and a non-volatile memory device. The method includes providing, by a memory controller, a first request indicating a word line selection operation of a target memory block to a non-volatile memory device; obtaining, by the non-volatile memory device, distribution information of a plurality of word lines of the target memory block based on the first request; determining, by the non-volatile memory device, a degraded word line among the plurality of word lines based on the distribution information; and providing, by the non-volatile memory device, word line information indicating the degraded word line to the memory controller.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0088309 filed on Jul. 7, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a storage device, and more particularly, to a method of operating a storage device and a storage device. Background Art

[0003] The memory device stores data in response to a write request and outputs data in response to a read request. For example, the memory device is classified into a volatile memory device (such as a dynamic random access memory (DRAM) device or a static RAM (SRAM) device) that loses data stored therein when power is turned off, or a nonvolatile memory device (such as a flash memory device, a phase change RAM (PRAM), a magnetic RAM (MRAM), or a resistive RAM (RRAM)) that retains data stored therein even when power is turned off.

[0004] When programming a memory cell of a nonvolatile memory device based on a data bit value, the memory cell may form a threshold voltage distribution corresponding to the data bit value. The threshold voltage distribution may change over time due to the retention or physical characteristics of the electronic components. The change in the threshold voltage distribution may result in a reduction in reliability. In order to limit the reduction in the reliability of the nonvolatile memory device, it is desirable to periodically check the change in the threshold voltage distribution and perform a reliability operation for compensating for the change in the threshold voltage distribution. Summary of the invention

[0005] The disclosed subject matter generally relates to memory devices that determine degraded word lines and methods of operating the memory devices.

[0006] According to one aspect, a method for operating a storage device including a storage controller and a non-volatile memory device includes: providing, by the storage controller, a first request indicating a word line selection operation of a target memory block to the non-volatile memory device; obtaining, by the non-volatile memory device, distribution information of a plurality of word lines of the target memory block based on the first request; determining, by the non-volatile memory device, a degraded word line among the plurality of word lines based on the distribution information; and providing, by the non-volatile memory device, word line information indicating the degraded word line to the storage controller.

[0007] According to one aspect, a method for operating a storage device including a storage controller and a non-volatile memory device includes: providing, by the storage controller, a first request indicating a word line selection operation of a target memory block to the non-volatile memory device; obtaining, by the non-volatile memory device, distribution information of multiple word lines of the target memory block based on the first request; determining, by the non-volatile memory device, a degraded word line among the multiple word lines based on the distribution information; determining, by the non-volatile memory device, whether a reclaim condition for the degraded word line is satisfied; and providing, by the non-volatile memory device, a determination result response indicating whether the reclaim condition is satisfied to the storage controller.

[0008] According to one aspect, a storage device includes: a memory cell array including a plurality of memory blocks; a storage controller generating a first request indicating a word line selection operation of a target memory block among the plurality of memory blocks; and control logic communicating with the memory cell array and the storage controller. The control logic obtains distribution information through an on-chip read operation of a plurality of word lines of the target memory block based on the first request, determines a degraded word line among the plurality of word lines based on the distribution information, and generates word line information indicating the degraded word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a storage system according to some embodiments of the present disclosure.

[0010] Figure 2 Some embodiments of the present disclosure are shown in Figure 1 A block diagram of a storage controller.

[0011] Figure 3 Some embodiments of the present disclosure are shown in Figure 1 A block diagram of a non-volatile memory device.

[0012] Figure 4 is a diagram describing a reliability operation of a conventional memory device.

[0013] Figure 5 is a diagram describing a reliability operation of a memory device according to some embodiments of the present disclosure.

[0014] Figure 6 Describes some embodiments of the present disclosure Figure 5 A diagram of the operating status of a storage device.

[0015] Fig. 7A is a diagram illustrating threshold voltage distribution of a single-level cell according to some embodiments of the present disclosure.

[0016] Figure 7B is a diagram illustrating threshold voltage distribution of a multi-level cell according to some embodiments of the present disclosure.

[0017] Figure 7C is a diagram illustrating threshold voltage distribution of a three-level cell according to some embodiments of the present disclosure.

[0018] Fig.7D is a diagram illustrating threshold voltage distribution of a quad-level cell according to some embodiments of the present disclosure.

[0019] Figure 8 is a diagram describing changes in threshold voltage distribution according to some embodiments of the present disclosure.

[0020] Fig. 9 is a flowchart describing a method of operating a storage device according to some embodiments of the present disclosure.

[0021] Fig.10 The operation of some embodiments of the present disclosure is described Fig. 9 A diagram of a method for a non-volatile memory device.

[0022] Fig.11 is a diagram for describing a method of operating a memory device according to some embodiments of the present disclosure.

[0023] Fig.12 is a flowchart describing a method of operating a storage device according to some embodiments of the present disclosure.

[0024] Fig.13 is a flowchart describing a method of operating a non-volatile memory device according to some embodiments of the present disclosure.

[0025] Fig.14 is a flowchart describing a method of operating a storage device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram of a storage system according to some embodiments of the present disclosure. Figure 1 , the storage system 10 includes a host 11 and a storage device 100. In some embodiments, the storage system 10 may represent a computing system configured to process various information (such as a personal computer (PC), a notebook computer, a laptop, a server, a workstation, a tablet PC, a smart phone, a digital camera, and a black box).

[0027] The host 11 may control the overall operation of the storage system 10. For example, the host 11 may store data in the storage device 100, or may read data stored in the storage device 100.

[0028] The storage device 100 includes a storage controller 110 and a nonvolatile memory device 120. The storage controller 110 may store data in the nonvolatile memory device 120 or may read data stored in the nonvolatile memory device 120. The nonvolatile memory device 120 may operate under the control of the storage controller 110. For example, based on a command CMD indicating an operation to be performed and an address ADD indicating a location of data, the storage controller 110 may store data in the nonvolatile memory device 120 or may read data stored in the nonvolatile memory device 120.

[0029] In some embodiments, the nonvolatile memory device 120 may be a NAND flash memory device, but the present disclosure is not limited thereto. For example, the nonvolatile memory device 120 may be one of various memory devices that retain data stored therein even when power is turned off, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), and a ferroelectric random access memory (FRAM).

[0030] The memory controller 110 includes a word line manager 111 and a reclaim manager 112 .

[0031] The word line manager 111 may manage word lines of a memory block of the nonvolatile memory device 120. For example, the word line manager 111 may provide a request indicating a word line selection operation to the nonvolatile memory device 120. Based on the request, the nonvolatile memory device 120 may determine a degraded word line (e.g., a word line for providing distribution information for determining a reclaim condition) among a plurality of word lines in the memory block, and may provide word line information indicating the degraded word line to the memory controller 110. That is, the word line selection operation may include monitoring the word lines of the memory block and determining the degraded word line.

[0032] In some embodiments, the word line selection operation may include monitoring some of all word lines of the memory block. The word lines to be monitored may be designated by the memory controller 110 or may be designated internally by the nonvolatile memory device 120.

[0033] In some embodiments, the wordline manager 111 may periodically provide a request indicating a wordline selection operation to the nonvolatile memory device 120. Alternatively, the wordline manager 111 may provide a request indicating a wordline selection operation to the nonvolatile memory device 120 for each specific operation (eg, an operation of reading user data).

[0034] A degraded word line may refer to a word line connected to a memory cell whose threshold voltage distribution is severely changed. The change in the threshold voltage distribution may cause a change in the bit value programmed in the memory cell, thereby reducing the reliability of the data stored in the memory device 100. That is, the memory cell of the degraded word line may store data with a high probability of reduced reliability. Figure 8 The change of the threshold voltage distribution is described in detail.

[0035] The reclaim manager 112 may provide a request indicating a read operation of a degraded word line to the nonvolatile memory device 120 based on the word line information. The reclaim manager 112 may determine whether a reclaim condition of a memory block including the degraded word line is satisfied based on data read from a memory cell of the degraded word line. The reclaim operation may be performed in units of a memory block, but the present disclosure is not limited thereto. For example, the reclaim operation may be performed in units of sub-blocks smaller than a memory block, or the reclaim operation may be performed in units of a word line.

[0036] The recycling operation may refer to an operation of copying data of a memory block including a degraded word line to any other memory block. The reliability of the data of the memory device 100 may be ensured by copying the data to a new memory block before the threshold voltage distribution is seriously changed. The recycling operation may also be referred to as a "reliability operation".

[0037] For example, the nonvolatile memory device 120 may include a first memory block including a degraded word line and a second memory block that has not yet stored data. The memory controller 110 may determine that a reclaiming condition of the first memory block is satisfied, may read block data of the first memory block (e.g., by using a read voltage whose level is optimized or adjusted), may store the read block data in the second memory block (e.g., after performing an error correction operation on the read block data), and may erase the block data of the first memory block. The above series of operations may be collectively referred to as a "reclaiming operation."

[0038] The reclaim condition may provide a criterion for performing a reclaim operation. In detail, when an error count value (e.g., the number of error bits) of read data of a degraded word line exceeds a threshold error count value (e.g., when an uncorrectable error occurs at the degraded word line), the reclaim manager 112 may determine that the reclaim condition of the memory block including the degraded word line is satisfied (when the reclaim unit is a word line, the reclaim manager 112 may determine that the degraded word line itself satisfies the reclaim condition). Thereafter, the memory controller 110 may perform a reclaim operation by using a read voltage whose level is optimized or adjusted.

[0039] The nonvolatile memory device 120 includes a distribution information generator 121 a and a word line selection circuit 121 b .

[0040] The distribution information generator 121a may perform an on-chip read operation. The on-chip read operation may refer to an operation in which the nonvolatile memory device 120 or the NAND flash memory chip reads data internally without additional communication with the memory controller 110.

[0041] For example, the distribution information generator 121a may receive a request indicating a word line selection operation from the word line manager 111. Based on the received request, the distribution information generator 121a may perform an on-chip read operation for each of the plurality of word lines, and may generate a plurality of word line distribution information corresponding to the plurality of word lines, respectively. The word line distribution information may indicate a threshold voltage distribution of the corresponding word line. The plurality of word line distribution information may be collectively referred to as "distribution information".

[0042] In some implementations, the word line distribution information may indicate the number of memory cells corresponding to a lowest threshold voltage state or a highest threshold voltage state.

[0043] For example, the word line distribution information may include the number of memory cells corresponding to the lowest threshold voltage state among the memory cells of the corresponding word line. In other words, the word line distribution information may include an on-cell count value indicating the number of transistors turned on by the read voltage with the lowest level.

[0044] As another example, the word line distribution information may include the number of memory cells corresponding to the highest threshold voltage state among the memory cells of the corresponding word line. In other words, the word line distribution information may include an off-cell count value indicating the number of transistors turned off by the read voltage having the highest level.

[0045] In the above example, instead of performing a plurality of on-chip read operations by using a plurality of read voltage levels for the purpose of identifying a specific threshold voltage state of a memory cell of a word line, one on-chip read operation may be performed by using one read voltage level for the purpose of identifying only the lowest threshold voltage state or the highest threshold voltage state of the memory cell of the word line, and thus, the speed of the on-chip read operation of the distribution information generator 121a may be increased. That is, the distribution information generator 121a may quickly monitor a degraded word line through the on-chip read operation. Fig. 7A , Figure 7B , Figure 7C and Fig.7D Describe the threshold voltage states in detail.

[0046] In some embodiments, the distribution information generator 121a may use a read voltage level optimized to generate word line distribution information. For example, the read voltage level used in an on-chip read operation for obtaining word line distribution information may be set equal to, less than, or greater than a default read voltage level suitable for an initial state.

[0047] The word line selection circuit 121b may determine the degraded word line based on the distribution information (eg, a plurality of word line distribution information of a plurality of word lines). The word line selection circuit 121b may provide the memory controller 110 with word line information indicating the degraded word line.

[0048] In some embodiments, the word line information may include at least one of an address of the degraded word line and word line distribution information of the degraded word line. The storage controller 110 may perform a read operation of the degraded word line based on the address of the degraded word line as a prerequisite operation for determining the recycling condition. Alternatively, the storage controller 110 may determine whether the recycling condition is met based on the word line distribution information of the degraded word line.

[0049] In some embodiments, the degraded word line may be determined relatively or absolutely. For example, the degraded word line may be a word line with the largest change in threshold voltage distribution among the monitored multiple word lines. In this case, the word line information may indicate a degraded word line. As another example, the degraded word line may be a word line with a change in threshold voltage distribution exceeding a threshold level among the monitored multiple word lines. In this case, the word line information may not only indicate a degraded word line, but the word line information may also indicate multiple word lines or the absence of a degraded word line.

[0050] Figure 2 Some embodiments of the present disclosure are shown in Figure 1 A block diagram of the storage controller. Figure 1 and Figure 2 , the storage controller 110 can communicate with the host 11 and the non-volatile memory device 120.

[0051] The memory controller 110 includes a word line manager 111, a recycle manager 112, a volatile memory device 113, a processor 114, a read only memory (ROM) 115, an error correction code (ECC) engine 116, a host interface circuit 117, and a non-volatile memory interface circuit 118. The word line manager 111 and the recycle manager 112 may correspond to Figure 1 The word line manager 111 and the recycling manager 112 are provided.

[0052] In some embodiments, the storage controller 110 includes a command manager. The command manager includes a word line manager 111 and a recycling manager 112. The command manager may be implemented using a firmware module. For example, the processor 114 may implement the command manager by loading instructions stored in the non-volatile memory device 120 into the volatile memory device 113 and executing the loaded instructions. However, the present disclosure is not limited thereto. For example, the command manager may be implemented using separate hardware, or may be implemented using a combination of hardware and software.

[0053] The volatile memory device 113 may be used as a main memory, a buffer memory, or a cache memory of the memory controller 110. The processor 114 may control the overall operation of the memory controller 110. The ROM 115 may be used as a read-only memory storing information for the operation of the memory controller 110.

[0054] The ECC engine 116 may detect and correct errors of data received from the nonvolatile memory device 120. The ECC engine 116 may have a given level of error correction capability. The ECC engine 116 may perform an error correction operation on read data in units of word lines. For example, when the error level (e.g., the number of flipped bits) of the read data does not exceed the error correction capability of the ECC engine 116, the ECC engine 116 may successfully perform an error correction operation on the read data.

[0055] As another example, when the error level of the read data exceeds the error correction capability of the ECC engine 116, the ECC engine 116 may fail in the error correction operation of the read data. In this case, the ECC engine 116 may determine that an uncorrectable error occurs in the read data. When an uncorrectable error occurs, the memory controller 110 may reduce the error level of the read data by performing the read operation again using an optimized or adjusted read voltage level.

[0056] In some embodiments, the reclaim manager 112 may determine whether the reclaim condition is met based on the result of the error correction operation of the ECC engine 116. For example, the reclaim manager 112 may provide a request indicating a read operation of a degraded word line to the nonvolatile memory device 120 based on the word line information. The ECC engine 116 may receive read data of the degraded word line from the nonvolatile memory device 120. An error count value (e.g., the number of error bits) of the read data may exceed a threshold count value (e.g., the error correction capability of the ECC engine 116). In this case, the ECC engine 116 may fail in the error correction operation. The reclaim manager 112 may detect the failure of the error correction operation of the ECC engine 116, and may determine that the reclaim condition is met.

[0057] The storage controller 110 may communicate with the host 11 through the host interface circuit 117. In some embodiments, the host interface circuit 117 may be implemented based on at least one of various interfaces such as a Serial Advanced Technology Attachment (ATA) (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Serial Attached SCSI (SAS), a Non-Volatile Memory Express (NVMe) interface, and a Universal Flash Storage (UFS) interface.

[0058] The memory controller 110 may communicate with the nonvolatile memory device 120 through the nonvolatile memory interface circuit 118. In some implementations, the nonvolatile memory interface circuit 118 may be implemented based on a NAND interface.

[0059] Figure 3 Some embodiments of the present disclosure are shown in Figure 1 A block diagram of a nonvolatile memory device is shown. Figure 1 and Figure 3 , the nonvolatile memory device 120 may communicate with the memory controller 110. For example, the nonvolatile memory device 120 may receive an address ADD and a command CMD from the memory controller 110. The nonvolatile memory device 120 may transfer data with the memory controller 110.

[0060] The nonvolatile memory device 120 includes a control logic 121 , a voltage generator 122 , a row decoder 123 , a memory cell array 124 , a page buffer unit 125 , a column decoder 126 , and an input / output (I / O) circuit 127 .

[0061] The control logic 121 may receive a command CMD and an address ADD from the memory controller 110. The command CMD may represent a signal indicating an operation to be performed by the nonvolatile memory device 120, such as a read operation, a write operation, an erase operation, a word line selection operation, or a reclaim operation. The address ADD may include a row address ADDR and a column address ADDC. The row address ADDR may be used to identify (or select) a word line. The control logic 121 may control the overall operation of the nonvolatile memory device 120 based on the command CMD and the address ADD.

[0062] The control logic 121 includes a distribution information generator 121 a , a word line selection circuit 121 b , and an electric fuse circuit 121 c .

[0063] The distribution information generator 121a may monitor the plurality of word lines WL1 to WLN of the memory block BLK of the memory cell array 124 through an on-chip read operation. Here, "N" is an integer greater than 1. For example, when a voltage corresponding to the on-chip read operation is applied to the memory cell array 124, the distribution information generator 121a may generate a plurality of word line distribution information corresponding to the plurality of word lines WL1 to WLN, respectively, by using the I / O circuit 127. The plurality of word line distribution information may be collectively referred to as "distribution information DI". The distribution information generator 121a may obtain the distribution information DI from the I / O circuit 127, and may store the distribution information DI in the electric fuse circuit 121c.

[0064] The word line selection circuit 121b may determine a degraded word line among the monitored word lines WL1 to WLN based on the distribution information DI stored in the electric fuse circuit 121c. The word line selection circuit 121b may generate word line information WI indicating the degraded word line. The word line selection circuit 121b may provide the word line information WI to the memory controller 110 in the form of data through the I / O circuit 127.

[0065] Under the control of the control logic 121 , the voltage generator 122 may control a voltage to be applied to the memory cell array 124 through the row decoder 123 .

[0066] The row decoder 123 may receive a row address ADDR from the control logic 121. The row decoder 123 may be connected to the memory cell array 124 through a string selection line SSL, a word line WL, and a ground selection line GSL. The row decoder 123 may decode the row address ADDR, and may control a voltage to be applied to the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoding result and a voltage received from the voltage generator 122.

[0067] The memory cell array 124 includes a plurality of memory blocks BLK. Each of the plurality of memory blocks BLK includes a plurality of word lines WL1 to WLN. Each of the plurality of word lines WL1 to WLN may be connected to a memory cell. The memory cell may store data.

[0068] For example, each of the memory cells may be implemented using various types of memory cells such as a single-level cell (SLC) storing one bit, a multi-level cell (MLC) storing two bits, a triple-level cell (TLC) storing three bits, a quad-level cell (QLC) storing four bits. This will be referred to Fig. 7A , Figure 7B , Figure 7C and Fig.7D Describe in detail.

[0069] The page buffer unit 125 includes a plurality of page buffers PB. The page buffer unit 125 may be connected to the memory cell array 124 through the bit lines BL. The page buffer unit 125 may read data from the memory cell array 124 by sensing the voltage of the bit lines BL under the control of the control logic 121. The column decoder 126 may receive a column address ADDC from the control logic 121. The column decoder 126 may decode the column address ADDC, and may provide the data read by the page buffer unit 125 to the I / O circuit 127 based on the decoding result. The I / O circuit 127 may provide the data received through the data lines DL to the memory controller 110.

[0070] The I / O circuit 127 may transfer data received from the memory controller 110 to the column decoder 126 through the data line DL. The column decoder 126 may receive a column address ADDC from the control logic 121. The column decoder 126 may decode the column address ADDC, and may provide the data received from the I / O circuit 127 to the page buffer unit 125 based on the decoding result. The page buffer unit 125 may store the data provided from the I / O circuit 127 in the memory cell array 124 through the bit line BL.

[0071] Figure 4 1 is a diagram describing the reliability operation of a conventional memory device. The conventional memory device may be provided for a better understanding of the present disclosure and is not intended to limit the scope and spirit of the invention.

[0072] A conventional storage device may include a storage controller and a non-volatile memory device. The storage controller may include a command manager and an ECC engine. The command manager may include a recycling manager. The non-volatile memory device may include control logic, a memory cell array, and an I / O circuit. The memory cell array may include a target memory block BLKx. The target memory block BLKx may include first to fourth word lines WL1 to WL4. Each of the first to fourth word lines WL1 to WL4 may be connected to a plurality of memory cells MC.

[0073] For better understanding of the present disclosure, four word lines WL1 to WL4 are described, but the number of word lines to be monitored in the target memory block BLKx may be greater than or less than four.

[0074] Next, the reliability operation of a conventional memory device will be described.

[0075] The command manager may provide a first request RQ1 indicating a read operation of the first word line WL1 to the control logic. The control logic may control the memory cell array based on the first request RQ1 so that the first read data DT1 of the first word line WL1 is output to the I / O circuit. The I / O circuit may provide the first read data DT1 to the ECC engine. The ECC engine may generate an error count value of the first word line WL1 by performing an error correction operation of the first read data DT1.

[0076] As described above, the command manager may provide the control logic with second requests RQ2 to fourth requests RQ4 corresponding to the second to fourth word lines WL2 to WL4, respectively. The control logic may provide the second to fourth read data DT2 to DT4 to the ECC engine via the I / O circuit by performing a read operation in response to the second to fourth requests RQ2 to RQ4. The ECC engine may generate error count values ​​of the second to fourth word lines WL2 to WL4 by performing an error correction operation of the second to fourth read data DT2 to DT4.

[0077] The recycle manager may obtain error count values ​​of the first to fourth word lines WL1 to WL4 from the ECC engine. The recycle manager may determine whether a recycle condition of the target memory block BLKx is satisfied based on the error count values ​​of the first to fourth word lines WL1 to WL4. When the recycle unit is smaller in size than the memory block, the recycle manager may determine whether a recycle condition of the word line is satisfied.

[0078] For example, when the ECC engine fails in an error correction operation on at least one of the first to fourth word lines WL1 to WL4, or when the error count value of at least one of the first to fourth read data DT1 to DT4 exceeds the error correction capability of the ECC engine, the recycling manager may determine that the recycling conditions of the target memory block BLKx are met.

[0079] As described above, a conventional memory device may perform a read operation for all word lines WL1 to WL4. At least four I / Os (e.g., request and read data) may be required between a memory controller and a nonvolatile memory device. At least four error correction operations may be required in an ECC engine. In this case, reliability operations of the conventional memory device may be delayed, and power consumption of the conventional memory device may increase.

[0080] Figure 5 is a diagram describing the reliability operation of a storage device according to some embodiments of the present disclosure. Figure 5 The storage device 100 is described. The storage device 100 includes a storage controller 110 and a non-volatile memory device 120. The storage device 100 may correspond to Figure 1 The storage device 100. The storage controller 110 may correspond to Figure 1 and Figure 2 The non-volatile memory device 120 may correspond to Figure 1 and Figure 3 The non-volatile memory device 120 is provided.

[0081] The memory controller 110 includes a command manager and an ECC engine 116. The command manager includes a word line manager 111 and a reclaim manager 112. The nonvolatile memory device 120 includes a control logic 121, a memory cell array 124, and an I / O circuit 127. The control logic 121 includes a distribution information generator 121a, a word line selection circuit 121b, and an electric fuse circuit 121c. The memory cell array 124 includes a target memory block BLKx. The target memory block BLKx includes a first word line WL1 to a fourth word line WL4. Each of the first word line WL1 to the fourth word line WL4 can be connected to a plurality of memory cells MC.

[0082] For better understanding of the present disclosure, four word lines WL1 to WL4 are described, but the number of word lines to be monitored in the target memory block BLKx may be greater than or less than four.

[0083] Next, a reliability operation of the memory device 100 according to some embodiments of the present disclosure will be described.

[0084] The word line manager 111 may provide the control logic 121 with a first request RQ1 indicating a word line selection operation of the target memory block BLKx. The control logic 121 may perform an on-chip read operation for the first to fourth word lines WL1 to WL4, respectively, based on the first request RQ1. In detail, when a voltage applied to the on-chip read operation is applied to the memory cell array 124, the distribution information generator 121a may generate distribution information by using the I / O circuit 127. The distribution information may include first to fourth word line distribution information corresponding to the first to fourth word lines WL1 to WL4, respectively. The distribution information generator 121a may obtain the distribution information from the I / O circuit 127, and may store the distribution information in the electric fuse circuit 121c.

[0085] The word line selection circuit 121b may determine the degraded word line WLx among the first to fourth word lines WL1 to WL4 based on the distribution information stored in the electric fuse circuit 121c. For example, the most severely degraded word line among the first to fourth word lines WL1 to WL4 of the target memory block BLKx may be the third word line WL3. The word line selection circuit 121b may determine the third word line WL3 as the degraded word line WLx based on the distribution information stored in the electric fuse circuit 121c. The word line selection circuit 121b may output word line information WI indicating that the third word line WL3 is the degraded word line WLx to the I / O circuit 127. The I / O circuit 127 may provide the word line information WI to the command manager.

[0086] The recycling manager 112 may provide the control logic 121 with a second request RQ2 indicating a read operation of the degraded word line WLx based on the word line information WI. The control logic 121 may control the memory cell array 124 based on the second request RQ2, and may output the read data DT of the third word line WL3, which is the degraded word line WLx, to the I / O circuit 127. The I / O circuit 127 may provide the read data DT to the ECC engine 116. The ECC engine 116 may generate an error count value of the third word line WL3 by performing an error correction operation of the read data DT.

[0087] The reclaim manager 112 may obtain an error count value of the third word line WL3 as the degraded word line WLx from the ECC engine 116. Based on the obtained error count value, the reclaim manager 112 may determine whether a reclaim condition of the degraded word line WLx itself or a reclaim condition of the target memory block BLKx including the degraded word line WLx is satisfied.

[0088] For example, when the ECC engine 116 fails in an error correction operation associated with a degraded word line WLx, or when the error count value of the read data DT of the degraded word line WLx exceeds the error correction capability of the ECC engine 116, the reclaim manager 112 may determine whether a reclaim condition of the degraded word line WLx itself or a reclaim condition of the target memory block BLKx including the degraded word line WLx is satisfied.

[0089] As described above, the memory device 100 can determine the degraded word line WLx among the first to fourth word lines WL1 to WL4 through an on-chip read operation. The I / O and error correction operations associated with the remaining word lines WL1, WL2, and WL4 other than the degraded word line WLx can be omitted. That is, the memory device 100 can quickly monitor the degraded word line WLx through an on-chip read operation. The delay of the reliability operation can be suppressed, and the power consumption of the memory device 100 can be reduced. Figure 6 Describe in detail the timing advantages of on-chip operations.

[0090] Figure 6 Describes some embodiments of the present disclosure Figure 5 The operating state of the storage device will be referred to in FIG. Figure 6 The storage device 100 (see Figure 5 ) changes over time. Figure 6 , the horizontal axis represents time, and the vertical axis represents the operating state of the storage device.

[0091] The operation status marked by dark shading may represent an on-chip cell monitoring (OCM) operation. OCM operation may be Figure 5 The operation state marked by light shading may represent a reclaim decision (RCD) operation. The RCD operation may represent an operation of determining whether reclaim is required based on the threshold voltage distribution of the word line selected by the OCM operation. The unshaded operation state may mean a "don't care" state. For example, the unshaded operation state may indicate that the memory device 100 is in an idle state, or may indicate that the memory device 100 performs any other operation.

[0092] In some embodiments, the memory device 100 may operate according to a first situation (Situation 1). The first situation may indicate a situation in which the memory device 100 performs an RCD operation whenever an OCM operation is performed. For example, at a first time point Tp1, the memory device 100 may perform a first OCM operation OCM1 on a first word line group, and may select a first degraded word line among the word lines of the first word line group. At a second time point Tp2, the memory device 100 may perform a first RCD operation RCD1 based on a read operation of the first degraded word line. The first RCD operation RCD1 may be performed to determine whether the recovery of a memory block including the first degraded word line is required.

[0093] As described above, at the third time point Tp3, the memory device 100 may perform a second OCM operation OCM2 on the second word line group, and may select a second degraded word line among the word lines of the second word line group. At the fourth time point Tp4, the memory device 100 may perform a second RCD operation RCD2 based on a read operation of the second degraded word line. The second RCD operation RCD2 may be performed to determine whether recycling of the memory block including the second degraded word line is required. In some embodiments, the second RCD operation RCD2 in case 1 may end at a fifth time point Tp5. In this case, the first word line group and the second word line group may be included in the same memory block, or may be included in different memory blocks, respectively.

[0094] In some embodiments, the memory device 100 may operate according to a second situation (Situation 2). The second situation may indicate a situation in which the memory device 100 performs an RCD operation after performing a plurality of OCM operations. For example, at a first time point Tp1, the memory device 100 may perform a first OCM operation OCM1 on a first word line group. At a second time point Tp2, the memory device 100 may perform a second OCM operation OCM2 on a second word line group. In this case, the first word line group and the second word line group may be included in the same memory block. The memory device 100 may determine a degraded word line among the word lines of the first word line group and the second word line group based on the first OCM operation OCM1 and the second OCM operation OCM2. The degraded word line may be the most severely degraded word line among the word lines of the first word line group and the second word line group. At a third time point Tp3, the memory device 100 may perform a first RCD operation RCD1 based on a read operation of the degraded word line.

[0095] For better understanding of the present disclosure, a second case including a first OCM operation OCM1 and a second OCM operation OCM2 is shown, but the number of OCM operations corresponding to one RCD operation may be greater than two.

[0096] In some embodiments, the memory device 100 may operate according to a third case (case 3). The third case may indicate a case where the memory device 100 selectively performs an RCD operation after performing a plurality of OCM operations. For example, at a first time point Tp1, the memory device 100 may perform a first OCM operation OCM1 on a first word line group. Based on the absolute degradation condition, the memory device 100 may determine at least one first degraded word line in the first word line group, or may determine that there is no degraded word line in the first word line group.

[0097] As described above, at the second time point Tp2, the memory device 100 may perform the second OCM operation OCM2 on the second word line group. Based on the absolute degradation condition, the memory device 100 may determine at least one second degraded word line in the second word line group, or may determine that there is no degraded word line in the second word line group. In this case, the first word line group and the second word line group may be included in the same memory block.

[0098] Thereafter, at a third time point Tp3, the memory device 100 may perform a first RCD operation RCD1 based on a read operation of at least one first degraded word line and one of at least one second degraded word line. When no degraded word line exists in the first word line group and the second word line group, the first RCD operation RCD1 may be omitted.

[0099] For better understanding of the present disclosure, a third case including a first OCM operation OCM1 and a second OCM operation OCM2 is shown, but the number of OCM operations corresponding to one RCD operation may be greater than two.

[0100] In some embodiments, the memory device 100 may operate according to a fourth case (Case 4). The fourth case may indicate a case where the memory device 100 performs a reclaim decision operation as an on-chip operation after performing a plurality of OCM operations.

[0101] For example, at a first time point Tp1, the memory device 100 may perform a first OCM operation OCM1 on a first word line group. At a second time point Tp2, the memory device 100 may perform a second OCM operation OCM2 on a second word line group. The memory device 100 may obtain distribution information of degraded word lines (e.g., a result of monitoring or information obtained by an additional read operation of the degraded word lines) based on the first OCM operation OCM1 and the second OCM operation OCM2. After a third time point Tp3, the memory device 100 may perform an on-chip recycling decision operation based on the distribution information of the degraded word lines. Because the on-chip recycling decision operation does not cause an I / O load between the storage controller and the non-volatile memory device, the on-chip recycling decision operation may be marked as a "don't care" operation state.

[0102] Fig. 7Ais a diagram illustrating threshold voltage distribution of a single-level cell according to some embodiments of the present disclosure. Fig. 7A Graphs showing threshold voltage distributions of single level cells SLC each storing one bit and a bit table corresponding to the threshold voltage distributions are shown in FIG.

[0103] In the graph of the single-level cell SLC, the horizontal axis represents the threshold voltage level, and the vertical axis represents the number of memory cells. The single-level cell SLC may have one of an erased state "E" and a programmed state "P". The voltage level of the programmed state "P" may be higher than the voltage level of the erased state "E". The read voltage level VR may be used to distinguish the erased state "E" from the programmed state "P".

[0104] The single-level cell SLC table shows the bit value of each cell state. For example, the bit value corresponding to the erased state "E" may be "0". The bit value corresponding to the programmed state "P" may be "1".

[0105] Figure 7B is a diagram illustrating threshold voltage distribution of a multi-level cell according to some embodiments of the present disclosure. Figure 7B 2 shows a graph of threshold voltage distribution of multi-level cells MLC each storing two bits and a bit table corresponding to the threshold voltage distribution.

[0106] In the graph of the multi-level cell MLC, the horizontal axis represents the threshold voltage level and the vertical axis represents the number of memory cells. The multi-level cell MLC may have an erase state 'E' and one of first to third program states P1 to P3 whose threshold voltage distribution sequentially increases.

[0107] In the multi-level cell MLC, the first read voltage level VR1 can be used to distinguish the erased state "E" from the first programmed state P1. As described above, each of the second read voltage level VR2 and the third read voltage level VR3 can be used to distinguish each of the second programmed state P2 and the third programmed state P3 from a previous state (i.e., an immediately previous state having a low threshold voltage distribution).

[0108] The table of the multi-level cell MLC shows the least significant bit LSB and the most significant bit MSB of each cell state. The least significant bit LSB may correspond to a first logical page of the multi-level cell MLC. The most significant bit MSB may correspond to a second logical page of the multi-level cell MLC.

[0109] In some embodiments, the first to third read voltage levels VR1 to VR3 of the multi-level cell MLC may be used to perform a read operation on one of the first logical page and the second logical page. For example, in the multi-level cell MLC, a read operation of the first logical page may be performed based on the second read voltage level VR2. A read operation of the second logical page may be performed based on the first read voltage level VR1 and the third read voltage level VR3.

[0110] Figure 7C is a diagram illustrating threshold voltage distribution of a three-level cell according to some embodiments of the present disclosure. Figure 7C Graphs showing threshold voltage distributions of triple-level cells TLC each storing three bits and a bit table corresponding to the threshold voltage distributions are shown in FIG.

[0111] In the graph of the three-level cell TLC, the horizontal axis represents the threshold voltage level and the vertical axis represents the number of memory cells. The three-level cell TLC may have an erase state "E" and one of first to seventh program states P1 to P7 whose threshold voltage distribution sequentially increases.

[0112] In the three-level cell TLC, the first read voltage level VR1 can be used to distinguish the erase state "E" from the first program state P1. As in the above description, each of the second to seventh read voltage levels VR2 to VR7 can be used to distinguish each of the second to seventh program states P2 to P7 from a previous state (i.e., an immediately previous state having a low threshold voltage distribution).

[0113] The table of the three-level cell TLC shows the least significant bit LSB, the center significant bit CSB and the most significant bit MSB of each cell state. The least significant bit LSB may correspond to the first logical page of the three-level cell TLC. The center significant bit CSB may correspond to the second logical page of the three-level cell TLC. The most significant bit MSB may correspond to the third logical page of the three-level cell TLC.

[0114] In some embodiments, the first read voltage level VR1 to the seventh read voltage level VR7 of the three-level cell TLC can be used to perform a read operation on one of the first to third logical pages. For example, in the three-level cell TLC, a read operation of the first logical page can be performed based on the first read voltage level VR1 and the fifth read voltage level VR5. A read operation of the second logical page can be performed based on the second read voltage level VR2, the fourth read voltage level VR4, and the sixth read voltage level VR6. A read operation of the third logical page can be performed based on the third read voltage level VR3 and the seventh read voltage level VR7.

[0115] Fig.7Dis a diagram illustrating threshold voltage distribution of a quad-level cell according to some embodiments of the present disclosure. Fig.7D Graphs showing threshold voltage distributions of quad-level cells QLC each storing four bits and a bit table corresponding to the threshold voltage distributions are shown in FIG.

[0116] In the graph of the quad level cell QLC, the horizontal axis represents the threshold voltage level and the vertical axis represents the number of memory cells. The quad level cell QLC may have an erase state "E" and one of first to fifteenth program states P1 to P15 whose threshold voltage distribution sequentially increases.

[0117] In the quad-level cell QLC, the first read voltage level VR1 may be used to distinguish the erased state "E" from the first programmed state P1. As described above, each of the second to fifteenth read voltage levels VR2 to VR15 may be used to distinguish each of the second to fifteenth programmed states P2 to P15 from a previous state (i.e., an immediately previous state having a low threshold voltage distribution).

[0118] The table of the quad-level cell QLC shows the least significant bit LSB, the first center significant bit ESB, the second center significant bit USB, and the most significant bit MSB of each cell state. The least significant bit LSB may correspond to the first logical page of the quad-level cell QLC. The first center significant bit ESB may correspond to the second logical page of the quad-level cell QLC. The second center significant bit USB may correspond to the third logical page of the quad-level cell QLC. The most significant bit MSB may correspond to the fourth logical page of the quad-level cell QLC.

[0119] In some embodiments, the first read voltage level VR1 to the fifteenth read voltage level VR15 of the quad-level cell QLC may be used to perform a read operation on one of the first to fourth logical pages. For example, in the quad-level cell QLC, a read operation of the first logical page may be performed based on the first read voltage level VR1, the fourth read voltage level VR4, the sixth read voltage level VR6, and the eleventh read voltage level VR11. A read operation of the second logical page may be performed based on the third read voltage level VR3, the seventh read voltage level VR7, the ninth read voltage level VR9, and the thirteenth read voltage level VR13. A read operation of the third logical page may be performed based on the second read voltage level VR2, the eighth read voltage level VR8, and the fourteenth read voltage level VR14. A read operation of the fourth logical page may be performed based on the fifth read voltage level VR5, the tenth read voltage level VR10, the twelfth read voltage level VR12, and the fifteenth read voltage level VR15.

[0120] As mentioned above, refer to 7A to 7DThe cell states and read voltage levels of a single-level cell SLC, a multi-level cell MLC, a three-level cell TLC, and a four-level cell QLC are described. In the case of a single-level cell SLC, a threshold voltage state can be identified by one read voltage level, and therefore, a read operation can be performed quickly. In the case of the remaining cells MLC, TLC, and QLC, because some threshold voltage states are identified by multiple read voltage levels, a read operation can be performed slowly; however, because each memory cell stores two or more bits, the storage capacity can be increased.

[0121] Figure 8 is a diagram describing changes in threshold voltage distribution according to some embodiments of the present disclosure. Figure 8 Describes the threshold voltage distribution of the initial state and the threshold voltage distribution of the retention state. The initial state may represent the state at a point in time (i.e., an initial point in time) when the memory cell is programmed to form the threshold voltage distribution. The retention state may represent the state at a point in time when time has passed from the initial state or the state at a point in time when a recovery operation is required.

[0122] In the graph of the initial state, the horizontal axis represents the threshold voltage level, and the vertical axis represents the number of memory cells. The threshold voltage level of each memory cell may correspond to one of the erased state "E" and the first to seventh programming states P1 to P7. The first initial read voltage level VR1i may be a valley voltage level optimized to distinguish the memory cell of the erased state "E" from the memory cell of the first programming state P1.

[0123] The optimized valley value may indicate a voltage level at which the number of memory cells each having an error bit (i.e., the number of memory cells each determined to have a bit value opposite to the programmed bit value) is minimized. For example, in the case of distinguishing an erased state "E" from a first programmed state P1 in an initial state, the voltage level of the optimized valley value may indicate a voltage level at which the number of memory cells each having an erased state "E" is minimized between a voltage level at which the number of memory cells each having the first programmed state P1 is maximized and a voltage level at which the number of memory cells each having the first programmed state P1 is maximized.

[0124] As described above, in the initial state, each of the second initial read voltage level VR2i to the seventh initial read voltage level VR7i may indicate a valley voltage level optimized to distinguish each of the second programming state P2 to the seventh programming state P7 from the previous state (i.e., the immediately previous state having a low threshold voltage distribution).

[0125] In the graph of the retention state, the horizontal axis represents the threshold voltage level, and the vertical axis represents the number of memory cells. The threshold voltage level of each memory cell may correspond to one of the erased state "E" and the first to seventh programming states P1 to P7. The first retention read voltage level VR1r may be a valley voltage level optimized to distinguish the memory cell of the erased state "E" from the memory cell of the first programming state P1.

[0126] As described above, in the retention state, each of the second retention read voltage level VR2r to the seventh retention read voltage level VR7r may indicate a valley voltage level optimized to distinguish each of the second programming state P2 to the seventh programming state P7 from the previous state (i.e., the immediately previous state having a low threshold voltage distribution).

[0127] Referring to the graph of the initial state and the graph of the retention state together, each of the first to seventh initial read voltage levels VR1i to VR7i may be different from each of the first to seventh retention read voltage levels VR1r to VR7r.

[0128] In some embodiments, the highest threshold voltage state and the lowest threshold voltage state may be susceptible to degradation over time.The highest threshold voltage state and the lowest threshold voltage state may be used as key factors for recycling conditions.

[0129] For example, as the threshold voltage level becomes higher, the decrement of the voltage level in the retention state may become larger. In detail, the difference between the seventh retention read voltage level VR7r and the seventh initial read voltage level VR7i may be greater than the difference between the third retention read voltage level VR3r and the third initial read voltage level VR3i. In detail, in the case of the highest programming state (i.e., P7 of the three-level cell TLC), because the threshold voltage level shifts left due to charge loss, the highest programming state may shift downward to be greater than any other programming state over time.

[0130] As another example, the voltage level corresponding to the low threshold voltage state may increase over time. In detail, in order to increase the time during which the reliability of the erased state and the programmed state of the memory cell is guaranteed, the memory cell may be programmed to have a threshold voltage level higher than the threshold voltage level of the erased state in the semiconductor process step. In the actual use step, the memory cell programmed to the erased state may have the property of returning to the threshold voltage level programmed at the semiconductor process step over time. In this way, the first retention read voltage level VR1r may be higher than the first initial read voltage level VR1i. Optionally, because the threshold voltage level of the erased state "E" is right-shifted due to the read disturbance caused by multiple read operations, the lowest state (i.e., the erased state) may shift upward to be greater than any other programmed state over time.

[0131] As described above, the change of the threshold voltage distribution in the retention state may mainly occur in the lowest threshold voltage state and the highest threshold voltage state. Whether a recovery operation is required can be effectively determined by monitoring the degradation of the lowest threshold voltage state or the highest threshold voltage state instead of monitoring all threshold voltage states.

[0132] For example, when the number of memory cells determined to be in the erased state "E" (i.e., the on-cell count value) is less than a first threshold, or when the number of memory cells determined to be in the seventh programming state P7 (i.e., the off-cell count value) is less than a second threshold, a recovery operation may be required. In order to better understand the present disclosure, the three-level cell TLC is described as an example, but the present disclosure is not limited thereto. In the case of the four-level cell QLC, when the number of memory cells determined to be in the erased state "E" (i.e., the on-cell count value) is less than a first threshold, or when the number of memory cells determined to be in the fifteenth programming state P15 (i.e., the off-cell count value) is less than a second threshold, a recovery operation may be required.

[0133] Fig. 9 is a flowchart describing a method of operating a storage device according to some embodiments of the present disclosure. Fig. 9 , the memory device 100 includes a memory controller 110 and a non-volatile memory device 120. The memory controller 110 includes a command manager. The command manager includes a word line manager 111 and a recycling manager 112. The non-volatile memory device 120 includes a control logic 121, a memory cell array 124, and an I / O circuit 127. The control logic 121 includes a distribution information generator 121a, a word line selection circuit 121b, and an electric fuse circuit 121c. The memory cell array 124 includes a plurality of memory blocks BLK1 to BLKM. Here, "M" is an integer greater than 1.

[0134] Next, a word line selection operation of the memory device 100 will be described.

[0135] In the first operation ①, the word line manager 111 may provide a first request RQ1 indicating a word line selection operation of a target memory block BLKx among the plurality of memory blocks BLK1 to BLKM to the control logic 121. The first request RQ1 may include addresses of the first to N-th word lines WL1 to WLN of the target memory block BLKx, or may include addresses of word lines selected from the first to N-th word lines WL1 to WLN.

[0136] In the second operation ②, based on the first request RQ1, the control logic 121 may perform an on-chip read operation in units of word lines, and may obtain distribution information DI of the target memory block BLKx. For example, when a voltage corresponding to the on-chip read operation is applied to the memory cell array 124, the distribution information generator 121a may generate first word line distribution information to Nth word line distribution information corresponding to the first word line WL1 to the Nth word line WLN, respectively, by using the I / O circuit 127. The first word line distribution information to the Nth word line distribution information may be collectively referred to as “distribution information DI”. The distribution information generator 121a may obtain the distribution information DI from the I / O circuit 127. The distribution information generator 121a may store the distribution information DI in the electric fuse circuit 121c.

[0137] In some embodiments, the distribution information generator 121a may perform an on-chip read operation in a single-level cell (SLC) manner. For example, the memory cells connected to the first word line WL1 to the Nth word line WLN may be implemented using a three-level cell TLC. Instead of performing an on-chip read operation in units of logical pages by using a plurality of read voltage levels, the distribution information generator 121a may read a memory cell corresponding to a lowest threshold voltage state (e.g., an erase state "E") by using only a first read voltage level VR1, or may read a memory cell corresponding to a highest threshold voltage state (e.g., a seventh program state P7) by using only a seventh read voltage level VR7.

[0138] In some embodiments, each of the multiple word line distribution information included in the distribution information DI may include at least one of a turn-on cell count value of the corresponding word line, a turn-off cell count value of the corresponding word line, valley search information of the corresponding word line, and a cell count value between two adjacent read voltages.

[0139] In detail, the on-cell count value may indicate the number of memory cells determined to have the lowest threshold voltage state among the memory cells connected to the corresponding word line. As the on-cell count value becomes smaller, the degree of degradation of the corresponding word line may become more serious.

[0140] The off-cell count value may indicate the number of memory cells determined to have the highest threshold voltage state among the memory cells connected to the corresponding word line. As the off-cell count value becomes smaller, the degree of degradation of the corresponding word line may become more serious.

[0141] For the corresponding word line, the valley search information may indicate the difference between the voltage level of the valley in the initial state and the voltage level of the optimized valley when the on-chip read operation is performed. As the difference corresponding to the valley search information becomes larger, the degradation degree of the corresponding word line may become more serious.

[0142] The cell count value between two adjacent read voltages may indicate the number of memory cells corresponding to a particular threshold voltage state. The two adjacent read voltages may be two predetermined read voltages.

[0143] The cell count values ​​of two adjacent read voltages may indicate the number of memory cells each having a threshold voltage state between two adjacent read voltage levels associated with a single-level cell SLC, a multi-level cell MLC, a three-level cell TLC, or a four-level cell QLC. For example, when a specific threshold voltage state is a first programming state P1, the cell count value may indicate the number of memory cells each having a threshold voltage level between a first read voltage level VR1 and a second read voltage level VR2. The degree of degradation of the corresponding word line may be determined according to a decrement or increment of the cell count value. The manner of determining the degree of degradation may be determined differently according to the type of memory cell (e.g., TLC or QLC), the kind of threshold voltage state, device characteristics, etc.

[0144] In detail, the degraded word line WLx may be a word line having the smallest cell count value between two adjacent read voltages among the first to Nth word lines WL1 to WLN. Alternatively, the degraded word line WLx may be a word line having the largest cell count value between two adjacent read voltages among the first to Nth word lines WL1 to WLN.

[0145] As another example, the degraded word line WLx may be a word line whose cell count values ​​of two adjacent read voltages among the first to N-th word lines WL1 to WLN are greater than the third threshold value (which may mean that there are multiple degraded word lines). Alternatively, the degraded word line WLx may be a word line whose cell count values ​​of two adjacent read voltages among the first to N-th word lines WL1 to WLN are less than the fourth threshold value (which may mean that there are multiple degraded word lines).

[0146] In the third operation ③, the word line selection circuit 121b may determine the degraded word line WLx among the first to Nth word lines WL1 to WLN based on the distribution information DI. The degraded word line WLx may be determined relatively or absolutely. The word line selection circuit 121b may generate word line information WI indicating the degraded word line WLx.

[0147] In some embodiments, the word line information WI may include at least one of an address of the degraded word line WLx and word line distribution information of the degraded word line WLx.

[0148] In some embodiments, the word line selection circuit 121b may determine the word line with the smallest number of memory cells in the lowest threshold voltage state among the word lines WL1 to WLN as the degraded word line WLx. For example, the lowest threshold voltage state may be the erased state "E" of the three-level cell TLC or the erased state "E" of the quad-level cell QLC. The distribution information DI may include a turn-on cell count value for each of the word lines WL1 to WLN. The turn-on cell count value may indicate the number of memory cells turned on in the lowest threshold voltage state. The word line selection circuit 121b may determine the word line with the smallest turn-on cell count value among the word lines WL1 to WLN as the degraded word line WLx based on the distribution information DI.

[0149] In some embodiments, the word line selection circuit 121b may determine a word line whose on-cell count value is smaller than a first threshold value from among the word lines WL1 to WLN as a degraded word line WLx. The first threshold value may provide a criterion for a decision of a degraded word line WLx based on the on-cell count value. When the number of word lines having an on-cell count value smaller than the first threshold value is 2 or more, the word line information WI may indicate a plurality of degraded word lines. When there is no word line having an on-cell count value smaller than the first threshold value, the word line information WI may indicate that there is no degraded word line.

[0150] In some embodiments, the word line selection circuit 121b may determine the word line with the smallest number of memory cells in the highest threshold voltage state from among the word lines WL1 to WLN as the degraded word line WLx. For example, the highest threshold voltage state may be the seventh programming state P7 of the three-level cell TLC or the fifteenth programming state P15 of the four-level cell QLC. The distribution information DI may include a cut-off cell count value for each of the word lines WL1 to WLN. The cut-off cell count value may indicate the number of memory cells cut off in the highest threshold voltage state. The word line selection circuit 121b may determine the word line with the smallest cut-off cell count value among the word lines WL1 to WLN as the degraded word line WLx based on the distribution information DI.

[0151] In some embodiments, the word line selection circuit 121b may determine a word line whose off-cell count value is smaller than a second threshold value from among the word lines WL1 to WLN as a degraded word line WLx. The second threshold value may provide a criterion for a decision of a degraded word line WLx based on the off-cell count value. When the number of word lines having an off-cell count value smaller than the second threshold value is 2 or more, the word line information WI may indicate a plurality of degraded word lines. When there is no word line having an off-cell count value smaller than the second threshold value, the word line information WI may indicate that there is no degraded word line.

[0152] In the fourth operation ④, the word line selection circuit 121b may provide the word line information WI to the command manager through the I / O circuit 127. Thereafter, the command manager may perform a read operation based on the word line information WI. This will refer to Fig.11 Described in detail.

[0153] Fig.10 The operation of some embodiments of the present disclosure is described Fig. 9 A method for performing a non-volatile memory device is shown in FIG. Fig.10 , the nonvolatile memory device 120 includes a control logic 121, a memory cell array 124, and an I / O circuit 127. The control logic 121 includes a distribution information generator 121a, a word line selection circuit 121b, and an electric fuse circuit 121c. The memory cell array 124 includes a target memory block BLKx. The target memory block BLKx includes a first word line WL1 to an Nth word line WLN.

[0154] The control logic 121 may receive a first request RQ1 indicating a word line selection operation of a target memory block BLKx. The word lines to be monitored for the word line selection operation may be specified by the first request RQ1 or may be specified internally by the nonvolatile memory device 120. The word lines to be monitored may be some of all word lines of the target memory block BLKx. For example, the target memory block BLKx includes a first word line WL1 to an N-th word line WLN. Some word lines WLO, WLP, WLQ, and WLR among the first word line WL1 to the N-th word line WLN may be susceptible to degradation. The nonvolatile memory device 120 may not monitor all word lines WL1 to WLN of the target memory block BLKx, but may monitor some word lines WLO, WLP, WLQ, and WLR of the target memory block BLKx, and may determine a degraded word line WLx.

[0155] For better understanding of the present disclosure, an example in which four word lines WLO, WLP, WLQ, and WLR are monitored is described, but the number of word lines to be monitored for the word line selection operation may be greater than or less than four.

[0156] The distribution information generator 121a may perform an on-chip read operation of the word lines WLO, WLP, WLQ, and WLR based on the first request RQ1. The on-chip read operation may be performed in a single-level cell (SLC) manner to identify a lowest threshold voltage state.

[0157] For example, the distribution information generator 121a may perform the first on-chip read operation to the fourth on-chip read operation based on the first request RQ1. In the first on-chip read operation, the distribution information generator 121a may determine the memory cells of the word line WLO having the erase state "E" by using the first read voltage level VR1, and may determine the on-cell count value of the word line WLO as the first count value CV1. The on-cell count value of the word line WLO may be referred to as "word line distribution information of the word line WLO". The distribution information generator 121a may store the word line distribution information of the word line WLO in the electrical fuse circuit 121c as part of the distribution information DI.

[0158] As described above, in the second on-chip read operation, the distribution information generator 121a may determine the memory cells of the word line WLP having the erase state “E” by using the first read voltage level VR1, and may determine the on-cell count value of the word line WLP as the second count value CV2. In the third on-chip read operation, the distribution information generator 121a may determine the memory cells of the word line WLQ having the erase state “E” by using the first read voltage level VR1, and may determine the on-cell count value of the word line WLQ as the third count value CV3. In the fourth on-chip read operation, the distribution information generator 121a may determine the memory cells of the word line WLR having the erase state “E” by using the first read voltage level VR1, and may determine the on-cell count value of the word line WLR as the fourth count value CV4. Similarly, the distribution information generator 121a may store the word line distribution information of the word lines WLP, WLQ, and WLR in the electrical fuse circuit 121c as part of the distribution information DI.

[0159] The word line selection circuit 121b may determine the degraded word line WLx based on the distribution information DI stored in the electric fuse circuit 121c. For example, the distribution information DI includes first to fourth count values ​​CV1, CV2, CV3, and CV4 corresponding to the on-cell count values ​​of the word lines WLO, WLP, WLQ, and WLR, respectively. The smallest count value among the first to fourth count values ​​CV1, CV2, CV3, and CV4 may be the fourth count value CV4. The word line selection circuit 121b may determine the word line WLR having the fourth count value CV4 as the degraded word line WLx. The word line selection circuit 121b may generate word line information WI indicating that the word line WLR is the degraded word line WLx. The word line selection circuit 121b may output the word line information WI through the I / O circuit 127.

[0160] In order to better understand the present disclosure, a method for relatively determining a degraded word line by using a conduction cell count value is described. However, the present disclosure is not limited thereto. For example, a degraded word line may be absolutely determined by comparing a conduction cell count value and a first threshold value, or a degraded word line may be absolutely determined by comparing a cutoff cell count value and a second threshold value. Alternatively, a degraded word line may be determined based on valley search information (e.g., the difference between the voltage level of the valley value in the initial state and the voltage level of the optimized valley value). A degraded word line may be relatively or absolutely determined based on a cell count value between two adjacent read voltages.

[0161] Fig.11 is a diagram describing a method of operating a storage device according to some embodiments of the present disclosure. Fig.11 , the memory device 100 includes a memory controller 110 and a non-volatile memory device 120. The memory controller 110 includes a command manager and an ECC engine 116. The command manager includes a word line manager 111 and a recycling manager 112. The non-volatile memory device 120 includes a control logic 121, a memory cell array 124, and an I / O circuit 127. The memory cell array 124 includes a plurality of memory blocks BLK1 to BLKM. Each of the plurality of memory blocks BLK1 to BLKM includes a plurality of word lines WL1 to WLN.

[0162] Next, it will be described how the memory device 100 performs a read operation on the degraded word line WLx. The read operation on the degraded word line WLx may be performed in Fig. 9 The word line selection operation is performed afterwards.

[0163] In the first operation ①, the reclaim manager 112 may provide a second request RQ2 indicating a read operation of the degraded word line WLx to the control logic 121. The second request RQ2 may include an address of the degraded word line WLx.

[0164] In the second operation ②, based on the second request RQ2, the control logic 121 may perform a read operation of the degraded word line WLx, and may generate read data DT of the degraded word line WLx as a result of the read operation by using the I / O circuit 127. In this case, the read operation may be a read operation based on a logical page. For example, unlike in Fig.10 In the manner of determining memory cells having the erase state “E” by using only the first read voltage level VR1 (ie, only one read voltage level), the control logic 121 may perform a read operation of the degraded word line WLx by using a plurality of read voltage levels in units of logical pages.

[0165] In the third operation ③, the I / O circuit 127 may provide the read data DT of the degraded word line WLx to the ECC engine 116. The ECC engine 116 may perform an error correction operation on the read data DT to generate an error count value of the degraded word line WLx. The error count value may indicate the number of flipped bits in the read data DT of the degraded word line WLx, or may indicate that the read data DT of the degraded word line WLx has an uncorrectable error.

[0166] In the fourth operation (4), the recycling manager 112 may obtain the error count value of the read data DT from the ECC engine 116. The recycling manager 112 may determine whether the recycling condition of the target memory block BLKx is met based on the error count value. For example, when the error count value of the read data DT exceeds the threshold error count value, the recycling manager 112 may determine that the recycling condition of the target memory block BLKx is met. The threshold error count value may provide a criterion for recycling execution. The threshold error count value may correspond to the error correction capability of the ECC engine 116.

[0167] Fig.12 is a flowchart describing a method of operating a storage device according to some embodiments of the present disclosure. Fig.12 , the storage device 100 includes a storage controller 110 and a non-volatile memory device 120 .

[0168] In operation S110 , the memory controller 110 may provide a first request RQ1 indicating a word line selection operation of a target memory block BLKx to the nonvolatile memory device 120 .

[0169] In operation S120, the nonvolatile memory device 120 may obtain distribution information DI of the target memory block BLKx based on the first request RQ1. The distribution information DI may include word line distribution information corresponding to each of a plurality of word lines of the target memory block BLKx.

[0170] In operation S130, the nonvolatile memory device 120 may determine a degraded word line WLx based on the distribution information DI. In some embodiments, based on the distribution information DI, the nonvolatile memory device 120 may determine a plurality of degraded word lines or may determine that no degraded word line exists in the target memory block BLKx.

[0171] In operation S140, the nonvolatile memory device 120 may provide word line information WI indicating the degraded word line WLx to the memory controller 110. The word line information WI may include at least one of an address of the degraded word line WLx and word line distribution information of the degraded word line WLx. When it is determined in operation S130 that there is no degraded word line, the word line information WI may indicate that there is no degraded word line.

[0172] In operation S150 , the memory controller 110 may provide the nonvolatile memory device 120 with a second request RQ2 indicating a read operation of the degraded word line WLx based on the word line information WI.

[0173] In operation S160 , based on the second request RQ2 , the nonvolatile memory device 120 may perform a read operation of the degraded word line WLx, and may provide read data DT of the degraded word line WLx to the memory controller 110 .

[0174] In operation S170, based on the read data DT of the degraded word line WLx, the memory controller 110 may determine whether a reclaim condition of the target memory block BLKx including the degraded word line WLx is satisfied. When it is determined that the reclaim condition is not satisfied, the memory controller 110 may perform operation S110 again. When it is determined that the reclaim condition is satisfied, the memory controller 110 may perform operation S180.

[0175] In operation S180 , the memory controller 110 may provide a third request RQ3 indicating a reclaim operation of a target memory block BLKx to the nonvolatile memory device 120 (eg, the control logic 121 ).

[0176] In operation S181, the memory device 100 may perform a reclaiming operation of the target memory block BLKx. In detail, the nonvolatile memory device 120 may provide the block data of the target memory block BLKx to the memory controller 110 based on the third request RQ3. The memory controller 110 may store the provided block data in any other memory block of the nonvolatile memory device 120. The memory controller 110 may erase the block data of the target memory block BLKx of the nonvolatile memory device 120.

[0177] As described above, according to some embodiments of the present disclosure, since degraded word lines are quickly monitored through an on-chip read operation and distribution information of the degraded word lines is accurately analyzed by a memory controller, a memory device may quickly and accurately perform reliability operations.

[0178] Fig.13 is a flowchart describing a method of operating a nonvolatile memory device according to some embodiments of the present disclosure. Fig.13 A method of operating a nonvolatile memory device is described. Operation S210 may correspond to Fig.12 Operation S220, operation S221, operation S222, operation S223, and operation S224 may correspond to Fig.12 Operation S120. Operation S230 may correspond to Fig.12 Operation S130.

[0179] In operation S210, the nonvolatile memory device may receive a request RQ indicating addresses of first to N-th word lines WL1 to WLN of a target memory block. The first to N-th word lines WL1 to WLN may be all word lines of the target memory block, or may be some selected from all word lines of the target memory block. In some embodiments, "N" may indicate the total number of word lines that are targets for monitoring. The first to N-th word lines WL1 to WLN mean word lines to be monitored, and are not intended to be limited to physically continuous word lines in the target memory block. The first to N-th word lines WL1 to WLN may be physically continuous in the target memory block, or may not be physically continuous in the target memory block.

[0180] In operation S220, the nonvolatile memory device may set the address index value 'K' to '1'.

[0181] In operation S221, the nonvolatile memory device may perform an on-chip read operation of the Kth word line WLK to generate Kth word line distribution information WLDIK of the Kth word line WLK. In some embodiments, "K" may be the same as the address index value "K" set in operation S220.

[0182] In operation S222 , the nonvolatile memory device may store K th word line distribution information WLDIK in the electric fuse circuit.

[0183] In operation S223, the nonvolatile memory device may determine whether the address index value "K" is equal to the total number "N" of word lines that are targets of monitoring. When the address index value "K" is different from the total number "N" of word lines, the monitoring operation of the first to N-th word lines WL1 to WLN may not be completed. In this case, the nonvolatile memory device may perform operation S224.

[0184] In operation S224 , the nonvolatile memory device may increase the address index value “K” by “1.” Thereafter, the nonvolatile memory device may also sequentially perform operation S221 , operation S222 , and operation S223 .

[0185] When the address index value "K" is equal to the total number "N" of word lines, all monitoring operations of the first to Nth word lines WL1 to WLN may be completed. In this case, the nonvolatile memory device may perform operation S230.

[0186] In operation S230, the nonvolatile memory device may determine at least one degraded word line among the first to Nth word lines WL1 to WLN based on the first to Nth word line distribution information stored in the electronic fuse circuit, and may generate word line information indicating the at least one degraded word line thus determined.

[0187] Fig.14 is a flowchart describing a method of operating a storage device according to some embodiments of the present disclosure. Fig.14 , the storage device 100 includes a storage controller 110 and a non-volatile memory device 120 .

[0188] In operation S310, the memory controller 110 may provide a first request RQ1 indicating a word line selection operation of the target memory block BLKx to the nonvolatile memory device 120. In some embodiments, the first request RQ1 may also indicate a reclaim decision operation based on a degraded word line WLx of the target memory block BLKx.

[0189] In operation S320 , the nonvolatile memory device 120 may obtain distribution information DI of the target memory block BLKx based on the first request RQ1 .

[0190] In operation S330 , the nonvolatile memory device 120 may determine a degraded word line WLx based on the distribution information DI.

[0191] In operation S340, the nonvolatile memory device 120 may determine whether a reclaiming condition of a target memory block BLKx including a degraded word line WLx is satisfied through an on-chip read operation. For example, based on the word line distribution information of the degraded word line WLx, the nonvolatile memory device 120 may determine whether a reclaiming condition of the degraded word line WLx itself or a reclaiming condition of a target memory block BLKx including the degraded word line WLx is satisfied. As another example, the nonvolatile memory device 120 may also perform a logical page-based read operation for the degraded word line WLx, and may obtain additional distribution information; in this case, based on the additional distribution information of the degraded word line WLx, the nonvolatile memory device 120 may determine whether a reclaiming condition of the degraded word line WLx itself or a reclaiming condition of a target memory block BLKx including the degraded word line WLx is satisfied.

[0192] In operation S350, the nonvolatile memory device 120 may provide a determination result response to the storage controller 110. The determination result response may indicate the result of operation S340 of determining whether the recycle condition is satisfied. For example, when it is determined in operation S340 that the recycle condition is satisfied, the nonvolatile memory device 120 may provide a determination result response having a first bit value to the storage controller 110. As another example, when it is determined in operation S340 that the recycle condition is not satisfied, the nonvolatile memory device 120 may provide a determination result response having a second bit value to the storage controller 110.

[0193] In operation S360, based on the determination result response, the memory controller 110 may provide a second request RQ2 indicating a reclamation operation of the degraded word line WLx itself or a reclamation operation of the target memory block BLKx including the degraded word line WLx to the nonvolatile memory device 120. For example, when the determination result response indicates the first bit value, the memory controller 110 may provide the second request RQ2 to the nonvolatile memory device 120. As another example, when the determination result response indicates the second bit value, the memory controller 110 may perform operation S310 again.

[0194] In operation S361 , based on the second request RQ2 , the memory device 100 may perform a reclamation operation of the degraded word line WLx itself or a reclamation operation of a target memory block BLKx including the degraded word line WLx.

[0195] As described above, according to some embodiments of the present disclosure, since degraded word lines are quickly monitored through an on-chip read operation and distribution information of the degraded word lines is accurately analyzed through the on-chip read operation, a memory device can quickly and accurately perform reliability operations.

[0196] According to some embodiments of the present disclosure, a memory device for determining a degraded word line and a method of operating the same are provided.

[0197] Furthermore, according to some embodiments, a memory device and a method of operating the same are provided which quickly monitor a degraded word line through an on-chip read operation and accurately analyze distribution information of the degraded word line through a memory controller.

[0198] In addition, according to some embodiments, a memory device that quickly monitors a degraded word line through an on-chip read operation and quickly analyzes distribution information of the degraded word line through the on-chip read operation and a method of operating the same are provided.

[0199] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the protection that can be claimed. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as working in a specific combination and even initially claimed as such, one or more features from the combination may be deleted from the combination in some cases, and the combination may point to a sub-combination or a variant of the sub-combination.

[0200] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for operating a storage device, the storage device comprising a storage controller and a non-volatile memory device, the method comprising: providing, by a memory controller, to a nonvolatile memory device a first request indicating a word line selection operation of a target memory block; obtaining, by a nonvolatile memory device, distribution information of a plurality of word lines of a target memory block based on a first request; determining, by a nonvolatile memory device, a degraded word line among the plurality of word lines based on the distribution information; as well as Word line information indicating a degraded word line is provided to a memory controller by the nonvolatile memory device.

2. The method according to claim 1, further comprising: providing, by the memory controller, to the nonvolatile memory device a second request for a read operation indicating a degraded word line based on the word line information; providing, by the nonvolatile memory device, read data of the degraded word line to the memory controller based on the second request; as well as It is determined by the memory controller whether a reclamation condition of the target memory block is satisfied based on the read data.

3. The method according to claim 2, wherein: The step of determining, by the storage controller, whether a reclaiming condition of a target memory block is satisfied based on read data comprises: obtaining an error count value of a degraded word line based on an error correction operation of read data by an error correction code engine of a memory controller; and Based on the error count value exceeding the threshold error count value, it is determined by the memory controller that a reclamation condition of the target memory block is satisfied.

4. The method according to claim 2, further comprising: In response to determining that a reclamation condition of the target memory block is satisfied, providing, by the storage controller, to the nonvolatile memory device a third request indicating a reclamation operation of the target memory block; as well as A reclaim operation of the target memory block is performed by the storage device based on the third request.

5. The method according to claim 4, wherein: The step of performing, by the storage device, a reclaiming operation of the target memory block based on the third request comprises: providing, by the nonvolatile memory device, block data of the target memory block to the storage controller based on the third request; storing, by the memory controller, the block data in another memory block of the non-volatile memory device; and Block data of a target memory block of the nonvolatile memory device is erased by a memory controller.

6. The method according to claim 1, wherein: The step of obtaining, by a nonvolatile memory device, distribution information of the plurality of word lines of a target memory block based on a first request comprises: performing, by a nonvolatile memory device, an on-chip read operation of the plurality of word lines based on a first request; and storing, by the nonvolatile memory device, a plurality of word line distribution information respectively corresponding to the plurality of word lines in an electric fuse circuit of the nonvolatile memory device based on an on-chip read operation, and The distribution information includes the distribution information of the plurality of word lines.

7. The method according to claim 6, wherein: Each memory cell of the plurality of word lines is implemented using a three-level cell or a four-level cell, and The on-chip read operation is implemented in a single-level cell manner and includes determining whether each memory cell of the plurality of word lines corresponds to a lowest threshold voltage state, or determining whether each memory cell of the plurality of word lines corresponds to a highest threshold voltage state.

8. The method according to claim 6, wherein: Each of the plurality of word line distribution information includes at least one of the following items: a count value of on-cells of a corresponding word line among the plurality of word lines; The off-cell count value of the corresponding word line; Valley search information of the corresponding word line; and A cell count value between two adjacent read voltages of the corresponding word line.

9. The method according to claim 1, in, The distribution information includes a plurality of on-cell count values ​​respectively corresponding to the plurality of word lines, wherein each of the plurality of on-cell count values ​​indicates the number of memory cells among a plurality of memory cells of a corresponding word line among the plurality of word lines, and The number of memory cells are in at least one of an erased state of a single-level cell, an erased state of a multi-level cell, an erased state of a triple-level cell, and an erased state of a quadruple-level cell.

10. The method according to claim 9, wherein: The step of determining, by the nonvolatile memory device, a degraded word line among the plurality of word lines based on the distribution information comprises: A word line is determined from among the plurality of word lines as a degraded word line by the nonvolatile memory device, wherein the degraded word line corresponds to a minimum on-cell count value among the plurality of on-cell count values.

11. The method according to claim 9, wherein: The step of determining, by the nonvolatile memory device, a degraded word line among the plurality of word lines based on the distribution information comprises: A word line is determined from among the plurality of word lines as a degraded word line by the nonvolatile memory device, wherein the degraded word line corresponds to an on-cell count value smaller than a first threshold value among the plurality of on-cell count values.

12. The method according to claim 1, in, The distribution information includes a plurality of off-cell count values ​​respectively corresponding to the plurality of word lines, and wherein each of the plurality of off-cell count values ​​indicates the number of memory cells among a plurality of memory cells of a corresponding word line among the plurality of word lines, and The number of memory cells are in at least one of a programming state of a single level cell, a third programming state of a multi-level cell, a seventh programming state of a triple level cell, and a fifteenth programming state of a quad level cell.

13. The method according to claim 12, wherein: The step of determining, by the nonvolatile memory device, a degraded word line among the plurality of word lines based on the distribution information comprises: A word line is determined from among the plurality of word lines as a degraded word line by the nonvolatile memory device, wherein the degraded word line corresponds to a minimum off-cell count value among the plurality of off-cell count values.

14. The method according to claim 12, wherein: The step of determining, by the nonvolatile memory device, a degraded word line among the plurality of word lines based on the distribution information comprises: A word line is determined from among the plurality of word lines as a degraded word line by the nonvolatile memory device, wherein the degraded word line corresponds to an off-cell count value smaller than a second threshold value among the plurality of off-cell count values.

15. The method according to claim 1, in, The distribution information includes a plurality of cell count values ​​respectively corresponding to the plurality of word lines, each of the plurality of cell count values ​​corresponding to the number of memory cells having a threshold voltage state between two adjacent read voltages, wherein each of the plurality of cell count values ​​indicates a number of memory cells each having a threshold voltage state between two adjacent read voltage levels associated with a single level cell, a multi-level cell, a triple level cell, or a quad level cell, The step of determining the degraded word lines among the plurality of word lines based on the distribution information by the non-volatile memory device comprises: determining, by the nonvolatile memory device, a word line from among the plurality of word lines as a degraded word line, wherein the degraded word line corresponds to a maximum cell count value among the plurality of cell count values, determining, by the nonvolatile memory device, a word line from among the plurality of word lines as a degraded word line, wherein the degraded word line corresponds to a minimum cell count value among the plurality of cell count values, determining, by the nonvolatile memory device, a word line from among the plurality of word lines as a degraded word line, wherein the degraded word line has a cell count value greater than a third threshold value among the plurality of cell count values, or A word line is determined from among the plurality of word lines by the nonvolatile memory device as a degraded word line, wherein the degraded word line has a cell count value smaller than a fourth threshold value among the plurality of cell count values.

16. A method of operating a storage device, the storage device comprising a storage controller and a non-volatile memory device, the method comprising: providing, by a memory controller, to a nonvolatile memory device a first request indicating a word line selection operation of a target memory block; obtaining, by a nonvolatile memory device, distribution information of a plurality of word lines of a target memory block based on a first request; determining, by a nonvolatile memory device, a degraded word line among the plurality of word lines based on the distribution information; determining, by a nonvolatile memory device, whether a reclaim condition of a degraded word line is satisfied; as well as A determination result response indicating whether the reclaim condition is satisfied is provided to the storage controller by the nonvolatile memory device.

17. The method according to claim 16, further comprising: In response to the determination result response indicating that the reclamation condition is satisfied, providing, by the storage controller, to the nonvolatile memory device a second request indicating a reclamation operation of the target memory block; as well as A reclaim operation of the target memory block is performed by the storage device based on the second request.

18. A storage device, comprising: a memory cell array comprising a plurality of memory blocks; a memory controller configured to generate a first request indicating a word line selection operation of a target memory block among the plurality of memory blocks; as well as control logic configured to communicate with the memory cell array and the memory controller, Among them, the control logic is configured as: Based on the first request, obtaining distribution information through an on-chip read operation of a plurality of word lines of a target memory block, determining a degraded word line among the plurality of word lines based on the distribution information, and Word line information indicating a degraded word line is generated.

19. The storage device according to claim 18, in, The memory controller is further configured to provide a second request for a read operation indicating a degraded word line to the control logic based on the word line information, The control logic is further configured to provide the read data of the degraded word line to the memory controller based on the second request, and The storage controller is configured as follows: Determine whether a reclaim condition of the target memory block is satisfied based on the read data, and A third request indicating a reclaim operation of the target memory block is provided to the control logic in response to determining that the reclaim condition is satisfied.

20. The storage device according to claim 18, wherein: The control logic is also configured to: obtaining read data of a degraded word line based on the word line information; Determining whether a reclamation condition of the target memory block is satisfied based on the read data; and A determination result response indicating whether the reclaim condition is satisfied is provided to the storage controller.

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