Memory circuit and operating method thereof

Abstract

The memory circuit may include a memory array including a plurality of memory cells, an input / output (I / O) circuit, and a power management circuit. The I / O circuitry may be operably coupled to the memory array and configured to read or write each memory cell. The power management circuit may be operably coupled to the memory array and the I / O circuit. The power management circuit may be configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage. The first supply voltage may be substantially twice higher than the second supply voltage. The embodiment of the invention also provides a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array comprising a plurality of memory cells; an input / output (I / O) circuit operably coupled to the memory array and configured to read or write each of the memory cells; and a power management circuit operably coupled to the memory array and the I / O circuit and configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage, wherein the first supply voltage is substantially higher than twice the second supply voltage; wherein, when at least one of the memory cells is being written, the first gate control signal is equal to a first fraction of the first supply voltage and the second control signal is equal to a first fraction of the first supply voltage, and wherein, when at least one of the memory cells is being read, the first gate control signal is equal to a first fraction of the second supply voltage and the second control signal is equal to a third supply voltage lower than either the first supply voltage or the second supply voltage.

[0004] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array, comprising a plurality of memory cells coupled to a first supply voltage, each of the plurality of memory cells comprising a fuse resistor coupled in series to a plurality of first transistors; an input / output (I / O) circuit, coupled to a second supply voltage, comprising a plurality of second transistors, and configured to read or write each of the memory cells; and a power management circuit, operably coupled to the first supply voltage and the second supply voltage, comprising a plurality of third transistors, and configured to provide a first gate control signal and a second gate control signal based on the first supply voltage and the second supply voltage, wherein the first supply voltage is substantially higher than twice the second supply voltage; wherein the voltage between any two terminals of each of the first transistor, the second transistor, and the third transistor is equal to or less than a fraction of the first supply voltage.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: receiving a first power supply voltage and a second power supply voltage, wherein the first power supply voltage is substantially higher than twice the second power supply voltage; based on the first power supply voltage and the second power supply voltage, providing a first gate control signal to a plurality of first transistors of the memory circuit, and providing a second gate control signal to a plurality of second transistors of the memory circuit; when writing to a memory cell of the memory circuit, configuring the first gate control signal to be equal to a fraction of the first power supply voltage, and configuring the second gate control signal to be equal to a fraction of the first power supply voltage; and when reading a memory cell of the memory circuit, configuring the first gate control signal to be equal to a fraction of the first power supply voltage, and configuring the second gate control signal to be equal to a third power supply voltage lower than either the first power supply voltage or the second power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory device including a memory array is shown in accordance with some embodiments.

[0008] Figure 2 According to some embodiments Figure 1 Schematic diagram of an efuse memory cell of a memory array.

[0009] Figure 3 A block diagram of an example control circuit with stacked circuits according to some embodiments of the present disclosure is shown.

[0010] Figure 4 A block diagram of an example control circuit with stacked circuits according to some embodiments of the present disclosure is shown.

[0011] Figure 5 A block diagram of an example control circuit with stacked circuits according to some embodiments of the present disclosure is shown.

[0012] Figure 6 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a power switch implemented with a control circuit.

[0013] Figure 7 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a power switch implemented with a control circuit.

[0014] Figure 8 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a power switch implemented with a control circuit.

[0015] Fig. 9 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a power switch implemented with a control circuit.

[0016] Fig.10 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a power switch implemented with a control circuit.

[0017] Fig.11 It shows that according to some embodiments of the present disclosure, Figure 1 2 is an example circuit diagram of a sense amplifier implemented with a control circuit.

[0018] Fig.12 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a half-power switch implemented by a control circuit.

[0019] Fig.13 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a bit line transfer gate implemented by a control circuit.

[0020] Fig.14 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a bit line level shifter implemented by a control circuit.

[0021] Fig.15 An example circuit simulation of a memory circuit according to some embodiments of the present disclosure is shown.

[0022] Fig.16 An example circuit simulation of a bit line level shifter according to some embodiments of the present disclosure is shown.

[0023] Fig.17 It shows that some embodiments of the present disclosure can be Figure 1 An example circuit diagram of a fractional voltage generator implemented by a control circuit.

[0024] Fig.18 It shows that some embodiments of the present disclosure can be Figure 1 An example circuit diagram of a fractional voltage generator implemented by a control circuit.

[0025] Fig.19 It shows that some embodiments of the present disclosure can be Figure 1An example circuit diagram of a fractional voltage generator implemented by a control circuit.

[0026] Fig. 20 A flow chart of an example method for operating a memory circuit having stacked circuits according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0029] One-time programmable (OTP) memory devices are one of various types of non-volatile memory devices. Example implementations of OTP memory devices include metal fuses, etc. Metal fuses use metal resistors as programming elements of corresponding OTP memory devices. Such metal fuses are sometimes referred to as efuse (electrical fuse) memory devices, in which metal resistors can usually be programmed (for example, once). The programming process usually involves burning or fusing the metal resistor to change it from a short circuit (state) to an open circuit (state). Efuse memory devices are commonly used in integrated circuits to adjust circuit systems after the integrated circuit is manufactured. For example, efuse memory devices are used to provide repair information that controls the use of redundant cells when replacing defective cells of a memory array. Another use is to tune analog circuits by fine-tuning the capacitance or resistance values ​​of analog circuits or enabling and disabling parts of the system. In another example, a recent trend is that an integrated circuit (or chip) can include multiple efuse memory cells with respective programming states, which can be used together as keys for integrated circuits for encryption or decryption purposes.

[0030] The general purpose of the present disclosure is to address common challenges associated with efuse (or general OTP) memory circuits, which typically require high voltages (e.g., above 0.96V) for programming. In advanced node technologies, input / output (I / O) devices are sometimes not readily available, which poses a significant challenge. Such I / O devices are typically referred to as transistors when compared to core devices (or core transistors), which are formed with relatively high threshold voltages and configured to operate at relatively high voltages. In this case, the problems faced by older products revolve around device reliability, especially when the circuit is subjected to high voltage stress. To address this issue, stacked core devices can be used in advanced processes. In addition, the present disclosure introduces a multi-level voltage generator to reduce power switch voltage stress, helping to improve circuit reliability and performance. For example, the present disclosure provides various embodiments of stacked circuits implemented in memory devices. The present disclosure is characterized in that stacked circuits are implemented within a bit cell in a memory system and / or across all peripheral circuits. Stacking technology optimizes the integration of memory components to improve performance. In various embodiments, peripheral circuits that may benefit from this approach may be MVDD generators, power switches, half-power switches, level shifters, sense amplifiers, delay maps, and BL / WL controllers.

[0031] Figure 1 is a block diagram of an example memory device 100 including a memory array according to some embodiments. Figure 1In the illustrated embodiment, memory device 100 may include memory array 102 and control circuit 110. Control circuit 110 may include row decoder 104, column decoder 106, input / output (I / O) circuit 108, and power management circuit 112. Figure 1 Although not shown in FIG. 1 , all components of the memory device 100 may be coupled to each other and to the power management circuit 112. Figure 1 In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1 Some or all of the components shown in can be integrated together. For example, memory array 102 can include embedded I / O circuits (eg, 108).

[0032] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other memory cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M Each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3, ... N , each column extends in a second direction (e.g., the Y direction). Each row and each column may include one or more conductive (e.g., metal) structures used as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and can be operated according to a voltage or current through the corresponding conductive structure of the column and row. For example, each row may include one or more corresponding word lines (WL), and each column may include one or more corresponding bit lines (BL). In some embodiments, each component, including components within the control circuit 110 and the memory array 102, can be constructed based on a stacking scheme (e.g., a stacking circuit). In some embodiments, any component in the memory device 100 that requires a high voltage (e.g., about 0.96V or more) can be constructed based on a stacking scheme (e.g., a stacking circuit).

[0033] In some embodiments, each memory cell 103 can be implemented as an efuse memory cell, which can include at least one fuse resistor and a WL transistor. In various embodiments, each fuse resistor is coupled to the WL transistor, and the WL transistor and the fuse resistor are coupled between the corresponding BL and the source line that is typically connected to the ground (VSS). For example, at least one fuse resistor can be coupled to each other in series, and one of the at least one fuse resistor can have a terminal electrically connected to the first source / drain terminal of the WL transistor. In addition, another of the at least one fuse resistor can have a terminal electrically connected to the corresponding BL. In another example, at least one fuse resistor can be coupled to each other in parallel, and at least one fuse resistor can each have a first terminal electrically connected to the first source / drain of the WL transistor. In addition, at least one fuse resistor can each have a second terminal electrically connected to the corresponding BL. In any example, the gate terminal of the WL transistor can be connected to the corresponding WL, and the second source / drain terminal of the WL transistor can be connected to the source line. Reference will be made to Figure 2 The details of various implementations of efuse memory cells are discussed in more detail. In some other embodiments, each memory cell 103 can be implemented as any of a variety of other non-volatile memory cells. For example, the memory cell 103 can include a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase change random access memory cell (PCRAM), an antifuse, etc., while still within the scope of the present disclosure.

[0034] The control circuit 110 may be a hardware component that may control coupled components (e.g., 102 to 112). The row decoder 104 may be a hardware component that may receive a row address of the memory array 102 and assert a conductive structure (e.g., WL) at the row address. The column decoder 106 may be a hardware component that may receive a column address of the memory array 102 and assert a conductive structure (e.g., BL) at the column address. The I / O circuit 108 may be a hardware component that may access (e.g., read, program) each memory cell 103 asserted by the row decoder 104 and the column decoder 106. The I / O circuit 108 may be operably coupled to the memory array 102 and configured to read or write each memory cell 103. The power management circuit 112 may be a hardware component that provides at least one gate control signal based on at least one supply voltage to control the voltage of each component in the memory device 100. The power management circuit 112 may be operably coupled to the memory array 102 and the I / O circuit 108. For example, the power management circuit 112 may be configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage. The first supply voltage may be substantially higher than twice the second supply voltage.

[0035] Figure 2 An example configuration 200 of an efuse memory unit 103 according to various embodiments is shown. In the following, Figure 2 The configuration in may be referred to as "efuse memory cell 200". In various embodiments, the efuse memory cell 200 may have at least one fuse resistor, such that the disclosed efuse memory cell presents a logic state with a randomly programmed fuse resistor. In addition, the fuse resistor may be physically formed at different vertical positions relative to the substrate, which may make the position of the programmed fuse resistor difficult to identify.

[0036] Reference Figure 2 , the efuse memory cell 200 includes a first fuse resistor 210 and a WL transistor 230 connected in series to each other between BL and ground (VSS), and the WL transistor 230 is selected by WL. For example, the first fuse resistor 210 may have a first terminal and a second terminal, and the WL transistor 230 may have a first source / drain terminal and a second source / drain terminal. The first terminal of the first fuse resistor 210 may be connected to BL, the second terminal of the first fuse resistor 220 may be connected to the first source / drain terminal of the WL transistor 230 at a node "Y", and the second source / drain terminal of the WL transistor 230 may be grounded.

[0037] The WL transistor 230 may be formed along a main (e.g., front side) surface of a semiconductor substrate, sometimes referred to as part of a front end of line (FEOL) process / network. On the front side surface, a plurality of first (or front side) metallization layers may be formed, each of which may include a plurality of interconnect (e.g., metal) structures / tracks, sometimes referred to as part of a back end of line (BEOL) process or network. These front side metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., and thus the front side metal tracks contained in the corresponding metallization layers (e.g., MX layers) are sometimes referred to as MX tracks. On the back side of the substrate, a plurality of second (or back side) metallization layers may be formed, each of which may include a plurality of interconnect (e.g., metal) structures / tracks. Such back side metallization layers are sometimes referred to as BM0 layers, BM1 layers, BM2 layers, etc. Such back side metallization layers are sometimes referred to as BM0 layers, BM1 layers, BM2 layers, etc., and thus the back side metal tracks contained in the corresponding metallization layers (e.g., BMX layers) are sometimes referred to as BMX tracks.

[0038] In some embodiments, the first fuse resistor 210 can be formed as a plurality of backside metal tracks. In some embodiments, the first fuse resistor 210 can be formed as a plurality of frontside metal tracks. In some other embodiments, the first fuse resistor 210 can be formed as a plurality of frontside metal tracks in a first frontside metallization layer. In other words, in various embodiments of the present disclosure, the metal tracks operable to serve as the first fuse resistor 210 and the WL transistor 230 are vertically spaced apart from each other.

[0039] Figure 3 A block diagram of an example control circuit 110 having stacked circuits according to some embodiments of the present disclosure is shown. Figure 3 An example operation of a memory device in a program / write mode is shown. Figure 3 In the illustrated embodiment, control circuitry 110 may include input / output (I / O) circuitry 108 and power management circuitry 112 .

[0040] The I / O circuit 108 may include a header 302, a power switch 304, a bit line (BL) control circuit 306 (e.g., BL transmission gate, BL selection), a BL level shifter 308, a word line (WL) level shifter 310, a WL control circuit 312 (e.g., efuse unit, WL selection), and a plurality of sense amplifiers 314. The power management circuit 112 may include an MVDD generator 316 and a half power switch 318. In some embodiments, each component (e.g., 302 to 318) within the control circuit 110 may be constructed based on a stacking scheme (e.g., a stacked circuit). In some embodiments, the header device 302 may be electrically coupled to at least a plurality of sense amplifiers 314. The power switch 304 may include a plurality of first p-type transistors electrically stacked relative to each other. For example, the power switch 304 may include a three-stack design. The bit line (BL) control circuit 306 may include a plurality of second p-type transistors electrically stacked relative to each other. For example, the BL control circuit (e.g., BL transmission gate, BL selection) 306 may include a double stack design. The BL control circuit 306 may receive a supply voltage (e.g., VDDQ, VDDHD) from the BL level shifter 308 and the power switch 304. The BL level shifter 308 may include a plurality of third p-type transistors electrically stacked relative to each other. The BL level shifter 308 may receive a supply voltage VDDHD (e.g., approximately 0.75V) and a supply voltage VDDQ (e.g., approximately 1.8V).

[0041] In some embodiments, the BL level shifter 308 can be configured to shift the voltage for the BL control circuit 306 from a first voltage domain (e.g., about 0 to 0.75V) to a second voltage domain (e.g., about 0.9 to 1.8V). The first voltage domain can range from a third supply voltage (e.g., about 0V) to a second supply voltage (e.g., about 0.75V). The second voltage domain can range from a first fraction of the first supply voltage (e.g., about 0.9V) to the first supply voltage (e.g., about 1.8V). In some embodiments, the BL level shifter 308 can include a delay circuit.

[0042] In some embodiments, the word line (WL) level shifter 310 may include a plurality of fourth p-type transistors electrically stacked relative to each other. The WL level shifter 310 may receive a supply voltage VDDHD (e.g., about 0.75V) and a gate control signal (e.g., NCGATE or PCGATE) from the power management circuit 112. In some embodiments, the WL level shifter 310 may be configured to shift the voltage for the memory cell from a first voltage domain (e.g., about 0 to 0.75V) to a third voltage domain (e.g., about 0 to 0.9V). The first voltage domain may range from a third supply voltage (e.g., about 0V) to a second supply voltage (e.g., about 0.75V). The second voltage domain may range from a third supply voltage (e.g., about 0V) to a first fraction of the first supply voltage (e.g., about 0.9V) or to a second fraction of the first supply voltage (e.g., about 1.2V). The second fraction (e.g., about 2 / 3) may be greater than the first fraction (e.g., about 1 / 2). In some embodiments, the WL level shifter 310 may include a CSB control circuit. The CSB control circuit may be configured to shift the voltage for the memory cell from a third voltage domain (e.g., about 0 to 0.9V) to a first voltage domain (e.g., about 0 to 0.75V) during a read mode. The word line (WL) control circuit 312 may include a fuse resistor and a plurality of second n-type transistors electrically stacked relative to each other. For example, the WL control circuit (e.g., EFCELL (EF cell), WL selection) 312 may include a double stack design. The WL control circuit 312 may receive a supply voltage (e.g., VDDQI, VDDHD) from the WL level shifter 310 and the BL control circuit 306. The plurality of sense amplifiers 314 may each include a plurality of first n-type transistors. For example, the plurality of sense amplifiers 314 may include a double stack design. The plurality of sense amplifiers 314 may receive a supply voltage VDDHD from the header 302. In some embodiments, each WL control circuit 312 may include a fuse resistor and a plurality of second n-type transistors coupled in series to each other. The plurality of second n-type transistors may be electrically stacked with each other.

[0043] In some embodiments, the power management circuit 112 can be configured to provide a first gate control signal 350 (e.g., NMOS control gate (NCGATE)) and a second gate control signal 352 (e.g., PMOS control gate (PCGATE)) based on a received first supply voltage 360 ​​(e.g., VQPS) and a received second supply voltage 362 (e.g., VDD). In some embodiments, the first supply voltage 360 ​​(e.g., about 1.8V) is substantially higher than the second supply voltage 362 (e.g., about 0.75V) by a factor of two. For example, the supply voltage VQPS 360 (received by the control circuit 110) can be about 1.8V, and the supply voltage VDD 362 (received by the control circuit 110) can be about 0.75V.

[0044] When at least one memory cell is written, the first gate control signal (e.g., NCGATE) 350 may be equal to a first fraction (e.g., half_VQPS) of the first power supply voltage 360, and the second control signal (e.g., PCGATE) 352 may be equal to a first fraction (e.g., half_VQPS) of the first power supply voltage 360. For example, the voltage of the first gate control signal NCGATE 350 may be equal to about 0.9V (e.g., half_VQPS), which is 1 / 2 of the power supply voltage VQPS 360 (about 1.8V). The voltage of the second control signal PCGATE 352 may be equal to about 0.9V (e.g., half_VQPS), which is 1 / 2 of the power supply voltage VQPS 360 (about 1.8V).

[0045] In the programming / writing mode (e.g., when PS=H), the power management circuit 112 may receive an external voltage VQPS and may provide a first gate control signal (e.g., NCGATE) 350 and a second gate control signal (e.g., PCGATE) 352. The external voltage VQPS 360 may be equal to about 1.8V. NCGATE 350 and PCGATE 352 may be equal to about 0.9V, which is half of the external voltage VQPS (e.g., about 1.8V). In this case, the power management circuit 112 may relieve the power switch voltage stress by reducing the voltage. The BL selector 306 may receive the second gate control signal PCGATE 352 and the first control signal. The first control signal may be a control signal for a bit line. In the programming / writing mode (e.g., when PS=H), the second gate control signal PCGATE 352 may be equal to about 0.9V and the first control signal may be equal to about 0.9V. In this case, BL select 306 is selected. The WL selector 312 may receive a first gate control signal NCGATE 350 and a second control signal. The second control signal may be a control signal for a word line. In a programming / write mode (e.g., when PS=H), the first gate control signal NCGATE 350 may be equal to approximately 0.9V, and the second control signal may be equal to approximately 0.9V. In various embodiments, the first gate control signal NCGATE may have opposite logic states (i.e., logic "1" and logic "0") corresponding to a supply voltage and a fractional voltage, respectively, and the second gate control signal PCGATE may correspond to opposite logic states of a fractional voltage and a ground voltage, respectively.

[0046] In some embodiments, regardless of whether the memory cell is being read or written / programmed, the voltage between any two terminals of each of the first p-type transistor, the second p-type transistor, and the third p-type transistor may be equal to or less than a first fraction of the first supply voltage VQPS 360 (e.g., about 1.8 V). The first supply voltage VQPS 360 may be configured to gate control at least one of the first n-type transistor and the at least one second n-type transistor. The second supply voltage VDD 362 may be configured to gate control at least one of the first p-type transistor, the second p-type transistor, the third p-type transistor, and the fourth p-type transistor.

[0047] In some embodiments, regardless of whether the memory cell is read or written / programmed, the voltage between any two terminals of each of the first p-type transistor, the second p-type transistor, and the third p-type transistor may be equal to or less than a first fraction (e.g., about 0.9V) of the first supply voltage VQPS 360. In some embodiments, the first gate control signal NCGATE 350 may be configured to gate control at least one of the first n-type transistors (e.g., SA) and at least one of the second n-type transistors (e.g., WL select). The second gate control signal PCGATE 352 may be configured to gate control at least one of the first p-type transistors (e.g., power switch), at least one of the second p-type transistors (e.g., BL control circuit), at least one of the third p-type transistors (e.g., BL level shifter), and at least one of the fourth p-type transistors (e.g., WL level shifter).

[0048] Figure 4 A block diagram of an example control circuit 110 having stacked circuits according to some embodiments of the present disclosure is shown. Figure 4 An example operation of a memory device in read mode is shown. Figure 4 In the illustrated embodiment, control circuitry 110 may include input / output (I / O) circuitry 108 and power management circuitry 112 . Figure 4 The control circuit 110 is basically similar to Figure 3 The difference is that the control circuit 110 operates in the read mode.

[0049] In some embodiments, the power management circuit 112 can be configured to provide a first gate control signal 350 (e.g., NCGATE) and a second gate control signal 352 (e.g., PCGATE) based on a received first supply voltage 360 ​​(e.g., VQPS) and a received second supply voltage 362 (e.g., VDD). In some embodiments, the first supply voltage 360 ​​(e.g., about 0.9V) is substantially twice higher than the second supply voltage 362 (e.g., about 0.75V). For example, the supply voltage VQPS 360 (received by the control circuit 110) can be about 1.8V, and the supply voltage VDD 362 (received by the control circuit 110) can be about 0.75V.

[0050] When at least one memory cell is being read, the first gate control signal (e.g., NCGATE) 350 may be equal to a first fraction of a second power supply voltage (e.g., VDDHD), and the second control signal (e.g., PCGATE) 352 may be equal to a third power supply voltage (e.g., VSS) that is lower than either the first or second power supply voltages. For example, the voltage of the first gate control signal NCGATE 350 may be equal to approximately 0.75V (e.g., VDDHD). In some embodiments, the voltage of the first gate control signal NCGATE 350 is equal to a first fraction of the second power supply voltage. The voltage of the second control signal PCGATE 352 may be equal to approximately 0V (e.g., VSS), which is lower than either the first or second power supply voltages.

[0051] In a read mode (e.g., when PS=L), the power management circuit 112 may receive an external voltage VQPS and may provide a first gate control signal (e.g., NCGATE) 350 and a second gate control signal (e.g., PCGATE) 352. The external voltage VQPS 360 may be equal to approximately 1.8V. NCGATE 350 may be equal to approximately 0.75V. PCGATE 350 may be equal to approximately 0V. In this case, the power management circuit 112 may relieve power switch voltage stress by reducing the voltage. The BL selector 306 may receive the second gate control signal PCGATE 352 and the first control signal. In a program / write mode (e.g., when PS=L), the second gate control signal PCGATE 352 may be equal to approximately 0V and the first control signal may be equal to approximately 0.75V. In this case, the BL select 306 is not selected. In some embodiments, the BL control signal may be received from the sense amplifier 314. The WL selector 312 may receive the first gate control signal NCGATE 350 and the second control signal. In the read mode (eg, when PS=L), the first gate control signal NCGATE 350 may be equal to approximately 0.75V and the second control signal may be equal to approximately 0.75V.

[0052] In some embodiments, regardless of whether the memory cell is being read or written / programmed, the voltage between any two terminals of each of the first p-type transistor, the second p-type transistor, and the third p-type transistor may be equal to or less than a first fraction of the first supply voltage VQPS 360 (e.g., about 1.8 V). The first supply voltage VQPS 360 may be configured to gate control at least one of the first n-type transistor and the at least one second n-type transistor. The second supply voltage VDD 362 may be configured to gate control at least one of the first p-type transistor, the second p-type transistor, the third p-type transistor, and the fourth p-type transistor.

[0053] In some embodiments, regardless of whether the memory cell is read or written / programmed, the voltage between any two terminals of each of the first p-type transistor, the second p-type transistor, and the third p-type transistor may be equal to or less than a first fraction (e.g., about 0.9V) of the first supply voltage VQPS 360. In some embodiments, the first gate control signal NCGATE 350 may be configured to gate control at least one of the first n-type transistors (e.g., SA) and at least one of the second n-type transistors (e.g., WL select). The second gate control signal PCGATE 352 may be configured to gate control at least one of the first p-type transistors (e.g., power switch), at least one of the second p-type transistors (e.g., BL control circuit), at least one of the third p-type transistors (e.g., BL level shifter), and at least one of the fourth p-type transistors (e.g., WL level shifter, etc.).

[0054] Figure 5 A block diagram of an example control circuit 110 having stacked circuits according to some embodiments of the present disclosure is shown. Figure 5 An example operation of a memory device in write mode is shown. Figure 5 In the illustrated embodiment, the control circuit 110 may include input / output (I / O) circuits 108 and power management circuits 112. In addition to the additional power switch 502, Figure 5 The control circuit 110 and Figure 3 Increasing the supply voltage of WL select 312 may improve performance during programming mode.

[0055] In some embodiments, the WL level shifter 310 may receive a supply voltage VDDHD (e.g., about 0.75V) and a gate control signal (e.g., VDDQ12) from the additional power switch 502. The additional power switch 502 may include a double stack design. The gate control signal may be received from the supply voltage VDDIO 504 or from a second portion of the first supply voltage VQPS 360. The gate control signal may be equal to about 1.2V.

[0056] In some embodiments, the WL level shifter 310 can be configured to shift the voltage for the memory cell from a first voltage domain (e.g., about 0 to 0.75V) to a third voltage domain (e.g., about 0 to 1.2V). The first voltage domain can range from a third supply voltage (e.g., about 0V) to a second supply voltage (e.g., about 0.75V). The second voltage domain can range from a third supply voltage (e.g., about 0V) to a second fraction (e.g., about 2 / 3) of the first supply voltage VQPS 360 (e.g., about 1.2V). The second fraction (e.g., about 2 / 3) can be greater than the first fraction (e.g., about 1 / 2). In some embodiments, the WL level shifter 310 can include a CSB control circuit. The word line (WL) control circuit 312 can include a fuse resistor and a plurality of second n-type transistors electrically stacked relative to each other. For example, the WL control circuit (e.g., EFCELL, WL select) 312 can include a dual stack design. WL control circuit 312 may receive supply voltages (eg, VDDQI, VDDHD) from WL level shifter 310 and BL control circuit 306 .

[0057] In the programming / writing mode (e.g., when PS=H), the power management circuit 112 may receive an external voltage VQPS and may provide a first gate control signal (e.g., NCGATE) 350 and a second gate control signal (e.g., PCGATE) 352. The external voltage VQPS 360 may be equal to about 1.8V. NCGATE 350 and PCGATE 352 may be equal to about 0.9V, which is half of the external voltage VQPS (e.g., about 1.8V). In this case, the power management circuit 112 may relieve the power switch voltage stress by reducing the voltage. The BL selector 306 may receive the second gate control signal PCGATE 352 and the first control signal. In the programming / writing mode (e.g., when PS=H), the second gate control signal PCGATE 352 may be equal to about 0.9V and the first control signal may be equal to about 0.9V. In this case, the BL selector 306 is selected. The WL selector 312 may receive the first gate control signal NCGATE 350 and the second control signal. In the programming / writing mode (eg, when PS=H), the first gate control signal NCGATE 350 may be equal to about 1.2 V and the second control signal may be equal to about 1.2 V. By increasing the supply voltage of the WL selector 312 , the memory circuit 100 may improve performance during the programming mode.

[0058] Figure 6 It shows that according to some embodiments of the present disclosure, Figure 1An example circuit diagram of a power switch (2 stack design) implemented by the control circuit 110. The control circuit 600 includes a voltage level shifter C1, a power switch control circuit P1, a fractional voltage generator MG, a plurality of first inverters I1-I4, and a plurality of second inverters I5-I9. Typically, the fractional voltage generator MG can provide a fractional voltage of the power supply voltage to the voltage level shifter C1. The voltage level shifter C1 can generate a first intermediate signal based on the fractional voltage, and the opposite logic states of the first intermediate signal correspond to the power supply voltage and the fractional voltage, respectively. The power switch control circuit P1 can generate a second intermediate signal, and the opposite logic states of the second intermediate signal correspond to the fractional voltage and the ground voltage, respectively. Then, the first inverter I1-I4 and the second inverter I5-I9 can respectively input the first intermediate signal and the second intermediate signal to jointly determine the voltage level at the output node of the control circuit 600. Figure 6 In the embodiment of the present invention, stacking transistors reduces the VQPS stress on each individual transistor within the power switch (eg, 1 / 2 VQPS stress).

[0059] The voltage level shifter C1 may include a voltage modulation circuit (voltage multiplex structure) S1 coupled between the PMOS transistors M3 and M4 and the NMOS transistors M1 and M2, which is configured to provide an intermediate signal qgb based on the control signals YSELB and YSELB'. In various embodiments, the control signals YESLB and YSELB' used as input signals of the control circuit 600 can each be converted within a first voltage domain (e.g., from 0V (VSS) to 0.75V (VDD)). Through the voltage level shifter C1, the intermediate signal qgb can present a first logic state corresponding to the supply voltage VQPS or a second logic state corresponding to a fractional voltage MVDD that is a fraction of the supply voltage VQPS. For example, the supply voltage VQPS (received by the control circuit 600) can be approximately 1.8V, while the fractional voltage MVDD is approximately half of VQPS, for example, approximately 0.9V. In other words, the control signal YSELB / YSELB' in the first voltage domain (0-0.75V) may be shifted to the intermediate signal qgb in the second voltage domain (0.9-1.8V).

[0060] The voltage level shifter C1 may include an NMOS transistor M1, which is gated with a control signal YSELB and has a ground voltage as a source. The voltage level shifter C1 may include an NMOS transistor M2, which is gated by a control signal YSELD' complementary to the control signal YSELB and has a ground voltage as a source. The voltage level shifter C1 includes a PMOS transistor M3 with a supply voltage VQPS as a source. The control circuit may include a PMOS transistor M4 with a supply voltage VQPS as a source.

[0061] Specifically, the voltage multiplex structure S1 (of the voltage level shifter C1) may include an NMOS transistor M5 gated by the fractional voltage MVDD and connected to the NMOS transistor M1. The voltage multiplex structure S1 may include an NMOS transistor M6 gated by the fractional voltage MVDD and connected to the NMOS transistor M2. The voltage multiplex structure S1 may include a PMOS transistor M7 gated by the drain voltage of the NMOS transistor M6 and drained by the fractional voltage MVDD. The voltage multiplex structure S1 may include a PMOS transistor M8 controlled by the drain voltage of the NMOS transistor M6 and drained by the fractional voltage MVDD. The voltage multiplex structure S1 may include an NMOS transistor M9 gated by the source voltage of the PMOS transistor M7, which is also coupled to the intermediate signal qgb. The voltage multiplex structure S1 may include an NMOS transistor M10 gated by the source voltage of the PMOS transistor M8, which is also coupled to the intermediate signal qgb.

[0062] In some embodiments, the voltage multiplex structure S1 may include a PMOS transistor M11 connected to the PMOS transistor M3 and a PMOS transistor M12 connected to the PMOS transistor M4. The PMOS transistors M11 and M12 may be commonly gated by a signal PCGATE, which may be a fixed voltage (e.g., 0.9 V when the fractional voltage MVDD is provided at 0.9 V). The voltage multiplex structure S1 may include a PMOS transistor M13 gated by the fractional voltage MVDD and an NMOS transistor M14 gated by the fractional voltage MVDD. The voltage multiplex structure S1 may include a PMOS transistor M15 sourced by the fractional voltage MVDD and an NMOS transistor M16 sourced by the fractional voltage MVDD.

[0063] In addition, the control circuit 600 may include inverters I1, I2, I3, and I4 coupled in series with each other, each inverter coupled between the power supply voltage VQPS and the fractional voltage MVDD. The control circuit 600 may include a PMOS transistor M17, which uses the power supply voltage VQPS as a source and drains with the output voltage VDDQ. The control circuit 600 may include a PMOS transistor M18 selected with the fractional voltage MVDD, which is connected to the PMOS transistor M17 to drain the output voltage VDDQ. The control circuit 600 may include an NMOS transistor M19, whose source is a ground voltage and whose drain is the output voltage VDDQ. The control circuit 600 may also include inverters I5, I6, I7, I8, and I9 coupled in series with each other, each inverter coupled between the power supply voltage VQPS and the fractional voltage MVDD. The control circuit 600 may include a power switch control circuit P1, which is configured to output an intermediate signal PV based on control signals PS and PD (complementary to each other). In various embodiments, the power switch control circuit P1 may further include a level shifter powered by the fractional voltage MVDD, the level shifter shifting the control signal PS / PD (e.g., in the first voltage domain, from 0V (VSS) to 0.75V (VDD)) into an intermediate signal PV, the intermediate signal PV presenting a first logic state corresponding to the fractional voltage MVD or a second logic state corresponding to the ground voltage. In other words, the control signal PS / PD in the first voltage domain (0-0.75V) may be shifted into an intermediate signal PV in the third voltage domain (0-0.9V).

[0064] In various embodiments, the two intermediate signals qgb and PV can be respectively input to the inverters I1-I4 and I5-I9 coupled in series so that the supply voltage VQPS or the ground voltage VSS is output as the output voltage VDDQ. In other words, the control circuit 600 can convert the signal from the first voltage domain to the second voltage domain. For example, the control circuit 600 can convert the control signal YSELB / YSELB' in the first voltage domain (0-0.75V) into the intermediate signal qgb in the second voltage domain (0.9-1.8V). In addition, using the intermediate signal PV in the third voltage domain (0-0.9V) (output by the power switch control circuit P1), the control circuit 600 can provide an output voltage VDDQ in the fourth voltage domain (0-1.8V). An example operation of the control circuit 600 will be described below.

[0065] To illustrate the operation of the disclosed voltage level shifter C1, some nodes are referenced below. Figure 6, the voltage multiplex structure S1 may include a node N1 connected to the drain of the NMOS transistor M5, the gate of the PMOS transistor M7, and the source of the NMOS transistor M9. The voltage multiplex structure S1 may include a node N2 connected to the drain of the NMOS transistor M6, the gate of the PMOS transistor M8, and the source of the NMOS transistor M10. The voltage multiplex structure S1 may include a node N3 connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M13, and the gate of the NMOS transistor M9. The voltage multiplex structure S1 may include a node N4 connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M14, and the gate of the NMOS transistor M10. The voltage multiplex structure S1 may include a node N5 connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M15, and the gate of the NMOS transistor M9. The voltage multiplex structure S1 may include a node N6 connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M16, and the gate of the NMOS transistor M10. The voltage multiplex structure S1 includes a node N7 connected to the drain of the PMOS transistor M11, the source of the PMOS transistor M13, and the drain of the NMOS transistor M9. The voltage multiplex structure S1 may include a node N8 connected to the drain of the PMOS transistor M12, the source of the PMOS transistor M14, and the drain of the NMOS transistor M10. The voltage multiplex structure S1 may include a node N9 connected to the drain of the PMOS transistor M11, the gate of the PMOS transistor M15, and the drain of the NMOS transistor M9. The voltage multiplex structure S1 may include a node N10 connected to the drain of the PMOS transistor M12, the gate of the PMOS transistor M16, and the drain of the NMOS transistor M10. The node N11 of the common drain of the PMOS transistor M18 and the NMOS transistor M19 may output the voltage VDDQ from the control circuit 600.

[0066] In response to control signals YSELB and YSELB' provided at low (e.g., 0V) and high (e.g., 0.75V), respectively, the low YSELB gate voltage turns off the NMOS transistor M1, and the high YSELB' gate voltage turns on the NMOS transistor M2. The NMOS transistor M2 pulls its drain voltage down to 0V. The NMOS transistor M6, which is gated by the fractional voltage MVDD, can be turned on, which pulls the voltage at the node N2 down to 0V. This 0V at the node N2 gates the PMOS transistor M8, which can turn on the PMOS transistor M8. Therefore, the source and drain of the PMOS transistor M8 can approximately present the same voltage (MVDD, e.g., 0.9V). This makes the intermediate signal qgb equal to the logical low fractional voltage MVDD.

[0067] At the same time, the control signals PS and PD can be provided to the power switch control circuit P1 at a high level (e.g., 0.75V) and a low level (e.g., 0V), respectively. This can allow the power switch control circuit P1 to output an intermediate signal PV equal to a logical high fractional voltage MVDD (e.g., 0.9V). By inputting the intermediate signals qgb (logical low) and PV (logical high) to the inverters I1-I4 and I5-I9 coupled in series, respectively, the PMOS transistor M17 can be turned on (the PMOS transistor M18 is always turned on), and the NMOS transistor M19 can be turned off, which allows the supply voltage VQPS to be coupled to the output node N11, that is, the output voltage VDDQ presenting VQPS (1.8V). For example, the logical low qgb is inverted by the inverter I1 and output as a logical high, the inverter I2 is further inverted and outputs a logical low, and the inverter I3 is further inverted and output as a logical high. Therefore, the output qg2b_i of the inverter I3 is a logic high, and is further inverted by the inverter I4 and output as a logic low to turn on the PMOS transistor M17. Similarly, the logic high PV is inverted by the inverter I9 and output as a logic low, which is further inverted by the inverter I8 and output as a logic high, and so on. Therefore, the output pstb1 of the inverter I6 is a logic high, which is further inverted by the inverter I5 and input as a logic low to turn off the NMOS transistor M19.

[0068] Table I below summarizes various logic states / voltage levels at some nodes of control circuit 600 .

[0069]

[0070] Table I

[0071] In response to the control signal YSELB being high (e.g., 0.75V) and the control signal YSELD' being low (e.g., 0V), the high YSELB gate voltage turns on the NMOS transistor M1 and the low YSELB' gate voltage turns off the NMOS transistor M2. The NMOS transistor M1 pulls its drain voltage down to 0V. The NMOS transistor M5, which is gated by the fractional voltage MVDD, can be turned on, which pulls the voltage at the node N1 down to 0V. This 0V at the node N1 gates the PMOS transistor M7, which can turn on the PMOS transistor M7. Therefore, the source and drain of the PMOS transistor M7 can present approximately the same voltage (MVDD, e.g., 0.9V). This causes the PMOS transistor M4 to turn on, which can help pass VQPS (at the source of the PMOS transistor M4) to the source of the PMOS transistor M12 gated by the fixed voltage (PCGATE). Therefore, the drain of the PMOS transistor M12 is approximately equal to 1.8 V, which causes the PMOS transistor M14 selected by MVDD (e.g., 0.9 V) to turn on, so that its drain presents 1.8 V. Therefore, the intermediate signal qgb (connected to the drain of the PMOS transistor M14) is equal to 1.8 V (i.e., the supply voltage VQPS), which is a logic high.

[0072] At the same time, the control signals PD and PS can be provided to the power switch control circuit P1 at a high level (e.g., 0.75V) and a low level (e.g., 0V), respectively. This can allow the power switch control circuit P1 to output an intermediate signal PV that is a logic low and is equal to the ground voltage (e.g., 0V). By inputting the intermediate signals qgb (logic high) and PV (logic low) to the inverters I1-I4 and I5-I9 coupled in series, respectively, the PMOS transistor M17 can be turned off and the NMOS transistor M19 can be turned on, which allows the ground voltage to be coupled to the output node N11, that is, the output voltage VDDQ presenting the ground voltage (0V). For example, the logic high qgb is inverted by the inverter I1 and output as a logic low, further inverted by the inverter I2 and output as a logic high, and further inverted by the inverter I3 and input as a logic low. Therefore, the output qg2b_i of the inverter I3 is a logic low, and is further inverted by the inverter I4 and output as a logic high to turn off the PMOS transistor M17. Likewise, logic low PV is inverted by inverter I9 and output as logic high, which is further inverted by inverter I8 and output as logic low, etc. Therefore, output pstb1 of inverter I6 is logic low, which is further inverted by inverter I5 and input as logic high to turn on NMOS transistor M19.

[0073] Table II below summarizes the various logic states / voltage levels at some nodes of control circuit 600 .

[0074]

[0075] Table II

[0076] Figure 7 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a power switch (three-stack design) implemented by the control circuit 110 of FIG. 700 is similar to the control circuit 600 ( Figure 6 ), the difference is that the control circuit 700 can provide an output voltage based on multiple fractional voltages. Therefore, the control circuit 700 can convert the input voltage to a relatively wide voltage domain (compared with the control circuit 600), or each transistor of the control circuit 700 can operate under lower voltage stress (compared with the control circuit 600). Therefore, the following discussion of the control circuit 700 will focus on the differences. Figure 7 In the embodiment of the present invention, stacking transistors reduces the VQPS stress on each individual transistor within the power switch (eg, 1 / 3 the VQPS stress).

[0077] For example, the control circuit 700 may include first and second fractional voltage generators G1 and G2, two voltage level shifters L1 and L2, a power switch control circuit P2, and a first group of inverters I10, I11, I12, and I13 coupled in series, a second group of inverters I14, I15, I16, and I17 coupled in series, and a third group of inverters I18, I19, and I20 coupled in series. The voltage generators G1 and G2 may provide a first fractional voltage HVDD and a second fractional voltage LVDD, respectively. In some embodiments, the supply voltage VQPS (received by the control circuit 700) may be approximately 1.8V, while the fractional voltage HVDD is approximately two-thirds of VQPS, i.e., approximately 1.2V, and the fractional voltage LVDD is approximately one-third of VQPS, i.e., approximately 0.6V. HVDD and LVDD may power the level shifters L1 and L2, respectively.

[0078] Based on about Fig.16 The level shifters L1 and L2 can respectively generate a first intermediate signal qgb and a second intermediate signal psvq_i based on the similar operating principle discussed in the level shifter C1 of the control circuit 600. For example, the first intermediate signal qgb can present a first logic state corresponding to the power supply voltage VQPS or a second logic state corresponding to the fractional voltage HVDD; the second intermediate signal psvq_i can present a first logic state corresponding to the fractional voltage HVDD or a second logic state corresponding to the fractional voltage LVDD. Similar to ( Figure 6The power switch control circuit P1 and the power switch control circuit P2 of the control circuit 600 can generate a third intermediate signal PV, whose opposite logic states correspond to the fractional voltage LVDD and the ground voltage, respectively. In other words, the first intermediate signal qgb can be converted from HVDD (e.g., 1.2V) to VQPS (e.g., 1.8V) in the first voltage domain; the second intermediate signal psvq_i can be converted from LVDD (e.g., 0.6V) to HVDD (e.g., 1.2V) in the second voltage domain; and the third intermediate signal PV can be converted from ground (e.g., 0V) to LVDD (e.g., 0.6V) in the third voltage domain.

[0079] The first inverter I10 - I13 , the second inverter I14 - I17 , and the third inverter I18 - I20 respectively input the first, second, and third intermediate signals qgb, psvq_i, and PV to jointly determine a voltage level VDDQ at the output node N11 . For example, in order to output the signal VDDQ at 1.8V (VQPS), the level shifter L1 provides the intermediate signal qgb of logic low (e.g., 1.2V), the level shifter L2 provides the intermediate signal psvq_i of logic low (e.g., 0.6V), and the power switch control circuit P2 provides the intermediate signal PV of logic high (e.g., 0.6V), the intermediate signals qg2b_i and qg2b_ii can be output as logic low by the first inverter I10-I13 and the second inverter I14-I17, respectively, which turns on the PMOS transistor M20 (the PMOS transistor M21 is turned on), turns on the PMOS transistor M22 and turns off the NMOS transistor M23 (the NMOS transistor M24 is turned off). The intermediate signal pstb1 can be output as logic low by the third inverter I18-20, which turns off the NMOS transistor M25. Therefore, the intermediate signals qg2b_i and qg2b_id can be output as logic low by the first inverter I10-I13 and the second inverter I14-I17, respectively, which turns on the PMOS transistor M20 (the PMOS transistor M21 is turned on), turns on the NMOS transistor M22 and turns off the NMOS transistor M23 (the NMOS transistor M24 is turned off). The intermediate signal pstb1 can be output as logic low by the third inverter I18-20, which turns off the NMOS transistor M25. Therefore, the supply voltage VQPS (e.g., 1.8V) can be passed to the node N11 as the output signal VDDQ through the turned-on transistors M20, M21, and M22, while keeping the node N11 decoupled from the ground through the turned-off transistors M23, M24, and M25.

[0080] On the other hand, in order to output the signal VDDQ of 0V (ground), the level shifter L1 provides the intermediate signal qgb of logic high (e.g., 1.8V), the level shifter L2 provides the intermediate signal psvq_i of logic high (e.g., 1.2V), and the power switch control circuit P2 provides the intermediate signal PV of logic low (e.g., 0V). Therefore, the intermediate signals qg2b_i and qg2b_ii can be output as logic high by the first inverter I10-I13 and the second inverter I14-I17, respectively, which turns off the PMOS transistor M20, turns off the NMOS transistor M22, and turns on the NMOS transistor M23. The intermediate signal pstb1 can be output as a logic high level by the third inverter I18-20, thereby turning on the NMOS transistor M25. Therefore, the output signal VDDQ may be coupled to the ground voltage through the turned-on transistors M23 , M24 , and M25 , while keeping the node N11 decoupled from the power supply voltage VQPS through the turned-off transistors M20 , M21 , and M22 .

[0081] Figure 8 It shows that according to some embodiments of the present disclosure, Figure 1 An example circuit diagram of a power switch (three-stack design) implemented by the control circuit 110 of FIG. 800 is similar to the control circuit 700 ( Figure 7 ), the difference is that even though there are two voltage generators, the control circuit 800 can also have one level shifter. Therefore, the control circuit 800 can also convert the input voltage to a relatively wide voltage domain (compared with the control circuit 600), or each transistor of the control circuit 800 can operate under a lower voltage stress (compared with the control circuit 600). Therefore, the following discussion of the control circuit 800 will focus on the differences. Figure 8 In the embodiment of the present invention, stacking transistors reduces the VQPS stress on each individual transistor within the power switch (eg, 1 / 3 the VQPS stress).

[0082] For example, the control circuit 800 may include first and second fractional voltage generators G1 and G2, a voltage level shifter L1, a power switch control circuit P2, a first group of inverters I10, I11, I12 and I13 coupled in series, and a second group of inverters I18, I19 and I20 coupled in series. The voltage generators G1 and G2 may provide a first fractional voltage HVDD and a second fractional voltage LVDD, respectively. In some embodiments, the supply voltage VQPS (received by the control circuit 800) may be approximately 1.8V, while the fractional voltage HVDD is approximately two-thirds of VQPS, i.e., approximately 1.2V, and the fractional voltage LVDD is approximately one-third of VQPS, i.e., approximately 0.6V. HVDD and LVDD may power the level shifters L1 and L2, respectively.

[0083] Based on ( Figure 6 Similar to the operation principle discussed above for the level shifter C1 of the control circuit 600, the level shifter L1 can generate a first intermediate signal qgb based on the fractional voltage HVDD. For example, the first intermediate signal qgb can present a first logic state corresponding to the power supply voltage VQPS or a second logic state corresponding to the fractional voltage HVDD. Figure 6 The power switch control circuit P1 and the power switch control circuit P2 of the control circuit 600 can generate a second intermediate signal PV, whose opposite logic states correspond to the fractional voltage LVDD and the ground voltage, respectively. In other words, the first intermediate signal qgb can be converted from HVDD (e.g., 1.2V) to VQPS (e.g., 1.8V) in the first voltage domain; and the second intermediate signal PV can be converted from ground (e.g., 0V) to LVDD (e.g., 0.6V) in the second voltage domain.

[0084] The first inverter I10-I13 and the second inverter I18-I20 input the first and second intermediate signals qgb and PV, respectively, to jointly determine the voltage level VDDQ at the output node N11. For example, in order to output the signal VDDQ at 1.8V (VQPS), the level shifter L1 provides the intermediate signal qgb of logic low (e.g., 1.2V), and the power switch control circuit P2 provides the intermediate signal PV of logic high (e.g., 0.6V). Therefore, the intermediate signal qg2b_i can be output as a logic low by the first inverter I10-I13, which turns on the PMOS transistor M20 (wherein the PMOS transistor M21 is turned on). The intermediate signal pstb1 can be output as a logic low by the third inverter I18-20, which turns off the NMOS transistor M25. Therefore, the supply voltage VQPS (eg, 1.8V) may be delivered to the node N11 as the output signal VDDQ through the turned-on transistors M20 and M21 , while the node N11 is kept decoupled from the ground by the turned-off transistor M25 .

[0085] On the other hand, in order to output the signal VDDQ of 0V (ground), the level shifter L1 provides the intermediate signal qgb of logic high (e.g., 1.8V), and the power switch control circuit P2 provides the intermediate signal PV of logic low (e.g., 0V). Therefore, the intermediate signal qg2b_i can be output as a logic high by the first inverter I10-I13, thereby turning off the PMOS transistor M20. The intermediate signal pstb1 can be output as a logic high by the third inverter I18-20, thereby turning on the NMOS transistor M25. Therefore, the output signal VDDQ can be coupled to the ground voltage through the turned-on transistors M22 and M25, while keeping the node N11 decoupled from the power supply voltage VQPS through the turned-off transistor M20.

[0086] Fig. 9It shows that according to some embodiments of the present disclosure, Figure 1 The control circuit 900 is similar to the control circuit 700 ( Figure 7 ), in addition to the control circuit 900, the control circuit 900 may also include a voltage detector. Therefore, the control circuit 900 may also convert the input voltage to a relatively wider voltage domain (compared with the control circuit 600), or each transistor of the control circuit 900 may operate under a lower voltage stress (compared with the control circuit 600). Therefore, the following discussion of the control circuit 900 will focus on the differences. Fig. 9 In the embodiment of the present invention, stacking transistors reduces the VQPS stress on each individual transistor within the power switch (eg, 1 / 3 the VQPS stress).

[0087] In various embodiments, the control circuit 900 may include a voltage detector VD1 configured to detect whether a relatively low logic voltage VDD driving a control signal (e.g., YSELB, YSELB', PS, PD, etc.) is ready or stable compared to a supply voltage VQPS. For example, if VDD is not ready while the supply voltage VQPS is provided, the voltage detector VD1 may force the output signal VDDQ to be pulled to ground. In some embodiments, the voltage detector VD1 is substantially composed of a plurality of inverters having relatively weak PMOS transistors, and may output another intermediate signal Vx based on comparing the voltage level of the logic voltage VDD with the voltage level of the supply voltage VQPS. In response to determining that VDD is not ready, the voltage detector VD1 outputs a logic high intermediate signal Vx. Therefore, regardless of whether the intermediate signal PV is output as a logic high or low, the inverter I18 may receive a logic low, which is pulled to a ground voltage by the NMOS transistor M30 turned on by the high Vx. Therefore, the intermediate signal pstb1 may be output at a logic high level, which turns on the NMOS transistor M25 to pull the output signal VDDQ to ground.

[0088] Fig.10 It shows that according to some embodiments of the present disclosure, Figure 1 1000 is similar to control circuit 700 ( FIG. 1001 ), except for N voltage generators and N level shifters. Figure 7 ). The control circuit 1000 may include N voltage generators, N level shifters, and a power switch control. By using N voltage generators and N level shifters, the control circuit 1000 reduces the VQPS stress on each individual transistor within the power switch (eg, 1 / N VQPS stressors).

[0089] Fig.11 It shows that according to some embodiments of the present disclosure, Figure 1 The control circuit 1100 is similar to the control circuit 110 ( Figure 1 ), except for stacked circuits in the sense amplifier, stacked circuits in the bias, and stacked circuits in the bit cells. For example, two stacked circuits may be used to implement the sense amplifier. To prevent leakage, VDDHD may not be equal to 0. In this configuration, multiple bit line (xBL) bit cell circuits may be connected in series within each bit cell circuit. There may be multiple word line (xWL) bit cells also connected in series. In various embodiments, this fractional voltage may allow Fig.11 Each transistor in the MCU operates at a relatively low voltage stress, for example, below 0.96 V. Therefore, each transistor, whether implemented as NMOS or PMOS, can be implemented as a core device with a relatively thin gate dielectric while not being affected by high voltage stress.

[0090] Fig.12 It shows that according to some embodiments of the present disclosure, Figure 1 1 . An example circuit diagram of a half-power switch 318 implemented by the control circuit 110 of FIG. 1 . The half-power switch 318 may include multiple circuits (e.g., circuits 1 to 5). The half-power switch 318 may be responsible for generating a first gate control signal NCGATE 350 and a second gate control signal PCGATE 352, which are used in both read and program modes. Circuit 1 may be designed as a control circuit responsible for managing a PSB signal, which is used as an input signal for circuits 2, 3, 4, and 5. In some embodiments, circuit 2 may be used as a level shifter, such as converting a signal from PSB to HPS and from PS1 to HPSB.

[0091] In various embodiments, circuits 3-1 and 3-2 can be used as half-power switches. Circuit 3 can be configured to generate a voltage for a first gate control signal NCGATE based on a programming or read mode. Circuit 3 can receive a supply voltage VDDHD and a supply voltage Half_VQPS. For example, the supply voltage Half_VQPS can be set to approximately 0.9V and the supply voltage VDDHD can be configured to approximately 0.75V. During the read mode (e.g., PS=L), the first gate control signal NCGATE 350 can be adjusted to approximately 0.75V. During the programming / write mode (e.g., PS=H), the first control signal NCGATE 350 can be set to approximately 0.9V. In some embodiments, NCGATE_B 1202 in circuit 3-2 can be used as a power switch. When Half_VQPS is 0 or floating, NCGATE_B 1202 can help prevent forward bias in certain modes.

[0092] In some embodiments, circuit 4 can be configured to generate a voltage for a second gate control signal PCGATE based on a programming or read mode. Circuit 4 can receive a supply voltage Half_VQPS that can be set to about 0.9V. During read mode (e.g., PS=L), the second control signal PCGATE 352 can be set to about 0V. During programming / write mode (e.g., PS=H), the second gate control signal PCGATE 352 can be set to about 0.9V. In some embodiments, circuit 5 can be used as a power switch. Circuit 5 can receive a supply voltage VDDQ and can generate a supply voltage VDDG. The supply voltage VDDG is then provided to a BL level shifter. In the BL level shifter, the supply voltage VDDG can be used to shut down / disable the VDD domain. The supply voltage VDDG can be equal to the supply voltage VDDQ or can be set to 0V.

[0093] Fig.13 It shows that according to some embodiments of the present disclosure, Figure 1 In addition to the delay circuit 1302, Fig.13 The BL transmission gate 306 and Figure 3 The BL transmission gate 306 of FIG. 1 is substantially similar. Therefore, the following discussion of the BL transmission gate 306 will focus on the differences. Without the delay circuit 1302, the Ifuse operation may cause a peak current in the EFCELL 312. To alleviate this problem, the delay circuit 1302 is designed to introduce a delay in the memory circuit 100 to prevent current surges within the overflow circuit. Through the implementation of the delay circuit 1302, the smaller circuit (e.g., x10) 1302 is activated before the main circuit (e.g., the larger circuit x100) of the BL transmission gate 306. The waveforms of the signals, including the voltage levels of Ifuse and Igate, illustrate how this approach effectively reduces the risk of misprogramming.

[0094] Fig.14 It shows that according to some embodiments of the present disclosure, Figure 11. An example circuit diagram of a bit line (BL) level shifter 308 implemented by the control circuit 110 of FIG. 1. The BL level shifter 308 may include a plurality of p-type transistors electrically stacked relative to each other. The BL level shifter 308 may receive a supply voltage VDDHD (e.g., approximately 0.75V) and a supply voltage VDDQ (e.g., approximately 1.8V). In some embodiments, the BL level shifter 308 may be configured to shift the voltage for the BL control circuit 306 from a first voltage domain (e.g., approximately 0 to 0.75V) to a second voltage domain (e.g., approximately 0.9 to 1.8V). The first voltage domain may range from a third supply voltage (e.g., approximately 0V) to a second supply voltage (e.g., approximately 0.75V). The second voltage domain may range from a first fraction of the first supply voltage (e.g., approximately 0.9V) to the first supply voltage (e.g., approximately 1.8V).

[0095] In some embodiments, the BL level shifter 308 can obtain the supply voltage VDDG from the half power switch 318. The VDDG voltage can be configured to shift the voltage domain to a first voltage domain, typically in the range of about 0 to 0.75V, or to a second voltage domain, typically in the range of about 0.9 to 1.8V. The supply voltage VDDG has the ability to disable or shut down the VDD domain. The supply voltage VDDG can be equal to the supply voltage VDDQ, or it can be set to 0V. For example, when the VDDG supply voltage is set to 1.8V, it will cause the VDDHD domain to be disabled.

[0096] Fig.15 An example circuit simulation of the memory circuit 100 according to some embodiments of the present disclosure is shown. Fig.15 The waveforms of signals (e.g., voltage levels) over time are shown. Fig.15 , a control signal PS and an output signal VDDQ are shown. Each signal is a pulse signal that switches between a low logic state (corresponding to the lower limit of the corresponding voltage domain) and a high logic state (corresponding to the upper limit of the corresponding voltage domain). Specifically, PS can each switch between a logic low (e.g., about 0V) and a logic high (e.g., about 0.75V), and VDDQ can switch between a logic low and a logic high. As a non-limiting example, when PS is high, the output signal VDDQ can be equal to about 1.8V (VQPS); and when PS is low, the output signal VDDQ can be equal to about 0V (ground). The VDDQ signal can remain stable even if the PS signal changes.

[0097] Fig.16 1 shows an example circuit diagram of another voltage level shifter C2 according to various embodiments. The voltage level shifter C2 is similar to the voltage level shifter C1 ( Figure 6), where some connections between NMOS transistors M9 and M10 are changed. Therefore, the following discussion will focus on the differences. Fig.16 As shown, the gate of the NMOS transistor M10 is connected to the gate of the PMOS transistor M8, rather than being connected to the source of the PMOS transistor M8 ( Figure 6 ). Similarly, the gate of the NMOS transistor M9 is connected to the gate of the PMOS transistor M7, rather than being connected to the source of the PMOS transistor M7 ( Figure 6 ). In this case, the gate of the NMOS transistor M9 and the gate of the NMOS transistor M10 can have a better gate bias.

[0098] Fig.17 An example circuit diagram of the voltage generator 316 is shown, which may be the MVDD generator 316 ( Figure 3 ) is one of various implementations of ). The MVDD generator 316 may generate a fractional voltage (eg, MVDD) based on a supply voltage (eg, VQPS) and a ground voltage (eg, VSS).

[0099] like Fig.17 As shown, the MVDD generator 316 may include a first part V1, a second part V2, and a third part V3. The first part V1 may be used as a power divider, the second part V2 may be used as a push / pull driver, and the third part V3 may be configured to stabilize the output, i.e., the fractional voltage MVDD. In some embodiments, the first part V1 may include two groups of resistors R1 and R2, a plurality of NMOS transistors, and a plurality of PMOS transistors, which are configured to jointly generate a bias voltage; the second part V2 includes a plurality of NMOS transistors and a plurality of PMOS transistors, which are configured to jointly pull or push the output; the third part V3 includes a plurality of MOS capacitors, which are configured to jointly stabilize the output. In some other embodiments, each resistor may be implemented as a MOS diode while still being within the scope of the present disclosure. Typically, the fractional voltage MVDD is equal to the ratio of the first group of resistors R1 to the second group of resistors R2 multiplied by the supply voltage VQPS:

[0100] MVDD=N×VQPS

[0101] The coefficient N is defined as:

[0102] R2 / (R1+R2)

[0103] For example, when R1 / R2 is equal to 1, N is equal to 1 / 2. Therefore, MVDD is equal to 1 / 2×VQPS. In another example, when R1 / R2 is equal to 1 / 2, N is equal to 2 / 3. Therefore, MVDD is equal to 2 / 3×VQPS. When R1 / R2 is equal to 2, N is equal to 1 / 3. Therefore, MVDD is equal to 1 / 3×VQPS.

[0104] Fig.18 It shows that some embodiments of the present disclosure can be Figure 1 In addition to the MP / MN bias voltage, Fig.18 The MVDD generator 316 is used with Fig.17 The MVDD generator 316 is substantially similar. The MP bias can be connected to net_p. The MN bias can be connected to net_n. The MP / MN bias can be used as the low voltage power supply MVDD generator bias. Therefore, MVDD is equal to 1 / 2×VQPS.

[0105] Fig.19 It shows that according to some embodiments of the present disclosure, Figure 1 FIG. 1 is an example circuit diagram of an MVDD generator 316 implemented by the control circuit 110 . Fig.19 An example circuit diagram of the MVDD generator 316 is shown, which may be one of various implementations of a combination of voltage generators G1 and G2 ( Figure 7 , Figure 8 and Fig. 9 ). The MVDD generator 316 can generate a plurality of fractional voltages (eg, HVDD and LVDD) based on a supply voltage (eg, VQPS) and a ground voltage (eg, VSS). Fig.17 , and therefore, the following discussion of the MVDD generator 316 will focus on the differences.

[0106] like Fig.19 As shown, the MVDD generator 316 includes a combination of two voltage generators 1910 and 1950, each of which is similar to Fig.17MVDD generator 316 in (e.g., including three parts operably coupled to each other). For example, voltage generator 1910 can provide a first fractional voltage HVDD based on a ratio of a first group of resistors R1 to a second group of resistors R2 multiplied by a supply voltage VQPS; and voltage generator 1950 can provide a second fractional voltage LVDD based on a ratio of a first group of resistors R1' to a second group of resistors R2' multiplied by a supply voltage VQPS. As a non-limiting example, the ratio of R1 to R1+R2 (22 to 60) can be approximately 0.36, and the ratio of R2 to R1+R2 (38 to 60) can be approximately 0.63, which results in outputs HVDD and LVDD of approximately 0.6V and 1.2V, respectively (when VQPS=1.8V). In addition, the MVDD generator 316 may include a voltage divider that is also coupled between the supply voltage VQPS and the ground voltage to provide reference voltages Vref_H and Vref_L to the voltage generators 1910 and 1950, respectively. In some embodiments, the voltage divider may include three sets of resistors R3, R4, and R5. Continuing with the above example, the ratio of the three sets of resistors R3, R4, and R5 may be 11:8:11.

[0107] Fig. 20 FIG. 2 is a flowchart of an example method 2000 for operating a memory circuit having stacked circuits according to some embodiments of the present disclosure. It should be noted that the method 2000 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 2000 may be used in the embodiment of the present disclosure. Fig. 20 Any additional operations are provided during, before, and after the method 2000, and some other operations may only be briefly described herein. The method 2000 may be used to operate the control circuit 110, and therefore, will be combined with Figure 1-Figure 19 The operations of method 2000 are discussed with reference to the components discussed in .

[0108] Briefly, method 2000 begins with operation 2002 of receiving a first supply voltage and a second supply voltage. Method 2000 continues to optional operation 2004 of providing a first gate control signal to a plurality of first transistors of a memory circuit based on the first supply voltage and the second supply voltage, and providing a second gate control signal to a plurality of second transistors in the memory circuit. Method 2000 continues to operation 2006 of configuring the first gate control signal to be equal to a fraction of the first supply voltage and configuring the second control signal to be equal to a fraction of the first supply voltage when writing to a memory cell of the memory circuit. Method 2000 continues to operation 2008 of configuring the first gate control signal to be equal to a fraction of the first supply voltage and configuring the second control signal to be equal to a third supply voltage that is lower than either the first or second supply voltages when reading a memory cell of the memory circuit. In various embodiments, the first supply voltage is substantially higher than twice the second supply voltage.

[0109] Corresponds to Fig. 20 At operation 2002, the memory circuit 100 may receive a first supply voltage 360 ​​and a second supply voltage 362. For example, at Figure 3 In the embodiment, the power management circuit 112 can receive a power supply voltage VQPS and a power supply voltage VDD. The power supply voltage VQPS is substantially higher than twice the power supply voltage VDD. For example, the power supply voltage VQPS can be equal to about 1.8V, and the power supply voltage VDD can be equal to about 0.75V.

[0110] Corresponds to Fig. 20 In optional operation 2004, a first gate control signal may be provided to a plurality of first transistors in the memory circuit based on the first power supply voltage and the second power supply voltage, and a second gate control signal may be provided to a plurality of second transistors in the memory circuit. Figure 3 In the embodiment, the power management circuit 112 can provide a first gate control signal NCGATE 350 and a second gate control signal PCGATE 352 based on the supply voltage VQPS and the supply voltage VDD. The first gate control signal NCGATE 350 can be configured to control a plurality of first transistors (e.g., BL select 306) of the memory circuit 100. The second gate control signal PCGATE 352 can be configured to control a plurality of second transistors (e.g., WL select 312) of the memory circuit 100.

[0111] Corresponds to Fig. 20 In operation 2006, when writing / programming the memory cell 103 of the memory circuit 100, the first gate control signal may be configured to be equal to a fraction of the first supply voltage, and the second control signal may be configured to be equal to a fraction of the first supply voltage. Figure 3 In the embodiment, the first gate control signal NCGATE 350 can be configured to be equal to about 0.9V, which is about 1 / 2 of the supply voltage VQPS (e.g., about 1.8V). The second control signal PCGATE 352 can be configured to be equal to about 0.9V, which is about 1 / 2 of the supply voltage VQPS (e.g., about 1.8V). In various embodiments, this half of the fractional voltage VQPS can allow Figure 1 , Figure 3 and Figure 5 Each transistor in the FET operates at a relatively low voltage stress, for example, at 0.96 V. Therefore, each transistor, whether implemented as NMOS or PMOS, can be implemented as a core device with a relatively thin gate dielectric while not being affected by high voltage stress.

[0112] Corresponds to Fig. 20In operation 2006, when reading the memory cell 103 of the storage circuit 100, the first gate control signal may be configured to be equal to a fraction of the first supply voltage, and the second control signal may be configured to be equal to a third supply voltage lower than either the first or second supply voltage. Figure 4 In the embodiment, the first gate control signal NCGATE 350 can be configured to be equal to about 0.75V, which is about a fraction of the supply voltage VQPS (e.g., about 1.8V). The second control signal PCGATE 352 can be configured to be equal to about 0V, which is lower than either the first or second supply voltage. In various embodiments, such a fractional voltage can allow Figure 1 and Figure 4 Each transistor in the FET operates at a relatively low voltage stress, for example, at 0.96 V. Therefore, each transistor, whether implemented as NMOS or PMOS, can be implemented as a core device with a relatively thin gate dielectric while not being affected by high voltage stress.

[0113] In some embodiments, the core device of the present disclosure involves utilizing a nanosheet (GAA) process, which provides several benefits. The present disclosure effectively solves the challenges associated with gate oxide thickness control in GAA, mainly due to the absence of IO devices in the process. Stacked structures have become critical in memory design to alleviate leakage issues, which are exacerbated by the GAA process. In addition, the core device of the present disclosure is suitable for high-voltage and high-current applications that require stacked designs, including components such as eFuse, antifuse, MRAM, and RRAM. In addition, the core device of the present invention is versatile and can be applied to a variety of other processes such as FinFET, forked nanosheets, planar devices, and CFET. It also includes a range of transistor functions, including horizontal, vertical, and LDMOS configurations, enabling it to adapt to different technical environments.

[0114] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array comprising a plurality of memory cells; an input / output (I / O) circuit operably coupled to the memory array and configured to read or write each of the memory cells; and a power management circuit operably coupled to the memory array and the I / O circuit and configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage, wherein the first supply voltage is substantially higher than twice the second supply voltage; wherein, when at least one of the memory cells is being written, the first gate control signal is equal to a first fraction of the first supply voltage and the second control signal is equal to a first fraction of the first supply voltage, and wherein, when at least one of the memory cells is being read, the first gate control signal is equal to a first fraction of the second supply voltage and the second control signal is equal to a third supply voltage lower than either the first supply voltage or the second supply voltage.

[0115] In the above-described memory circuit, the memory cells each include an electric fuse memory cell.

[0116] In the above memory circuit, the first fraction is approximately 1 / 2.

[0117] In the above-mentioned memory circuit, the I / O circuit includes: a power switch, including a plurality of first p-type transistors electrically stacked on each other; a bit line control circuit, including a plurality of second p-type transistors electrically stacked on each other; a bit line level shifter, including a plurality of third p-type transistors electrically stacked on each other; a word line level shifter, including a plurality of fourth p-type transistors electrically stacked on each other; and a plurality of sense amplifiers, each sense amplifier including a plurality of first n-type transistors.

[0118] In the above-mentioned memory circuit, each of the memory cells includes a fuse resistor and a plurality of second n-type transistors coupled to each other in series, and wherein the plurality of second n-type transistors are electrically stacked on each other.

[0119] In the above memory circuit, regardless of whether the memory cell is read or written, the voltage between any two terminals of each of the first p-type transistor, the second p-type transistor and the third p-type transistor is equal to or less than the first fraction of the first supply voltage.

[0120] In the above-mentioned memory circuit, the first gate control signal is configured to gate control at least one of the first n-type transistor and the second n-type transistor, and the second gate control signal is configured to gate control at least one first p-type transistor, at least one second p-type transistor and at least one third p-type transistor.

[0121] In the above-mentioned memory circuit, regardless of whether the memory cell is read or written, the voltage between any two terminals of each of the first p-type transistor, the second p-type transistor, the third p-type transistor and the first n-type transistor is equal to or less than a first fraction of the first power supply voltage, and the voltage between any two terminals of each of the n-type transistor and the fourth p-type transistor is equal to or less than a second fraction of the second power supply voltage, and the second fraction is greater than the first fraction.

[0122] In the above-mentioned memory circuit, the first gate control signal is configured to gate control at least one of the first n-type transistor and the second n-type transistor, and the second gate control signal is configured to gate control at least one first p-type transistor, at least one second p-type transistor and at least one third p-type transistor.

[0123] In the above memory circuit, the L level shifter is configured to shift a first voltage domain for the BL control circuit to a second voltage domain, the first voltage domain ranges from the third supply voltage to the second supply voltage, and the second voltage domain ranges from a first fraction of the first supply voltage to the first supply voltage.

[0124] In the above-mentioned memory circuit, the word line level shifter is configured to shift a first voltage domain for the memory cell to a second voltage domain, the first voltage domain ranges from a third supply voltage to a second supply voltage, and the second voltage domain ranges from the third supply voltage to a first fraction of the first supply voltage or to a second fraction of the first supply voltage, and the second fraction is greater than the first fraction.

[0125] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array, comprising a plurality of memory cells coupled to a first supply voltage, each of the plurality of memory cells comprising a fuse resistor coupled in series to a plurality of first transistors; an input / output (I / O) circuit, coupled to a second supply voltage, comprising a plurality of second transistors, and configured to read or write each of the memory cells; and a power management circuit, operably coupled to the first supply voltage and the second supply voltage, comprising a plurality of third transistors, and configured to provide a first gate control signal and a second gate control signal based on the first supply voltage and the second supply voltage, wherein the first supply voltage is substantially higher than twice the second supply voltage; wherein the voltage between any two terminals of each of the first transistor, the second transistor, and the third transistor is equal to or less than a fraction of the first supply voltage.

[0126] In the above memory circuit, the fraction is about 1 / 2.

[0127] In the above memory circuit, the memory cells each comprise a one-time programmable memory cell.

[0128] In the above memory circuit, when writing to at least one of the memory cells, the first gate control signal is equal to a fraction of the first supply voltage, and the second control signal is equal to a fraction of the first supply voltage.

[0129] In the above memory circuit, when reading at least one of the memory cells, the first gate control signal is equal to a fraction of the first supply voltage, and the second control signal is equal to a third supply voltage lower than either the first supply voltage or the second supply voltage.

[0130] In the above-described memory circuit, the plurality of first transistors of each of the memory cells have n-type conductivity and are coupled to each other in series.

[0131] In the above memory circuit, the plurality of second transistors include a plurality of p-type transistor subsets and a plurality of n-type transistor subsets, and wherein each of the p-type transistor subsets are coupled in series with each other, and each of the n-type transistor subsets are coupled in series with each other.

[0132] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: receiving a first power supply voltage and a second power supply voltage, wherein the first power supply voltage is substantially higher than twice the second power supply voltage; based on the first power supply voltage and the second power supply voltage, providing a first gate control signal to a plurality of first transistors of the memory circuit, and providing a second gate control signal to a plurality of second transistors of the memory circuit; when writing to a memory cell of the memory circuit, configuring the first gate control signal to be equal to a fraction of the first power supply voltage, and configuring the second gate control signal to be equal to a fraction of the first power supply voltage; and when reading a memory cell of the memory circuit, configuring the first gate control signal to be equal to a fraction of the first power supply voltage, and configuring the second gate control signal to be equal to a third power supply voltage lower than either the first power supply voltage or the second power supply voltage.

[0133] In the above method, the fraction is about 1 / 2.

[0134] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0135] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory circuit, comprising: a memory array comprising a plurality of memory cells; an input / output circuit operatively coupled to the memory array and configured to read or write to each of the memory cells; as well as a power management circuit operatively coupled to the memory array and the input / output circuit and configured to provide a first gate control signal and a second gate control signal based on a received first supply voltage and a received second supply voltage, wherein the first supply voltage is substantially higher than twice the second supply voltage; wherein, when at least one of the memory cells is being written, the first gate control signal is equal to a first fraction of a first supply voltage and the second control signal is equal to a first fraction of the first supply voltage, and wherein, when at least one of the memory cells is being read, the first gate control signal is equal to a first fraction of the second supply voltage and the second control signal is equal to a third supply voltage lower than either the first supply voltage or the second supply voltage.

2. The memory circuit according to claim 1, wherein: The memory cells each comprise an electrical fuse memory cell.

3. The memory circuit according to claim 1, wherein: The input / output circuit comprises: a power switch including a plurality of first p-type transistors electrically stacked on each other; A bit line control circuit including a plurality of second p-type transistors electrically stacked on each other; a bit line level shifter including a plurality of third p-type transistors electrically stacked on each other; a word line level shifter including a plurality of fourth p-type transistors electrically stacked on each other; and A plurality of sense amplifiers are provided, each sense amplifier comprising a plurality of first n-type transistors.

4. The memory circuit according to claim 3, wherein: Each of the memory cells includes a fuse resistor and a plurality of second n-type transistors coupled to each other in series, and wherein the plurality of second n-type transistors are electrically stacked on each other.

5. The memory circuit according to claim 4, wherein: Regardless of whether the memory cell is being read or written, a voltage between any two terminals of each of the first, second, and third p-type transistors is equal to or less than the first fraction of the first supply voltage.

6. The memory circuit according to claim 4, wherein: Regardless of whether the memory cell is being read or written, a voltage between any two terminals of each of the first p-type transistor, the second p-type transistor, the third p-type transistor, and the first n-type transistor is equal to or less than a first fraction of the first supply voltage, and a voltage between any two terminals of each of the n-type transistor and the fourth p-type transistor is equal to or less than a second fraction of the second supply voltage, and wherein the second fraction is greater than the first fraction.

7. The memory circuit according to claim 3, wherein: The bit line level shifter is configured to shift a first voltage domain for the bit line control circuit to a second voltage domain, the first voltage domain ranging from the third supply voltage to the second supply voltage, and the second voltage domain ranging from a first fraction of the first supply voltage to the first supply voltage.

8. A memory circuit comprising: a memory array comprising a plurality of memory cells coupled to a first supply voltage, each of the plurality of memory cells comprising a fuse resistor coupled in series to a plurality of first transistors; an input / output circuit coupled to a second supply voltage, including a plurality of second transistors, and configured to read or write each of the memory cells; as well as a power management circuit operatively coupled to the first supply voltage and the second supply voltage, comprising a plurality of third transistors, and configured to provide a first gate control signal and a second gate control signal based on the first supply voltage and the second supply voltage, wherein the first supply voltage is substantially higher than twice the second supply voltage; The voltage between any two terminals of each of the first transistor, the second transistor and the third transistor is equal to or less than a fraction of the first supply voltage.

9. The memory circuit according to claim 8, wherein: When writing to at least one of the memory cells, the first gate control signal is equal to the fraction of the first supply voltage, and the second control signal is equal to the fraction of the first supply voltage.

10. A method for operating a memory circuit, comprising: receiving a first supply voltage and a second supply voltage, wherein the first supply voltage is substantially higher than twice the second supply voltage; Based on the first power supply voltage and the second power supply voltage, providing a first gate control signal to a plurality of first transistors of a memory circuit, and providing a second gate control signal to a plurality of second transistors of the memory circuit; When writing to a memory cell of the memory circuit, configuring the first gate control signal to be equal to a fraction of the first supply voltage and configuring the second gate control signal to be equal to the fraction of the first supply voltage; and When reading the memory cell of the memory circuit, the first gate control signal is configured to be equal to the fraction of the first supply voltage, and the second gate control signal is configured to be equal to a third supply voltage lower than either the first supply voltage or the second supply voltage.

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