Three-way hole chain for advanced interconnects in memory devices

Abstract

The invention relates to a three-way via chain for advanced interconnects in memory devices. A memory device can include a first portion having a memory array including a plurality of memory cells and a first via segment for performing a test operation. The memory device can include a second portion including processing circuitry and a second via segment for performing a test operation. The memory device can also include an interconnect coupling the first portion and the second portion, the interconnect including a third via segment, where the first via segment, the second via segment, and the third via segment can be independently selected.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to a three-via chain for advanced interconnect implementations in memory devices of a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, nonvolatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present application provides a memory device comprising: a first portion comprising a memory array including a plurality of memory cells and a first via segment for performing a test operation; a second portion comprising a processing circuit system and a second via segment for performing the test operation; and an interconnect coupling the first portion and the second portion, the interconnect comprising a third via segment, wherein the first via segment, the second via segment, and the third via segment can be independently selected.

[0004] In another aspect, the present application provides a method comprising: selecting a first via segment of one or more via segments of the memory device for a test operation at a first portion of the memory device, wherein the one or more via segments include a second via segment at a second portion of the memory device and a third via segment at a third portion of the memory device; testing the first portion of the memory device in response to selecting the first via segment; and determining one or more errors associated with the first portion of the memory device in response to testing the first portion of the memory device.

[0005] In yet another aspect, the present application provides a memory device comprising: a memory array comprising memory cells; and control logic coupled to the memory array, the control logic being used to: select a first via segment of one or more via segments of the memory device for a test operation at a first portion of the memory device, wherein the one or more via segments include a second via segment at a second portion of the memory device and a third via segment at a third portion of the memory device; test the first portion of the memory device in response to selecting the first via segment; and determine one or more errors associated with the first portion of the memory device in response to testing the first portion of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be understood as limiting the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1A An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 1B is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 2 Some embodiments of the present invention may be used for reference. Figure 1B A schematic diagram of a portion of a memory cell array depicting a type of memory.

[0010] Figure 3 is a diagram illustrating a three-through hole chain according to some embodiments of the present disclosure.

[0011] Figure 4 is a diagram illustrating via chain measurement according to some embodiments of the present disclosure.

[0012] Figure 5 is a flow chart of an example method of utilizing a three-via chain of advanced interconnects according to some embodiments of the present disclosure.

[0013] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to a three-via chain for advanced interconnect implementations. For example, a memory subsystem may include three independent via chains for testing an advanced interconnect system. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1A Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device, that stores data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may include a high-density non-volatile memory device, where it is desirable to retain data when no power is supplied to the memory device. For example, NAND memory (e.g., 3D flash NAND memory) provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die comprising one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane comprises a set of physical blocks. Each block comprises a set of pages. Each page comprises a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states related to the number of bits stored. The logical state may be represented by a binary value such as "0" and "1" or a combination of such values.

[0016] A memory device may consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells of a memory device used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. A block refers to a unit of a memory device for storing data hereinafter and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a separate partition (e.g., a plane) of a memory device in order to allow concurrent operations on each plane. Each data block may include several sub-blocks, wherein each sub-block is defined by an associated column (e.g., a vertical conductive trace) extending from a shared bit line. A memory page (also referred to herein as a "page") stores one or more binary data bits corresponding to data received from a host system. In order to achieve high density, a string of memory cells in a non-volatile memory device may be constructed to include several memory cells that at least partially surround a column of channel material. The memory cells may be coupled to access lines, often referred to as "word lines," that are often fabricated together with the memory cells to form a string array in a memory block. The compact nature of certain non-volatile memory devices, such as 3D flash NAND memory, means that the word lines are common to many memory cells within a memory block.

[0017] As described above, memory cells may be formed on a silicon wafer with an array of bit lines and word lines. In some examples, an array of memory devices (e.g., an array chip or integrated circuit that can store data) may be coupled to a processing circuit system (e.g., to a complementary metal oxide semiconductor (CMOS) component). The processing circuit system may be on a separate chip (e.g., on a second integrated circuit). Therefore, the memory device may include an interconnect (e.g., an advanced interconnect) to couple the memory array portion with the processing circuit system. As manufacturing technology improves, advanced interconnects may present additional processing challenges and stresses. For example, as memory devices become smaller and store more data, interconnects may become more compact, resulting in performance degradation. Smaller interconnects may also result in an increase in resistance-capacitance delays. In addition, improved manufacturing technology may result in thinner silicon, which is more susceptible to cracking and results in additional edge stresses (e.g., bending, expansion, or contraction). Therefore, performing quality checks and verifying manufacturing processes may be critical to ensuring that memory cells can reliably store data.

[0018] Some solutions may perform quality checks by including electrical connections between layers in a board, for example, vertical electrical connections (vias) through copper layers in a printed circuit board (PCB). Vias may be connected together to form a via chain that enables signals to be transmitted from one end of the via chain to the other. This may enable the system to perform quality checks by forcing a current or voltage on one terminal and grounding the other terminal and measuring the voltage or current, respectively. For example, the system may determine a high voltage measurement or a zero (0) current measurement, respectively, which may indicate the presence of a crack, misalignment, or disconnection in the memory device. In other examples, the test may include forcing a voltage on one terminal and floating the other terminal to measure the current. In such examples, the system may determine a non-zero measurement of the current, which indicates that there is some error that causes the via chain to short. The solution may include one via chain around each edge of the memory die. These solutions may allow a via chain from the bottom of a first chip (e.g., at the bottom of a CMOS chip or a memory array chip) up to the top of a second chip (e.g., at the top of the other of the CMOS chip or the memory array chip) - for example, the via chain may pass through the first chip, through the interconnect, up to the top of the second chip. The via chain may then continue from the top of the second chip back down to the bottom of the first chip. However, having a single via chain that passes up and down through all chips and interconnects may result in a large portion of the top or bottom chip not being tested - for example, a large portion of the upper portion or the bottom portion may not include a via chain and not be tested because the via chain is instead in another chip. As a result, it may be difficult to accurately detect cracks, misalignments, breaks, or other potential errors in the manufacturing process.

[0019] Aspects of the present disclosure address the above and other deficiencies by using a triple via chain (e.g., referring to a combination of via chains included in each of the three layers of a memory device) for advanced interconnect implementations in a memory device—e.g., there may be three via chain segments (triple via chains), one in each layer of the memory device. For example, a memory device may include a separate via chain for each chip and / or interconnect—e.g., a memory device may include a top chip, a bottom chip, and via chains in an interconnect layer. In one example, each via chain may run from the bottom of a chip or interconnect to the top of the chip of the chip or interconnect, and then connect back down to the bottom of the chip or interconnect. Thus, each chip or interconnect may include additional vias, thereby enabling more accurate manufacturing testing. By utilizing previously determined programming voltages for the segments, a non-volatile memory device may more accurately determine cracks, disconnects, misalignments, and edge stresses in array chips, CMOS chips, and interconnects.

[0020] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or a combination thereof.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1AAn example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0024] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0025] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices such as memory device 140 may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices, such as memory device 130, include non-and (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes in conjunction with a stackable cross-grid data access array. Furthermore, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0029] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) have been described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, extracted data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0033] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, the memory device 130 may represent a single die with some control logic (e.g., the local media controller 135) embodied thereon. In some embodiments, one or more components of the memory subsystem 110 may be omitted.

[0036] In at least one embodiment, the memory device 130 may include a three-via chain component 113. In at least one embodiment, the three-via chain component 113 is used to test the interconnect layers of the memory subsystem 110 or the corresponding memory device 130. In at least one embodiment, as described above, the memory subsystem 110 or the memory device 130 may include an array 104 coupled to a processing circuit system (e.g., to a complementary metal oxide semiconductor (CMOS) component) via a high-level interconnect. In at least one embodiment, each layer (e.g., the array 104, the CMOS circuit system, and the interconnect) may include an independent via chain segment, as described in reference to Figure 3 Thus, memory device 130 can independently test array 104, CMOS circuitry, and interconnects. In some embodiments, testing can include measuring voltage or current across via segments to determine if there are cracks, misalignments, or breaks within array 104, CMOS circuitry, or interconnects.

[0037] In some embodiments, the memory subsystem controller 115 includes at least a portion of the three-via chain component 113 - for example, some circuitry for testing the via chain segments. In other embodiments, the local media controller 135 includes at least a portion of the three-via chain component 113 and is configured to perform the functionality described herein. In this embodiment, the three-via chain component 113 can be implemented using hardware or as firmware, stored on the memory device 130, and executed by the control logic (e.g., the local media controller 135) to perform operations related to the programming operations described herein.

[0038] Figure 1B is in accordance with an embodiment and presents a memory subsystem (eg, Figure 1A 1 is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 of a memory subsystem 110 of the present invention. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device. The local media controller 135 may include a three-via chain component 113.

[0039] Memory device 130 includes a memory cell array 104 that is logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1B In one embodiment, memory cell array 104 (i.e., "memory array") may include several sacrificial memory cells for detecting the occurrence of read disturbance in memory device 130, as described in detail herein.

[0040] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 160 for managing the input of commands, addresses, and data to memory device 130 and the output of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 160 and row decoding circuitry 108 and column decoding circuitry 109 to latch address signals prior to decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0041] A controller, such as a local media controller 135 inside the memory device 130, controls access to the memory cell array 104 in response to commands and generates status information for the external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local media controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 109 to control the row decoding circuitry 108 and the column decoding circuitry 109 in response to addresses.

[0042] The local media controller 135 also communicates with cache registers 172. The cache registers 172 latch incoming or outgoing data according to the direction of the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from the cache registers 172 to the data registers 170 for transfer to the memory cell array 104; then, the new data may be latched in the cache registers 172 from the I / O control circuitry 160. During a read operation, data may be transferred from the cache registers 172 to the I / O control circuitry 160 for output to the memory subsystem controller 115; then, the new data may be transferred from the data registers 170 to the cache registers 172. The cache registers 172 and / or the data registers 170 may form a page buffer of the memory device 130 (e.g., may form part of a page buffer). The page buffer may further include a sensing device (eg, a sensing device) for sensing the data state of a memory cell connected to the memory cell array 104, such as by sensing the state of a data line of the memory cell. Figure 1B 1 . The status register 122 may communicate with the I / O control circuitry 160 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0043] The memory device 130 receives control signals from the memory subsystem controller 115 through the control link 132 at the local media controller 135. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the nature of the memory device 130, additional or alternative control signals (not shown) may be further received through the control link 132. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory subsystem controller 115 through a multiplexed input / output (I / O) bus 134 and outputs the data to the memory subsystem controller 115 through the I / O bus 134.

[0044] For example, a command may be received at I / O control circuitry 160 via input / output (I / O) pins [7:0] of I / O bus 134 and then may be written into command register 124. An address may be received at I / O control circuitry 160 via input / output (I / O) pins [7:0] of I / O bus 134 and then may be written into address register 114. Data may be received at I / O control circuitry 160 via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device and then may be written into cache register 172. The data may then be written into data register 170 to program memory cell array 104.

[0045] In an embodiment, cache register 172 may be omitted and data may be written directly into data register 170. Data may also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference may be made to an I / O pin, it may include any conductive node provided by an external device (e.g., memory subsystem controller 115) for electrical connection to memory device 130, such as a commonly used conductive pad or conductive bump.

[0046] It will be appreciated by those skilled in the art that additional circuitry and signals may be provided and that the Figure 1B It should be appreciated that reference Figure 1B The functionality of the various block components described may not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1B Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1BAdditionally, although specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0047] Figure 2 is according to the embodiment as can be used for reference Figure 1B 1 is a schematic diagram of a portion of a memory cell array 104 (eg, a NAND memory array) in a memory of the type described. The memory array 104 includes access lines (eg, word lines 2020 to 2021). N ) and data lines (e.g., bit lines 2040 to 204 M ). The word lines 202 may be connected to the Figure 2 For some embodiments, memory array 104 may be formed on a semiconductor, which may be conductively doped to have one conductivity type (e.g., to have p-type conductivity, such as to form a p-well, or to have n-type conductivity, such as to form an n-well).

[0048] The memory array 104 can be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string of memory cells (e.g., nonvolatile memory cells or replacement gate (RG) NAND memory cells) connected in series, such as NAND strings 2060-206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N Memory cell 208 may represent a non-volatile memory cell for data storage. Memory cells 208 of each NAND string 206 may be connected in series to a select gate 210 (eg, a field effect transistor) (eg, select gates 2100 to 210 M One of the transistors (eg, which may be a source select transistor, commonly referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M One of the select gates 2100 to 210 (for example, which may be a drain select transistor, often referred to as a select gate drain)). M The select gates 2120 to 2124 may be commonly connected to a select line 214 (eg, a source select line (SGS)), and the select gates 2120 to 2124 may be commonly connected to a select line 214 (eg, a source select line (SGS)). Mmay be commonly connected to a select line 215, such as a drain select line (SGD). Although depicted as conventional field effect transistors, select gates 210 and 212 may utilize a similar (e.g., identical) structure as memory cell 208. Select gates 210 and 212 may represent a number of select gates connected in series, where each select gate in the series is configured to receive the same or an independent control signal.

[0049] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of the select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0050] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204. The control gate of each select gate 212 can be connected to a select line 215.

[0051] In one embodiment, one or more of the NAND strings 206 may be designated as a sacrificial string and used to detect read disturbance in the memory array 104. For example, NAND string 2060 may be designated as a sacrificial string. In other embodiments, there may be different NAND strings or additional NAND strings designated as sacrificial strings, including two or more NAND strings. In one embodiment, NAND string 2060 may include at least one sacrificial memory cell 208 from each word line 202. These sacrificial memory cells 208 in the sacrificial memory string 2060 are not available to the memory subsystem controller and are therefore not used to store host data. Instead, the sacrificial memory cells 208 remain in a default state (e.g., an erased state) or are programmed to a known voltage (e.g., a voltage corresponding to a known state). When a read operation is performed on any word line in the memory array 104, a read voltage is applied to the selected word line and a pass voltage is applied to the unselected word lines, and the sacrificial memory cells will experience the same read disturb effects as the memory cells storing host data. When the read disturb effect becomes strong enough, one or more of the sacrificial memory cells may transition from a default or known state to a different state (e.g., to a state associated with a higher voltage level). Therefore, the local media controller 135 may perform a string sensing operation on the string of sacrificial memory cells to determine whether a read disturb has occurred. In one embodiment, to perform the string sensing operation, a predefined read voltage is concurrently applied to each word line 202, and the current through the sacrificial string 2060 is sensed. If any of the sacrificial memory cells 208 in the sacrificial string 2060 has transitioned to a different state, the sacrificial string 2060 will not conduct electricity, and current will not flow. Therefore, in this case, the local media controller 135 can determine that there is a read disturb in the block of the memory array 104.

[0052] Figure 2 The memory array 104 in may be a quasi-two-dimensional memory array and may have a substantially planar structure, such as where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2 The memory array 104 in can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and a plane containing the bit lines 204 can extend substantially parallel to the plane containing the common source 216 .

[0053] The typical construction of the memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine the data state of the memory cell (e.g., by a change in threshold voltage) and a control gate 236, such as Figure 22. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases formed of) the word line 202.

[0054] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 may be memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly connected to a given word line 202. Multiple rows of memory cells 208 may generally be divided into one or more physical page groups of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a row of memory cells 208 that is commonly connected to a word line 202 may be grouped into one or more physical pages of memory cells 208, and a physical page of memory cells 208 may generally include every other memory cell 208 that is commonly connected to a given word line 202. N The memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be a physical page of memory cells 208 (eg, even memory cells), and the memory cells 208 are commonly connected to the word line 202. N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041 , 2043 , 2045 , etc.) may be another physical page of the memory cells 208 (eg, odd memory cells).

[0055] Despite Figure 2 The bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is obvious from the figure that the bit lines 204 of the memory cell array 104 can be from the bit line 2040 to the bit line 204 M 202. Other groupings of memory cells 208 commonly connected to a given word line 202 may also define a physical page of memory cells 208. For a particular memory device, all memory cells commonly connected to a given word line may be considered a physical page of memory cells. A portion of a physical page of memory cells (which may still be a full row in some embodiments) that is read during a single read operation or programmed during a single program operation (e.g., an upper page or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as those connected to word lines 2020 to 2021. N All memory cells of a common word line 202 (e.g., all NAND strings 206 that share a common word line 202). Unless explicitly distinguished, references herein to a page of memory cells refer to memory cells of a logical page of memory cells. Figure 2The examples are discussed in conjunction with NAND flash memory, but the embodiments and concepts described herein are not limited to a particular array architecture or structure, and may include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0056] Figure 3 is a diagram illustrating a three-via chain for an interconnect implementation according to at least one embodiment. Figure 3 Illustrated is a top view 301 of a memory die 305 and a side cross-section 302 of the memory die 305. As described above, the memory die 305 can include multiple chips coupled via interconnects—for example, the memory die can include a chip 315-a coupled via interconnect 320 with a chip 315-b.

[0057] As illustrated in the top view 301, there may be a via chain segment 310 along each side of the memory die 305—e.g., via chain segment 310-a along the leftmost edge of the memory die 305, via chain segment 310-b along the topmost edge of the memory die 305, via chain segment 310-c along the rightmost edge of the memory die 305, and via chain segment 310-a along the bottommost edge of the memory die 305. In at least one embodiment, each via chain segment 310 may enable a signal to be transmitted along a respective edge of the memory die 305. In such an embodiment, as described with reference to FIG. 1, the three-via chain assembly 113 may perform a quality check by transmitting a signal from one end of the via chain segment 310 to the other end of the via chain segment 310—e.g., via chain segment 310-a may enable a signal to be transmitted along the right edge of the memory die 305 from the bottommost edge to the topmost edge to test for cracks, misalignments, or breaks within the memory die 305. In one embodiment, the system may perform a quality test using the via segment 310-a by forcing a voltage on one terminal while grounding the other terminal and measuring the current. Conversely, the system may alternatively force a current on one terminal while grounding the other terminal and measuring the voltage. In at least one embodiment, a current measurement of zero (0) or a high voltage measurement (e.g., a voltage approaching infinity that meets or exceeds a non-zero threshold voltage level) may indicate the presence of a crack, misalignment, or disconnection within the memory device. In other examples, the system may perform a quality test by forcing a voltage on one terminal and floating the other terminal to measure the current. Conversely, the system may alternatively be used for current on one terminal while the other terminal floats to measure the voltage. In such embodiments, if the system measures a non-zero current or a low voltage (e.g., a voltage that is less than the non-zero threshold voltage level and is not approaching infinity), the system may determine that there are some errors that cause the via chain to short. In some embodiments, the system may also utilize the via chain 310 to determine transmission line (T-line) characteristics—for example, to determine series resistance due to conductor resistivity, to determine shunt conductance due to leakage current, to determine series inductance due to magnetic fields around conductors, or to determine shunt capacitance due to electric fields between conductors. In one example, the system may transmit a high-frequency signal having a rising edge and / or a falling edge from a first end of the via chain 310. In such an example, the system may then measure the output at the second end of the via chain 310 to determine the frequency response of the transmission line—for example, an edge that matches the initial signal at the output may indicate that the high-frequency signal is being accurately transmitted, while an edge that does not match the initial signal at the output may indicate that the high-frequency signal is not being accurately transmitted. Reference Figure 4 Describes additional details about transmission line testing.

[0058] Although the top view 301 illustrates four (4) via chain segments 310, the memory die 305 may include any number of via chain segments that verify the continuity of the sides and / or corners 310 - for example, one (1), two (2), three (3), four (4), five (5), six (6), etc. In at least one embodiment, each via chain segment 310 is independent of another via chain segment 310. For example, a crack along the rightmost edge in the memory die 305 may cause a short in the via chain 310-a, but not affect the remaining via chain segments 310 because the remaining via chain segments are independent of the via chain 310-a. Thus, the system can determine which edge, if any, includes a crack, misalignment, or break. Additionally, the top view 301 may illustrate the via chain segments 310 of one (1) layer of the memory die 305 - for example, the top view 301 may illustrate the via chain segments 310 that pass through the chip 315-a. As illustrated by the side cross-sectional view 302 , there may be at least three (3) via chain segments 355 along any given edge of the memory die 305 .

[0059] Figure 3 The side cross-section 302 may illustrate chip 315-a coupled to chip 315-b via interconnects 320 in memory die 305. In one embodiment, chip 315-a or chip 315-b is an array chip—for example, a chip that includes a memory array. In another embodiment, chip 315-a or chip 315-b is an instance of a complementary metal oxide semiconductor (CMOS) chip—for example, a chip that includes CMOS circuitry. As illustrated by the side cross-section 302, chip 315-a is an array chip and chip 315-b is a CMOS chip. In one example, each chip 315 may include multiple layers or levels—for example, multiple oxide or metal levels. Each level may include components or memory cells. For example, chip 315-a may include component 365, component 370, component 375, and component 380, where each respective component is in a different level. In one embodiment, components 365, components 370, components 375, and components 380 are reference numerals. Figure 1B Examples of components described - for example, a component may represent I / O control 160, address register 114, address register 122, etc., as shown in reference Figure 1B305 . In other embodiments, components 365, 370, 375, and 380 may be examples of other circuit systems that perform functions related to the memory array. In at least one embodiment, chip 315-a may include any number of additional components or levels not illustrated to store and process data. Additionally, side cross-section 302 may illustrate a portion of memory die 305 along an edge. Each level illustrated in side cross-section 302 may extend along the edge—for example, there may be additional components 365, 370, through-array contacts 330, components 375, and 380.

[0060] In at least one embodiment, chip 315-a may include array stack 325—e.g., a portion of chip 315-a may be used for array stack 325. In one embodiment, array stack 325 may include one or more layers (e.g., oxide or metal levels) with memory cells formed on each layer. Array stack 325 may also include through-array contacts 330—e.g., contacts that enable signals to travel through layers of memory cells. For example, through-array contacts 330 may enable signals from component 370 to travel through array stack 325 or to corresponding layers of array stack 325.

[0061] In one embodiment, chip 315-a may include via segments 355 (e.g., including via segments 310-a). For example, chip 315-a may include vias 345 that couple various components within chip 315-a to enable signal 340-c to pass through chip 315-a. In at least one embodiment, vias 345 may couple component 365-a with component 370-a, component 370-a with through-array contacts 330, through-array contacts with component 375-a, and component 375-a with component 380-a. Thus, signal 340-c may travel from component 365-a upward through component 370, through-array contacts 330, component 375 to component 380-b. As previously described, side cross-section 302 may show a portion of an edge of memory die 305. Thus, chip 315-a may include additional vias 345 that enable signal 340-c to pass from component 380 downward through chip 315-a to component 365—for example, chip 315-a may include additional vias 345 that enable signal 340-c to then travel from component 380 to component 375, downward through array contacts 330, through component 370 and back to component 365—for example, signal 340-c may travel from bottom to top and then back downward to bottom, as illustrated with reference to signal 340-a passing through chip 315-b.

[0062] By utilizing a via chain in chip 315-a, the three-via chain assembly 113 described with reference to FIG. 1 can more accurately monitor cracks. Additionally, implementing a via chain in chip 315-a can enable the system to monitor through-array contacts 330—for example, verifying that a signal is accurately transmitted through through-array contacts 330 and / or determining transmission line (T-line) characteristics of through-array contacts 330. In one embodiment, the signal 340-c passing through the via chain can enable the system to verify the routing of chip 315-a without relying on advanced interconnect 320. For example, if the via chain is shorted, the system can determine that there is a problem with the routing within chip 315-a, rather than having to verify whether there is a problem with the routing within chip 315-a or whether there is a problem with interconnect 320 itself.

[0063] In at least one embodiment, chip 315-b may also include multiple layers or levels - for example, multiple oxide or metal levels. In one embodiment, chip 315-b may include components 350, 355, and 360, each in a corresponding level. In one embodiment, components 350, 355, and 360 are referenced Figure 1B Examples of components described - for example, a component may represent I / O control 160, address register 114, address register 122, etc., as shown in reference Figure 1B In other embodiments, components 350, 355, and 360 may be examples of other circuitry that performs functions associated with a memory array. In at least one embodiment, chip 315-b may include any number of additional components or levels not described to store and process data.

[0064] In at least one embodiment, chip 315-b may include via segments 355. For example, chip 315-b may include vias 345 that couple various components within chip 315-b to enable signal 340-a to pass through chip 315-b. For example, vias 345 may couple component 350-a with component 355-b, component 355-b with component 360-b, component 360-b with component 355-c, and component 355-c with component 350-b. Thus, signal 340-a may travel through component 350-a up to component 355-b, then up and through component 360-b, and then down through component 355-c back to component 350-b. Thus, the via segments may enable signal 340 - a to travel from the bottom of chip 315 - b to the top of chip 315 - b , and then from the top of chip 315 - b to the bottom of chip 315 - b .

[0065] By utilizing the via chain in chip 315-b, the system can more accurately monitor cracks. In at least one embodiment, the via chain can have safe high voltage (SPH) capability. In such embodiments, the system can utilize the via chain within chip 315-b to determine or measure delamination (e.g., a break within a layer or tier of chip 315-b) from the center of memory die 305 outward to the boundary of memory die 305 - for example, to the corresponding edge of memory die 305. In at least one embodiment, the system can also utilize the via chain within chip 315-b (as if it were an SPH capacitor) to measure signal 340-a at a relatively high voltage.

[0066] In at least one embodiment, the interconnect 320 may couple the chip 315-a with the chip 315-b. In one embodiment, a coupler 350 (e.g., a coupling mechanism) may couple the chip 315-a with the chip 315-b through the interconnect 320. In one embodiment, the memory die 305 may also include at least a third via segment 355 passing through the interconnect 320. For example, the memory die 305 may include a via 345 that couples a component 360-a of the chip 315-b with a component 365-b of the chip 315-a—e.g., enabling a signal 340-b to pass through the interconnect 320. In some embodiments, the memory die 305 may include an additional via 345 that enables the signal 340-b to pass through the interconnect 320 back to another component 360 of the chip 315-b.

[0067] In at least one embodiment, the system may utilize a chain of vias across interconnect 320 to check for misalignment, cracks, or additional stress and expansion at the edge of memory die 305—for example, to check for bending, expansion, or shrinkage. In at least one embodiment, if there is a high resistance across interconnect 320 when transmitting signal 340-b, then the system may determine that there may be a crack, stress, or misalignment. In one embodiment, the system may utilize a chain of vias across interconnect 320 to monitor interconnect 320—for example, to monitor the connection between chip 315-a and chip 315-b to ensure that it is transmitting signals reliably. In one embodiment, the system may also utilize a chain of vias across interconnect 320 to measure the t-line characteristics of the interconnect 320 contacts.

[0068] Although not illustrated, the memory die 305 may include circuitry (e.g., a multiplexer) such that any respective via chain segment may be selected. That is, the via chain may be segmented into any number of via chain segments 310 and multiplexed to enable the system to select an edge, edge segment, or corner of the memory die 305 for testing—e.g., the system may independently check or verify each edge, edge segment, or corner of the memory die 305. In one embodiment, each via chain passing through the chip 315-a, chip 315-b, and interconnect 320 may also be multiplexed to enable the system to select the chip 315-a, chip 315-b, and / or interconnect 320 for testing—e.g., the system may independently check the chip 315-a, chip 315-b, or interconnect 320. Additionally, the system may include a multiplexer or other circuitry to select the type of test to be performed—for example, one of forcing a current on one end and grounding the other end, forcing a voltage on one end and floating the other end, or transmitting a high-frequency signal to compare the input at one end of the via chain segment to the output at the other end of the via chain segment.

[0069] Figure 4 is a diagram illustrating via chain measurement in accordance with at least one embodiment. Figure 4 A top or bottom view 400 and a via chain output 401 may be illustrated. Figure 3 As described, a system (eg, system 100) may utilize a via chain (eg, via chain segment 310) to measure transmission line (t-line) characteristics—eg, as described in reference Figure 3 The system may measure the t-line characteristics of the through-array contacts 330 or the interconnects 320 as described. In such embodiments, the system may transmit the high-frequency signal from the first end of the via chain segment 310 to the second end of the via chain segment 310. In at least one embodiment, the system may compare the input (e.g., the signal at the first end of the via chain) with the output (e.g., the signal at the second end of the via chain). For example, the high-frequency signal may have a rising edge and / or a falling edge. The system may compare the edge of the signal measured at the first end with the edge measured at the second end. Thus, the system may determine whether the high-frequency signal is accurately routed through the memory die (e.g., as described in reference Figure 3 Memory die 305 as described).

[0070] In at least one embodiment, an end (e.g., a second end) of a via chain segment may include a buffer 415 coupled to a bonding pad 410. In one embodiment, a signal (e.g., signal 340) may be measured at the buffer 415—for example, the system may include additional components for measuring the signal at the buffer 415. In some embodiments, the buffer may be a safety high voltage (SHV) component. In such embodiments, the capacitance of the bonding pad 410 may affect the buffer 415—for example, the buffer 415 may not be able to accurately measure high frequency signals. In such embodiments, the system may perform measurement of the signal at the probe pad 405. For example, the top or bottom of the chip 315 (e.g., chip 315-a or chip 315-b) may include one or more probe pads 405. In one embodiment, the probe pad 405 may enable the system to measure the signal before the signal is affected by the bonding pad 410. For example, the system may measure the signal at the probe pad 405 illustrated in the via chain output 401 (e.g., signal 340). This may enable the signal to be accurately measured and not affected by the capacitance of the bonding pad 410. Thus, the system may compare the input of the signal to the output at the probe pad 405 or buffer 415 - for example, depending on the capacitance of the bond pad 410 and its effect on the signal.

[0071] Figure 5 is a flow chart of an example method for using a three-via chain for advanced interconnects according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by utilizing a method such as that described in reference Figure 3 1. In at least one embodiment, method 500 is performed by processing logic or by the three-through-hole chain component 113 described with reference to FIG. 1. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At operation 505, a first via segment of the one or more via segments is selected for a test operation. For example, processing logic may select a first via segment at a first portion of a memory device (e.g., memory device 130) for a test operation. In one embodiment, the one or more via segments may include a second via segment at a second portion of the memory device and a third via segment at a third portion of the memory device. In at least one embodiment, the first portion, the second portion, and the third portion of the memory device may correspond to chip 315-a, chip 315-b, and advanced interconnect 320, as described with reference to FIG. Figure 3 As described above, for example, each chip and interconnect of a memory device may include a separate via chain for testing purposes. In at least one embodiment, a first via chain segment may include multiple portions, each portion corresponding to a side of the memory device. That is, the memory device may include four (4) sides, and each side may have a portion of a via chain segment, such as Figure 3 301 of . In one embodiment, processing logic may select a first portion of a plurality of portions of a first via chain segment, wherein the first portion is associated with a first side of a memory device, and test the first side of the memory device in response to selecting the first portion. In at least one embodiment, each portion of the via chain segment may be independent of the other - for example, any portion of the via chain segment may be selected to perform a test operation associated with a side of the memory device. In some embodiments, processing logic may select a second via chain segment of one or more via chains of a memory device for a second test operation at a second portion of the memory device, wherein the second test operation is independent of the first test operation. That is, processing logic may select each via chain segment for a respective test operation independent of the other - for example, processing logic may select the first via chain segment to test the first portion and select the second via chain segment to test the second portion.

[0073] At operation 510, a first portion of a memory device is tested. For example, processing logic tests the first portion of the memory device in response to selecting a first via chain segment. In at least one embodiment, processing logic may test the first portion by driving a current on a first terminal of the first via chain segment, grounding a second terminal of the first via chain segment, and measuring a voltage at the second terminal in response to grounding the second terminal. In such embodiments, processing logic may measure a voltage across the via chain. For example, processing logic may determine that the voltage is zero, wherein determining one or more errors associated with the first portion of the memory device is in response to determining that the voltage is zero—for example, a zero voltage may indicate a crack, misalignment, or other problem within the first portion of the memory device that causes the voltage at the second terminal to be zero. In other embodiments, processing logic may determine that the voltage is non-zero and determine that there are no errors associated with the first portion in response to determining that the voltage is non-zero—for example, if processing logic determines that the voltage is non-zero, then there may be no crack or misalignment within the first portion of the memory device. In at least one embodiment, the processing logic may test the first portion by driving a voltage on a first terminal of the first via segment, floating a second terminal of the first via segment, and measuring a current at the second terminal in response to grounding the second terminal. In this embodiment, floating the second terminal may refer to isolating the second terminal from any voltage source—for example, the second terminal may be isolated and in a floating state. In at least one embodiment, the processing logic may measure the current while driving the voltage at the first terminal. For example, the processing logic may determine a non-zero current, wherein determining one or more errors associated with the first portion of the memory device is in response to determining that the current is non-zero—for example, determining that the current is non-zero may indicate a crack or misalignment. In other embodiments, the processing logic may determine that the current is zero and accordingly determine that there are no errors—for example, measuring 0 current may indicate that there are no cracks or misalignments. In one embodiment, the processing logic may perform a test operation by transmitting a signal from the first terminal of the first via segment to the second terminal of the first via segment and comparing the signal at the first terminal to the signal at the second terminal—for example, the memory device may include a comparator that compares the signal transmitted to the first terminal with the signal received at the second terminal. In at least one embodiment, the processing logic may determine a transmission line characteristic of the first via chain segment in response to the comparison signal—for example, determining a series resistance due to the resistivity of the conductor, determining a shunt conductance due to leakage current, determining a series inductance due to the magnetic field around the conductor, or determining a shunt capacitance due to the electric field between the conductors, as described in reference to FIG. Figure 3 describe.

[0074] At operation 515, one or more errors associated with the first portion of the memory device are determined. For example, the processing logic may determine one or more errors associated with the first portion in response to testing the first portion of the memory device. That is, the processing logic may detect cracks, misalignments, disconnects, or other potential errors in the manufacturing process in response to performing the test operation.

[0075] In at least one embodiment, a memory device includes a first portion, the first portion including a memory array, the memory array including a plurality of memory cells and a first via chain segment for performing a test operation—for example, as described in reference Figure 3 The memory device also includes a second portion including a processing circuit system and a second via chain segment for performing a test operation - for example, as described in reference Figure 3 In at least one embodiment, the memory device includes an interconnect coupling the first portion and the second portion, the interconnect including a third via segment—for example, as described in reference Figure 3 320 is depicted. In at least one embodiment, the first via chain segment, the second via chain segment, and the third via chain segment can be independently selected - for example, a multiplexer can select any one of the via chain segments for a test operation. In at least one embodiment, the first via chain segment, the second via chain segment, and the third via chain segment each include a plurality of portions, wherein a portion of the plurality of portions corresponds to a side of the memory device - for example, as illustrated in top view 301.

[0076] In some embodiments, the memory device includes a multiplexer coupled to a plurality of portions of the first via chain segment, the second via chain segment, and the third via chain segment, wherein the multiplexer is used to select a first portion of the plurality of portions during a test operation—e.g., to select which side of the memory device is to be tested. In some embodiments, the first via chain segment includes a first terminal and a second terminal, and a comparator is coupled to the second terminal of the first via chain segment, the comparator is used to compare a first signal at the second terminal with a second signal generated at the first terminal—e.g., to determine whether the first signal is a signal generated at the second terminal as described in the reference signal. Figure 3 In some embodiments, the first terminal is used to drive a current or voltage to the first via segment, and the second terminal is grounded during the test operation. In other embodiments, the first terminal is used to drive a current or voltage to the first via segment, and the second terminal is in a floating state during the test operation. In at least one embodiment, the memory device includes a multiplexer coupled to the first via segment, the second via segment, and the third via segment, wherein the multiplexer is used to select the first via segment, the second via segment, or the third via segment for the test operation.

[0077] Figure 6An example machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., host system 120 of FIG. 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of FIG. 1 ), or may be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to the three-via chain 113 of FIG. 1 to perform a test operation). In at least one embodiment, a memory device may include a three-via chain, wherein each portion of the memory device includes an independent via chain segment. For example, the memory device may include a first chip, a second chip, and an interconnect for coupling the first chip and the second chip. In at least one embodiment, the first chip, the second chip, and the interconnect may include independent via chain segments, as described with reference to FIGS. 1 to 5 . In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. In a networked deployment, the machine may operate in the capacity of a server or a client machine in server-client network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0078] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0079] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0080] The processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

[0081] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functionality described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or the processing device 602 during execution thereof by the computer system 600, which also constitute machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to the memory subsystem 110 of FIG. 1 .

[0082] In one embodiment, the instructions 626 include instructions that implement functionality corresponding to the three-way chain component 113 to perform a read operation of the processing device 602. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0083] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes for reasons of customary usage, to refer to these signals, in principle, as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0084] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0085] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0087] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0088] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device, comprising: A first portion including a memory array including a plurality of memory cells and a first via chain segment for performing a test operation; a second portion including a processing circuit system and a second via chain segment for performing the test operation; and An interconnect couples the first portion and the second portion, the interconnect comprising a third via chain segment, wherein the first via chain segment, the second via chain segment, and the third via chain segment are independently selectable. 2 . The memory device of claim 1 , wherein the first via chain segment, the second via chain segment, and the third via chain segment each include a plurality of portions, wherein a portion of the plurality of portions corresponds to a side of the memory device.

3. The memory device of claim 2, further comprising: A multiplexer is coupled to the plurality of portions of the first, second, and third via chain segments, wherein the multiplexer is used to select a first portion of the plurality of portions during the testing operation.

4. The memory device of claim 1 , wherein the first via segment comprises a first terminal and a second terminal, the memory device further comprising: A comparator is coupled to the second terminal of the first via chain segment, the comparator being configured to compare a first signal at the second terminal with a second signal generated at the first terminal.

5. The memory device of claim 1 , wherein the first via chain segment comprises a first terminal and a second terminal, and wherein: The first terminal is used to drive at least one of a current or a voltage to the first via chain segment; and The second terminal is grounded during the testing operation.

6. The memory device of claim 1 , wherein the first via chain segment comprises a first terminal and a second terminal, and wherein: The first terminal is used to drive at least one of a current or a voltage to the first via segment; and The second terminal is in a floating state during the testing operation.

7. The memory device of claim 1, further comprising: A multiplexer is coupled to the first via chain segment, the second via chain segment, and the third via chain segment, wherein the multiplexer is used to select the first via chain segment, the second via chain segment, or the third via chain segment for the test operation.

8. A method comprising: selecting a first via chain segment of one or more via chains of the memory device for a test operation at a first portion of the memory device, wherein the one or more via chain segments include a second via chain segment at a second portion of the memory device and a third via chain segment at a third portion of the memory device; testing the first portion of the memory device in response to selecting the first via chain segment; and One or more errors associated with the first portion of the memory device are determined in response to testing the first portion of the memory device.

9. The method of claim 8, wherein testing the first portion of the memory device further comprises: driving at least one of a current or a voltage on a first terminal of the first via segment; grounding the second terminal of the first through hole segment; and At least one of an output voltage or an output current at the first terminal is measured in response to grounding the second terminal.

10. The method according to claim 9, further comprising: At least one of determining that the output voltage is near ground or the output current is high, wherein determining the one or more errors associated with the first portion of the memory device is responsive to determining the at least one of the output voltage is near ground or the output current is high.

11. The method according to claim 9, further comprising: determining at least one of that the output voltage is not near ground or that the output current is not high; and Responsive to determining the at least one of the output voltage is not near ground or the output current is not high, determining that there is no error associated with the first portion.

12. The method of claim 8, wherein testing the first portion of the memory device further comprises: driving a voltage on a first terminal of the first via segment; Floating the second terminal of the first through hole segment; and A current at the first terminal is measured in response to floating the second terminal.

13. The method according to claim 12, further comprising: A non-zero current is determined, wherein determining the one or more errors associated with the first portion of the memory device is responsive to determining the current is non-zero.

14. The method of claim 8, wherein testing the first portion of the memory device further comprises: transmitting a signal from a first terminal of the first via chain segment to a second terminal of the first via chain segment; comparing the signal at the first terminal to the signal at the second terminal; and A transmission line characteristic of the first via chain segment is determined in response to comparing the signals.

15. The method of claim 8, wherein the first via chain segment comprises a plurality of portions, each portion corresponding to at least one of a side, a segment, or a corner of the memory device, the method further comprising: selecting a first portion of the plurality of portions of the first via chain segment, wherein the first portion is associated with at least one of a first side, a first segment, or a first corner of the memory device; and The at least one of the first side, the first section, or the first corner of the memory device is tested in response to selecting the first portion.

16. The method according to claim 8, further comprising: The second via chain segment of the one or more via chains of the memory device is selected at the second portion of the memory device for a second test operation, wherein the second test operation is independent of the test operation.

17. A memory device comprising: a memory array comprising memory cells; and A control logic coupled to the memory array, the control logic being configured to: selecting a first via chain segment of one or more via chains of the memory device for a test operation at a first portion of the memory device, wherein the one or more via chain segments include a second via chain segment at a second portion of the memory device and a third via chain segment at a third portion of the memory device; testing the first portion of the memory device in response to selecting the first via chain segment; and One or more errors associated with the first portion of the memory device are determined in response to testing the first portion of the memory device.

18. The memory device of claim 17, wherein to test the first portion, the control logic is to: driving at least one of a current or a voltage on a first terminal of the first via segment; grounding the second terminal of the first through-hole segment; and At least one of an output voltage or an output current at the first terminal is measured in response to grounding the second terminal.

19. The memory device of claim 18, wherein the control logic is to: At least one of determining that the output voltage is zero or the output current is high, wherein the control logic is used to determine the one or more errors associated with the first portion of the memory device in response to determining the at least one of the output voltage is zero or the output current is high.

20. The memory device of claim 18, wherein the control logic is to: determining that the output voltage is non-zero or the output current is not high; and Responsive to determining the at least one of the output voltage is non-zero or the output current is not high, determining that there is no error associated with the first portion.

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