Memory programming method, memory and memory system

Abstract

The invention provides a memory programming method, a memory and a memory system, and relates to the technical field of semiconductor chips. The memory programming method comprises the steps that in the programming stage of a first programming period, first programming voltage and second programming voltage are continuously applied to a selected word line, and the second programming voltage is larger than the first programming voltage; a selection word line coupled to the first memory cell and the second memory cell; programming the first memory cell and the second memory cell when a first programming voltage is applied; when a second program voltage is applied, the second memory cell is programmed and the first memory cell is prevented from being programmed. According to the invention, the programming time of the memory can be well reduced, and the programming speed of the memory with a plurality of programming levels is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a memory programming method, a memory, and a memory system. Background Art

[0002] At present, for NAND flash memory, the incremental step programming pulse (ISPP) method is generally used for programming. Each programming cycle of ISPP includes a programming stage and a subsequent verification stage. In the programming stage, a programming voltage is first applied to the gate of the storage cell to allow the charge to enter the floating gate layer of the storage cell; in the verification stage, a verification voltage is applied to the gate of the storage cell. If the verification passes, the programming of the storage cell ends. If the verification fails, an increment is superimposed on the programming voltage to continue to the next programming stage.

[0003] However, for memories with multiple programming levels, such as multi-level cell (MLC), trinary-level cell (TLC), and quad-level cell (QLC), different numbers of programming cycles are required to program storage cells of different programming levels, and each programming cycle requires additional ramp-up time and ramp-down time for the programming voltage and ramp-up time and ramp-down time for the verification voltage, which makes the programming time of the memory longer, thereby affecting the data writing speed of the memory. Summary of the invention

[0004] The embodiments disclosed in the present application provide a memory programming method, a memory, and a memory system, which are used to improve the programming speed of a memory with multiple programming levels.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a memory programming method is provided, the memory programming method comprising: in a programming phase of a first programming cycle, continuously applying a first programming voltage and a second programming voltage to a selection word line, the second programming voltage being greater than the first programming voltage; the selection word line is coupled to a first memory cell and a second memory cell; when the first programming voltage is applied, the first memory cell and the second memory cell are programmed; when the second programming voltage is applied, the second memory cell is programmed and programming of the first memory cell is prevented.

[0007] The memory programming method provided in the present application continuously applies a first programming voltage and a second programming voltage to a selected word line in a programming phase of a first programming cycle to complete programming of two programming levels, thereby reducing the ramp-up time and ramp-down time of the programming voltage; thereby being able to better reduce the programming time of the memory, and further improve the programming speed of the memory with multiple programming levels.

[0008] In some embodiments, the programming method further includes: in the verification phase of the first programming cycle, continuously applying a first verification voltage and a second verification voltage to the selection word line; the first verification voltage is configured to verify whether the first storage cell reaches the first target programming level, and the second verification voltage is configured to verify whether the second storage cell reaches the second target programming level. In the verification phase of the first programming cycle, the first verification voltage and the second verification voltage are continuously applied to the selection word line to complete the verification of the two programming levels, reducing the ramp-up time and ramp-down time of the verification voltage. Further reducing the programming time of the memory can further improve the programming speed of the memory with multiple programming levels.

[0009] In some embodiments, programming the first memory cell and the second memory cell specifically includes: applying a first bit line voltage to a first bit line and a second bit line; the first bit line is coupled to a memory cell string where the first memory cell is located, and the second bit line is coupled to a memory cell string where the second memory cell is located. The first bit line voltage can generate a lower channel potential of the first memory cell and the second memory cell, so that a larger potential difference can be generated between the control gate and the channel, so that the charge can tunnel into the floating gate, so as to program the first memory cell and the second memory cell.

[0010] In some embodiments, programming the first memory cell and the second memory cell further includes: applying a first pass voltage to a non-selected word line, the non-selected word line is coupled to the non-selected memory cell in the memory cell string where the first memory cell is located, and the non-selected memory cell in the memory cell string where the second memory cell is located; and applying a turn-on voltage to a selected top selection line, the selected top selection line is coupled to the top selection tube of the memory cell string where the first memory cell is located, and the top selection tube of the memory cell string where the second memory cell is located. For a three-dimensional (3D) NAND flash memory in which memory cells are stacked into a memory cell string, by applying a first pass voltage to the non-selected word line and applying a turn-on voltage to the selected top selection line. Thus, the line between the first bit line and the first memory cell is turned on, ensuring that there is a large potential difference between the control gate and the channel of the first memory cell; and the line between the second bit line and the second memory cell is turned on, ensuring that there is a large potential difference between the control gate and the channel of the second memory cell.

[0011] In some embodiments, programming the second memory cell and preventing programming of the first memory cell specifically includes: applying a first bit line voltage to the second bit line, applying a second bit line voltage to the first bit line; the second bit line voltage is greater than the first bit line voltage. The second bit line voltage can generate a higher channel potential of the first memory cell, so that a smaller potential difference can be generated between the control gate and the channel, making it difficult for charges to tunnel into the floating gate, so as to prevent programming of the first memory cell.

[0012] In some embodiments, programming the second memory cell and preventing programming of the first memory cell further includes: applying a second pass voltage to the non-selected word line, the second pass voltage being greater than the first pass voltage.

[0013] For the same second bit line voltage, the second pass voltage with a higher voltage value can also increase the channel potential of the second storage unit. Therefore, under the second programming voltage with a higher voltage value, it can better ensure that the potential difference between the control gate and the channel of the first storage unit does not exceed the tunneling threshold, so that it is difficult for the charge to tunnel, and thus to a certain extent, it can overcome the program disturbance caused by the increase of the programming voltage (the first programming voltage increases to the second programming voltage).

[0014] In some embodiments, the memory cell string where the first memory cell is located is coupled to the first bit line, and the memory cell string where the second memory cell is located is coupled to the second bit line; the first verification voltage and the second verification voltage are continuously applied to the selection word line, and the method further includes: applying the bit line verification voltage to the first bit line and the second bit line. If the first memory cell reaches the first target programming level, the first memory cell is turned off at the first verification voltage, and no significant voltage drop occurs at the sensing node (SO) coupled to the first bit line BL1; similarly, if the second memory cell reaches the second target programming level, the second memory cell is turned off at the second verification voltage, and no significant voltage drop occurs at the sensing node coupled to the first bit line BL1.

[0015] In some embodiments, the non-selected memory cells in the memory cells where the first memory cell is located and the non-selected memory cells in the memory cells where the second memory cell is located are coupled to the non-selected word line, the top selection tube in the memory cells where the first memory cell is located and the top selection tube in the memory cells where the second memory cell is located are coupled to the selected top selection line, and the bottom selection tube in the memory cells where the first memory cell is located and the bottom selection tube in the memory cells where the second memory cell is located are coupled to the bottom selection line; the first verification voltage and the second verification voltage are continuously applied to the selected word line, and further comprising: applying a third pass voltage to the non-selected word line; applying a turn-on voltage to the selected top selection line and the bottom selection line. For a 3D NAND flash memory in which memory cells are stacked into a memory cell string, the non-selected memory cells on the memory cell string where the first memory cell is located and the non-selected memory cells on the memory cell string where the second memory cell is located are turned on by applying the first pass voltage to the non-selected word line and applying the turn-on voltage to the selected top selection line; thereby providing the bit line verification voltage to the first memory cell and the second memory cell to verify the first memory cell and the second memory cell.

[0016] In some embodiments, when a turn-on voltage is applied to the selected top selection line, the programming method further includes: applying a turn-off voltage to non-selected top selection lines other than the selected top selection line, the non-selected top selection lines and the selected top selection line being coupled to top selection tubes of different memory cell strings. In both the programming phase and the verification phase of the programming cycle, the turn-off voltage is applied to the non-selected top selection lines, thereby avoiding programming of multiple memory cell pages at the same time.

[0017] In a second aspect, a memory is provided, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array, the peripheral circuit being configured as follows: in a programming phase of a first programming cycle, applying a first programming voltage and a second programming voltage in sequence to a selection word line, the second programming voltage being greater than the first programming voltage; the selection word line is coupled to a first memory cell and a second memory cell; when the first programming voltage is applied, programming the first memory cell and the second memory cell; and when the second programming voltage is applied, programming the second memory cell and preventing programming of the first memory cell.

[0018] In some embodiments, the peripheral circuit is further configured to: continuously apply a first verification voltage and a second verification voltage to a selected word line during a verification phase of a first programming cycle; the first verification voltage is configured to verify whether the first storage cell reaches a first target programming level, and the first verification voltage is configured to verify whether the second storage cell reaches a second target programming level.

[0019] In some embodiments, the first storage cell and the second storage cell are programmed, and the peripheral circuit is specifically configured to: apply a first bit line voltage to the first bit line and the second bit line; the first bit line is coupled to the storage cell string where the first storage cell is located, and the second bit line is coupled to the storage cell string where the second storage cell is located.

[0020] In some embodiments, the first memory cell and the second memory cell are programmed, and the peripheral circuit is also configured to: apply a first pass voltage to a non-selected word line, the non-selected word line is coupled to the non-selected memory cells in the memory cell string where the first memory cell is located, and the non-selected memory cells in the memory cell string where the second memory cell is located; and, apply a turn-on voltage to a selected top selection line, the selected top selection line is coupled to the top selection tube of the memory cell string where the first memory cell is located, and the top selection tube of the memory cell string where the second memory cell is located.

[0021] In some embodiments, the second memory cell is programmed and the first memory cell is prevented from being programmed, and the peripheral circuit is specifically configured to: apply the first bit line voltage to the second bit line, apply the second bit line voltage to the first bit line; the second bit line voltage is greater than the first bit line voltage.

[0022] In some embodiments, the second memory cell is programmed and the first memory cell is blocked from being programmed, and the peripheral circuit is further configured to: apply a second pass voltage to the non-selected word line, the second pass voltage being greater than the first pass voltage.

[0023] In some embodiments, a memory cell string where a first memory cell is located is coupled to a first bit line, and a memory cell string where a second memory cell is located is coupled to a second bit line; a first verification voltage and a second verification voltage are continuously applied to a selection word line, and the peripheral circuit is also configured to apply a bit line verification voltage to the first bit line and the second bit line.

[0024] In some embodiments, a non-selected memory cell in the memory cell where the first memory cell is located and a non-selected memory cell in the memory cell where the second memory cell is located are coupled to a non-selected word line, a top selection tube in the memory cell where the first memory cell is located and a top selection tube in the memory cell where the second memory cell is located are coupled to a selected top selection line, and a bottom selection tube in the memory cell where the first memory cell is located and a bottom selection tube in the memory cell where the second memory cell is located are coupled to a bottom selection line; a first verification voltage and a second verification voltage are continuously applied to the selected word line, and the peripheral circuit is also configured to: apply a third pass voltage to the non-selected word line; and apply a turn-on voltage to the selected top selection line and bottom selection line.

[0025] In some embodiments, when a turn-on voltage is applied to a selected top selection line, the peripheral circuit is also configured to: apply a turn-off voltage to non-selected top selection lines other than the selected top selection line, and the non-selected top selection lines and the selected top selection line are coupled to top selection tubes of different memory cell strings.

[0026] According to a third aspect, a memory system is provided. The memory system comprises a memory controller and the memory according to the second aspect, wherein the memory controller is configured to control the memory.

[0027] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented.

[0028] In a fifth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the first aspect can be implemented.

[0029] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present application, the following briefly introduces the drawings required to be used in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0031] Figure 1 A possible waveform diagram for conventional ISSP programming of a memory with multiple programming levels;

[0032] Figure 2 A schematic diagram of a memory system provided in one embodiment of the present application;

[0033] Figure 3 A schematic diagram of a memory provided in one embodiment of the present application;

[0034] Figure 4 A schematic diagram of a possible memory cell array provided for one of the embodiments of the present application;

[0035] Figure 5A schematic diagram of the structure of a row of memory cell strings in a memory cell array provided for one of the embodiments of the present application;

[0036] Figure 6 A waveform diagram of a memory with multiple programming levels provided for programming in one embodiment of the present application;

[0037] Figure 7 A flow chart is provided for one of the embodiments of the present application.

[0038] Figure numerals: 200, memory system; 210, memory controller; 220, memory; 310, peripheral circuit; 311, I / O interface; 312, control logic unit; 313, row decoder; 314, voltage generator; 315, column decoder; 316, page buffer; 317, data bus; 318, register; 320, memory cell array; 410, memory cell string; 511, top selection tube; 512, dummy memory cell; 520, memory cell page; 521, first memory cell; 522, second memory cell; 523, third memory cell; 513, bottom selection tube. DETAILED DESCRIPTION

[0039] The following will be combined Figure 1-Figure 7 , the technical solutions in some embodiments of the present application are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0040] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0041] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0042] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0043] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0044] NAND flash memory is a non-volatile random access storage medium. NAND flash memory usually uses floating gate transistors as memory cells. Unlike traditional transistors, the gate of a floating gate transistor includes a floating gate (FG) that can store charge in addition to a control gate. An insulating layer is provided between the floating gate and the control gate, and a tunneling layer (such as a silicon dioxide layer) is provided between the floating gate and the substrate.

[0045] Based on the tunneling (Fowler-Nordheim, FN) effect, when a high potential (i.e., programming voltage, exemplary, programming voltage is 20V) is applied to the control gate, a conductive channel (referred to as a channel) can be formed between the source (source, S) and drain (drain, D) of the floating gate transistor, and when a low potential (i.e., programming selection voltage, exemplary programming selection voltage is 0V) is applied to the substrate, a large potential difference is formed between the control gate and the channel, so that the charge in the channel passes through the tunneling layer and enters the floating gate. This process is called a programming operation. At the same time, since the tunneling layer isolates the floating gate from the substrate, and the insulating layer isolates the floating gate from the control gate, the floating gate can maintain the charge for a long time without losing the charge even in the case of power failure, thereby realizing the power failure without losing the data. Only when a high potential is applied to the substrate and a low potential is applied to the control gate, can the charge in the floating gate pass through the tunneling layer and enter the substrate. This process is called an erase operation.

[0046] The electric field generated by the charge stored in the floating gate further affects the threshold voltage of the floating gate transistor. Generally, the more charge stored in the floating gate, the greater the threshold voltage of the floating gate transistor. When the threshold voltage of the floating gate transistor is greater than a threshold, it is recognized as data "0", and when the threshold voltage is less than a threshold, it is recognized as data "1", thereby being able to represent different storage information. Furthermore, by setting multiple threshold voltages, the storage cells can be divided into MLC (one storage cell can store 2 bits of data, storing 00, 01, 10 and 11), TLC (one storage cell can store 3 bits of data, storing 000, 001, 010, 011, 100, 101, 110 and 111) and QLC (one storage cell can store 4 bits of data, storing 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 and 1111), so that one storage cell can store more data.

[0047] Figure 1 A possible waveform diagram of conventional ISSP programming of a memory with multiple programming levels is shown. The waveform diagram shows two programming cycles, each of which includes a programming phase and a verification phase.

[0048] In the programming stage of a programming cycle, a programming voltage Vpgm1 is applied to the selected word line, a turn-on voltage Von is applied to the selected top selection line (correspondingly, a turn-off voltage Voff is applied to the non-selected top selection line), a pass voltage Vpass1 is applied to the non-selected word line, a pseudo word line pass voltage Vpass-dmy1 is applied to the pseudo word line, and a turn-off voltage Voff is applied to the bottom selection line; at the same time, a programming selection voltage Vss is applied to the bit lines (such as BL1 and BL2) coupled to the memory cell string where the memory cells that need to be programmed are located, and correspondingly, a programming inhibition voltage Vinhibit is applied to the bit lines (such as BL3) coupled to the memory cell string where the memory cells that do not need to be programmed are located.

[0049] Different from the programming stage, in the verification stage of a programming cycle, the verification voltage Vverify1 is applied to the selected word line, the bit line verification voltage Vbl is applied to all bit lines, the verification pass voltage Vpass3 is applied to the non-selected word line and the pseudo word line, and the turn-on voltage Von is applied to the bottom selection line. In the verification stage, if the verification fails, the next programming cycle is entered. In the next programming cycle, the programming voltage Vpgm1, the pass voltage Vpass1 and the pseudo word line pass voltage Vpass-dmy1 increase the incremental step pulse, that is, Vpgm1 is increased to Vpgm2, Vpass1 is increased to Vpass2, and Vpass-dmy1 is increased to Vpass-dmy2, and this is repeated for multiple cycles.

[0050] When ISPP is used to program memories with multiple programming levels such as MLC (four levels from L0 to L3, where L0 is the erased state, and L0-level storage cells do not need to be programmed and verified), TLC (eight levels from L0 to L7), or QLC (sixteen levels from L0 to L15), programming storage cells at different programming levels often requires a different number of programming cycles, and each programming cycle requires a ramp-up time and a ramp-down time for the programming voltage as well as a ramp-up time and a ramp-down time for the verification voltage, which results in a longer programming time for the memory, and thus has the defect of affecting the data writing speed of the memory.

[0051] When programming a memory having multiple programming levels, such as an MLC, TLC or QLC, the embodiments of the present application continuously programs multiple different programming levels in the programming phase of the first programming cycle, thereby reducing the ramp-up time and ramp-down time of the programming voltage in the programming cycle and improving the programming speed of the memory having multiple programming levels.

[0052] like Figure 2 As shown, the embodiment of the present application provides a memory system, including a memory controller 210 and a memory 220, wherein the memory controller 210 is used to store data in the memory 220 or read data from the memory 220. The memory system 200 can be applied to and packaged in different types of electronic devices, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, servers, and any other electronic devices that can store data.

[0053] Of course, the storage controller 210 may also perform any other suitable functions, such as formatting the memory 220; for example, the storage controller 210 may communicate with an external device (e.g., a host) through at least one of various interface protocols. The interface protocol may include at least one of a universal serial bus (USB) protocol, a multi-media card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0054] Specifically, Figure 3 As shown, the memory 220 includes a peripheral circuit 310 and a memory cell array 320 .

[0055] The peripheral circuit 310 is used to control the memory cell array 320. The peripheral circuit 310 includes an I / O interface 311, a control logic unit 312, a row decoder 313, a voltage generator 314, a column decoder 315, a page buffer 316, a data bus 317, and a register 318. It should be understood that in some examples, the peripheral circuit 310 may also include Figure 3 Additional circuitry not shown.

[0056] The I / O interface 311 may be coupled to the control logic unit 312 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 312, and to buffer status information received from the control logic unit 312 and relay them to the host. The I / O interface 311 may also be coupled to the column decoder 315 via the data bus 317 and act as a data I / O interface 311 and a data buffer to buffer data and relay them to or from the memory cell array 320.

[0057] The control logic unit 312 controls the row decoder 313, the column decoder 315, the page buffer 316, and the voltage generator 314 in response to a command (CMD) and an address from the I / O circuit; wherein the command may be a programming command and a read command. In addition, the control logic unit 312 may perform a programming operation to program the memory cell array 320 to a desired programming level.

[0058] The row decoder 313 is controlled by the control logic unit 312, and selects / deselects a memory cell block of the memory cell array 320, and selects / deselects a word line of the block. The row decoder 313 may also drive the word line using a word line voltage generated from the voltage generator 314. In some embodiments, the row decoder 313 may also select / deselect a top selection line and a bottom selection line, and drive the top selection line and the bottom selection line using a selection voltage generated from the voltage generator 314.

[0059] The voltage generator 314 is controlled by the control logic unit 312 to generate various voltages for performing operations such as erasing, programming, reading, writing and verifying on the memory cell array 320, such as the programming voltage Vpgm, the pass voltage Vpass, the read voltage Vread and the verification voltage Vverify applied to the word line, as well as the programming inhibit voltage Vinhibit and the programming select voltage Vss applied to the bit line.

[0060] The column decoder 315 is controlled by the control logic unit 312 and selects one or more memory cell strings 410 (eg, Figure 4 shown).

[0061] The page buffer 316 reads data from the memory cell array 320 and programs (writes) data to the memory cell array 320 according to the control signal from the control logic unit 312. In one example, the page buffer 316 can store the programming data (write data) to be programmed into the memory cell array 320. In another example, the page buffer 316 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer 316 can also detect a low-power signal from a bit line representing a data bit stored in the memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation.

[0062] Registers 318 may be coupled to the control logic unit 312 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address.

[0063] Those skilled in the art should understand that the operations performed by the row decoder 313, the page buffer 316, the control logic unit 312, and the voltage generator 314 described in the present application may be performed by a processing circuit, wherein the processing circuit may include but is not limited to hardware of a logic circuit or a hardware / software combination of a processor that executes software.

[0064] Figure 4 A possible memory cell array is shown. The memory cell array 320 includes a plurality of memory cell strings 410; wherein N memory cell strings 410 arranged along a first direction form a row of memory cell strings 410, and M rows of memory cell strings 410 are arranged along a second direction perpendicular to the first direction; illustratively, N=3, M=3.

[0065] like Figure 5 As shown, the memory cell string 410 includes a top select gate (TSG) 511 , a dummy (DMY) memory cell 512 , a plurality of memory cells, and a bottom select gate (BSG) 513 which are sequentially connected in series.

[0066] Combination Figure 4 and Figure 5 For N memory cell strings 410 in the same row, the gates of the top selection transistors 511 in the memory cell strings 410 are all coupled to the same top selection line (string select line, SSL); illustratively, the first row ( Figure 4N memory cell strings 410 (end of the second direction in the memory cell string) are coupled to SSL1. The gates of the bottom selection tubes 513 in the memory cell string 410 are all coupled to the bottom selection line (ground select line, GSL). The control gates of the dummy memory cells 512 in the memory cell string 410 and the control gates of the dummy memory cells 512 at corresponding positions in other memory cell strings 410 are coupled to the same dummy word line (dummy word line, DWL); illustratively, in the order from the top selection tube 511 to the bottom selection tube 513, the control gates of the first dummy memory cells 512 in the memory cell string 410 and the control gates of the first dummy memory cells 512 in other memory cell strings 410 are coupled to DWL1. Similarly, the control gates of the memory cells in the memory cell string 410 and the control gates of the memory cells at the corresponding positions in other memory cell strings 410 are coupled to the same wordline (WL); illustratively, the control gate of the first memory cell in the memory cell string 410 and the control gates of the first memory cells in other memory cell strings 410 are coupled to WL1 in the order from the top selection tube 511 to the bottom selection tube 513. Multiple memory cells coupled to the same wordline are referred to as a memory cell page 520.

[0067] For the M rows of memory cell strings 410 arranged along the second direction, the M rows of memory cell strings 410 are coupled via bit lines (BL). There are N bit lines, and each bit line is coupled to the drain of the top selection tube 511 in the M memory cell strings 410 along the second direction; for example, the leftmost ( Figure 4 The memory cell string 410 at the beginning of the first direction in the memory cell string 410 is coupled to BL1. The source of the bottom selection transistor 513 in the memory cell string 410 is coupled to a common source line (CSL), which can also be called an array common source (ACS) and is grounded.

[0068] like Figure 6 As shown in one embodiment of the present application, in the programming phase of the first programming cycle, the row decoder 313 selects the word line (eg Figure 5WL4 in the program cycle) continuously applies multiple programming voltages with increasing voltage values. Exemplarily, in the programming stage of the first programming cycle, the row decoder 313 sequentially and continuously applies the first programming voltage Vpgm1 and the second programming voltage Vpgm2 to the selected word line, and the second programming voltage Vpgm2 is greater than the first programming voltage Vpgm1. The selected word line is coupled to the control gates of the first storage cell 521 and the second storage cell 522. Among them, the threshold voltage for programming the second storage cell 522 is higher than the threshold voltage for programming the first storage cell 521 (that is, the second target programming level of the second storage cell 522 is higher than the first target programming level of the first storage cell 521). In the embodiment of the present application, the selected word line can also be referred to as selected WL.

[0069] When the first program voltage Vpgm1 is applied, the peripheral circuit 310 programs the first memory cell 521 and the second memory cell 522 .

[0070] Specifically, when the row decoder 313 provides the first programming voltage Vpgm1 to the selected word line, the page buffer 316 applies the first bit line voltage to the first bit line BL1 and the second bit line BL2; the first bit line BL1 is coupled to the storage cell string 410 where the first storage cell 521 is located, and the second bit line BL2 is coupled to the storage cell string 410 where the second storage cell 522 is located. The first bit line voltage is the programming selection voltage Vss, and illustratively, the programming selection voltage Vss is 0V. At this time, the control gate of the first storage cell 521 and the channel have a large potential difference, so that the charge (free electron) can tunnel into the floating gate of the first storage cell 521; the control gate of the second storage cell 522 and the channel also have a large potential difference, so that the charge can also tunnel into the floating gate of the second storage cell 522. Thereby, the first storage cell 521 and the second storage cell 522 are programmed by the first programming voltage Vpgm1.

[0071] For 3D NAND flash memory, in addition to the first storage cell 521, the storage cell string 410 where the first storage cell 521 is located also includes a plurality of non-selected storage cells, a dummy storage cell 512, and a top selection transistor 511, etc.; similarly, in addition to the second storage cell 522, the storage cell string 410 where the second storage cell 522 is located also includes a plurality of non-selected storage cells, a dummy storage cell 512, and a top selection transistor 511, etc. The word line to which the control gate of the non-selected storage cell in the storage cell string 410 where the first storage cell 521 is located and the control gate of the non-selected storage cell in the storage cell string 410 where the second storage cell 522 is located is coupled is a non-selected word line (e.g. Figure 5The dummy word line (e.g., WL1, WL2, WL3, WL5, and WL6 in the memory cell string 410) to which the dummy memory cell 512 in the memory cell string 410 where the first memory cell 521 is located and the dummy memory cell 512 in the memory cell string 410 where the second memory cell 522 is located are coupled. Figure 5 The top selection line coupled to the top selection tube 511 in the storage unit where the first storage unit 521 is located and the top selection tube 511 in the storage unit where the second storage unit 522 is located is the selected top selection line (for example Figure 4 In the embodiment of the present application, the unselected word line may also be referred to as unselected WL; the selected top selection line may also be referred to as selected SSL.

[0072] Therefore, different from 2D NAND flash memory, when the row decoder 313 provides the first programming voltage Vpgm1 to the selected word line, for programming of 3D NAND flash memory, the row decoder 313 also needs to provide the first pass voltage Vpass1 to the non-selected word line, the first pass voltage Vpass1 is less than the first programming voltage Vpgm1 (exemplarily, the first pass voltage Vpass1 is 10V, and the first programming voltage Vpgm1 is 20V), and provide the on-voltage Von to the selected top selection line (exemplarily, the on-voltage Von is 3V), and provide the first dummy word line pass voltage Vpass-dmy1 to the dummy word line. Thus, it is ensured that there is a large potential difference between the control gate and the channel of the first storage unit 521 and the second storage unit 522.

[0073] In addition, the row decoder 313 also needs to send a signal to non-selected top selection lines (eg, Figure 4 The off voltage Voff is applied to the SSL2 and SSL3 in the memory cell string 410, and the unselected top selection line and the selected top selection line are coupled to the gates of the top selection tubes 511 in different memory cell strings 410. In the embodiment of the present application, the unselected top selection line can also be referred to as unselected SSL.

[0074] That is, in the programming stage of the first programming cycle, when the peripheral circuit 310 applies the first programming voltage Vpgm1 to the selected word line through the row decoder 313, it also applies the first pass voltage Vpass1 to the non-selected word line through the row decoder 313, applies the first pseudo word line pass voltage Vpass-dmy1 to the pseudo word line, applies the turn-on voltage Von to the selected top selection line, and applies the turn-on voltage Voff to the non-selected top selection line; and combines with the page buffer 316 to apply the programming selection voltage Vss to the first bit line BL1 coupled to the storage cell string 410 where the first storage cell 521 is located and the second bit line BL2 coupled to the storage cell string 410 where the second storage cell 522 is located.

[0075] It should be understood that for the third storage cell 523 with level L0 (i.e., erased state) in the selected word line, it is also necessary to apply a program inhibition voltage Vinhibit to the third bit line BL3 coupled to the storage cell string 410 where the third storage cell 523 is located through the page buffer 316. The program inhibition voltage Vinhibit is greater than the program selection voltage Vss. Exemplarily, the program inhibition voltage Vinhibit is 3 V. Thus, the third storage cell 523 reduces the potential difference between the control gate and the channel of the third storage cell 523 through a self-boosting program inhibition (SBPI) mechanism, reduces the possibility of charge tunneling, and thus prevents the third storage cell 523 from being programmed.

[0076] When the second program voltage Vpgm2 is applied, the peripheral circuit 310 programs the second memory cell 522 and blocks programming of the first memory cell 521 .

[0077] Regarding selecting to program the second storage cell 522, specifically, when the row decoder 313 provides the second programming voltage Vpgm2 to the selected word line, the page buffer 316 keeps applying the first bit line voltage (i.e., the programming selection voltage Vss) to the second bit line BL2, and applies the second bit line voltage to the first bit line BL1, and the second bit line voltage is the programming inhibition voltage Vinhibit.

[0078] Furthermore, when the row decoder 313 provides the second programming voltage Vpgm2 to the selected word line, the row decoder 313 also provides the second pass voltage Vpass2 to the non-selected word line, and the second pass voltage Vpass2 is greater than the first pass voltage Vpass1. For the same programming inhibition voltage Vinhibit, compared with the first pass voltage Vpass1, the second pass voltage Vpass2 can make the first storage unit 521 have a higher channel potential. Therefore, when the first programming voltage Vpgm1 is increased to the second programming voltage Vpgm2, the potential difference between the control gate and the channel of the first storage unit 521 can be better controlled so that the charge will not tunnel, thereby overcoming the program interference caused by the second programming voltage Vpgm2 to a certain extent.

[0079] For the pseudo word line, it can be controlled similarly to the non-selected word line. That is, when the row decoder 313 provides the second programming voltage Vpgm2 to the selected word line, it also provides the second pseudo word line pass voltage Vpass-dmy2 to the pseudo word line; and the second pseudo word line pass voltage Vpass-dmy2 is greater than the first pseudo word line pass voltage Vpass-dmy1.

[0080] That is, in contrast to applying the first programming voltage Vpgm1 to the selected word line, when the second programming voltage Vpgm2 is applied to the selected word line through the row decoder 313, the page buffer 316 applies the programming inhibit voltage Vinhibit to the first bit line BL1, while maintaining the application of the programming selection voltage Vss to the second bit line BL2; the row decoder 313 applies the second pass voltage Vpass2 to the non-selected word line, and applies the second pseudo word line pass voltage Vpass-dmy2 to the pseudo word line.

[0081] In another embodiment of the present application, when the row decoder 313 applies the first programming voltage Vpgm1 to the selected word line, the peripheral circuit 310 may also only program the first memory cell 521. At this time, the page buffer 316 only applies the programming selection voltage Vss to the first bit line BL1 coupled to the memory cell string 410 where the first memory cell 521 is located. When the row decoder 313 applies the second programming voltage Vpgm2 to the selected word line, the peripheral circuit 310 programs the second memory cell 522 and prevents the second memory cell 522 from being programmed.

[0082] Furthermore, when programming a memory device with multiple programming levels such as MLC, TLC or QLC, the embodiments of the present application can also continuously complete the verification of multiple programming levels in the verification phase of the first programming cycle, thereby reducing the ramp-up time and ramp-down time of the programming voltage and the ramp-up time and ramp-down time of the verification voltage in the programming cycle, thereby improving the programming speed of the memory device with multiple programming levels.

[0083] Specifically, Figure 6 As shown, in the verification phase of the first programming cycle, the row decoder 313 continuously applies multiple verification voltages to the selected word line. For example, in the verification phase of the first programming cycle, the row decoder 313 continuously applies the first verification voltage Vverify1 and the second verification voltage Vverify2 to the selected word line; the first verification voltage Vverify1 is configured to verify whether the first storage cell 521 reaches the first target programming level, and the second verification voltage Vverify2 is configured to verify whether the second storage cell 522 reaches the second target programming level.

[0084] Specifically, when the row decoder 313 provides the first verification voltage Vverify1 to the selected word line, the page buffer 316 applies the bit line verification voltage Vbl to the first bit line BL1 and the second bit line BL2; of course, the page buffer 316 can also apply the bit line verification voltage Vbl to all bit lines (i.e., the first bit line BL1, the second bit line BL2, and the third bit line BL3). Thus, the bit line verification voltage Vbl is loaded on the drain of the first storage cell 521, and the source of the first storage cell 521 is grounded. At this time, if the first storage cell 521 reaches the first target programming level, the threshold voltage of the first storage cell 521 should be greater than the first verification voltage Vverify1, so the first storage cell 521 is turned off (no current in the channel or a small current is leaked) under the first verification voltage Vverify1, so that the charge accumulated at the sensing node coupled to the first bit line BL1 during the sensing time (Tsense) cannot be discharged through the first bit line BL1 and the channel. After the sensing time, the total discharge amount of the sensing node coupled to the first bit line BL1 is small, and no significant voltage drop occurs at the sensing node. That is, after the sensing time, if no significant voltage drop occurs at the sensing node coupled to the first bit line BL1, the first storage cell 521 reaches the first target programming level.

[0085] Similarly, when the row decoder 313 provides the second verification voltage Vverify2 to the selected word line, if the second storage cell 522 reaches the second target programming level, the second storage cell 522 is cut off under the second verification voltage Vverify2, so that after the sensing time, no obvious voltage drop occurs at the sensing node coupled to the second bit line BL1.

[0086] Similarly, unlike 2D NAND flash memory, when the row decoder 313 provides the first verification voltage Vverify1 and the second verification voltage Vverify2 to the selected word line, for the verification of the 3D NAND flash memory, the row decoder 313 also provides the on-voltage Von to the selected top selection line and the bottom selection line GSL coupled to the bottom selection tube 513 of the storage cell string 410, and provides the off-voltage Voff to the non-selected top selection line, and provides the verification pass voltage Vpass3 to the non-selected word line.

[0087] It should be understood that the continuous application of multiple programming voltages with increasing voltage values ​​to the selected word line is not limited to the first programming voltage Vpgm1 and the second programming voltage Vpgm2 provided in the implementation of the present application, but may also include a third programming voltage Vpgm3 and a fourth programming voltage Vpgm4, etc.; the continuous application of multiple verification voltages to the selected word line is not limited to the first verification voltage Vverify1 and the second verification voltage Vverify2, but may also include a third verification voltage Vverify3 and a fourth verification voltage Vverify4, etc.

[0088] When the peripheral circuit 310 is working, the following steps are performed: Figure 7 The programming method shown in the figure performs step S1 in the programming phase of the first programming cycle.

[0089] S1. Continuously apply a first programming voltage and a second programming voltage to a selected word line.

[0090] The threshold voltage for programming the second storage unit 522 is higher than the threshold voltage for programming the storage unit, and the selection word line is coupled to the first storage unit 521 and the second storage unit 522. Specifically, the second programming voltage is greater than the first programming voltage; that is, in the programming phase of the first programming cycle, a programming voltage with an increasing voltage is continuously applied to the selection word line.

[0091] Specifically, step S1 can be divided into sub-step S11 and sub-step S12.

[0092] S11 , when a first programming voltage is applied, the first memory cell 521 and the second memory cell 522 are programmed.

[0093] It can also be said that in response to applying the first programming voltage to the selection word line, the first storage unit 521 and the second storage unit 522 are programmed. The first storage unit and the second storage unit 522 are programmed by the first programming voltage; specifically, when the first programming voltage is applied to the selection word line, the first bit line voltage (i.e., the programming selection voltage) is applied to the first bit line coupled to the storage cell string 410 where the first storage unit 521 is located, and the second bit line coupled to the storage cell string 410 where the second storage unit 522 is located.

[0094] For 3D NAND, programming the first storage cell 521 and the second storage cell 522 also requires: applying a turn-on voltage to the top selection tube 511 of the storage cell string 410 where the first storage cell 521 is located, and the selected top selection line coupled to the top selection tube 511 of the storage cell string 410 where the second storage cell 522 is located; and applying a first pass voltage to the non-selected storage cells in the storage cell string 410 where the first storage cell 521 is located, and the non-selected word line coupled to the non-selected storage cells in the storage cell string 410 where the second storage cell 522 is located; and applying a first pseudo word line pass voltage to the pseudo word line coupled to the dummy storage cell 512 in the storage cell string 410 where the first storage cell 521 is located, and the dummy storage cell 512 in the storage cell string 410 where the second storage cell 522 is located.

[0095] It should be understood that when a turn-on voltage is applied to the selected top selection line, a turn-off voltage also needs to be applied to non-selected top selection lines other than the selected top selection line. The non-selected top selection lines and the selected top selection line are coupled to top selection tubes 511 of different storage cell strings 410.

[0096] S12. When a second programming voltage is applied, the second memory cell 522 is programmed, and the first memory cell 521 is prevented from being programmed.

[0097] It can also be said that in response to applying the second programming voltage to the selected word line, the second storage cell 522 is programmed, and the first storage cell 521 is prevented from being programmed. The second programming voltage only programs the second storage cell 522; the difference from applying the first programming voltage to the selected word line is that when the first programming voltage is applied to the selected word line, the first bit line voltage is kept applied to the second bit line, and the second bit line voltage (i.e., programming inhibition voltage) is applied to the first bit line. At this time, the potential difference between the control gate and the channel of the second storage cell 522 can enable the charge to tunnel into the floating gate of the second storage cell 522, so as to continue programming the second storage cell 522 to program the second storage cell 522 to a higher programming level. However, due to the SBPI mechanism, under the action of the second bit line voltage, the channel potential of the first storage cell 521 is increased, thereby ensuring that there is a lower potential difference between the control gate and the channel of the first storage cell 521 to prevent the charge from tunneling, thereby preventing the first storage cell 521 from being programmed.

[0098] Further, when the second programming voltage is applied to the selected word line, the second pass voltage is applied to the non-selected word line, and the second pass voltage is greater than the first pass voltage. For the same programming inhibition voltage, the second pass voltage can make the first storage unit 521 have a higher channel potential than the first pass voltage. When the first programming voltage is increased to the second programming voltage, it can be ensured to a certain extent that the potential difference between the control gate and the channel of the first storage unit 521 is not increased, thereby reducing the possibility of charge tunneling into the floating gate of the first storage unit 521, and thus better overcoming the programming interference of the second programming voltage on the first storage unit 521.

[0099] Furthermore, during the verification phase of the first programming cycle, the programming method further performs step S2.

[0100] S2, continuously applying a first verification voltage and a second verification voltage to the selected word line.

[0101] Specifically, the first verification voltage is configured to verify whether the first storage cell 521 reaches the first target programming level. When the first verification voltage is applied to the selected word line, the bit line verification voltage is also applied to the first bit line. If the first storage cell 521 reaches the first target programming level, the first storage cell 521 is cut off under the first verification voltage; thus, the total discharge amount of the sensing node coupled to the first bit line BL1 is small after the sensing time, and no obvious voltage drop occurs at the sensing node.

[0102] The second verification voltage is configured to verify whether the second storage cell 522 reaches the second target programming level. Similarly, when the second verification voltage is applied to the selected word line, the bit line verification voltage is also applied to the second bit line. If the second storage cell 522 reaches the second target programming state programming level, no significant voltage drop occurs at the sensing node coupled to the second bit line BL2.

[0103] At the same time, for the verification of 3D NAND flash memory, when the first verification voltage and the second verification voltage are continuously applied to the selected word line, a third pass voltage is also applied to the non-selected word line, a turn-on voltage is applied to the selected top selection line and the bottom selection line, and an off voltage is applied to the non-selected top selection line.

[0104] like Figure 6As shown, the programming cycle also includes a preprocessing stage, which is located between the programming stage of the current programming cycle and the verification stage of the current programming cycle. Specifically, after the programming stage of the current programming cycle and before the verification stage of the current programming cycle, a prepulse voltage is applied to the selected top selection line and the non-selected top selection line; the prepulse voltage applied to the selected top selection line can be a turn-on voltage. To extract or neutralize the electrons remaining in the channel of the memory cell string coupled to the selected top selection line and the memory cell string coupled to the non-selected top selection line, thereby reducing the influence of the electrons remaining in the channel on the verification stage of the current programming cycle.

[0105] The programming cycle also includes a post-processing stage, which is located between the verification stage of the current programming cycle and the programming stage of the next programming cycle. Specifically, after the verification stage of the current programming cycle and before the programming stage of the next programming cycle, a post-pulse voltage is applied to the selected top selection line and the non-selected top selection line to extract or neutralize the electrons remaining in the channel of the memory cell string coupled to the selected top selection line and the memory cell string coupled to the non-selected top selection line, thereby reducing the influence of the electrons remaining in the channel on the programming stage of the next programming cycle.

[0106] In addition, the post-processing stage includes a recovery stage. In some embodiments, the recovery stage restores the voltages of the selected word lines, non-selected word lines, selected top selection lines, non-selected top selection lines, and all bit lines to an initial voltage, which may be 0V.

[0107] The memory programming method, memory and memory system provided by the embodiments of the present application continuously apply the first programming voltage and the second programming voltage to the selected word line in the programming phase of the first programming cycle to complete the programming of the two programming levels, thereby reducing the ramp-up time and ramp-down time of the programming voltage; continuously apply the first verification voltage and the second verification voltage to the selected word line in the verification phase of the first programming cycle to complete the verification of the two programming levels, thereby reducing the ramp-up time and ramp-down time of the verification voltage. Therefore, when programming a memory with multiple programming levels such as MLC, TLC or QLC, the present application can better reduce the programming time of the memory, thereby improving the programming speed of the memory with multiple programming levels.

[0108] The present application embodiment provides a computer-readable storage medium, which stores computer-executable instructions; after the computer-executable instructions are executed, the following can be achieved: Figure 7 The method in .

[0109] The embodiment of the present application provides a computer device, including a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions. When the executable instructions are executed by the processor, the following can be achieved: Figure 7 The method in .

[0110] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and for the parts not described in detail in a certain embodiment, reference can be made to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0111] In the several embodiments provided in the present application, it should be understood that the provided programming method and memory can be implemented in other ways. For example, the division of a module is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0112] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0113] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory programming method, characterized in that: include: In a programming phase of a first programming cycle, a first programming voltage and a second programming voltage are continuously applied to a selected word line, wherein the second programming voltage is greater than the first programming voltage; The selection word line is coupled to the first memory cell and the second memory cell; When the first programming voltage is applied, programming the first memory cell and the second memory cell; When the second programming voltage is applied, the second memory cell is programmed and the first memory cell is blocked from being programmed.

2. The programming method according to claim 1, characterized in that: The programming method also includes: During the verification phase of the first programming cycle, a first verification voltage and a second verification voltage are continuously applied to the selection word line; the first verification voltage is configured to verify whether the first storage cell reaches a first target programming level, and the second verification voltage is configured to verify whether the second storage cell reaches a second target programming level.

3. The programming method according to claim 1, characterized in that: The programming of the first storage unit and the second storage unit specifically includes: A first bit line voltage is applied to a first bit line and a second bit line; the first bit line is coupled to a memory cell string where the first memory cell is located, and the second bit line is coupled to a memory cell string where the second memory cell is located.

4. The programming method according to claim 3, characterized in that: The programming of the first storage unit and the second storage unit further includes: Applying a first pass voltage to a non-selected word line, wherein the non-selected word line is coupled to a non-selected memory cell in the memory cell string where the first memory cell is located, and a non-selected memory cell in the memory cell string where the second memory cell is located; Furthermore, a conduction voltage is applied to a selected top selection line, wherein the selected top selection line is coupled to a top selection tube of a storage cell string where the first storage cell is located, and a top selection tube of a storage cell string where the second storage cell is located.

5. The programming method according to claim 4, characterized in that: The programming of the second storage unit and preventing programming of the first storage unit specifically include: The first bit line voltage is applied to the second bit line, and a second bit line voltage is applied to the first bit line; the second bit line voltage is greater than the first bit line voltage.

6. The programming method according to claim 5, characterized in that: The step of programming the second storage cell and preventing programming of the first storage cell further includes: A second pass voltage is applied to the non-selected word line, the second pass voltage being greater than the first pass voltage.

7. The programming method according to claim 2, characterized in that: The memory cell string where the first memory cell is located is coupled to a first bit line, and the memory cell string where the second memory cell is located is coupled to a second bit line; the first verification voltage and the second verification voltage are continuously applied to the selection word line, and further includes: A bit line verification voltage is applied to the first bit line and the second bit line.

8. The programming method according to claim 7, characterized in that: The non-selected memory cells in the memory cells where the first memory cell is located and the non-selected memory cells in the memory cells where the second memory cell is located are coupled to the non-selected word line, the top selection tube in the memory cells where the first memory cell is located and the top selection tube in the memory cells where the second memory cell is located are coupled to the selected top selection line, and the bottom selection tube in the memory cells where the first memory cell is located and the bottom selection tube in the memory cells where the second memory cell is located are coupled to the bottom selection line; The method of continuously applying a first verification voltage and a second verification voltage to the selected word line further comprises: applying a third pass voltage to the non-selected word lines; A turn-on voltage is applied to the selected top selection line and the bottom selection line.

9. The programming method according to any one of claims 4 to 8, characterized in that: When applying a turn-on voltage to the selected top selection line, the programming method further includes: An off voltage is applied to non-selected top selection lines other than the selected top selection line, and the non-selected top selection lines and the selected top selection line are coupled to top selection tubes of different memory cell strings.

10. A memory, characterized in that: include: A memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured as follows: In a programming phase of a first programming cycle, a first programming voltage and a second programming voltage are sequentially applied to a selected word line, wherein the second programming voltage is greater than the first programming voltage; The selection word line is coupled to the first memory cell and the second memory cell; When the first programming voltage is applied, programming the first memory cell and the second memory cell; When the second programming voltage is applied, the second memory cell is programmed and the first memory cell is blocked from being programmed.

11. The memory according to claim 10, characterized in that: The peripheral circuit is further configured as: During the verification phase of the first programming cycle, a first verification voltage and a second verification voltage are continuously applied to the selection word line; the first verification voltage is configured to verify whether the first storage cell reaches a first target programming level, and the first verification voltage is configured to verify whether the second storage cell reaches a second target programming level.

12. The memory according to claim 10, characterized in that: The programming of the first storage unit and the second storage unit, the peripheral circuit is specifically configured as follows: A first bit line voltage is applied to a first bit line and a second bit line; the first bit line is coupled to a memory cell string where the first memory cell is located, and the second bit line is coupled to a memory cell string where the second memory cell is located.

13. The memory according to claim 12, characterized in that: The first storage unit and the second storage unit are programmed, and the peripheral circuit is further configured as follows: Applying a first pass voltage to a non-selected word line, wherein the non-selected word line is coupled to a non-selected memory cell in the memory cell string where the first memory cell is located, and a non-selected memory cell in the memory cell string where the second memory cell is located; Furthermore, a conduction voltage is applied to a selected top selection line, wherein the selected top selection line is coupled to a top selection tube of a storage cell string where the first storage cell is located, and a top selection tube of a storage cell string where the second storage cell is located.

14. The memory according to claim 13, characterized in that: The programming of the second storage unit and the prevention of programming of the first storage unit, the peripheral circuit is specifically configured as follows: The first bit line voltage is applied to the second bit line, and a second bit line voltage is applied to the first bit line; the second bit line voltage is greater than the first bit line voltage.

15. The memory according to claim 14, characterized in that: The second storage unit is programmed and the first storage unit is prevented from being programmed, and the peripheral circuit is further configured to: A second pass voltage is applied to the non-selected word line, the second pass voltage being greater than the first pass voltage.

16. The memory according to claim 11, characterized in that: The storage cell string where the first storage cell is located is coupled to a first bit line, and the storage cell string where the second storage cell is located is coupled to a second bit line; the first verification voltage and the second verification voltage are continuously applied to the selection word line, and the peripheral circuit is further configured as follows: A bit line verification voltage is applied to the first bit line and the second bit line.

17. The memory according to claim 16, characterized in that: The non-selected memory cells in the memory cells where the first memory cell is located and the non-selected memory cells in the memory cells where the second memory cell is located are coupled to the non-selected word line, the top selection tube in the memory cell where the first memory cell is located and the top selection tube in the memory cell where the second memory cell is located are coupled to the selected top selection line, and the bottom selection tube in the memory cell where the first memory cell is located and the bottom selection tube in the memory cell where the second memory cell is located are coupled to the bottom selection line; the first verification voltage and the second verification voltage are continuously applied to the selected word line, and the peripheral circuit is further configured as: applying a third pass voltage to the non-selected word lines; A turn-on voltage is applied to the selected top selection line and the bottom selection line.

18. The memory according to any one of claims 13 to 17, characterized in that: When a turn-on voltage is applied to the selected top selection line, the peripheral circuit is further configured to: An off voltage is applied to non-selected top selection lines other than the selected top selection line, and the non-selected top selection lines and the selected top selection line are coupled to top selection tubes of different memory cell strings.

19. A memory system, characterized in that: The invention comprises a storage controller and the memory according to any one of claims 10 to 18, wherein the storage controller is configured to control the memory.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method described in any one of claims 1 to 9 can be implemented.

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