Memory device, operating method thereof, and method of operating memory controller

Abstract

The present disclosure provides a memory device for performing bad block check, a method of operating the memory device, and a method of operating a memory controller in communication with the memory device. The memory device may include: a first region including first memory cells; a second region including a second memory cell, the first memory cell and the second memory cell coupled to a same word line; and a control circuit configured to perform a first operation on the first region and a second operation on the second region, and configured to store a first result indicating whether the first operation is successful and a second result indicating whether the second operation is successful.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0086452 filed on July 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a memory device, and more particularly, to a memory device for performing bad block checking, a method of operating a memory device, and a method of operating a memory controller communicating with the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device that stores data and a storage controller that controls the memory device. The memory device may be classified into a volatile memory device and a non-volatile memory device.

[0005] A nonvolatile memory device may include bad blocks that cannot guarantee normal operation. The nonvolatile memory device may designate memory blocks that cannot guarantee normal operation as bad blocks during operation. Summary of the invention

[0006] Embodiments of the present disclosure may provide a memory device. The memory device may include: a first region including a first memory cell; a second region including a second memory cell, the first memory cell and the second memory cell being coupled to the same word line; and a control circuit configured to perform a first operation on the first region and a second operation on the second region, and configured to store a first result indicating whether the first operation is successful and a second result indicating whether the second operation is successful.

[0007] Embodiments of the present disclosure may provide a method for operating a storage controller that communicates with a nonvolatile memory device including a target block. The method may include: sending a first request for a first area of ​​the target block to the nonvolatile memory device, sending a second request for a second area of ​​the target block to the nonvolatile memory device, determining whether to process the target block as a bad block based on a first result indicating whether a first operation corresponding to the first request is successful and a second result indicating whether a second operation corresponding to the second request is successful, wherein the first area includes memory cells connected to a first pass gate group among memory cells of the target block, the second area includes memory cells connected to a second pass gate group among memory cells of the target block, and a plurality of pass gates in the first pass gate group and a plurality of pass gates in the second pass gate group are respectively connected to the same word line.

[0008] An embodiment of the present disclosure may provide a method for operating a memory device, the memory device including a memory block, the memory block including a first region and a second region. The method may include: performing a first operation corresponding to the first region, storing a first result indicating whether the first operation is successful, performing a second operation corresponding to the second region after storing the first result, storing a second result indicating whether the second operation is successful, and processing at least one of the first region and the second region as a failed region based on the first result and the second result, wherein the first region includes memory cells of the memory block connected to a first pass gate group, the second region includes memory cells of the memory block connected to a second pass gate group, and a plurality of pass gates in the first pass gate group and a plurality of pass gates in the second pass gate group are respectively connected to the same word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a storage system according to an embodiment of the present disclosure.

[0010] Figure 2 According to the embodiment of the present disclosure Figure 1 Detailed block diagram of the storage controller.

[0011] Figure 3 According to the embodiment of the present disclosure Figure 1 Detailed block diagram of a non-volatile memory device.

[0012] Figure 4 is a circuit diagram showing a memory block including a first region and a second region.

[0013] Figure 5 is a flowchart for explaining bad block checking according to an embodiment of the present disclosure.

[0014] Figure 6 is a flowchart for explaining bad block checking according to an embodiment of the present disclosure.

[0015] Figure 7 is a flowchart illustrating a method of operating a storage controller according to an embodiment of the present disclosure.

[0016] Figure 8 is a circuit diagram showing a memory block including a plurality of areas.

[0017] Fig. 9 is a flowchart illustrating a method of operating a storage controller according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The specific structure or functional description of the embodiments according to the concepts of the present disclosure introduced in this specification or this application is only used to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0019] In addition, terms such as "unit" and "module" or functional blocks depicted in the drawings may be implemented in the form of software configuration, hardware configuration, or a combination thereof. In order to clearly explain the technical spirit of the present disclosure, detailed descriptions of the same components will be omitted.

[0020] Various embodiments of the present disclosure relate to a memory device for performing bad block checking.

[0021] Figure 1 is a block diagram illustrating a storage system according to an embodiment of the present disclosure.

[0022] Reference Figure 1 , the storage system 10 may include a host 11 and a storage device 12. In some embodiments, the storage system 10 may be a computing system configured to process various types of information, such as a personal computer, a notebook computer, a laptop computer, a server, a workstation, a tablet personal computer (PC), a smart phone, a digital camera, and a black box.

[0023] The host 11 may control the overall operation of the storage system 10. For example, the host 11 may store data in the storage device 12, or may read data stored in the storage device 12. For example, the host 11 may provide write data to the storage device 12, or may request read data stored in the storage device 12 from the storage device 12.

[0024] The storage device 12 may include a storage controller 100 and a nonvolatile memory device 200. The nonvolatile memory device 200 may store data. The storage controller 100 may store data in the nonvolatile memory device 200 through a program operation or may read data stored in the nonvolatile memory device 200 through a read operation. The nonvolatile memory device 200 may operate under the control of the storage controller 100. For example, the storage controller 100 may store data in the nonvolatile memory device 200 or may read data stored in the nonvolatile memory device 200 based on a command CMD that determines an operation and an address ADD that determines a location of data.

[0025] The nonvolatile memory device 200 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a first region and a second region. For example, the first region may include memory cells located in the left portion of the corresponding memory block. The second region may include memory cells located in the right portion of the corresponding memory block. Figure 4 A detailed description of the first region and the second region is disclosed.

[0026] The nonvolatile memory device 200 may determine whether to apply a voltage to the first region or the second region in response to the first control signal and the second control signal. For example, the nonvolatile memory device 200 may prevent a voltage from being applied to the first region in response to the first control signal. The nonvolatile memory device 200 may prevent a voltage from being applied to the second region in response to the second control signal. Therefore, the nonvolatile memory device 200 may perform a read operation and a program operation on any one of the first region and the second region.

[0027] In some embodiments, the nonvolatile memory device 200 may be, but is not limited to, a NAND flash memory. Also, the nonvolatile memory device 200 may be one of various memory devices that can retain stored data even when power supply is interrupted, such as a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).

[0028] The memory controller 100 may include a bad block manager 110. The bad block manager 110 may perform a bad block check on the nonvolatile memory device 200. The bad block check may be an operation of determining whether at least one of a first region and a second region in a target block of the nonvolatile memory device 200 has failed. The failed region may refer to a region where the reliability of the memory cells in the corresponding region cannot be guaranteed, thereby preventing normal operation from being performed. The memory controller 100 may not perform a read operation or a program operation on the failed region. The memory controller 100 may output a signal for preventing a voltage from being applied to the failed region. When both the first region and the second region are determined to be failed, the target block may be processed as a bad block.

[0029] The bad block manager 110 may perform a bad block check on a target block suspected of being a bad block among the storage blocks in the nonvolatile memory device 200. For example, when an error occurs in a read operation performed on a target block even when a read retry operation is performed on the target block where an uncorrectable error correction code (UECC) occurs, the bad block manager 110 may perform a bad block check on the target block. Figure 5 In addition, when the programming operation on the target block fails, the bad block manager 110 may perform an erase operation on the target block and may perform a bad block check on the target block. Figure 6 Describe it in detail.

[0030] Figure 2 According to the embodiment of the present disclosure Figure 1 Detailed block diagram of the storage controller.

[0031] Reference Figure 1 and Figure 2 , the storage controller 100 may communicate with the host 11 and the non-volatile memory device 200. The storage controller 100 may include a bad block manager 110, a volatile memory device 120, a read-only memory (ROM) 130, a processor 140, an error correction code (ECC) engine 150, a host interface circuit 160, and a non-volatile memory interface circuit 170.

[0032] The bad block manager 110 may send a first request and a second request to the nonvolatile memory device 200. The first request may indicate that a first operation is performed on a first region. The first request may include a second control signal for preventing a voltage from being applied to a second region. The second request may indicate that a second operation is performed on a second region. The second request may include a first control signal for preventing a voltage from being applied to the first region. The first operation may be a read operation or a program operation. The second operation may be a read operation or a program operation.

[0033] In some embodiments, when a read retry operation on a target block fails, the bad block manager 110 may send a first request for performing a read operation on a first region and a second request for performing a read operation on a second region. When a program operation on a target block fails, after performing an erase operation on the target block, the bad block manager 110 may send a first request for performing a program operation on the first region and a second request for performing a program operation on the second region.

[0034] The bad block manager 110 may send a request for obtaining a first result and a second result to the nonvolatile memory device 200. The first result may indicate whether the first operation is successful. The second result may indicate whether the second operation is successful.

[0035] Based on the first result and the second result, the bad block manager 110 may determine whether to process at least one of the first region and the second region as a failed region.

[0036] For example, when the first result indicates that the first operation is successful and the second result indicates that the second operation fails, the bad block manager 110 may process the second area as a failed area. When the first result indicates that the first operation fails and the second result indicates that the second operation is successful, the bad block manager 110 may process the first area as a failed area. When the first result indicates that the first operation fails and the second result indicates that the second operation fails, the bad block manager 110 may process both the first area and the second area as failed areas. That is, the target block may be processed as a bad block.

[0037] The memory controller 100 may perform neither a read operation nor a program operation on a region processed as a fail region in the target block. The memory controller 100 may perform a read operation and a program operation on a region not processed as a fail region in the target block.

[0038] In some embodiments, the memory controller 100 may transmit a control signal for preventing a voltage from being applied to an area processed as a failed area. For example, when a first area is processed as a failed area, the memory controller 100 may transmit a first control signal for preventing a voltage from being applied to the first area during operation of the target block. When a second area is processed as a failed area, the memory controller 100 may transmit a second control signal for preventing a voltage from being applied to the second area during operation of the target block.

[0039] The volatile memory device 120 may be used as a main memory, a cache memory, or a working memory of the memory controller 100. For example, the volatile memory device 120 may be implemented as a static RAM (SRAM), a dynamic RAM (DRAM), or the like.

[0040] The ROM 130 may be used as a read-only memory for storing information required for the operation of the storage controller 100. The processor 140 may control the overall operation of the storage controller 100. The ECC engine 150 may detect errors in data read from the nonvolatile memory device 200 and may correct the errors. For example, the ECC engine 150 may have a certain level of error correction capability. For data having an error level (e.g., the number of flipped bits) exceeding the error correction capability, the ECC engine 150 may process the data as uncorrectable data.

[0041] The storage controller 100 may communicate with the host 11 through the host interface circuit 160. In some embodiments, the host interface circuit 160 may be implemented as at least one of various interfaces such as a serial ATA (SATA) interface, a peripheral component interconnect express (PCIe) interface, a serial attached SCSI (SAS) interface, a non-volatile memory express (NVMe) interface, and a universal flash storage (UFS) interface.

[0042] The memory controller 100 may communicate with the nonvolatile memory device 200 through the nonvolatile memory interface circuit 170. In some embodiments, the nonvolatile memory interface circuit 170 may be implemented based on a NAND interface.

[0043] Figure 3 According to the embodiment of the present disclosure Figure 1 Detailed block diagram of a non-volatile memory device.

[0044] In some embodiments, the nonvolatile memory device 200 may be a NAND flash memory-based nonvolatile memory device. However, the scope of the present disclosure is not limited thereto, and the nonvolatile memory device 200 may be any of various types of memory devices such as DRAM, SRAM, PRAM, MRAM, RRAM, and FRAM.

[0045] Reference Figure 3 , the nonvolatile memory device 200 may include a memory cell array 210 , a row decoder 220 , a voltage generating circuit 230 , a page buffer circuit 240 , an input / output (I / O) circuit 250 , and a control logic circuit 260 .

[0046] The memory cell array 210 may include a plurality of memory blocks. Each of the plurality of memory blocks may be divided into a first region and a second region. Figure 3 The row decoder 220 is shown as being located on the left side of the memory cell array 210, but the first region may include memory cells located on the left side of the row decoder 220. The second region may include memory cells located on the right side of the row decoder 220.

[0047] In an embodiment, the row decoder 220, the voltage generating circuit 230, the page buffer circuit 240, and the input / output circuit 250 may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array 210 under the control of the control logic circuit 260. The peripheral circuit may drive the memory cell array 210 to perform a program operation, a read operation, or an erase operation.

[0048] The row decoder 220 may be coupled to the memory cell array 210 through word lines. The row decoder 220 may select one of the word lines under the control of the control logic circuit 260. The row decoder 220 may transfer a voltage received through the global word line GWL to the memory cell through the word line.

[0049] Moreover, the row decoder 220 may receive an enable signal EN, a first control signal DA_L, and a second control signal DA_R from the control logic circuit 260. The row decoder 220 may determine whether to apply a voltage to one of the first and second regions of the selected word line in response to the first and second control signals DA_L and DA_R. The first control signal DA_L may prevent a voltage from being applied to the first region. The second control signal DA_R may prevent a voltage from being applied to the second region.

[0050] The voltage generation circuit 230 may generate various voltages required for operating the nonvolatile memory device 200. For example, based on the power supply voltage VCC, the voltage generation circuit 230 may generate various voltages such as a plurality of program voltages, a plurality of pass voltages, a plurality of verification voltages, a plurality of selection read voltages, a plurality of non-selection read voltages, a plurality of erase voltages, and a plurality of erase verification voltages. The voltage generation circuit 230 may output the generated voltages to the row decoder 220 through the global word line GWL.

[0051] The page buffer circuit 240 may be coupled to the memory cell array 210 through the bit lines BL. The page buffer circuit 240 may read data stored in the memory cell array 210 by sensing a voltage change in the bit lines BL, and may temporarily store the read data. The page buffer circuit 240 may receive data from the input / output circuit 250, and may store the data in the memory cell array 210 by controlling the bit lines BL based on the received data.

[0052] The input / output circuit 250 may exchange data DATA with an external device (e.g., a memory controller). For example, the input / output circuit 250 may receive data DATA from the external device and may transfer the received data DATA to the page buffer circuit 240. The input / output circuit 250 may receive data DATA from the page buffer circuit 240 and may transfer the received data to the external device.

[0053] The control logic circuit 260 may control the overall operation of the nonvolatile memory device 200. For example, the control logic circuit 260 may receive a command CMD and an address ADDR from an external device (eg, a memory controller), and may control peripheral circuits by generating control signals in response to the command CMD and the address ADDR.

[0054] The control logic circuit 260 may perform a first operation on the first region and a second operation on the second region based on the command CMD and the address ADDR received from the memory controller. For example, the control logic circuit 260 may transmit the enable signal EN and the second control signal DA_R to the row decoder 220 while performing the first operation on the first region. The control logic circuit 260 may transmit the enable signal EN and the first control signal DA_L to the row decoder 220 while performing the second operation on the second region.

[0055] The control logic circuit 260 may include a register 261. The register 261 may store the first result and the second result. In response to a request received from the memory controller, the control logic circuit 260 may output the first result and the second result stored in the register 261 to the memory controller. Figure 3 , although the control logic circuit 260 is illustrated as including the register 261 , the present disclosure is not limited thereto, and the register 261 may be a separate component that is not included in the control logic circuit 260 .

[0056] Figure 4 is a circuit diagram showing a memory block including a first region and a second region.

[0057] Reference Figure 4 , a first area AR1 and a second area AR2 of a memory block and a row decoder 220 are shown.

[0058] Each of the first area AR1 and the second area AR2 may include a memory cell of a memory block. The first area AR1 may be arranged at a first position relative to the row decoder 220, and the second area AR2 may be arranged at a second position relative to the row decoder 220. For example, the first area AR1 may be arranged on the left side of the row decoder 220, and the second area AR2 may be arranged on the right side of the row decoder 220.

[0059] The first area AR1 may include the first memory cell MC1L to the Nth memory cell MCNL, and the second area AR2 may include the first memory cell MC1R to the Nth memory cell MCNR. The first memory cell MC1L to the Nth memory cell MCNL of the first area AR1 and the first memory cell MC1R to the Nth memory cell MCNR of the second area AR2 may be respectively connected to the same word line. In other words, the first memory cell MC1L of the first area and the first memory cell MC1R of the second area may be connected to the same first word line WL1, the second memory cell MC2L of the first area and the second memory cell MC2R of the second area may be connected to the same second word line WL2, and so on. N may be a natural number greater than 1.

[0060] For example, the first memory cell MC1L of the first area AR1 and the first memory cell MC1R of the second area AR2 may be coupled to the first word line WL1. The second memory cell MC2L of the first area AR1 and the second memory cell MC2R of the second area AR2 may be coupled to the second word line WL2. The Nth memory cell MCNL of the first area AR1 and the Nth memory cell MCNR of the second area AR2 may be coupled to the Nth word line WLN.

[0061] The first to Nth word lines WL1 to WLN may be coupled to the first to Nth global word lines GWL1 to GWLN, respectively. For example, the first word line WL1 may be coupled to the first global word line GWL1, the second word line WL2 may be coupled to the second global word line GWL2, and the Nth word line WLN may be coupled to the Nth global word line GWLN.

[0062] The first to N-th global word lines GWL1 to GWLN may transmit voltages to the first to N-th word lines WL1 to WLN, respectively. The first to N-th word lines WL1 to WLN may transmit applied voltages to the first to N-th memory cells MC1L to MCNL of the first area AR1, respectively, through the first pass gate group PGL. Further, the first to N-th word lines WL1 to WLN may transmit applied voltages to the first to N-th memory cells MC1R to MCNR of the second area AR2, respectively, through the second pass gate group PGR.

[0063] The row decoder 220 may include a first pass gate group PGL, a second pass gate group PGR, a first switch SW1 , and a second switch SW2 .

[0064] The first pass gate group PGL may include first to Nth pass gates PG1_L to PGN_L. The first to Nth pass gates PG1_L to PGN_L may be coupled to the first to Nth memory cells MC1L to MCNL in the first region AR1, respectively.

[0065] The first switch SW1 may be coupled to each of the pass gates PG1_L to PGN_L of the first pass gate group PGL. The first switch SW1 may turn off each of the pass gates PG1_L to PGN_L of the first pass gate group PGL based on the enable signal EN and the first control signal DA_L. For example, the first switch SW1 may be a high voltage switch.

[0066] When only the enable signal EN is received, the first switch SW1 may turn on each of the pass gates PG1_L to PGN_L of the first pass gate group PGL. When each of the pass gates PG1_L to PGN_L of the first pass gate group PGL is turned on, a voltage applied to the global word lines GWL1 to GWLN may be transmitted to the memory cells MC1L to MCNL of the first area AR1 through the word lines WL1 to WLN.

[0067] When receiving the enable signal EN and the first control signal DA_L, the first switch SW1 may turn off each of the pass gates PG1_L to PGN_L of the first pass gate group PGL. When each of the pass gates PG1_L to PGN_L of the first pass gate group PGL is turned off, the voltage applied to the global word lines GWL1 to GWLN cannot be transmitted to the memory cells MC1L to MCNL of the first area AR1.

[0068] That is, when the memory controller performs an operation on the second area AR2 of the memory block or processes the first area AR1 of the memory block as a fail area, the memory controller may output the first control signal DA_L to the memory block.

[0069] The second switch SW2 may be coupled to each of the pass gates PG1_R to PGN_R of the second pass gate group PGR. The second switch SW2 may turn off each of the pass gates PG1_R to PGN_R of the second pass gate group PGR based on the enable signal EN and the second control signal DA_R. For example, the second switch SW2 may be a high voltage switch.

[0070] When only the enable signal EN is received, the second switch SW2 may turn on each of the pass gates PG1_R to PGN_R of the second pass gate group PGR. When each of the pass gates PG1_R to PGN_R of the second pass gate group PGR is turned on, a voltage applied to the global word lines GWL1 to GWLN may be transmitted to the memory cells MC1R to MCNR of the second area AR2 through the word lines WL1 to WLN.

[0071] When receiving the enable signal EN and the second control signal DA_R, the second switch SW2 can turn off each of the pass gates PG1_R to PGN_R of the second pass gate group PGR. When the pass gates PG1_R to PGN_R of the second pass gate group PGR are turned off, the voltage applied to the global word lines GWL1 to GWLN cannot be transmitted to the memory cells MC1R to MCNR of the second area AR2.

[0072] That is, when the memory controller performs an operation on the first area AR1 of the memory block or processes the second area AR2 of the memory block as a fail area, the memory controller may output the second control signal DA_R to the memory block.

[0073] Figure 5 is a flowchart for explaining bad block checking according to an embodiment of the present disclosure.

[0074] Reference Figure 4 and Figure 5 , a method of operating the memory controller 100 and the nonvolatile memory device 200, which performs a bad block check through a read operation on a target block including the first area AR1 and the second area AR2, will be described. Figure 5 The nonvolatile memory device 200 may include Figure 4 , a row decoder 220, a first area AR1, and a second area AR2 are shown in FIG. Figure 5 The storage controller 100 may include Figure 2 A bad block manager 110 is provided.

[0075] At step S110, the memory controller 100 may send a first region read request to the nonvolatile memory device 200. The first region read request may be a request for performing a read operation on the first region AR1 of the target block and preventing a read operation from being performed on the second region AR2. In some embodiments, the first region read request may include an enable signal EN and a second control signal DA_R.

[0076] In some embodiments, when the read retry operation on the target block fails, the storage controller 100 may perform step S110 .

[0077] At step S120, the nonvolatile memory device 200 may perform a read operation on the first region AR1. In some embodiments, the first switch SW1 may turn on each of the pass gates PG1_L to PGN_L of the first pass gate group PGL based on the enable signal EN. Therefore, a voltage required for the read operation may be applied to the memory cells MC1L to MCNL of the first region AR1.

[0078] The second switch SW2 may turn off each of the pass gates PG1_R to PGN_R of the second pass gate group PGR based on the enable signal EN and the second control signal DA_R. Therefore, a voltage required for a read operation cannot be applied to the memory cells MC1R to MCNR of the second area AR2.

[0079] After performing a read operation on the first area AR1, the nonvolatile memory device 200 may store a first result. The first result may indicate whether the read operation on the first area AR1 is successful. In some embodiments, the nonvolatile memory device 200 may store the first result in a register.

[0080] At step S130, the nonvolatile memory device 200 may send a first region response to the memory controller 100. The first region response may indicate that the nonvolatile memory device 200 has performed a read operation on the first region AR1.

[0081] At step S140, the memory controller 100 may send a second region read request to the nonvolatile memory device 200. The second region read request may be a request for performing a read operation on the second region AR2 of the target block and preventing a read operation from being performed on the first region AR1. In some embodiments, the second region read request may include an enable signal EN and a first control signal DA_L.

[0082] At step S150, the nonvolatile memory device 200 may perform a read operation on the second region AR2. In some embodiments, the second switch SW2 may turn on each of the pass gates PG1_R to PGN_R of the second pass gate group PGR based on the enable signal EN. Therefore, a voltage required for the read operation may be applied to the memory cells MC1R to MCNR of the second region AR2.

[0083] The first switch SW1 may turn off the pass gates PG1_L to PGN_L of the first pass gate group PGL based on the enable signal EN and the first control signal DA_L. Therefore, a voltage required for a read operation cannot be applied to the memory cells MC1L to MCNL of the first area AR1.

[0084] After performing the read operation on the second area AR2, the nonvolatile memory device 200 may store a second result. The second result may indicate whether the read operation on the second area AR2 is successful. In some embodiments, the nonvolatile memory device 200 may store the second result in a register.

[0085] At step S160, the nonvolatile memory device 200 may send a second region response to the memory controller 100. The second region response may indicate that the nonvolatile memory device 200 has performed a read operation on the second region AR2.

[0086] In step S170 , the memory controller 100 may send a result request to the nonvolatile memory device 200 .

[0087] In step S180 , the nonvolatile memory device 200 may transmit the first result and the second result to the memory controller 100 in response to the result request.

[0088] In step S190, the storage controller 100 may determine whether to process the target block as a bad block based on the first result and the second result. When the first result indicates that the read operation fails and the second result indicates that the read operation is successful, the storage controller 100 may process the first area AR1 as a failed area. When the first area AR1 is processed as a failed area, the storage controller 100 cannot perform a read operation or a program operation on the first area AR1, but may perform a read operation or a program operation on the second area AR2. In some embodiments, when the first area AR1 is processed as a failed area, the storage controller 100 may transmit a first control signal DA_L for preventing a voltage from being applied to the first area when performing a read operation on the target block.

[0089] When the first result indicates that the read operation is successful and the second result indicates that the read operation fails, the memory controller 100 may process the second area AR2 as a failed area. When the second area AR2 is processed as a failed area, the memory controller 100 cannot perform a read operation or a program operation on the second area AR2, but may perform a read operation or a program operation on the first area AR1. In some embodiments, when the second area AR2 is processed as a failed area, the memory controller 100 may transmit a second control signal DA_R for preventing a voltage from being applied to the second area when performing a read operation on the target block.

[0090] When the first result indicates that the read operation fails and the second result indicates that the read operation fails, the memory controller 100 may process the target block as a bad block.

[0091] Based on the result of the read operation on the first area AR1 and the second area AR2 of the target block, only the area with reliability problems can be processed as a failed area, and the area not processed as a failed area can continue to be used. That is, based on the control signal for preventing voltage from being applied to each area, the defective area in the target block can be detected, and only the detected area can be prevented from being used, thereby enabling the memory device to be effectively used without wasting the capacity of the memory device.

[0092] Figure 6 is a flowchart for explaining bad block checking according to an embodiment of the present disclosure.

[0093] Reference Figure 4 and Figure 6, a method of operating the memory controller 100 and the nonvolatile memory device 200, which perform a bad block check through a program operation on a target block including the first area AR1 and the second area AR2, will be described. Figure 6 The nonvolatile memory device 200 may include Figure 4 , a row decoder 220, a first area AR1, and a second area AR2 are shown in FIG. Figure 6 The storage controller 100 may include Figure 2 A bad block manager 110 is provided.

[0094] In step S210, the memory controller 100 may send a first area program request to the nonvolatile memory device 200. The first area program request may be a request for performing a program operation on the first area AR1 of the target block and preventing the program operation from being performed on the second area AR2. In some embodiments, the first area program request may include an enable signal EN and a second control signal DA_R.

[0095] In some embodiments, when the program operation on the target block fails, the memory controller 100 may perform an erase operation on the target block and may thereafter perform step S210 .

[0096] At step S220, the nonvolatile memory device 200 may perform a programming operation on the first region AR1. In some embodiments, the first switch SW1 may turn on each of the pass gates PG1_L to PGN_L of the first pass gate group PGL based on the enable signal EN. Therefore, a voltage required for the programming operation may be applied to the memory cells MC1L to MCNL of the first region AR1.

[0097] The second switch SW2 may turn off each of the pass gates PG1_R to PGN_R of the second pass gate group PGR based on the enable signal EN and the second control signal DA_R. Therefore, a voltage required for a program operation cannot be applied to the memory cells MC1R to MCNR of the second area AR2.

[0098] After performing a program operation on the first area AR1, the nonvolatile memory device 200 may store a first result. The first result may indicate whether the program operation on the first area AR1 is successful. In some embodiments, the nonvolatile memory device 200 may store the first result in a register.

[0099] At step S230, the nonvolatile memory device 200 may send a first region response to the memory controller 100. The first region response may indicate that the nonvolatile memory device 200 has performed a program operation on the first region AR1.

[0100] At step S240, the memory controller 100 may send a second area program request to the nonvolatile memory device 200. The second area program request may be a request for performing a program operation on the second area AR2 of the target block and preventing the program operation from being performed on the first area AR1. In some embodiments, the second area program request may include an enable signal EN and a first control signal DA_L.

[0101] At step S250, the nonvolatile memory device 200 may perform a programming operation on the second region AR2. In some embodiments, the second switch SW2 may turn on each of the pass gates PG1_R to PGN_R of the second pass gate group PGR based on the enable signal EN. Thus, a voltage required for the programming operation may be applied to the memory cells MC1R to MCNR of the second region AR2.

[0102] The first switch SW1 may turn off the pass gates PG1_L to PGN_L of the first pass gate group PGL based on the enable signal EN and the first control signal DA_L. Therefore, a voltage required for a program operation cannot be applied to the memory cells MC1L to MCNL of the first area AR1.

[0103] After performing the programming operation on the second area AR2, the nonvolatile memory device 200 may store a second result. The second result may indicate whether the programming operation on the second area AR2 is successful. In some embodiments, the nonvolatile memory device 200 may store the second result in a register.

[0104] At step S260, the nonvolatile memory device 200 may send a second region response to the memory controller 100. The second region response may indicate that the nonvolatile memory device 200 has performed a program operation on the second region AR2.

[0105] In step S270 , the memory controller 100 may send a result request to the nonvolatile memory device 200 .

[0106] In step S280 , the nonvolatile memory device 200 may transmit the first result and the second result to the memory controller 100 in response to the result request.

[0107] In step S290, the memory controller 100 may determine whether to process the target block as a bad block according to the first result and the second result. When the first result indicates that the programming operation fails and the second result indicates that the programming operation is successful, the memory controller 100 may process the first area AR1 as a failed area. In some embodiments, when the first area AR1 is processed as a failed area, the memory controller 100 may transmit a first control signal DA_L for preventing a voltage from being applied to the first area when performing a programming operation on the target block.

[0108] When the first result indicates that the program operation is successful and the second result indicates that the program operation fails, the memory controller 100 may process the second region AR2 as a failed region. In some embodiments, when the second region AR2 is processed as a failed region, the memory controller 100 may transmit a second control signal DA_R for preventing a voltage from being applied to the second region when performing a program operation on the target block.

[0109] When the first result indicates that the program operation fails and the second result indicates that the program operation fails, the memory controller 100 may process the target block as a bad block.

[0110] Figure 7 is a flowchart illustrating a method of operating a storage controller according to an embodiment of the present disclosure.

[0111] Reference Figure 7 , will describe Figure 2 The method of operation of the storage controller to perform bad block checking. Figure 7 The storage controller can correspond to Figure 5 and Figure 6 A storage controller 100 is provided.

[0112] In step S310, the storage controller 100 may send a first operation request to the non-volatile memory device. The first operation request may be a read request for the first area or a program request for the first area. In some embodiments, when a retry operation on a target block fails, the storage controller 100 may send a first operation request to the non-volatile memory device. When a program operation on a target block fails, the storage controller 100 may perform an erase operation on the target block, after which the storage controller 100 may send a first operation request to the non-volatile memory device.

[0113] In step S320, the memory controller 100 may send a second operation request to the nonvolatile memory device. The second operation request may be a read request for the second region or a program request for the second region.

[0114] In step S330, the memory controller 100 may obtain a first result and a second result from the nonvolatile memory device. The first result may indicate whether the first operation on the first region is successful. The second result may indicate whether the second operation on the second region is successful.

[0115] In step S340, the memory controller 100 may check whether the first result indicates that the first operation failed. When the first result indicates that the first operation failed, the memory controller 100 may perform step S350. When the first result does not indicate that the first operation failed, the memory controller 100 may perform step S360.

[0116] In step S350, the storage controller 100 may check whether the second result indicates that the second operation failed. When the second result indicates that the second operation failed, the storage controller 100 may perform step S352. When the second result does not indicate that the second operation failed, the storage controller 100 may perform step S354. In step S352, the storage controller 100 may process the target block as a bad block. In step S354, the storage controller 100 may process the first area as a failed area.

[0117] In step S360, the storage controller 100 may check whether the second result indicates that the second operation has failed. When the second result indicates that the second operation has failed, the storage controller 100 may perform step S362. When the second result does not indicate that the second operation has failed, the storage controller 100 may perform step S364. In step S362, the storage controller 100 may process the second area as a failed area. In step S364, the storage controller 100 may terminate the bad block check.

[0118] Although it is disclosed that the storage controller 100 performs the step of checking whether the first result indicates the failure of the first operation earlier than the step of checking whether the second result indicates the failure of the second operation, the present disclosure is not limited thereto, and the storage controller 100 may perform the step of checking whether the second result indicates the failure of the second operation earlier than the step of checking whether the first result indicates the failure of the first operation. In addition, the storage controller 100 may perform the step of checking whether the first result indicates the failure of the first operation and the step of checking whether the second result indicates the failure of the second operation simultaneously.

[0119] Figure 8 is a circuit diagram showing a memory block including a plurality of areas.

[0120] Reference Figure 8 , a first area AR1, a second area AR2, a third area AR3, and a fourth area AR4 of a target block and a row decoder 220 are shown.

[0121] Each of the first to fourth areas AR1 to AR4 may include memory cells of the target block. The first area AR1 may include first to N-th memory cells MC11 to MCN1, the second area AR2 may include first to N-th memory cells MC12 to MCN2, the third area AR3 may include first to N-th memory cells MC13 to MCN3, and the fourth area AR4 may include first to N-th memory cells MC14 to MCN4.

[0122] The first memory cells MC11 to the Nth memory cells MCN1 of the first area AR1, the first memory cells MC12 to the Nth memory cells MCN2 of the second area AR2, the first memory cells MC13 to the Nth memory cells MCN3 of the third area AR3, and the first memory cells MC14 to the Nth memory cells MCN4 of the fourth area AR4 may be connected to the same word line, respectively. In other words, the first memory cells MC11 to the first memory cells MC14 of the first area may be connected to the same first word line WL1, and the second memory cells MC21 to the second memory cells MC24 of the first area may be connected to the same second word line WL2, and so on.

[0123] For example, the first memory cell MC11 of the first area AR1, the first memory cell MC12 of the second area AR2, the first memory cell MC13 of the third area AR3, and the first memory cell MC14 of the fourth area AR4 may be coupled to the first word line WL1. The second memory cell MC21 of the first area AR1, the second memory cell MC22 of the second area AR2, the second memory cell MC23 of the third area AR3, and the second memory cell MC24 of the fourth area AR4 may be coupled to the second word line WL2. The Nth memory cell MCN1 of the first area AR1, the Nth memory cell MCN2 of the second area AR2, the Nth memory cell MCN3 of the third area AR3, and the Nth memory cell MCN4 of the fourth area AR4 may be coupled to the Nth word line WLN.

[0124] The first to Nth word lines WL1 to WLN may be coupled to the first to Nth global word lines GWL1 to GWLN, respectively. For example, the first word line WL1 may be coupled to the first global word line GWL1, the second word line WL2 may be coupled to the second global word line GWL2, and the Nth word line WLN may be coupled to the Nth global word line GWLN.

[0125] The first to N-th global word lines GWL1 to GWLN may apply voltages to the first to N-th word lines WL1 to WLN, respectively. The first to N-th word lines WL1 to WLN may output the applied voltages to the first to N-th memory cells MC11 to MCN1 of the first region AR1, respectively, through the first pass gate group PG1. The first to N-th word lines WL1 to WLN may output the applied voltages to the first to N-th memory cells MC12 to MCN2 of the second region AR2, respectively, through the second pass gate group PG2. The first to N-th word lines WL1 to WLN may output the applied voltages to the first to N-th memory cells MC13 to MCN3 of the third region AR3, respectively, through the third pass gate group PG3. In addition, the first to N-th word lines WL1 to WLN may output the applied voltages to the first to N-th memory cells MC14 to MCN4 of the fourth region AR4, respectively, through the fourth pass gate group PG4.

[0126] The row decoder 220 may include a first pass gate group PG1 , a second pass gate group PG2 , a third pass gate group PG3 , a fourth pass gate group PG4 , a first switch SW1 , a second switch SW2 , a third switch SW3 , and a fourth switch SW4 .

[0127] The first pass gate group PG1 may include first to Nth pass gates PG11 to PGN1. The first to Nth pass gates PG11 to PGN1 may be coupled to the first to Nth memory cells MC11 to MCN1 in the first region AR1, respectively.

[0128] The first switch SW1 may be coupled to each of the pass gates PG11 to PGN1 of the first pass gate group PG1. The first switch SW1 may turn off each of the pass gates PG11 to PGN1 of the first pass gate group PG1 based on the enable signal EN and the first control signal DA1. For example, the first switch SW1 may be a high voltage switch.

[0129] When only the enable signal EN is received, the first switch SW1 may turn on each of the pass gates PG11 to PGN1 of the first pass gate group PG1. When each of the pass gates PG11 to PGN1 of the first pass gate group PG1 is turned on, a voltage applied to the global word lines GWL1 to GWLN may be transmitted to the memory cells MC11 to MCN1 of the first area AR1 through the word lines WL1 to WLN.

[0130] When receiving the enable signal EN and the first control signal DA1, the first switch SW1 may turn off each of the pass gates PG11 to PGN1 of the first pass gate group PG1. When each of the pass gates PG11 to PGN1 of the first pass gate group PG1 is turned off, the voltage applied to the global word lines GWL1 to GWLN cannot be transmitted to the memory cells MC11 to MCN1 of the first area AR1.

[0131] The second switch SW2 may be coupled to each of the pass gates PG12 to PGN2 of the second pass gate group PG2. The second switch SW2 and the first switch SW1 may operate in a similar manner. When receiving the enable signal EN and the second control signal DA2, the second switch SW2 may turn off each of the pass gates PG12 to PGN2 of the second pass gate group PG2. When receiving the enable signal EN, the second switch SW2 may turn on each of the pass gates PG12 to PGN2 of the second pass gate group PG2. For example, the second switch SW2 may be a high voltage switch.

[0132] The third switch SW3 may be coupled to each of the pass gates PG13 to PGN3 of the third pass gate group PG3. The third switch SW3 and the first switch SW1 may operate in a similar manner. When receiving the enable signal EN and the third control signal DA3, the third switch SW3 may turn off each of the pass gates PG13 to PGN3 of the third pass gate group PG3. When receiving the enable signal EN, the third switch SW3 may turn on each of the pass gates PG13 to PGN3 of the third pass gate group PG3. For example, the third switch SW3 may be a high voltage switch.

[0133] The fourth switch SW4 may be coupled to each of the pass gates PG14 to PGN4 of the fourth pass gate group PG4. The fourth switch SW4 and the first switch SW1 may operate in a similar manner. When receiving the enable signal EN and the fourth control signal DA4, the fourth switch SW4 may turn off each of the pass gates PG14 to PGN4 of the fourth pass gate group PG4. When receiving the enable signal EN, the fourth switch SW4 may turn on each of the pass gates PG14 to PGN4 of the fourth pass gate group PG4. For example, the fourth switch SW4 may be a high voltage switch.

[0134] Although a target block including the first to fourth areas AR1 to AR4 is illustrated, the present disclosure is not limited thereto, and the target block may include more than four areas.

[0135] Fig. 9 is a flowchart illustrating a method of operating a storage controller according to an embodiment of the present disclosure.

[0136] Reference Figure 8 and Fig. 9 , a method of operating a memory device that performs a bad block check through a read operation on a target block including the first to fourth areas AR1 to AR4 will be described. Fig. 9 The nonvolatile memory device 200 may include Figure 8 The row decoder 220 and the first to fourth areas AR1 to AR4 are shown in FIG. Fig. 9 The storage controller 100 may include Figure 2 A bad block manager 110 is provided.

[0137] In step S410, the memory controller 100 may send a first region read request to the nonvolatile memory device 200. The first region read request may be a request for performing a read operation on the first region AR1 of the target block and preventing the second region AR2 to the fourth region AR4 from performing a read operation. In some embodiments, the first region read request may include an enable signal EN, a second control signal DA2, a third control signal DA3, and a fourth control signal DA4.

[0138] In some embodiments, when the read retry operation on the target block fails, the storage controller 100 may perform step S410 .

[0139] At step S412, the nonvolatile memory device 200 may perform a read operation on the first region AR1. In some embodiments, the first switch SW1 may turn on each of the pass gates PG11 to PGN1 of the first pass gate group PG1 based on the enable signal EN. Thus, a voltage required for the read operation may be applied to the memory cells MC11 to MCN1 of the first region AR1.

[0140] The second switch SW2 may turn off each of the pass gates PG12 to PGN2 of the second pass gate group PG2 based on the enable signal EN and the second control signal DA2. The third switch SW3 may turn off each of the pass gates PG13 to PGN3 of the third pass gate group PG3 based on the enable signal EN and the third control signal DA3. The fourth switch SW4 may turn off each of the pass gates PG14 to PGN4 of the fourth pass gate group PG4 based on the enable signal EN and the fourth control signal DA4.

[0141] After performing a read operation on the first area AR1, the nonvolatile memory device 200 may store a first result. The first result may indicate whether the read operation on the first area AR1 is successful. In some embodiments, the nonvolatile memory device 200 may store the first result in a register.

[0142] At step S414, the nonvolatile memory device 200 may send a first region response to the memory controller 100. The first region response may indicate that the nonvolatile memory device 200 has performed a read operation on the first region AR1.

[0143] At step S420, the memory controller 100 may send a second region read request to the nonvolatile memory device 200. The second region read request may be a request for performing a read operation on the second region AR2 of the target block and preventing the first region AR1, the third region AR3, and the fourth region AR4 from performing a read operation. In some embodiments, the second region read request may include an enable signal EN, a first control signal DA1, a third control signal DA3, and a fourth control signal DA4.

[0144] At step S422, the nonvolatile memory device 200 may perform a read operation on the second region AR2. In some embodiments, the second switch SW2 may turn on each of the pass gates PG12 to PGN2 of the second pass gate group PG2 based on the enable signal EN. Thus, a voltage required for the read operation may be applied to the memory cells MC12 to MCN2 of the second region AR2.

[0145] The first switch SW1 may turn off each of the pass gates PG11 to PGN1 of the first pass gate group PG1 based on the enable signal EN and the first control signal DA1. The third switch SW3 may turn off each of the pass gates PG13 to PGN3 of the third pass gate group PG3 based on the enable signal EN and the third control signal DA3. The fourth switch SW4 may turn off each of the pass gates PG14 to PGN4 of the fourth pass gate group PG4 based on the enable signal EN and the fourth control signal DA4.

[0146] After performing the read operation on the second area AR2, the nonvolatile memory device 200 may store a second result. The second result may indicate whether the read operation on the second area AR2 is successful. In some embodiments, the nonvolatile memory device 200 may store the second result in a register.

[0147] At step S424, the nonvolatile memory device 200 may send a second region response to the memory controller 100. The second region response may indicate that the nonvolatile memory device 200 has performed a read operation on the second region AR2.

[0148] At step S430, the memory controller 100 may send a third region read request to the nonvolatile memory device 200. The third region read request may be a request for performing a read operation on the third region AR3 of the target block and preventing the first region AR1, the second region AR2, and the fourth region AR4 from performing a read operation. In some embodiments, the third region read request may include an enable signal EN, a first control signal DA1, a second control signal DA2, and a fourth control signal DA4.

[0149] At step S432, the nonvolatile memory device 200 may perform a read operation on the third region AR3. In some embodiments, the third switch SW3 may turn on each of the pass gates PG13 to PGN3 of the third pass gate group PG3 based on the enable signal EN. Therefore, a voltage required for the read operation may be applied to the memory cells MC13 to MCN3 of the third region AR3.

[0150] The first switch SW1 may turn off each of the pass gates PG11 to PGN1 of the first pass gate group PG1 based on the enable signal EN and the first control signal DA1. The second switch SW2 may turn off each of the pass gates PG12 to PGN2 of the second pass gate group PG2 based on the enable signal EN and the second control signal DA2. The fourth switch SW4 may turn off each of the pass gates PG14 to PGN4 of the fourth pass gate group PG4 based on the enable signal EN and the fourth control signal DA4.

[0151] After performing the read operation on the third area AR3, the nonvolatile memory device 200 may store a third result. The third result may indicate whether the read operation on the third area AR3 is successful. In some embodiments, the nonvolatile memory device 200 may store the third result in a register.

[0152] At step S434, the nonvolatile memory device 200 may send a third region response to the memory controller 100. The third region response may indicate that the nonvolatile memory device 200 has performed a read operation on the third region AR3.

[0153] At step S440, the memory controller 100 may send a fourth region read request to the nonvolatile memory device 200. The fourth region read request may be a request for performing a read operation on the fourth region AR4 of the target block and preventing the first to third regions AR1 to AR3 from performing a read operation. In some embodiments, the fourth region read request may include an enable signal EN, a first control signal DA1, a second control signal DA2, and a third control signal DA3.

[0154] At step S442, the nonvolatile memory device 200 may perform a read operation on the fourth region AR4. In some embodiments, the fourth switch SW4 may turn on each of the pass gates PG14 to PGN4 of the fourth pass gate group PG4 based on the enable signal EN. Therefore, a voltage required for the read operation may be applied to the memory cells MC14 to MCN4 of the fourth region AR4.

[0155] The first switch SW1 may turn off each of the pass gates PG11 to PGN1 of the first pass gate group PG1 based on the enable signal EN and the first control signal DA1. The second switch SW2 may turn off each of the pass gates PG12 to PGN2 of the second pass gate group PG2 based on the enable signal EN and the second control signal DA2. The third switch SW3 may turn off each of the pass gates PG13 to PGN3 of the third pass gate group PG3 based on the enable signal EN and the third control signal DA3.

[0156] After performing the read operation on the fourth area AR4, the nonvolatile memory device 200 may store a fourth result. The fourth result may indicate whether the read operation on the fourth area AR4 is successful. In some embodiments, the nonvolatile memory device 200 may store the fourth result in a register.

[0157] At step S444, the nonvolatile memory device 200 may send a fourth region response to the memory controller 100. The fourth region response may indicate that the nonvolatile memory device 200 has performed a read operation on the fourth region AR4.

[0158] In step S450 , the memory controller 100 may send a result request to the nonvolatile memory device 200 .

[0159] In step S452 , the nonvolatile memory device 200 may transmit the first to fourth results to the memory controller 100 in response to the result request.

[0160] In step S460, the memory controller 100 may determine whether to process the target block as a bad block according to the first to fourth results. The memory controller 100 may process a region corresponding to a result indicating a read operation failure among the first to fourth results as a failed region.

[0161] For example, when the first result and the second result indicate that the read operation fails and the third result and the fourth result indicate that the read operation succeeds, the memory controller 100 may process the first region and the second region as failed regions. When the first region and the second region are processed as failed regions, the memory controller 100 may transmit a first control signal and a second control signal for preventing a voltage from being applied to the first region and the second region when performing a read operation on the target block. That is, the memory controller 100 may perform a read operation on the third region and the fourth region.

[0162] When the third result indicates that the read operation fails and the first result, the second result, and the fourth result indicate that the read operation is successful, the memory controller 100 may process the third region as a failed region. When the third region is processed as a failed region, the memory controller 100 may transmit a third control signal for preventing a voltage from being applied to the third region when performing a read operation on the target block. That is, the memory controller 100 may perform a read operation on the first region, the second region, and the fourth region.

[0163] When the first to fourth results all indicate that the read operation fails, the memory controller 100 may process the target block as a bad block.

[0164] Although a method of operating a storage device to perform a bad block check by a read operation on a target block including the first to fourth areas AR1 to AR4 has been described, the present disclosure is not limited thereto, and the storage controller 100 may perform a bad block check by a program operation on a target block including the first to fourth areas AR1 to AR4.

[0165] In some embodiments, the storage controller 100 can determine whether to process the target block as a bad block based on a first result indicating whether the programming operation on the first area AR1 is successful, a second result indicating whether the programming operation on the second area AR2 is successful, a third result indicating whether the programming operation on the third area AR3 is successful, and a fourth result indicating whether the programming operation on the fourth area AR4 is successful.

[0166] The present disclosure includes a memory device and a memory controller that perform bad block area check. The present disclosure can detect an area in the bad block where an operation is normally performed, and can use the detected area, thereby improving the efficiency of the memory device.

Claims

1. A memory device, comprising: a first region including a first memory cell; a second region including second memory cells, the first memory cells and the second memory cells being coupled to the same word line; as well as The control circuit performs a first operation on the first area and a second operation on the second area, and stores a first result indicating whether the first operation is successful and a second result indicating whether the second operation is successful.

2. The memory device according to claim 1, wherein: When the first result indicates that a first operation on the first region fails and the second result indicates that a second operation on the second region succeeds, treating the first region as a failed region, When the first result indicates that the first operation is successful and the second result indicates that the second operation is failed, treating the second region as a failed region, and When the first result indicates that the first operation has failed and the second result indicates that the second operation has failed, a storage block including the first area and the second area is processed as a bad block.

3. The memory device according to claim 1, further comprising: A voltage generating circuit generates a first voltage and a second voltage; as well as A decoder applies a first voltage to the first region when performing the first operation and applies a second voltage to the second region when performing the second operation.

4. The memory device according to claim 3, wherein: The control circuit: When the second operation is performed, an enable signal and a first control signal that prevents a voltage from being applied to the first region are output to the decoder, and When the first operation is performed, the enable signal and a second control signal that prevents a voltage from being applied to the second region are output to the decoder.

5. The memory device according to claim 4, wherein: The decoder comprises: a first pass gate coupled to the first memory cell; a first switch, which turns on the first pass gate when receiving the enable signal, and turns off the first pass gate when receiving the first control signal; a second pass gate coupled to the second memory cell; and The second switch turns on the second pass gate when receiving the enable signal, and turns off the second pass gate when receiving the second control signal.

6. The memory device according to claim 1, wherein: The first operation is one of a program operation on the first region and a read operation on the first region, and The second operation is one of a program operation on the second region and a read operation on the second region.

7. The memory device of claim 1 , further comprising: a third region including third memory cells coupled to the same word line; as well as a fourth region including fourth memory cells coupled to the same word line, The control circuit performs a third operation on the third region, performs a fourth operation on the fourth region, and stores a third result indicating whether the third operation is successful and a fourth result indicating whether the fourth operation is successful.

8. A method of operating a storage controller, the storage controller communicating with a non-volatile memory device including a target block, the method comprising: sending a first request for a first region of the target block to the nonvolatile memory device; sending a second request for a second region of the target block to the nonvolatile memory device; as well as determining whether to process the target block as a bad block based on a first result indicating whether a first operation corresponding to the first request is successful and a second result indicating whether a second operation corresponding to the second request is successful, wherein the first region includes memory cells connected to a first pass gate group among the memory cells of the target block, The second region includes memory cells coupled to a second pass gate group among the memory cells of the target block, and A plurality of pass gates in the first pass gate group and a plurality of pass gates in the second pass gate group are respectively coupled to the same word line.

9. The method according to claim 8, wherein: Determining whether to process the target block as a bad block based on the first result and the second result includes: When the first result indicates that the first operation failed, checking whether the second result indicates that the second operation failed; and When the second result indicates that the second operation fails, the target block is processed as a bad block.

10. The method according to claim 9, further comprising: When the second result indicates that the second operation is successful, the storage controller processes the first region as a failed region.

11. The method according to claim 9, further comprising: When the first result indicates that the first operation is successful, checking whether the second result indicates that the second operation is failed; as well as When the second result indicates that the second operation fails, the second region is processed as a failed region.

12. The method according to claim 9, wherein: Sending a second request for a second region of the target block to the nonvolatile memory device includes sending the second request to the nonvolatile memory device based on receiving a response to the first request from the nonvolatile memory device.

13. The method according to claim 9, wherein: The first operation is one of a read operation on the first region and a program operation on the first region, and The second operation is one of a read operation on the second region and a program operation on the second region.

14. The method according to claim 13, wherein: When the first operation is a read operation of the first region and the second operation is a read operation of the second region, sending a first request for a first region of the target block to the nonvolatile memory device includes: performing a read retry operation on the target block; and When the read retry operation fails, a first request for a first area of ​​the target block is sent to the nonvolatile memory device.

15. The method according to claim 13, wherein: When the first operation is a programming operation for the first region and the second operation is a programming operation for the second region, sending a first request for a first region of the target block to the nonvolatile memory device includes: performing a programming operation on the target block; When the programming operation fails, performing an erasing operation on the target block; and After performing the erase operation, a first request for a first area of ​​the target block is sent to the nonvolatile memory device.

16. The method according to claim 8, wherein: The first request includes a signal to turn off each of the plurality of pass gates of the second pass gate group, and The second request includes a signal to turn off each of the plurality of pass gates of the first pass gate group.

17. A method for operating a memory device, the memory device comprising a memory block, the memory block comprising a first area and a second area, the method comprising: performing a first operation corresponding to the first area; storing a first result indicating whether the first operation is successful; After storing the first result, performing a second operation corresponding to the second area; storing a second result indicating whether the second operation is successful; as well as Based on the first result and the second result, processing at least one of the first region and the second region as a failed region, wherein the first region includes memory cells of the memory block connected to the first pass gate group, The second region includes memory cells coupled to a second pass gate group among the memory cells of the memory block, and A plurality of pass gates in the first pass gate group and a plurality of pass gates in the second pass gate group are respectively coupled to the same word line.

18. The method according to claim 17, wherein: The memory device comprises: A control circuit, executing the first operation and the second operation, and storing the first result and the second result; a voltage generating circuit that generates a first voltage and a second voltage; and A decoder applies a first voltage to the first region when performing the first operation and applies a second voltage to the second region when performing the second operation.

19. The method according to claim 17, wherein: The first operation is one of a read operation on the first region and a program operation on the first region, and The second operation is one of a read operation on the second region and a program operation on the second region.

20. The method of claim 17, further comprising: When the first result indicates that the first operation fails and the second result indicates that the second operation succeeds, treating the first region as a failed region; When the first result indicates that the first operation is successful and the second result indicates that the second operation is failed, treating the second region as a failed region; and When the first result indicates that the first operation failed and the second result indicates that the second operation failed, the storage block is processed as a bad block.

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