Package-on-package structure and forming method thereof

Abstract

The invention discloses a stacked packaging structure and a forming method thereof, and the forming method comprises the steps: enabling a first active surface of a first chip to face downwards, and enabling the first active surface to be mounted on the upper surface of a substrate; a chip stacking structure is formed on the first back face of the first chip and comprises a plurality of second chips sequentially stacked in the vertical direction, each second chip comprises a second active face and a second back face which are opposite, the second active face is provided with micro protrusions, and the second back face is provided with second connecting terminals; at least one flow guide channel extending from one end of the second chip to the other end of the second chip is arranged between the micro bulges, the second active surface of each second chip faces downwards, and the micro bulges on the second active surface of the second chip on the upper layer in the chip stacking structure are welded together with the second connecting terminals on the second back surface of the second chip on the adjacent lower layer; a plastic package layer filling the space between the upper and lower second chips is formed, and the flow guide channel is beneficial to the flowing of a plastic package layer material when the plastic package layer is formed, so that the filling difficulty of the plastic package layer material is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a stacked packaging structure and a method for forming the same. Background Art

[0002] HBM (High Bandwidth Memory) is a new type of CPU / GPU memory chip (i.e. "RAM"), which is actually a number of DDR chips stacked together and packaged together with the GPU to achieve a large-capacity, high-bit-width DDR combination array.

[0003] The existing 3D HBM (3D High Bandwidth Memory) packaging structure vertically stacks multiple memory chips (such as DRAM) through advanced packaging technology (such as TSV through silicon via technology and micro-bump technology) to increase storage capacity, and then interconnects them with the computing unit chip (GPU / CPU / SOC Die) based on the high-speed interface of the interposer.

[0004] The existing stacking processes for HBM production mainly include TC-NCF (Thermal Compression bonding, TC, Non-Conductive Film, NCF, thermal compression non-conductive adhesive film) process and MR-MUF (Mass Reflow bonding with Molded Underfill, batch reflow molding bottom filling) process.

[0005] The TC-NCF process requires placing a layer of non-conductive adhesive film (Non-Conductive Film) between each layer of memory chips during each stacking process to isolate the upper and lower layers of memory chips from each other and protect the soldering points from impact. This process has the problems of complex manufacturing process, low efficiency and high cost.

[0006] Compared with the TC-NCF process, the MR-MUF process reduces the chip stacking pressure to 6%, shortens the process time, increases production efficiency by 4 times, and improves the heat dissipation rate by 45%. However, after the MR-MUF process forms a memory chip stack, the memory chips need to be filled with plastic layer materials for isolation. However, when filling the plastic layer materials, the spacing between the upper and lower memory chips is very small, so there is a problem of difficulty in filling the plastic layer materials. Summary of the invention

[0007] The problem to be solved by the present application is to provide a stacked package structure and a method for forming the same, so as to reduce the difficulty in filling the plastic packaging layer material in the stacked chip structure.

[0008] In order to solve the above problems, the present application first provides a method for forming a stacked package structure, comprising:

[0009] providing a substrate, the substrate comprising opposing upper and lower surfaces;

[0010] Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate;

[0011] Provide a plurality of second chips, each of which comprises a second active surface and a second back surface opposite to each other, the second active surface having a plurality of discrete micro-bumps, the second back surface having a plurality of discrete second connection terminals, at least one guide channel extending from one end of the second chip to the other end of the second chip is provided between the plurality of discrete micro-bumps, and the width of the guide channel at both ends is greater than the width of the middle position of the guide channel;

[0012] forming a chip stacking structure on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, the second active side of each second chip facing downward, the micro-bumps on the second active side of the second chip in the upper layer of the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip in the adjacent lower layer, and the micro-bumps on the second active side of the second chip in the bottom layer being welded together with the first connection terminals on the first back side of the first chip;

[0013] A molding bottom filling process is performed to form a plastic layer that covers the chip stacking structure and the first chip, and fills between the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The guide channel is conducive to the flow and filling of the plastic layer material when the plastic layer is formed.

[0014] In an optional embodiment, the number of the guide channels is one or more. When the number of the guide channels is multiple, the multiple guide channels are arranged in parallel; a passivation layer is provided on the second active surface of the second chip, the micro-protrusion portion is located in the passivation layer, and at least one guide groove having the same extension direction as the guide channel is provided in the passivation layer between the several discrete micro-protrusions, and the guide groove is located directly below the corresponding guide channel.

[0015] In an optional embodiment, the guide channel and the guide groove are both arranged along the direction in which the plastic encapsulation layer material flows in; the width of the two ends of the guide groove is equal to or greater than the width of the middle position of the guide groove.

[0016] In an optional embodiment, the guiding channels of the upper layer and the guiding channels of the lower layer may be arranged in the same direction or in different directions.

[0017] In an optional embodiment, the width of the two ends of the first guide channel is greater than the width of the middle position of the guide channel, which includes: the width of the guide channel gradually decreases from the two ends to the middle position.

[0018] In an optional embodiment, the process of forming a chip stacking structure on the first back side of the first chip includes a pre-fixing process and a batch reflow process; the pre-fixing process is first performed to stack and pre-fix a plurality of the second chips in sequence in a vertical direction; and a batch reflow process is performed to weld the micro-bumps on the second active surface of the second chip in the upper layer of the chip stacking structure to the second connecting terminal on the second back side of the adjacent second chip in the lower layer, and the micro-bumps on the second active surface of the second chip in the bottom layer to the first connecting terminal on the first back side of the first chip.

[0019] In an optional embodiment, when performing the pre-fixing process, the second chip of the upper layer and the adjacent second chip of the lower layer are pre-fixed by pre-soldering the flux in or on the surface of the micro-bumps with the corresponding second connecting terminals.

[0020] In an optional embodiment, when performing the pre-fixing process, the second chip of the upper layer is bonded and fixed to the adjacent second chip of the lower layer via a bonding layer located between the second chip of the upper layer and the second chip of the lower layer to achieve the pre-fixing.

[0021] In an optional embodiment, the bonding layer is a temporary bonding layer or a mechanical bonding layer. The temporary bonding layer decomposes during a batch reflow process, and the mechanical bonding layer does not decompose during the mechanical bonding process and remains in the stacked packaging structure.

[0022] The present application also provides a stacked package structure, comprising:

[0023] a substrate comprising opposing upper and lower surfaces;

[0024] A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate;

[0025] A chip stacking structure located on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface having a plurality of discrete micro-bumps, the second back side having a plurality of discrete second connection terminals, at least one guide channel extending from one end of the second chip to the other end of the second chip is provided between the plurality of discrete micro-bumps, and the widths of the two ends of the guide channel are greater than the width of the middle position of the guide channel, the second active surface of each second chip faces downward, the micro-bumps of the second active surface of the second chip of the upper layer in the chip stacking structure are welded to the second connection terminals of the second back side of the second chip of the adjacent lower layer, and the micro-bumps of the second active surface of the second chip of the bottom layer are welded to the first connection terminals of the first back side of the first chip;

[0026] A plastic encapsulation layer is provided to cover the chip stacking structure and the first chip, and to fill the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The guide channel is beneficial to the flow and filling of the plastic encapsulation layer material when the plastic encapsulation layer is formed.

[0027] In an optional embodiment, the number of the guide channels is one or more. When the number of the guide channels is multiple, the multiple guide channels are arranged in parallel; a passivation layer is provided on the second active surface of the second chip, the micro-protrusion portion is located in the passivation layer, and at least one guide groove having the same extension direction as the guide channel is provided in the passivation layer between the several discrete micro-protrusions, and the guide groove is located directly below the corresponding guide channel.

[0028] In an optional embodiment, the guide channel and the guide groove are both arranged along the direction in which the plastic encapsulation layer material flows in; the setting directions of the guide channel of the upper layer and the guide channel of the lower layer can be the same or different; the width of the two ends of the guide groove is equal to or greater than the width of the middle position of the guide groove.

[0029] In an optional embodiment, the width of the two ends of the guide channel is greater than the width of the middle position of the guide channel, which includes: the width of the guide channel gradually decreases from the two ends to the middle position.

[0030] In an optional embodiment, a bonding layer is further provided between the second chip of the upper layer and the adjacent second chip of the lower layer, and the bonding layer is used for bonding and fixing the second chips of the upper and lower layers when the second chips are stacked.

[0031] In an optional embodiment, a third chip is also mounted on the upper surface of the substrate on one side of the second chip, and the third chip is electrically connected to the substrate; the first chip is a logic chip, the second chip is a storage chip, and the third chip is a processing chip.

[0032] The advantages of the technical solution of this application are:

[0033] In the present application, at least one guide channel extending from one end of the second chip to the other end of the second chip is arranged between the several discrete micro-bumps of the second chip. After the several second chips are formed into a stacked chip structure, when the plastic encapsulation layer material is filled between the second chips of the stacked chip structure, the existence of the guide channel increases the flow space of the plastic encapsulation layer material between adjacent micro-bumps, so that the plastic encapsulation layer material can easily flow to the middle area of ​​the second chip through the guide channel, and the width of the two ends of the guide channel is greater than the width of the middle position of the guide channel, so that the plastic encapsulation layer material can easily flow to the middle area of ​​the second chip through the guide channel, so that the plastic encapsulation layer material can be well filled between the upper and lower layers of the second chips, reducing the difficulty of filling the plastic encapsulation layer material, and preventing defects such as gaps from being generated in the plastic encapsulation layer formed between the upper and lower layers of the second chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1-Figure 5 This is a structural schematic diagram of a stacked package structure forming process in one embodiment of the present application;

[0035] Figure 6-Figure 10 It is a structural schematic diagram of a stacked package structure forming process in another embodiment of the present application. DETAILED DESCRIPTION

[0036] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0037] In one embodiment of the present application, a method for forming a stacked package structure is first provided. The formation process of the stacked package structure of the present application is described in detail below with reference to the accompanying drawings.

[0038] refer to Figure 1, providing a substrate 101, wherein the substrate 101 includes a relative upper surface and a lower surface; providing a first chip 201, wherein the first chip 201 includes a relative first active surface and a first back surface, wherein the first active surface has a welding protrusion 202, and the first back surface has a first connecting terminal 203, and the first active surface of the first chip 201 is mounted downward on the upper surface of the substrate 101, and the welding protrusion 202 is welded to the substrate 101.

[0039] The substrate 101 serves as a support carrier and a connection carrier in the packaging process. In one embodiment, the upper surface of the substrate 101 has a plurality of discrete first pads (not shown in the figure), the lower surface of the substrate 101 has a plurality of discrete second pads (not shown in the figure), and the substrate 101 has a connection circuit (not shown in the figure), and the connection circuit may include one or more of a metal layer, a connection plug, a through-hole connection structure (TSV), and a via connection structure. The connection circuit can be used for the electrical connection between the first pad on the upper surface of the substrate 101 and the corresponding second pad on the lower surface of the substrate 101. The connection circuit can also be used for the electrical connection between some of the first pads on the upper surface of the substrate 101, and the connection circuit is also used for the electrical connection between some of the second pads on the lower surface of the substrate 101. The first pad on the upper surface of the substrate 101 is electrically connected to the first chip or other device mounted on the upper surface of the substrate 101, and an external protrusion can be formed on the second pad on the lower surface of the substrate later, and the external protrusion is used to connect with other devices or packaging structures. In one embodiment, the material of the first pad, the second pad and the connecting line is metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the external protrusion is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. In one embodiment, the substrate may be a silicon substrate, an RDL substrate (Re-distribution Layer), a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a flexible circuit board (FPC). In one embodiment, the substrate may be a single-layer board or a multi-layer board. In one embodiment, the substrate 101 may be used as an interposer.

[0040] The first chip 201 includes a first active surface and a first back surface opposite to each other, the first active surface has a welding protrusion 202, the first back surface has a first connection terminal 203, the first connection terminal 203 includes a through silicon via interconnection structure (TSV, Through Silicon Via), an integrated circuit (with specific functions) (such as a logic control circuit, not shown in the figure) is formed in the first chip 201, and the welding protrusion 202 and the first connection terminal 203 are electrically connected to the integrated circuit. In one embodiment, the welding protrusion 202 can be a solder protrusion or include a metal bump and a solder layer located on the top surface of the metal bump. In a specific embodiment, the material of the first connecting terminal 203 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver; the material of the metal bump is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver; the material of the solder bump or solder layer is tin or a tin alloy; the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0041] The first chip 201 can function together with the second chip 301 (see Figure 3 ) have the same or different functions. In one embodiment, the function of the first chip 201 may be different from the function of the second chip 301 that is subsequently stacked. The first chip 201 is a logic chip, and the second chip 301 is a memory chip (such as a DRAM chip). The logic chip is used to control and manage the storage, reading (and deletion) of data in the memory chip. In other embodiments, the function of the first chip 201 may be different from the function of the second chip 301 that is subsequently stacked (refer to Figure 3 ) have the same functions, and the first chip 201 and the second chip 301 are both storage chips.

[0042] In one embodiment, a third chip (not shown in the figure) is also mounted on the upper surface of the substrate 101 on one side of the first chip 201, and the third chip is electrically connected to the substrate 101. Specifically, the third chip can be electrically connected to the second chip 201 through some connecting lines in the substrate 101. The first chip 201 is a logic chip, the second chip 301 is a storage chip, and the third chip is a processing chip, which can be a CPU chip or a GPU chip.

[0043] Combined with reference Figure 2-Figure 4 ,in Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 4 For the general Figure 3The schematic diagram of the structure of the second chip after stacking shown in the figure provides a plurality of second chips 301, each of the second chips 301 includes a second active surface and a second back surface opposite to each other, the second active surface has a plurality of discrete micro-bumps 302, the second back surface has a plurality of discrete second connection terminals 303, at least one guide channel 306 extending from one end of the second chip 301 to the other end of the second chip 301 is arranged between the plurality of discrete micro-bumps 302, and the width of the guide channel 306 at both ends is greater than the width of the middle position of the guide channel 306; A chip stacking structure is formed on the first back side of the first chip 201, and the chip stacking structure includes a plurality of second chips 301 stacked in sequence along a vertical direction, with the second active side of each second chip 301 facing downward, and the micro-bumps 302 on the second active side of the second chip 301 in the upper layer of the chip stacking structure are welded together with the second connecting terminals 303 on the second back side of the adjacent second chip 301 in the lower layer, and the micro-bumps 302 on the second active side of the second chip 301 in the bottom layer are welded together with the first connecting terminals 203 on the first back side of the first chip 201.

[0044] In the present application, at least one guide channel 306 extending from one end of the second chip 301 to the other end of the second chip 301 is arranged between the several discrete micro-bumps 302 of the second chip 301. After the several second chips 301 are formed into a stacked chip structure, when the plastic encapsulation layer material is subsequently filled between the second chips 301 of the stacked chip structure, the existence of the guide channel 306 increases the flow space of the plastic encapsulation layer material between adjacent micro-bumps 302, so that the plastic encapsulation layer material can easily flow to the middle area of ​​the second chip 301 through the guide channel 306, and the width of the two ends of the guide channel 306 is greater than the width of the middle position of the guide channel 306, so that the plastic encapsulation layer material can easily flow to the middle area of ​​the second chip 301 through the guide channel 306, so that the plastic encapsulation layer material can be well filled between the upper and lower layers of the second chips 301, reducing the difficulty of filling the plastic encapsulation layer material, and preventing defects such as gaps from being generated in the plastic encapsulation layer formed between the upper and lower layers of the second chips.

[0045] In one embodiment, the guide channel 306 is arranged along the direction in which the plastic encapsulation layer material flows in; the width of the guide channel 306 at both ends is greater than the width of the middle position of the guide channel 306: the width of the guide channel 306 gradually decreases from both ends to the middle position, so as to reduce the resistance of the micro-bumps 302 on both sides of the guide channel 306 to the flow of the plastic encapsulation layer material, which is more conducive to the filling of the plastic encapsulation layer material.

[0046] In one embodiment, the number of the guide channels 306 is one or more. When the number of the guide channels 306 is multiple, the multiple guide channels 306 are arranged in parallel. When filling the plastic sealing layer material, it is beneficial to balance the filling speed of the plastic sealing layer material in different directions, improve the uniformity during filling, and be more conducive to the filling of the plastic sealing layer material.

[0047] In one embodiment, the guiding channels 306 of the upper layer and the guiding channels 306 of the lower layer may be arranged in the same direction or in different directions.

[0048] The second active surface of the second chip 301 has a micro-bump 302, and the second back surface of the second chip 301 has a second connection terminal 303, the micro-bump 302 is a micro solder ball, and the second connection terminal 303 includes a through silicon via interconnection structure (TSV, Through Silicon Via), and an integrated circuit with a specific function (such as data storage, reading circuit, not shown in the figure) is formed in the second chip 301, and the second connection terminal 303 and the micro-bump 302 are electrically connected to the integrated circuit. In a specific embodiment, the material of the second connection terminal 303 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver, and the material of the micro-bump 302 is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony. It should be noted that, in some embodiments, the second chip 301 at the top layer in the chip stacking structure may have a second connection terminal 303 or a through silicon via interconnection structure (TSV, Through Silicon Via).

[0049] In one embodiment, the second chip 301 is a memory chip, which may include a volatile memory chip (such as dynamic random access memory (DRAM) or static RAM (SRAM) or a non-volatile memory chip (such as flash memory (Flash), phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM) or resistive RAM (ReRAM)).

[0050] In one embodiment, the second active surface of the second chip 301 further has a passivation layer 305, and the micro-protrusions 302 are partially located in the passivation layer 305. At least one guide groove 307 extending in the same direction as the guide channel 306 is provided in the passivation layer 305 between the several discrete micro-protrusions 302, and the guide groove 307 is located directly below the corresponding guide channel 306. The cooperation between the guide groove 307 and the guide channel 306 further increases the flow space of the plastic encapsulation layer material between adjacent micro-bumps 302, so that the plastic encapsulation layer material can more easily flow to the middle area of ​​the second chip 301 through the guide channel 306, so that the plastic encapsulation layer material can be well filled between the upper and lower second chips 301, which is more conducive to reducing the difficulty of filling the plastic encapsulation layer material, and can more effectively prevent defects such as gaps from being generated in the plastic encapsulation layer formed between the upper and lower second chips.

[0051] In one embodiment, the guide groove 307 is arranged along the direction in which the plastic encapsulation material flows in; the width of the two ends of the guide groove 307 is greater than or equal to the width of the middle position of the guide groove 307. The width of the guide groove 307 gradually decreases from the two ends to the middle position, so as to reduce the resistance of the passivation layer 305 on both sides of the guide groove 307 to the flow of the plastic encapsulation material, which is more conducive to the filling of the plastic encapsulation material.

[0052] In one embodiment, the number of the guide grooves 307 is one or more. When the number of the guide grooves 307 is multiple, the multiple guide grooves 307 are arranged in parallel. When filling the plastic sealing layer material, it is beneficial to balance the filling speed of the plastic sealing layer material in different directions, improve the uniformity during filling, and be more conducive to the filling of the plastic sealing layer material.

[0053] In one embodiment, the guiding grooves 307 of the upper layer and the guiding grooves 307 of the lower layer may be arranged in the same direction or in different directions.

[0054] In one embodiment, the guide groove 307 can be formed in the process of manufacturing the second chip 301 by using a semiconductor integration manufacturing process in the previous stage.

[0055] In one embodiment, the passivation layer 305 may be a single layer or a multi-layer stacked structure. The material of the passivation layer 305 may be an organic material and / or an inorganic material. The inorganic material is one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the inorganic material is a high molecular polymer.

[0056] In one embodiment, the process of forming a chip stacking structure on the first back side of the first chip 201 includes a pre-fixing process and a batch reflow process; the pre-fixing process is first performed to stack and pre-fix a plurality of the second chips 301 in sequence in a vertical direction; and a batch reflow process is performed to weld the micro-bumps 302 of the second active surface of the upper second chip 301 in the chip stacking structure to the second connecting terminal 303 of the second back side of the adjacent lower second chip 301, and the micro-bumps 302 of the second active surface of the bottom second chip 301 to the first connecting terminal 203 of the first back side of the first chip 201.

[0057] In one embodiment, reference Figure 4 When the pre-fixing process is performed, the second chip 301 of the upper layer and the adjacent second chip 301 of the lower layer are pre-fixed by pre-soldering the corresponding second connection terminal 203 with the flux in or on the surface of the micro-bump 302. When pre-fixed by flux, the micro-bump 302 and the corresponding second connection terminal 203 are only preliminarily and weakly welded, and are not completely welded. When the batch reflow process is performed later, the micro-bump 302 and the corresponding second connection terminal 203 can be completely welded.

[0058] In another embodiment, reference Figure 6-Figure 8 ,in Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 8 For the general Figure 7The schematic diagram of the structure of the second chip after stacking is shown. When the pre-fixing process is performed, the second chip 301 of the upper layer is bonded and fixed to the adjacent second chip 301 of the lower layer through the bonding layer 304 located between the second chip 301 of the upper layer and the second chip 301 of the lower layer to achieve the pre-fixing. When the second chips 301 of the upper and lower layers are bonded and fixed through the bonding layer 304, the micro-bump 302 of the second active surface of the second chip 301 of the upper layer is not in contact with the second connection terminal 303 of the second back side of the adjacent second chip 301 of the lower layer (or the micro-bump 302 of the second active surface of the second chip 301 of the upper layer is suspended above the second back side of the second chip 301 of the lower layer), or the micro-bump 302 of the second active surface of the second chip 301 of the upper layer is slightly in contact with the second connection terminal 303 of the second back side of the adjacent second chip 301 of the lower layer, but there is no bonding connection or welding connection between the micro-bump 302 and the second connection terminal 303. That is, the upper and lower second chips 301 of the present application are bonded and fixed by the bonding layer 304, and there is no need to place a layer of non-conductive adhesive film (Non-Conductive Film) for bonding and isolation of each layer of memory chips in the existing TC-NCF process when stacking chips, so the process is simple and efficient. And the upper and lower second chips 301 of the present application are bonded and fixed by the bonding layer 304, and there is no need to perform a thermal compression bonding on the solder balls at the bottom of each layer of memory chips in the existing MR-MUF process when stacking chips, so as to avoid the micro-bumps 302 on the second chip 301 from undergoing multiple reflows (especially reducing the number of reflows of the micro-bumps 302 on the bottom second chip 301), thereby preventing the collapse or instability of the micro-bumps 302 on the second chip 301 in the stacked chip structure, and also preventing the problem of uneven stacking of the upper and lower second chips 301.

[0059] In one embodiment, when the plurality of second chips 301 are stacked in sequence, the bonding layer 304 can be pre-formed on the second back surface of the stacked lower layer second chip 301, or the bonding layer 304 can also be pre-formed on the second active surface of the upper layer second chip 301 to be stacked.

[0060] In one embodiment, the portion of the bonding layer 304 close to the bottom can be embedded in or located in the passivation layer 305, which can improve the accuracy and firmness of the position of the passivation layer 305 itself on the one hand; on the other hand, it can further improve the firmness of the bonding and fixing between the upper and lower second chips.

[0061] The number of the bonding layers 304 between the upper and lower second chips 301 includes a discrete plurality. In one embodiment, the discrete plurality of bonding layers 304 are evenly distributed between the upper second chip 301 and the adjacent lower second chip 301 to stably support and fix the upper second chip 301. In one embodiment, the positions of the bonding layers 304 of different layers are the same to simplify the stacking process while ensuring stability and flatness during the stacking process. In a specific embodiment, the discrete plurality of bonding layers 304 are evenly distributed between the upper second chip 301 and the adjacent lower second chip 301 at a plurality of positions close to the edge, or may also be other optimized positions.

[0062] In one embodiment, the thickness of the bonding layer 304 is equal to or greater than (slightly greater than) the thickness of the micro-bump 302 .

[0063] The bonding layer 304 is a temporary bonding layer or a mechanical bonding layer. The temporary bonding layer is decomposed during the batch reflow process, while the mechanical bonding layer is not decomposed during the batch reflow process and remains in the stacked package structure.

[0064] In one embodiment, the material of the temporary bonding layer is UV glue or heat-curing glue that can be decomposed at the reflow temperature during the batch reflow process; the temporary bonding layer is also formed between the second chip 301 of the bottom layer and the first chip 201; the reflow temperature of the batch reflow process is 230 degrees Celsius-250 degrees Celsius. On the one hand, the temporary bonding layer can be used for bonding and fixing between the upper and lower second chips 301 when the second chips 301 are stacked, and on the other hand, in the subsequent batch reflow process, the micro-bumps 302 of the second active surface of the upper second chip 301 in the chip stacking structure are welded together with the second connection terminals 303 of the second back side of the adjacent lower second chip 301, and the micro-bumps 302 of the second active surface of the bottom second chip 301 are welded together with the first connection terminals 203 of the first back side of the first chip 201 (refer to Fig.10 ), the temporary bonding layer is easily decomposed in whole or in part during the batch reflow process, thereby preventing or reducing the influence of the temporary bonding layer on the flow of the plastic encapsulation layer material during the subsequent molding bottom filling process. In a specific embodiment, the reflow temperature of the subsequent batch reflow process is 230 degrees Celsius to 250 degrees Celsius, and the reflow temperature is the highest temperature range during the batch reflow process.

[0065] In one embodiment, the temporary bonding layer is entirely made of UV glue or heat-curing glue that can be decomposed at the reflow temperature during the batch reflow process, and the temporary bonding layer is completely decomposed during the batch reflow process. In another embodiment, the temporary bonding layer includes micro-support bumps and a coating layer that covers the micro-support bumps, and the material of the coating layer is UV glue or heat-curing glue that can be decomposed at the reflow temperature during the batch reflow process, and the material of the micro-support bumps is a metal material, an organic material, or an inorganic material that will not decompose at the reflow temperature during the batch reflow process; when the batch reflow process is performed, the coating layer in the temporary bonding layer is decomposed, and the micro-support bumps are retained. The coating layer plays the role of bonding and fixing the upper and lower second chips 301 during the aforementioned chip stacking. During the subsequent batch reflow process, the coating layer decomposes at the reflow temperature, while the micro-support bumps will not decompose at the reflow temperature during the batch reflow process, and will be retained between the upper and lower second chips 301 to support the upper second chip 301, so as to better ensure the mechanical stability and flatness of the chip stacking structure, prevent the chip stacking structure from being tilted or uneven during the batch reflow process, thereby further improving the welding accuracy of the micro-bumps 302 of the upper second chip 301 and the second connection terminals 203 of the lower second chip 301 during the batch reflow process, and can more effectively prevent deformation or short circuit between the micro-bumps 302 on the lower second chip 301 due to excessive pressure.

[0066] In one embodiment, when the temporary bonding layer is UV glue, the temporary bonding layer is cured by UV light irradiation during the stacking process; when the temporary bonding layer is thermal curing glue, the temporary bonding layer is cured by thermal reflow during the stacking process. In one embodiment, the process of stacking a plurality of the second chips 301 is performed in a bonding device, and the bonding device includes a thermal compression bonding (TCB) device or a laser compression bonding (LCB) device.

[0067] In one embodiment, the material of the mechanical bonding layer is a non-conductive glue or a non-conductive adhesive film. On the one hand, the mechanical bonding layer can be used for bonding and fixing the upper and lower second chips 301 when the second chips 301 are stacked. On the other hand, during the subsequent batch reflow process, the mechanical bonding layer will not decompose at high temperature. The mechanical bonding layer is in a softened or semi-softened state and can still provide support for the upper second chip 301, thereby improving the flatness and mechanical stability of the chip stacking structure during the batch reflow process, preventing the chip stacking structure from tilting or being uneven during the batch reflow process, thereby improving the welding accuracy of the micro-bumps 302 of the upper second chip 301 and the second connection terminals 203 of the lower second chip 301 during the batch reflow process, and preventing deformation or short circuit between the micro-bumps 302 on the lower second chip 301 due to excessive pressure.

[0068] In one embodiment, the mechanical bonding layer of the non-conductive glue or non-conductive adhesive film material may be in a softened state or a semi-softened state at a reflow temperature during a subsequent batch reflow process. The reflow temperature of the batch reflow process is generally 230 degrees Celsius to 250 degrees Celsius.

[0069] In one embodiment, the mechanical bonding layer is entirely made of non-conductive glue or non-conductive adhesive film.

[0070] In another embodiment, the mechanical bonding layer includes a micro-support bump and a coating layer covering the micro-support bump, the material of the coating layer is a non-conductive glue or a non-conductive adhesive film material, the material of the micro-support bump is a metal material, an organic material or an inorganic material that will not soften at the reflow temperature during the batch reflow process, the metal material is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver, the organic material is a polymer or resin, and the inorganic material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The formation process of the temporary bonding layer includes first forming the micro-support bump on the second back side or second active surface of the second chip 301, and then forming the coating layer covering the micro-support bump. The micro-support bump can be formed when the second chip 301 is formed by a front-end integrated manufacturing process, that is, before a number of second chips 301 on the wafer are cut, the micro-support bump is formed on the second back side or second active surface of the second chip on the wafer. The coating layer plays a role in bonding and fixing the upper and lower second chips 301 during the aforementioned chip stacking. During the subsequent batch reflow process, the coating layer can be softened or semi-softened at the reflow temperature, while the micro-support bumps will not soften at the reflow temperature during the batch reflow process, and can better and more stably support the upper second chip 301, so as to better ensure the mechanical stability and flatness of the chip stacking structure, prevent the chip stacking structure from being tilted or uneven during the batch reflow process, thereby further improving the welding accuracy of the micro-bumps 302 of the upper second chip 301 and the second connection terminals 203 of the lower second chip 301 during the batch reflow process, and can more effectively prevent deformation or short circuit between the micro-bumps 302 on the lower second chip 301 due to excessive pressure.

[0071] refer to Figure 4 or Figure 8 , a mass reflow bonding (MR) process is performed to weld the micro-bumps 302 of the second active surface of the second chip 301 of the upper layer in the chip stacking structure to the second connection terminals 303 of the second back surface of the adjacent lower layer second chip 301, and the micro-bumps 302 of the second active surface of the second chip 301 of the bottom layer to the first connection terminals 203 of the first back surface of the first chip 201. When the bonding layer 304 is the mechanical bonding layer, the mechanical bonding layer still adheres and fixes the upper and lower first chips 301 during the mass reflow process (refer to Figure 8 ), when the bonding layer 304 is a temporary bonding layer, the temporary bonding layer is decomposed during the batch reflow process (refer to Fig.10 ).

[0072] refer to Figure 5 , or refer to Fig. 9, or refer to Fig.10 , a molded underfill (MUF) process is performed to form a plastic layer 102 that covers the chip stacking structure and the first chip 201, and fills the second chips 301 in the upper and lower layers, between the second chip 301 and the first chip 201 in the bottom layer, and between the first chip 201 and the upper surface of the substrate 101. The guide channel 306 is beneficial to the flow and filling of the plastic layer material when forming the plastic layer 102.

[0073] In one embodiment, the material of the molding layer 102 is liquid epoxy molding compound (LMC). In other embodiments, the material of the molding layer 102 may also be other liquid resin molding compounds, such as liquid polyimide resin molding compounds, liquid benzocyclobutene resin molding compounds, or liquid polybenzoxazole resin molding compounds.

[0074] In one embodiment, the reflow curing temperature when forming the plastic encapsulation layer 102 is 160 degrees Celsius to 180 degrees Celsius.

[0075] In one embodiment, the plastic encapsulation layer 102 may cover or expose the second back side of the second chip 301 of the top layer. In one embodiment, the plastic encapsulation layer 102 may also cover the first chip 201 and fill the space between the first chip 201 and the substrate 101 .

[0076] In one embodiment, continue to refer to Fig.10 When the bonding layer 304 is a temporary bonding layer, the temporary bonding layer is decomposed during the batch reflow process. At this time, a groove is formed at the position of the bonding layer 304 in the passivation layer 305. When the plastic encapsulation layer 102 is formed, the groove is also filled with the plastic encapsulation layer 102 material, which can further improve the firmness of the bonding and fixing between the upper and lower second chips 301.

[0077] Another embodiment of the present application further provides a stacked package structure. Figure 5 or Figure 8 or Fig. 9 , and combined with reference Figure 2-Figure 3 ,include:

[0078] A substrate 101, wherein the substrate 101 includes an upper surface and a lower surface opposite to each other;

[0079] A first chip 201, wherein the first chip 201 comprises a first active surface and a first back surface opposite to each other, wherein the first active surface has a welding protrusion 202, and the first back surface has a first connection terminal 203, and the first active surface of the first chip 201 is mounted on the upper surface of the substrate 101 with the first active surface facing downward, and the welding protrusion 202 is welded to the substrate 101;

[0080] A chip stacking structure located on the first back side of the first chip 201, the chip stacking structure comprising a plurality of second chips 301 stacked in sequence in a vertical direction, each of the second chips 301 comprising a second active surface and a second back side opposite to each other, the second active surface having a micro-bump 302, the second back side having a second connection terminal 303, at least one guide channel 306 extending from one end of the second chip 301 to the other end of the second chip 301 is arranged between the plurality of discrete micro-bumps 302, and the widths of the two ends of the guide channel 306 are greater than the width of the middle position of the guide channel 306, the second active surface of each second chip 301 faces downward, the micro-bump 302 of the second active surface of the second chip 301 of the upper layer in the chip stacking structure is welded to the second connection terminal 303 of the second back side of the adjacent second chip 301 of the lower layer, and the micro-bump 302 of the second active surface of the second chip 301 of the bottom layer is welded to the first connection terminal 203 of the first back side of the first chip 201;

[0081] The plastic encapsulation layer 102 covers the chip stacking structure and the first chip 201, and fills the second chips 301 in the upper and lower layers, between the second chip 301 in the bottom layer and the first chip 201, and between the first chip 201 and the upper surface of the substrate 101. The guide channel 306 is beneficial to the flow and filling of the plastic encapsulation layer material when forming the plastic encapsulation layer 102.

[0082] In one embodiment, the number of the guide channels 306 is one or more, and when the number of the guide channels 306 is multiple, the multiple guide channels 306 are arranged in parallel. The second active surface of the second chip 301 has a passivation layer 305, the micro-protrusions 302 are partially located in the passivation layer 305, and the passivation layer 305 between the several discrete micro-protrusions 302 is provided with at least one guide groove 307 extending in the same direction as the guide channel 306, and the guide groove 307 is located directly below the corresponding guide channel 306.

[0083] In one embodiment, the guide channel 306 and the guide groove 307 are both arranged along the direction in which the plastic encapsulation layer material flows in; the setting directions of the guide channel 306 of the upper layer and the guide channel 306 of the lower layer can be the same or different; the widths of the two ends of the guide groove 307 are equal to or greater than the width of the middle position of the guide groove 307.

[0084] In one embodiment, the width of the two ends of the guide channel 306 is greater than the width of the middle position of the guide channel, which includes: the width of the guide channel 306 gradually decreases from the two ends to the middle position.

[0085] In one embodiment, reference Fig. 9 A bonding layer 304 is provided between the upper second chip 301 and the adjacent lower second chip 301 , and the bonding layer 304 is used for bonding and fixing the upper and lower second chips 301 when the second chips 301 are stacked.

[0086] In one embodiment, the material of the bonding layer 304 is non-conductive glue or non-conductive adhesive film; the bonding layer 304 is also formed between the second chip 301 and the first chip 201 of the bottom layer.

[0087] In one embodiment, the bonding layers 304 are discretely multiple and evenly distributed between the second chip 301 of the upper layer and the adjacent second chip 301 of the lower layer. The bonding layers 304 of different layers are located at the same position.

[0088] In one embodiment, it further includes: a third chip (not shown in the figure) mounted on the upper surface of the substrate 101 on one side of the first chip 201, and the third chip is electrically connected to the substrate.

[0089] In one embodiment, the first chip 201 is a logic chip, the second chip 301 is a memory chip, and the third chip is a processing chip.

[0090] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a stacked package structure, characterized in that: include: providing a substrate, the substrate comprising opposing upper and lower surfaces; Providing a first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, mounting the first active surface of the first chip on the upper surface of the substrate with the first active surface facing downward, and the welding protrusion being welded to the substrate; A plurality of second chips are provided, each of the second chips comprises a second active surface and a second back surface opposite to each other, the second active surface has a plurality of discrete micro-bumps, the second back surface has a plurality of discrete second connection terminals, at least one guide channel extending from one end of the second chip to the other end of the second chip is provided between the plurality of discrete micro-bumps, and the width of the guide channel at the edge position of the second chip is greater than the width of the guide channel at the middle position of the second chip; forming a chip stacking structure on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, the second active side of each second chip facing downward, the micro-bumps on the second active side of the second chip in the upper layer of the chip stacking structure being welded together with the second connection terminals on the second back side of the second chip in the adjacent lower layer, and the micro-bumps on the second active side of the second chip in the bottom layer being welded together with the first connection terminals on the first back side of the first chip; A molding bottom filling process is performed to form a plastic layer that covers the chip stacking structure and the first chip, and fills between the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The guide channel is conducive to the flow and filling of the plastic layer material when the plastic layer is formed.

2. The method for forming a stacked package structure according to claim 1, wherein: The number of the guide channels is one or more. When the number of the guide channels is multiple, the multiple guide channels are arranged in parallel; a passivation layer is provided on the second active surface of the second chip, the micro-protrusion portion is located in the passivation layer, and at least one guide groove with the same extension direction as the guide channel is provided in the passivation layer between the several discrete micro-protrusions, and the guide groove is located directly below the corresponding guide channel.

3. The method for forming a stacked package structure according to claim 1 or 2, wherein: The guide channel and the guide groove are both arranged along the direction in which the plastic encapsulation layer material flows in; the width of the guide groove at the edge of the second chip is equal to or greater than the width of the guide groove at the middle of the second chip.

4. The method for forming a stacked package structure according to claim 1 or 2, wherein: The guiding channels of the upper layer and the guiding channels of the lower layer may be arranged in the same direction or in different directions.

5. The method for forming a stacked package structure according to claim 1 or 2, wherein: The width of the guide channel at the edge of the second chip is greater than the width of the guide channel at the middle of the second chip, which includes: the width of the guide channel gradually decreases from the edge of the second chip to the middle of the second chip.

6. The method for forming a stacked package structure according to claim 1, wherein: The process of forming a chip stacking structure on the first back side of the first chip includes a pre-fixing process and a batch reflow process; the pre-fixing process is first performed to stack and pre-fix a plurality of the second chips in sequence in a vertical direction; and the batch reflow process is performed to weld the micro-bumps on the second active surface of the second chip in the upper layer of the chip stacking structure to the second connecting terminal on the second back side of the adjacent second chip in the lower layer, and the micro-bumps on the second active surface of the second chip in the bottom layer to the first connecting terminal on the first back side of the first chip.

7. The method for forming a stacked package structure according to claim 6, wherein: When the pre-fixing process is performed, the second chip of the upper layer and the second chip of the adjacent lower layer are pre-fixed by pre-soldering the corresponding second connecting terminals through the soldering flux in or on the surface of the micro-bumps.

8. The method for forming a package-on-package structure according to claim 6, wherein: When the pre-fixing process is performed, the second chip of the upper layer is bonded and fixed to the adjacent second chip of the lower layer via a bonding layer located between the second chip of the upper layer and the second chip of the lower layer to achieve the pre-fixing.

9. The method for forming a package-on-package structure according to claim 8, wherein: The bonding layer is a temporary bonding layer or a mechanical bonding layer. The temporary bonding layer is decomposed during a batch reflow process, and the mechanical bonding layer is not decomposed during the mechanical bonding process and remains in the stacked package structure.

10. A stacked package structure, characterized in that: include: a substrate comprising opposing upper and lower surfaces; A first chip, the first chip comprising a first active surface and a first back surface opposite to each other, the first active surface having a welding protrusion, the first back surface having a first connecting terminal, the first active surface of the first chip being mounted downward on the upper surface of the substrate, the welding protrusion being welded to the substrate; A chip stacking structure located on the first back side of the first chip, the chip stacking structure comprising a plurality of second chips stacked in sequence in a vertical direction, each of the second chips comprising a second active surface and a second back side opposite to each other, the second active surface having a plurality of discrete micro-bumps, the second back side having a plurality of discrete second connection terminals, at least one guide channel extending from one end of the second chip to the other end of the second chip is provided between the plurality of discrete micro-bumps, and the widths of the two ends of the guide channel are greater than the width of the middle position of the guide channel, the second active surface of each second chip faces downward, the micro-bumps of the second active surface of the second chip of the upper layer in the chip stacking structure are welded to the second connection terminals of the second back side of the second chip of the adjacent lower layer, and the micro-bumps of the second active surface of the second chip of the bottom layer are welded to the first connection terminals of the first back side of the first chip; A plastic encapsulation layer is provided to cover the chip stacking structure and the first chip, and to fill the second chips in the upper and lower layers, between the second chip in the bottom layer and the first chip, and between the first chip and the upper surface of the substrate. The guide channel is beneficial to the flow and filling of the plastic encapsulation layer material when the plastic encapsulation layer is formed.

11. The package-on-package structure according to claim 10, wherein: The number of the guide channels is one or more. When the number of the guide channels is multiple, the multiple guide channels are arranged in parallel; a passivation layer is provided on the second active surface of the second chip, the micro-protrusion portion is located in the passivation layer, and at least one guide groove with the same extension direction as the guide channel is provided in the passivation layer between the several discrete micro-protrusions, and the guide groove is located directly below the corresponding guide channel.

12. The package stacking structure according to claim 10 or 11, wherein: The guide channel and the guide groove are both arranged along the direction in which the plastic encapsulation layer material flows in; the setting directions of the guide channel of the upper layer and the guide channel of the lower layer can be the same or different; the widths of the two ends of the guide groove are equal to or greater than the width of the middle position of the guide groove.

13. The package-on-package structure according to claim 10 or 11, wherein: The width of the two ends of the guide channel is greater than the width of the middle position of the guide channel, which includes: the width of the guide channel gradually decreases from the two ends to the middle position.

14. The package-on-package structure according to claim 10, wherein: A third chip is also mounted on the upper surface of the substrate on one side of the second chip, and the third chip is electrically connected to the substrate; the first chip is a logic chip, the second chip is a storage chip, and the third chip is a processing chip.

Images