A packaging process and product for solving the problem of poor wetting of small-diameter bumps at the chip edge in FCQFN products.

Abstract

This invention relates to the field of chip packaging technology, specifically to a process and product for solving the problem of poor wetting of small-diameter bumps on the edge of FCQFN product chips. The process includes the following steps: S1, fabricating a screen printing process with a one-to-one correspondence between bumps and leads according to the frame drawing and bump mounting positions, and then printing flux onto the frame surface using screen printing to obtain a pre-treated frame; S2, performing a first reflow soldering process on the pre-treated frame to obtain a frame to be mounted; S3, mounting the chip onto the frame to obtain a mounted chip; S4, performing a second reflow soldering process on the mounted chip to complete the reflow soldering of the bumps and frame leads, obtaining the finished FCQFN product chip. This invention solves the problem of poor solder wetting in the prior art by removing the anti-oxidation layer on the frame surface through flux printing and reflow soldering, and then mounting the chip and reflow soldering, thereby improving the product yield and reliability.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, specifically to a packaging process and product that solves the problem of poor wetting of small-diameter bumps on the edge of FCQFN product chips. Background Technology

[0002] QFN (Quad Flat No-leads Package) is a surface-mount package. It uses a bare copper frame as the flip-chip substrate, with the lead surfaces directly soldered to the bump solder. For some chips, due to electrical performance requirements, the diameter of the edge bump is much smaller than that of other bumps in the chip bump design. For example, the difference in diameter between large and small bumps can be greater than 25µm, while a normal difference is within 20µm, as shown below. Figure 1 , 2 The chip design shown has an edge bump diameter of 65µm and other bump diameters of 100µm, with a diameter difference of 35µm.

[0003] Under current bumping process capabilities, the height difference between small-diameter bumps and large-diameter bumps at the top edge tends to approach the upper limit of process control. This is because the smaller the diameter of the chip edge bumps, the more difficult it is to control the height difference with the large-diameter bumps. After the chip is attached to the frame in the flip-chip process of packaging, there may be missing flux markings on the small-diameter bumps (e.g.) Figure 3 As shown). After reflow soldering, poor die shearing and poor cross-section wetting occur when the small-diameter bumps at the chip edge are soldered to the bare copper frame surface (e.g. Figure 4 As shown), the cause of the poor wetting phenomenon is analyzed as follows: the height of the small-diameter bump at the edge is lower than the height of the large-diameter bump. When the bumping process accuracy is close to the lower limit (such as...), Figure 5 As shown in the figure, the height difference between small-diameter bumps and large-diameter bumps exceeds the current flip-chip process capability. When applying flux during the flip-chip process, small-diameter bumps cannot pick up enough flux due to their low height, resulting in the inability to effectively remove the anti-oxidation layer on the bare copper frame welding surface during reflow soldering, leading to poor solder wetting. Summary of the Invention

[0004] To address the problem of poor solder wetting caused by the inability to effectively remove the anti-oxidation layer on the solder surface of the bare copper frame during reflow soldering in existing technologies, this invention provides a packaging process that solves the problem of poor wetting of small-diameter bumps on the chip edge of FCQFN products.

[0005] This invention is achieved through the following technical solution:

[0006] A packaging process for resolving poor wetting of small-diameter bumps at the chip edge in FCQFN products includes the following steps:

[0007] S1. According to the frame drawing and the bump mounting position, make a screen with one-to-one correspondence between bumps and pins, and then use screen printing to print flux on the frame surface to obtain a pre-treated frame.

[0008] S2, the pre-processed frame undergoes its first reflow soldering process to obtain the frame to be cored;

[0009] S3, the chip is mounted on the frame to be mounted, and the mounted chip is obtained;

[0010] S4. Perform a second reflow soldering process on the mounted chip to complete the reflow soldering of the bumps and frame pins, and obtain the finished FCQFN product chip.

[0011] Preferably, in S1, the wire mesh is woven from stainless steel.

[0012] Preferably, the thickness of the wire mesh is 40~50μm.

[0013] Preferably, in S1, the area of ​​the mesh is 80% of the area of ​​the protrusions.

[0014] Preferably, in S1, the flux printing thickness is 40±0.5μm.

[0015] Preferably, the flux used is a water-free flux with low residue.

[0016] Preferably, in S2, during the first reflow soldering process, the temperature is 240~245℃ and the time is 40~45S.

[0017] Preferably, in S3, the chip mounting is completed within 30 minutes after the first reflow soldering process on the chip frame.

[0018] Preferably, in S4, during the second reflow soldering process, the temperature is 245~250℃ and the time is 45~55s.

[0019] A product obtained by using a packaging process to solve the problem of poor wetting of small-diameter bumps on the edge of FCQFN product chips.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] This invention provides a packaging process to address the issue of poor wetting of small-diameter bumps on the edge of FCQFN product chips. The process first involves reflowing printed flux to remove the antioxidant layer on the frame surface. Then, the chip is mounted and reflow soldered. The first reflow soldering removes the antioxidant layer from the frame surface, improving the cleanliness and activity of the soldering surface and providing good bonding conditions for subsequent soldering processes. The second reflow soldering completes the electrical connection between the bumps and the frame pins, thus solving the problem of poor solder wetting in existing technologies and improving product yield and reliability.

[0022] Furthermore, limiting the material and thickness of the screen is to ensure the stability of the screen and the printing accuracy.

[0023] Furthermore, limiting the thickness of the flux is to ensure uniformity and wetting effect, while selecting a waterless and low-residue flux is to reduce subsequent cleaning steps and potential residue problems.

[0024] Furthermore, the chip mounting is completed within 30 minutes after the first reflow soldering process. Performing this operation within this time helps maintain the activity of the flux and good wetting performance. Attached Figure Description

[0025] Figure 1 This is a design schematic diagram of a chip in the existing technology;

[0026] Figure 2 This is a design schematic diagram of a chip from another perspective in the existing technology;

[0027] Figure 3 This is a diagram illustrating the phenomenon of missing flux markings on small-diameter bumps of a chip in existing technology.

[0028] Figure 4 This is a diagram illustrating the phenomenon of poor cross-section wetting in existing technologies;

[0029] Figure 5 This is a schematic diagram of the protrusion wetting process in the prior art;

[0030] Figure 6 This is a flowchart of a packaging process for solving the problem of poor wetting of small-diameter bumps on the edge of FCQFN product chips according to the present invention;

[0031] Figure 7 This is a schematic diagram of a product chip manufactured using a packaging process that solves the problem of poor wetting of small-diameter bumps on the edge of FCQFN product chips. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0033] This invention discloses a packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips, referring to... Figure 6 , 7 This includes the following steps:

[0034] S1. According to the frame drawing and the bump mounting positions, a screen is made to correspond one-to-one with the bumps and pins. Then, flux is printed onto the frame surface using screen printing equipment to obtain a pre-treated frame. The screen material, thickness, and mesh design meet process requirements to improve printing accuracy and flux uniformity. In this embodiment, the screen is woven from stainless steel, with a thickness controlled at 40-50 μm, and the mesh area is 80% of the bump area. The flux printing thickness is 40 ± 0.5 μm. A water-free, low-residue flux is used, such as NC-809 ultra-low residue flux, 3M flux, or Alpha flux. Water-free, low-residue flux reduces subsequent cleaning steps and potential residue problems, improving product reliability.

[0035] S2, the pre-treated frame undergoes its first reflow soldering process to obtain the frame ready for chip mounting. Specifically, after flux printing, the frame must pass through a reflow oven within 30 minutes. During the first reflow soldering process, the temperature is 240~245℃, and the time is 40~45 seconds, to effectively remove the anti-oxidation film or oxide components from the bare copper surface. The 30-minute reflow soldering time limit is crucial to maintain the flux's activity and wetting properties, ensuring an effective coating is formed on the frame surface and ready for bonding with the subsequent chip bumps. The parameters for the first reflow soldering are designed to effectively remove the anti-oxidation film or oxide components from the bare copper surface of the frame, providing good surface conditions for subsequent soldering. Secondly, it ensures the flux fully penetrates and acts on the soldering surface while preventing damage to the frame or affecting soldering quality due to excessively long high-temperature treatment.

[0036] S3, the chip is mounted onto the frame to be mounted, thus obtaining the mounted chip; that is, the frame after the first reflow soldering enters the flip chip mounting equipment within 30 minutes to complete the chip mounting.

[0037] S4 involves a second reflow soldering process to complete the reflow soldering of the bumps and frame pins, resulting in the finished FCQFN product chip. During this second reflow soldering process, the temperature is 245~250℃ and the time is 45~55s.

[0038] This invention also discloses a product obtained by addressing the problem of poor wetting of small-diameter bumps on the chip edges of FCQFN products. During the chip packaging process, the anti-oxidation layer on the frame surface is first removed by printing flux and performing a first reflow soldering, followed by chip mounting, and finally a second reflow soldering. This successfully solves the problem of poor wetting of small-diameter bumps, thereby improving the electrical performance and reliability of the product. This product can be widely used in electronic products requiring high-density, high-reliability packaging, such as mobile communication equipment, computers, automotive electronics, and industrial control.

[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the technical solution of the present invention in any way. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can be modified and replaced in several simple ways, and these modifications and replacements are all within the scope of protection covered by the claims.

Claims

1. A packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips, characterized in that, Includes the following steps: S1. According to the frame drawing and the bump mounting position, make a screen with one-to-one correspondence between bumps and pins, and then use screen printing to print flux on the frame surface to obtain a pre-treated frame. S2, the pre-processed frame undergoes its first reflow soldering process to obtain the frame to be cored; S3, the chip is mounted on the frame to be mounted, and the mounted chip is obtained; S4. Perform a second reflow soldering process on the mounted chip to complete the reflow soldering of the bumps and frame pins, and obtain the finished FCQFN product chip.

2. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, In S1, the wire mesh is woven from stainless steel.

3. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, The thickness of the screen is 40~50μm.

4. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, In S1, the mesh design requires 80% of the bump area.

5. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, In S1, the flux printing thickness is 40±0.5μm.

6. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, The flux used is a water-free flux with low residue.

7. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, In S2, during the first reflow soldering process, the temperature is 240~245℃ and the time is 40~45S.

8. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, In S3, the chip mounting is completed within 30 minutes after the first reflow soldering process in the chip mounting frame.

9. The packaging process for solving the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips according to claim 1, characterized in that, In S4, during the second reflow soldering process, the temperature is 245~250℃ and the time is 45~55s.

10. A product obtained by the packaging process according to any one of claims 1 to 9 to solve the problem of poor wetting of small-diameter bumps at the edge of FCQFN product chips.

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