Method of manufacturing semiconductor device and corresponding semiconductor device

Abstract

The invention relates to a method of manufacturing a semiconductor device and a corresponding semiconductor device. A semiconductor die is mounted on a substrate having a conductive substrate portion. The conductive substrate portion includes a die mounting location and a conductive lead surrounding the die mounting location. A semiconductor die is mounted on the first surface of the die mounting location. The substrate and the semiconductor die are packaged in an electrically insulating package having a surface opposite the first surface. A conductive path is provided to electrically couple the semiconductor die to one of the conductive substrate portions. The electrically conductive path includes: a first path segment extending through and / or over the electrically insulating package between the conductive substrate portion and an intermediate point at a surface of the electrically insulating package; and a second path segment provided via wire bonding and extending between the semiconductor die and an intermediate point at a surface of the electrically insulating package.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000014250 filed on Jul. 7, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] This description relates to fabricating semiconductor devices.

[0004] One or more embodiments may be applied to fabricating integrated circuit (IC) semiconductor devices, for example, for automotive applications. Background Art

[0005] Semiconductor devices provided with a so-called quad flat package (QFP), for example, for automotive or industrial applications, may have a relatively large number of input / output (I / O) pins (or leads).

[0006] For example, in the case of a super high density (SHD) or super super high density (SSHD) device, there may be more than a hundred pins.

[0007] In such leadframe-based packages, a semiconductor chip / die is arranged on a die pad of a leadframe and electrically coupled to a plurality of leads disposed around the die pad.

[0008] Wires are typically used to provide the desired coupling between the semiconductor die and the leads.

[0009] Wires may also be used to provide electrical coupling between the semiconductor die and a die pad, which is often used to provide a ground level for the device.

[0010] Using current processing techniques (such as stamping or etching), leads can be formed with a minimum pitch of approximately 150 microns to 180 microns; due to the relatively large number of leads and the reduced package size, the distance between the die pad and the proximal end of the lead cannot be reduced beyond a minimum value, resulting in relatively long wires coupling the die to the leads.

[0011] It has been observed that longer wires are more prone to problems associated with the molding step; in fact, current manufacturing processes for semiconductor devices include a molding step in which a resin or epoxy molding compound (e.g., EMC, epoxy) is molded onto the device to form a protective plastic body. During this process, the flow of resin in the molding cavity can cause the wire to "sweep," i.e., deform in response to the viscous drag exerted by the flowing molding compound.

[0012] Wire sweeps may exceed specifications or, in the worst case, cause two adjacent wires to touch, creating an undesirable short circuit.

[0013] Furthermore, it has been found that long wires tend to be more susceptible to damage (failure) during handling (or merely processing, for example) of the device.

[0014] Damaged or shorted wires may cause device failure during processing and, therefore, rejection, adversely affecting manufacturing yields and resulting in relatively low time and cost efficiency of the manufacturing process.

[0015] There is a need in the art for embodiments that overcome the above-mentioned shortcomings. Summary of the invention

[0016] One or more embodiments are directed to a method.

[0017] One or more embodiments relate to a corresponding semiconductor device.

[0018] The solutions described herein help reduce the length of wires used to electrically couple a semiconductor die to a lead or die pad.

[0019] In a solution as described herein, a portion of the conductive path providing the desired coupling is formed via deposition / growth of a conductive material (eg, a metal such as copper).

[0020] The solution described herein may utilize laser direct structuring (LDS) to form a portion of the required electrical coupling. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0022] Figure 1 is a plan view illustrating the structure of a semiconductor device;

[0023] FIG. 2A to FIG. 2F is a series of cross-sectional views illustrating processing steps according to an embodiment of the present specification;

[0024] Figure 3A and Figure 3B shows processing steps according to an embodiment of the present specification; and

[0025] Figure 4A and Figure 4B are plan views illustrating coupling patterns in a semiconductor device according to a conventional method and according to an embodiment of the present specification, respectively. DETAILED DESCRIPTION

[0026] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0027] The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0028] The edges of a feature drawn in a drawing do not necessarily indicate the end of the extent of the feature.

[0029] In the following description, various specific details are shown to provide a deeper understanding of various examples of embodiments according to the description. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the embodiments.

[0030] References to "one embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc., which may appear in various points of this specification, do not necessarily refer to exactly the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments. The references used herein are provided merely for convenience and therefore do not limit the scope of protection or the scope of the embodiments.

[0031] Figure 1 A portion of an integrated circuit (IC) semiconductor device is shown that includes a semiconductor chip or die 14 (as used herein, the terms chip and die are considered synonymous) arranged on a mounting location 12A (die pad) of a conductive substrate (commonly referred to as a lead frame).

[0032] The name "leadframe" (or "leadframe") (see, e.g., the USPCO's USPC Incorporated Glossary) refers to the metal frame that provides support for an integrated circuit chip or die, and the electrical leads that interconnect the integrated circuits in the die or chip to other components or contacts.

[0033] refer to Figure 1 , the leadframe includes an array of conductive structures or leads 12B extending inwardly from an outline position in the direction of the (integrated circuit) semiconductor chip or die 14, thereby forming an array of conductive structures by a die pad 12A, which is configured to have at least one semiconductor chip or die 14 attached thereto. This can be achieved by, for example, a die attach adhesive (die attach film, such as Figures 2A to 2F and Figure 3A and Figure 3B It is achieved by conventional means as shown in FIG. 1 and represented here by the reference character DA).

[0034] Conductive structures are provided to electrically couple the semiconductor chip to selected ones of the leads (external pads) 12B in the lead frame.

[0035] As shown, such coupling may be provided by a wire bonding pattern of wires 16, as is conventional in the art.

[0036] After electrical coupling is formed between chip 14 and leads 12B, an encapsulation material, such as epoxy molding compound (EMC), is molded over the thus formed assembly to provide a protective plastic package for the device.

[0037] The molding step is typically performed by placing the lead frame with the die 14 mounted thereon in a molding cavity, wherein a molding compound is injected at a relatively high pressure.

[0038] like Figure 1 The integrated circuit semiconductor device shown may have a relatively large number of input / output (I / O) leads 12B; for example, a device such as a microcontroller or an ASIC for automotive applications provided with a quad flat package (QFP) as shown in the drawing may have more than a hundred leads 12B.

[0039] The minimum pitch of leads 12B achievable with current technology—approximately 150 to 180 microns, depending on the technique used to form the leadframe and leads 12B (e.g., etching or stamping)—can reduce device design flexibility when a large number of leads 12B are required, such as in so-called super high density (SHD) or super-ultra high density (SSHD) devices.

[0040] Due to the minimum lead pitch, the distance between leads 12B and die pad 12A cannot be reduced beyond a certain value: therefore, relatively long wires 16 are used to provide the required electrical coupling between semiconductor die 14 (mounted / attached to die pad 12A) and I / O leads 12B.

[0041] It has been observed that long wires 16 are more susceptible to deformation (bending) in response to the drag forces exerted by the viscous flow of the molding compound during the molding step. Excessive sweeping may result in the rejection of the device, and in the worst case, may cause adjacent wires to contact to form an undesirable short circuit leading to device failure (and rejection).

[0042] Figure 1 Wire sweeping, ie, undesired displacement of the wire 16 caused by conventional molding processes, is shown.

[0043] In the case of some exemplary conductive lines 16, this effect is represented by showing the position of the wire 16 before and after the molding process with dashed and solid lines, respectively.

[0044] It has been found that long wires are also more susceptible to damage or failure during processing / handling of the device.

[0045] The solution described herein aims to overcome the above mentioned drawbacks.

[0046] The solution described herein can be advantageously applied to SHD or SSHD devices having a QFP type package.

[0047] The solution described herein helps to reduce the length of the wire, thereby reducing its sweep and damage.

[0048] The solution described herein comprises providing a first partial package and subsequently forming the desired electrical coupling.

[0049] In a solution as described herein, the desired electrical coupling is provided by forming a conductive path comprising two parts: a first part provided via growth / deposition of a conductive material (eg, a metal such as copper); and a second part provided by wire bonding.

[0050] The solution described herein may utilize laser direct structuring (LDS) to form a portion of the required electrical coupling.

[0051] Laser Direct Structuring (LDS) is a laser-based processing technology now widely used in various sectors of the industrial and consumer electronics markets, for example for high-performance antenna integration, where antenna designs can be formed directly onto molded plastic parts.

[0052] In an exemplary process, molded parts may be produced with commercially available insulating resins including additives suitable for the LDS process; a wide range of resins, for example polymer resins such as PC, PC / ABS, ABS, LCP are currently available for this purpose.

[0053] In LDS, a laser beam can be used to transfer ("build") a desired conductive pattern onto a plastic molding, which can then be metallized to complete the desired conductive pattern.

[0054] Metallization may include electroless plating followed by electrolytic plating.

[0055] Electroless plating, also known as chemical plating, is a class of industrial chemical processes that produce metallic coatings on various materials by the autocatalytic chemical reduction of metal cations in a liquid bath.

[0056] In electrolytic plating, an electric field between the anode and the workpiece acting as the cathode forces the positively charged metal ions to move to the cathode where they release their charge and deposit themselves as metal on the surface of the workpiece.

[0057] Refer to U.S. Patent Application Publication Nos. 2018 / 0342453, 2019 / 0115287, 2020 / 0203264, 2020 / 0321274, 2021 / 0050226, 2021 / 0050299, 2021 / 0183748 or 2021 / 0305203 (all of which are incorporated herein by reference) as examples of the possibility of applying LDS technology in the manufacture of semiconductor devices.

[0058] FIG. 2A to FIG. 2F The sequence of FIG. 1 illustrates a sequence of processing steps to provide the desired electrical coupling between die 14 and leads 12B.

[0059] It should also be understood that FIG. 2A to FIG. 2F The sequence of steps is exemplary only insofar as: FIG. 2A to FIG. 2F One or more of the steps shown may be at least partially omitted, performed in a different manner (e.g., with other tools), and / or replaced with other steps; additional steps may be added; and one or more steps may be performed in an order different from that shown.

[0060] Figure 2A A lead frame of a quad flat package (QFP) device is shown, which is an example of a device to which embodiments of the present description may be advantageously applied.

[0061] As shown, the die pad 12A may have a downset relative to the array of conductive leads 12B disposed around the die pad 12A.

[0062] The semiconductor die 14 is arranged (e.g., attached via a die attach material DA) on the top / front surface of the die pad 12A and has a die bonding pad 18 on its top / front surface (only one bonding pad is shown for simplicity) configured to be electrically coupled to a selected lead 12B or die pad 12A.

[0063] The assembly is arranged in a conventional moulding cavity C in order to carry out a first (partial) moulding step.

[0064] For simplicity and ease of explanation, reference will be made to the manufacturing process of a single device in the following description, it being understood that multiple devices may be processed simultaneously and may be separated into individual devices in a final singulation step, as known to those skilled in the art.

[0065] Figure 2B An electrically insulating molding compound 20 (eg, epoxy) is shown molded onto the leadframe (including leads 12B) having the semiconductor die mounted thereon to provide a first partial package for the device.

[0066] As shown, the semiconductor die 14 and the proximal portions of the leads 12B are embedded in the molding compound 20, while the bottom / rear surface of the die pad 12A (configured to be mounted / soldered to a support member such as a printed circuit board PCB) and the distal portions of the leads 12B are not covered by the molding compound 20.

[0067] In certain embodiments, the mold compound 20 used to form the first portion of the package may be a mold compound suitable for LDS; as described above, such a mold compound includes additive particles that can be activated by laser beam energy to promote growth of metal material.

[0068] Figure 2C A laser processing step is illustrated in which laser beam energy LB is applied to the molding compound 20 to construct therein: a via 181 extending from a front / top surface of a portion of the package 20 to a die bonding pad 18 disposed on the front / top surface of the semiconductor die 14; and a trace 182' extending from the lead 12B at the front / top surface of the package 20 to an intermediate position P between the lead 12B and the die 14.

[0069] As shown, laser ablation of mold compound 20 to construct trace 182' advantageously involves constructing additional vias (visible in the figure but not explicitly labeled for simplicity) at the distal ends of trace 182' to expose the metallic material (eg, copper) of lead 12B.

[0070] Those skilled in the art will appreciate that these additional vias are optional as their presence depends on the thickness of mold compound 20 and the relative heights of leads 12B and semiconductor die 14 .

[0071] The trace 182' has a reference number with a superscript mark (') to highlight that the conductive trace / line 182 will (only) be used as shown. Figure 2D The fact that subsequent metal growth is then formed at those locations is represented in .

[0072] In a case where the LDS molding compound has been used to form the first (partial) package 20, laser beam energy LB is applied to the LDS compound (i.e., the molding compound to which the LDS additive is added) to simultaneously remove (ablate) the LDS compound 20 and to "activate" the additive particles embedded in the LDS compound that are exposed at the surface of the LDS compound in response to a portion of the LDS compound being removed (ablated) via the laser.

[0073] Figure 2D Growth / deposition of a metallic material (eg, copper) to form conductive traces 182 is shown.

[0074] For example, the conductive traces 182 may be formed by conductive glue jetting or by laser induced forward transfer (LIFT).

[0075] The acronym LIFT refers to a deposition process in which the transfer of material from a donor tape or sheet to a receptor substrate (here the electrically insulating molding compound 20) is facilitated by laser pulses.

[0076] General information on the LIFT process can be found in, for example, P. Serra et al.:

[0077] “Laser-Induced Forward Transfer: Fundamentals and Applications,” Advanced Materials Technologies / Vol. 4, No. 1 (incorporated herein by reference).

[0078] Advantageously, the traces 182 may be provided using laser direct structuring techniques.

[0079] In this case, a first ("seed") layer of metallic material (eg, copper) is grown via electroless deposition at locations of the mold compound 20 that have been activated via laser energy (ie, traces 182').

[0080] The seed layer grown by electroless deposition facilitates the growth of the (complete) trace 182 by electrolytic growth / deposition.

[0081] However, the trace 182 is formed to provide a first portion (from lead 12B to intermediate point P) of the conductive path from lead 12B to die bond pad 18 on the top / front surface of semiconductor die 14 .

[0082] The plasma cleaning / etching step can be Figure 2D After the growth / deposition steps shown.

[0083] Figure 2E Conductive wire 16 is shown for coupling die pad 18 to the proximal end of conductive trace 182 (approximately at midpoint P). This method may be performed by any conventional method; for example, conventional wire bonding may be used to provide the desired electrical coupling between die pad 18 and the proximal end of trace 182.

[0084] As shown, the conductive line 16 electrically coupling the die bond pad 18 to the trace 182 provides a second portion of the conductive path coupling the lead 12B to the semiconductor die 14 .

[0085] Figure 2F A second molding step is shown which completes the protective plastic encapsulation of the device. A standard (ie, non-LDS) molding compound 22 can be used for this second molding step.

[0086] The shorter wire 16 electrically coupling the semiconductor die 14 to the intermediate point P (ie, the proximal portion of the trace 182) experiences lower drag forces during the second molding step, and therefore less sweeping.

[0087] In a similar manner, the aforementioned processing steps may also be applied to provide electrical coupling between the die bond pad 18 and the die pad 12A (typically providing ground to the device).

[0088] Figure 3A and Figure 3B Processing steps are shown that provide the desired electrical coupling between the semiconductor die 14 and the die pad 12A in accordance with an embodiment of the present description.

[0089] Figure 3A Vias 181, 183' are shown opening through an insulating mold compound 20 molded onto a lead frame on which a semiconductor die 14 is mounted to form a first (partial) package of the device.

[0090] Vias 181 and 183 ′ extend from the top / front surface of the first partial package to the die bond pad 18 and the die pad 12A, respectively.

[0091] As shown, trace 182 ′ may also be formed at the top / front surface of package 20 , extending outward from midpoint P of the top / front surface of package 20 to the end of via 183 at the surface of the first portion of package 20 .

[0092] Furthermore, traces 182' and vias 183' have reference numerals marked with a superscript (') in order to highlight the fact that conductive traces 182 and vias 183 will be formed at those locations (only) after subsequent metal growth.

[0093] Figure 3B A conductive path is shown provided to electrically couple the die bond pad 18 on the top / front surface of the semiconductor die 14 to the die pad 12A.

[0094] Similar to the situation discussed above (for example, regarding Figure 2E ), the conductive path includes two parts / segments, namely: a first segment 182, 183, which extends from the die pad 12A to a midpoint P on the surface of the package 20, formed by deposition / growth of a conductive material (e.g., a metal such as copper); and a second portion from the die bonding pad 18 to the midpoint P provided by wire bonding.

[0095] As shown, a first portion of the conductive path may include vias 183 extending through a portion of the mold compound of the package 20 and traces 182 formed at a surface of the package 20 .

[0096] Also in this case, LDS techniques may be advantageously used to form the first portion of the conductive path, namely the conductive via 183 and the trace 182 .

[0097] The process of providing electrical coupling between the die bond pad 18 and the die pad 12A as previously described results in relatively short conductive lines 16 that are less exposed to problems during molding steps (sweeping) and / or problems during handling steps (failures).

[0098] It should be noted that Figures 2A to 2F The process steps for electrically coupling semiconductor die 14 to lead 12B as illustrated in FIG. Figure 3A and Figure 3B The processing steps illustrated in illustrative embodiments of electrically coupling semiconductor die 14 to die pad 12A may be applied in the same device.

[0099] In practice, some of the die bond pads 18 of the semiconductor die 14 may be configured to be electrically coupled to selected ones of the leads 12B, while other die bond pads 18 may be configured to be electrically coupled to the die pad 12A (eg, to provide a ground level).

[0100] In summary, the solution described herein involves mounting a semiconductor die 14 on a substrate (i.e., a lead frame) having a conductive substrate portion including a die mounting location (die pad) 12A and a plurality of conductive leads 12B surrounding the die mounting location 12A. The semiconductor die 14 is mounted on a first (top / front) surface of the die mounting location 12A.

[0101] The substrate with the semiconductor die 14 mounted thereon is packaged in an electrically insulating package 20. The electrically insulating package 20 has a (top / front) surface opposite to the first surface of the die mounting location 12A.

[0102] One or more conductive paths are provided to electrically couple the semiconductor die 14 to one of the conductive substrate portions (eg, the leads 12B or the die pad 12A).

[0103] The conductive path includes: a first path segment 182, 183, which extends through the electrically insulating package 20 and / or extends above the electrically insulating package 20 between the conductive substrate portion (lead 12B or die pad 12A) and a midpoint P at the surface of the electrically insulating package 20; and a second path segment, which is joined via a wire 16 and extends between the semiconductor die 14 and a midpoint P at the surface of the first package 22.

[0104] The first section of the conductive path pad is provided by deposition / growth of a conductive material (eg a metal such as copper).

[0105] Advantageously, the first section of the conductive path can be provided via LDS technology, which involves, for example: molding an LDS suitable molding compound to form a first (partial) package 20 of a substrate on which the semiconductor die 14 is mounted; transferring the desired pattern to the first package via laser structuring (ablating the LDS molding compound and activating additive particles embedded therein) to form vias 181, 183' and traces 182'; and metallizing the vias 183 and traces 182, which are pre-activated to provide the first portion of the conductive path.

[0106] Figure 4A and Figure 4B is an example of a QFP device (such as an SHD or SSHD), in which according to the conventional method ( Figure 4A ) and according to the embodiments of this specification ( Figure 4B ) provides the desired electrical coupling (for simplicity, only from semiconductor die 14 to lead 12B).

[0107] like Figure 4A As illustrated in FIG. 1 , the conductive line 16 extending between the die bond pad 18 on the top / front surface of the semiconductor die 14 and the lead 12B has a relatively large first length L1 (on average).

[0108] On the contrary, Figure 4B The illustrated embodiment provides only a portion of the desired electrical coupling between the semiconductor die 14 and the leads, namely, only extends to the first portion of the package (at Figure 4A and 4B The wire 16 at the intermediate point P on the surface (not visible in the figure) has a second length L2 which is (on average) smaller than L1.

[0109] Without prejudice to the essential principles, the details and embodiments may vary even significantly with respect to what is described merely by way of example, without departing from the scope of the embodiments.

[0110] The claims are an integral part of the technical teaching provided with respect to the embodiments.

[0111] The scope of protection is determined by the appended claims.

Claims

1. A method comprising: mounting a semiconductor die on a substrate having a conductive substrate portion, wherein the conductive substrate portion includes a die mounting location and a plurality of conductive leads surrounding the die mounting location, wherein the semiconductor die is mounted on a first surface of the die mounting location; encapsulating both the semiconductor die and the substrate in a first electrically insulating package, wherein the first electrically insulating package has a surface opposite the first surface where the die is mounted; providing an opening in the surface of the first electrically insulating package to expose a die bond pad of the semiconductor die; providing a conductive path segment extending through and over the first electrically insulating package between a conductive lead and an intermediate point at the surface of the first electrically insulating package; A wire bond is provided in the opening in the surface of the first electrically insulating package and extends between the die bond pad of the semiconductor die and the conductive path segment at the intermediate point. 2 . The method of claim 1 , further comprising encapsulating the conductive path segments and the wire bonds in a second electrically insulating package. 3 . The method of claim 1 , wherein the die mounting location is disposed displaced relative to the plurality of conductive leads surrounding the die mounting location. The method of claim 1 , wherein the first electrically insulating encapsulation comprises a laser direct structuring (LDS) molding compound.

5. The method of claim 4, wherein providing the conductive path segments comprises: LDS processing the LDS molding compound to form trace and via openings; as well as Conductive structures are formed at the traces and via openings.

6. The method according to claim 1, further comprising: providing another opening in the first electrically insulating package to expose another die bond pad of the semiconductor die; providing another conductive path segment extending through and on the first electrically insulating package between the substrate and another intermediate point at the surface of the first electrically insulating package; as well as Another wire bond is provided in the further opening and extends between the further die bond pad of the semiconductor die and the further conductive path segment at the further intermediate point. 7 . The method of claim 6 , further comprising encapsulating the conductive path segment, the further conductive path segment, the wire bond, and the further wire bond in a second electrically insulating package.

8. The method of claim 6, wherein the die mounting location is disposed displaced relative to the plurality of conductive leads surrounding the die mounting location.

9. The method of claim 6, wherein the first electrically insulating encapsulation comprises a laser direct structuring (LDS) molding compound.

10. The method of claim 9, wherein providing the further conductive path segment comprises: LDS processing the LDS molding compound to form trace and via openings; as well as Conductive structures are formed at the traces and via openings.

11. A device comprising: a substrate having a conductive substrate portion, wherein the conductive substrate portion includes a die mounting location and a plurality of conductive leads surrounding the die mounting location; a semiconductor die mounted on a first surface of the substrate at the die mounting location; a first electrically insulating package encapsulating both the substrate and the semiconductor die, wherein the first electrically insulating package has a surface opposite the first surface where the die is mounted; an opening in the first electrically insulating package, the opening exposing a die bond pad of the semiconductor die; a conductive path segment extending through and on the first electrically insulating package between a conductive lead and an intermediate point at the surface of the first electrically insulating package; as well as A wire bond is in the opening in the first electrically insulating package and extends between the die bond pad of the semiconductor die and the conductive path segment at the intermediate point.

12. The device of claim 11 further comprising a second electrically insulating package encapsulating the conductive path segments and the wire bonds.

13. The device of claim 11, wherein the die mounting location is disposed displaced relative to the plurality of conductive leads surrounding the die mounting location.

14. The device of claim 11, wherein the first electrically insulating encapsulation comprises a laser direct structuring (LDS) molding compound.

15. The device of claim 14, wherein the conductive path segment comprises: trace and via openings formed in the LDS molding compound by LDS processing; as well as Conductive structures at the trace and via openings.

16. The device according to claim 11, further comprising: another opening, in the first electrically insulating package, the other opening exposing another die bond pad of the semiconductor die; a further electrically conductive path segment extending through the first electrically insulating package between the substrate and a further intermediate point at the surface of the first electrically insulating package and / or extending over the first electrically insulating package between the substrate and the further intermediate point at the surface of the first electrically insulating package; as well as Another wire bond is in the another opening and extends between the another die bond pad of the semiconductor die and the another conductive path segment at the another intermediate point. 17 . The device of claim 16 , further comprising a second electrically insulating package encapsulating the conductive path segment, the further conductive path segment, the wire bond, and the further wire bond.

18. The device of claim 16, wherein the die mounting location is disposed displaced relative to the plurality of conductive leads surrounding the die mounting location.

19. The device of claim 16, wherein the first electrically insulating encapsulation comprises a laser direct structuring (LDS) molding compound.

20. The method of claim 19, wherein the another conductive path segment comprises: trace and via openings formed in the LDS molding compound by LDS processing; as well as Conductive structures at the trace and via openings.

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