Housing, semiconductor module and production method thereof

Abstract

A housing for a power semiconductor module device includes a sidewall and a top portion, where the top portion includes: a first layer of a first material, the first layer including a plurality of openings; and a second layer of a second material, the second material being different from the first material, where the second material has a relative tracking index CTI higher than a relative tracking index CTI of the first material, and at least one of the second layers partially covers at least one of a bottom surface of the first layer and a top surface of the first layer, and the first layer comprises at least one gap, each of the at least one gap being sealed by a section of the second layer such that the second layer forms at least one section of the housing.

Description

Technical Field

[0001] The present disclosure relates to a housing, a semiconductor module including the housing, and a production method thereof. Background Art

[0002] A power semiconductor module arrangement typically includes at least one semiconductor substrate arranged in a housing. A semiconductor arrangement including a plurality of controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) or uncontrollable semiconductor elements (e.g., an arrangement of diodes) is arranged on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are mounted on, for example, the first metallization layer. The second metallization layer can optionally be attached to a base plate. Other semiconductor module arrangements that do not include a substrate are known, for example, semiconductor module arrangements using a cooling structure with a floating potential.

[0003] The semiconductor substrate and the components mounted thereon are usually electrically coupled to the outside of the housing through terminal elements. Such terminal elements are electrically coupled to the substrate or one or more of the components mounted on the substrate with a first end, and extend from the substrate through the housing to the outside of the housing. The power semiconductor module device usually includes a plurality of such terminal elements. Different terminal elements can be coupled to the same or different potentials. If two terminal elements coupled to different potentials are arranged close to each other, the creepage distance between the second ends of such terminal elements located outside the housing may be shorter than the minimum creepage distance. This may lead to an undesirable short circuit, which may have a negative impact on the operation of the power semiconductor module, or even destroy the power semiconductor module device.

[0004] There is a need for a housing and a power semiconductor module including the housing, wherein the length of the creepage distance is equal to or greater than the minimum creepage distance, and the housing and the power semiconductor module can be produced at a relatively low cost. Summary of the invention

[0005] A housing for a power semiconductor module device comprises a side wall and a top, wherein the top comprises: a first layer of a first material, the first layer comprising a plurality of openings; and a second layer of a second material, the second material being different from the first material, wherein the second material has a higher relative tracking index (CTI) than the relative tracking index (CTI) of the first material, and at least one of the second layers partially covers at least one of a bottom surface of the first layer and a top surface of the first layer, and the first layer comprises at least one gap, each of the at least one gap is sealed by a section of the second layer, so that the second layer forms at least one section of the housing.

[0006] A power semiconductor module comprises a semiconductor substrate, at least one semiconductor body arranged on a top surface of the semiconductor substrate, and a housing, wherein the semiconductor substrate on which the at least one semiconductor body is arranged is arranged within the housing or forms a bottom of the housing.

[0007] A method for forming a top portion of an enclosure includes forming a first layer of a first material, the first layer including a plurality of openings, and forming a second layer of a second material, the second material being different from the first material, wherein the second material has a higher relative tracking index (CTI) than the relative tracking index (CTI) of the first material, and at least one of the second layers partially covers at least one of a bottom surface of the first layer and a top surface of the first layer, and the first layer includes at least one gap, each of the at least one gap being sealed by a segment of the second layer, such that the second layer forms at least one segment of the enclosure.

[0008] The present invention may be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily to scale, but rather emphasis is placed on illustrating the principles of the present invention. In addition, in the various drawings, the same reference numerals refer to corresponding parts in different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view of a power semiconductor module device.

[0010] Figure 2 A 3D view of a power semiconductor module arrangement.

[0011] Figure 3 is a cross-sectional view of a section of the housing.

[0012] Figure 4 is a cross-sectional view of another section of the housing.

[0013] FIG. 5A to FIG. 5D A cross-sectional view of a section of a housing according to an embodiment of the present disclosure is schematically shown.

[0014] Figure 6 is a cross-sectional view of a power semiconductor module device according to an embodiment of the present disclosure.

[0015] Figure 7 is a cross-sectional view of another power semiconductor module device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the present invention can be practiced. It should be understood that, unless otherwise specifically noted, the features and principles described with respect to the various examples can be combined with each other. In the specification and in the claims, naming certain elements as "first element", "second element", "third element", etc. should not be understood as being enumerable. On the contrary, such naming is only used to refer to different "elements". That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element". The wires or electrical connectors described herein may be a single conductive element, or include at least two separate conductive elements connected in series and / or in parallel. The wires and electrical connectors may include metal and / or semiconductor materials, and may be permanently conductive (i.e., non-switching). The semiconductor body described herein may be made of (doped) semiconductor material, and may be a semiconductor chip or be included in a semiconductor chip. The semiconductor body has an electrical connection pad, and includes at least one semiconductor element having an electrode.

[0017] refer to Figure 1 , a cross-sectional view of a power semiconductor module device 100 is shown. The power semiconductor module device 100 includes a housing 7 and a semiconductor substrate 10. The semiconductor substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is arranged between the first metallization layer 111 and the second metallization layer 112.

[0018] Each of the first metallization layer 111 and the second metallization layer 112 may consist of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The semiconductor substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may consist of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. In addition, the substrate 10 may be an insulated metal substrate (IMS). For example, the insulated metal substrate generally includes a dielectric insulating layer 11, which includes a (filled) material, such as an epoxy resin or a polyimide. For example, the material of the dielectric insulating layer 11 can be filled with ceramic particles. Such particles can include, for example, SiO2, Al2O3, AlN or BN, and can have a diameter between about 1 μm and about 50 μm. The substrate 10 can also be a conventional printed circuit board (PCB) with a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 can be composed of or include a cured resin.

[0019] The semiconductor substrate 10 is arranged in the housing 7. Figure 1 In the example shown in , the semiconductor substrate 10 forms the grounding surface of the housing 7, while the housing 7 itself includes only side walls and a cover. However, this is only an example. It is also possible that the housing 7 also includes a grounding surface and the semiconductor substrate 10 is arranged inside the housing 7. According to another example, the semiconductor substrate 10 can be mounted on a base plate (not shown). In some power semiconductor module devices 100, more than one semiconductor substrate 10 is arranged on a single base plate. For example, the base plate can form the grounding surface of the housing 7. The top of the housing 7 can be a separate cover or cover plate that can be removed from the side wall, or it can be formed integrally with at least the side wall of the housing 7. In the latter case, the top and at least the side wall of the housing 7 can be formed as a single piece, so that the top cannot be removed from the side wall without destroying the housing. Other semiconductor module devices that do not include a substrate are known, for example, semiconductor module devices using a cooling structure with a floating potential.

[0020] One or more semiconductor bodies 20 may be arranged on the semiconductor substrate 10. Each of the semiconductor bodies 20 arranged on the semiconductor substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable controllable or uncontrollable semiconductor element.

[0021] One or more semiconductor bodies 20 may form a semiconductor device on the semiconductor substrate 10. Figure 1 In FIG. 2 , only two semiconductor bodies 20 are shown by way of example. Figure 1 The second metallization layer 112 of the semiconductor substrate 10 is a continuous layer. Figure 1 In the example shown in , the first metallization layer 111 is a structured layer. "Structured layer" means that the first metallization layer 111 is not a continuous layer, but comprises recesses between different sections of the layer. Figure 1 Schematically illustrating such a recess. In this example, the first metallization layer 111 includes four different sections. Different semiconductor bodies 20 can be mounted to the same section or different sections of the first metallization layer 111. Different sections of the first metallization layer may not be electrically connected, or may be electrically connected to one or more other sections using, for example, bonding wires 3. For example, to name a few examples, the electrical connector 3 may also include a connecting plate or a conductor track. One or more semiconductor bodies 20 may be electrically and mechanically connected to the semiconductor substrate 10 via a conductive connection layer 30. For example, such a conductive connection layer may be a solder layer, a layer of a conductive adhesive, or a layer of a sintered metal powder (e.g., a sintered silver powder).

[0022] Figure 1 The power semiconductor module device 100 shown in FIG. 1 further includes a terminal element 4. The terminal element 4 is electrically connected to the first metallization layer 111 and provides an electrical connection between the inside and the outside of the housing 7. The terminal element 4 can be electrically connected to the first metallization layer 111 at a first end 41, while a second end 42 of the terminal element 4 protrudes out of the housing 7. The terminal element 4 can be electrically contacted from the outside at the second end 42 of the terminal element 4. However, Figure 1 The terminal elements 4 shown in are only examples. The terminal elements 4 can be implemented in any other way and can be arranged at any other position. For example, one or more terminal elements 4 can be arranged close to or adjacent to the side wall of the housing 7. Any other suitable embodiment is possible. For example, the terminal elements 4 can be composed of a metal such as copper, aluminum, gold or silver, or include a metal such as copper, aluminum, gold or silver.

[0023] Conventional power semiconductor module devices 100 also typically include a casting compound 5. For example, the casting compound 5 may be composed of or include silicone gel, or may be a rigid molding compound. The casting compound 5 may at least partially fill the interior of the housing 7, thereby covering the components and electrical connectors arranged on the semiconductor substrate 10. The terminal element 4 may be partially embedded in the casting compound 5. However, at least the second end 42 of the terminal element 4 is not covered by the casting compound 5 and extends from the casting compound 5 (e.g., through the opening 722 of the housing 7 to the outside of the housing 7). The casting compound 5 is configured to protect the components and electrical connectors located inside the power semiconductor module 100 (particularly located inside the housing 7) from certain environmental conditions and mechanical damage. The casting compound 5 also provides electrical isolation of the components located inside the housing 7. The casting compound 5 is typically selected to have a very high CTI (e.g., 600V or greater) so that it is possible to ensure that the terminal elements 4 arranged close to each other have a sufficiently large creepage distance (e.g., the creepage distance on the surface of the casting compound 5).

[0024] Figure 2 A semiconductor module having a plurality of terminal elements 4 (the second end 42 of the terminal element) extending from the top of the housing 7 is schematically shown. The top in this example includes a plurality of openings 722. The terminal element 4 extends from some, but not all, of the openings 722. By providing a plurality of openings 722 in the top, the same housing 7 can be used for a variety of different layouts or applications without having to customize the housing 7 for a specific application or customer. For example, each of the openings 722 may have a circular, square, or any other suitable cross-section, and each terminal element 4 may (centrally) extend through one of the openings 722. However, a housing 7 including more openings 722 (as required) is only an example. The housing 7 may alternatively include the same number of openings 722 as the number of terminal elements 4. That is, for each terminal element 4, a separate opening 722 may be provided, rather than more openings 722. According to other examples, the terminal element 4 may be considered as part of the housing 7. For example, the terminal element may be molded into the material forming the housing 7, or may be snapped into the housing 7 by appropriate elements.

[0025] from Figure 2As can be seen in FIG. 7 , different terminal elements 4 may extend through adjacent openings 722, or through openings 722 arranged relatively close to each other. The terminal elements 4 are generally used to electrically contact components inside the housing 7. Therefore, during use of the power semiconductor module device, one or more of the terminal elements 4 may be coupled to a first potential, while one or more different terminal elements of the terminal elements 4 may be coupled to a second potential. Other terminal elements 4 may also be coupled to even other potentials. In a power semiconductor module device, it is not always possible to arrange terminal elements 4 connected to different potentials away from each other. Therefore, it is possible that a first terminal element 4 is coupled to a first potential (e.g., a positive potential), while another terminal element 4 arranged close to the first terminal element 4 is coupled to a second potential different from the first potential (e.g., a negative potential). In order to avoid short circuits, arcing or breakdown between such adjacent (or close) terminal elements 4, the distance between two corresponding terminal elements 4 should be selected so as to achieve a minimum creepage distance. The creepage distance is generally the shortest path between two conductive parts along the surface of a solid insulating material.

[0026] This is Figure 3 A schematic illustration of a flat surface is given in the cross-sectional view of FIG. Figure 3 A section of the top of the housing 7 between two adjacent terminal elements 4 is schematically shown. In this example, the creepage distance (shown in dashed lines) is defined by the direct path between adjacent terminal elements 4. That is, the creepage distance corresponds to the shortest distance d4 between the terminal elements 4.

[0027] For example, the creepage distance may be extended by providing grooves 730, 732 in the surface of the top and / or providing protrusions 734 on the surface of the top. Figure 4 If the width w732 of the groove 732 is greater than the minimum width, the creepage distance can be extended by doubling the height h734 of the protrusion 734 and / or by doubling the depth d732 of the groove 732. Figure 4 In the example shown, one of the grooves 730 has a width w730 that is less than the minimum width. Therefore, the depth d730 of this groove does not extend the creepage distance. The minimum width of the groove 730 required to achieve the extension of the creepage distance generally depends on different factors, such as the degree of pollution of the environment in which the power semiconductor module device is installed during operation. For example, different degrees of pollution may include a clean room environment, a normal environment, or a highly polluted environment. For example, under normal conditions, the minimum width required for the groove to extend the creepage distance may be 1 mm. In a clean room environment, the minimum width may be shorter, and in a highly polluted environment, it may be longer.

[0028] The required creepage distance also depends on the material of the corresponding surface. For example, different materials do have different properties, such as different relative tracking indices (CTI). CTI is a proportionality factor required for the correct calculation of the creepage distance. In particular, for power semiconductor modules with very high requirements in terms of electrical isolation, materials with a high CTI may be required. In general, it can be said that the higher the CTI, the shorter the minimum creepage distance. For example, another important property of the material used for the top of the housing 7 is the relative temperature index RTI. The RTI of a material generally defines the maximum temperature at which the key properties of the material remain within acceptable limits for a long time.

[0029] Materials with a high CTI are usually more expensive than materials with a lower CTI. Furthermore, materials with both a high CTI and a high RTI are rare and even more expensive, or are unstable in terms of the mechanical requirements for the housing of the power semiconductor module device (as in the case of silicone materials, which are usually not hard enough to be used for the power semiconductor module housing). Therefore, in order to keep the overall cost of the power semiconductor module device at a minimum level, materials with a high CTI or a high RTI are often used instead of using materials with both a high CTI and a high RTI. If a material with a low CTI is used to form the housing 7, the minimum distance d between different terminal elements 4 connected to different potentials is min is quite large (d4 ≥ d min ), or a very complex top with many grooves 732 and / or protrusions 734 is required, which is usually difficult to produce and can only be produced at high production costs. In some cases, it is possible that it is even impossible to produce a geometry of the housing that meets the requirements regarding the minimum creepage distance.

[0030] Reference now FIG. 5A to FIG. 5D , schematically showing a section of a housing according to an embodiment of the present disclosure. The housing combines the properties of different materials while still being able to be produced at a relatively low cost. The housing 7 according to an embodiment of the present disclosure comprises a first layer 72 and a second layer 74. The first layer 72 forms at least the top of the housing 7 and optionally the side walls. Thus, the first layer 72 comprises a plurality of openings 722 (in FIG. 5A to FIG. 5D The first layer 72 is formed of a first material including certain material properties. The housing 7 further includes a second layer 74, which is formed of a second material including certain material properties. At least one of the material properties of the second material is different from the corresponding material property of the first material. Specifically, the second material has a higher relative tracking index CTI than the relative tracking index CTI of the first material.

[0031] According to one example, the first material comprises a sufficiently high RTI and sufficient mechanical properties. Thus, the housing 7 generally meets thermal and mechanical requirements. As already discussed above, in order to reduce the overall cost of the housing, the first material may comprise a relatively low CTI. This will generally require a considerable distance d4 between the terminal elements 4 (or any other element) coupled to different potentials P1, P2. In order to reduce the minimum distance d4 required between the terminal elements 4 (or any other element) coupled to different potentials P1, P2 min , while still keeping the overall cost of the housing 7 fairly low, the second layer 42 is arranged only on some sections of the first layer 72. For example, the second layer 74 can be arranged in such sections of the housing 7 where a higher CTI is required, so that elements coupled to different potentials P1, P2 (e.g., terminal elements 4) can be arranged closer to each other.

[0032] In order to keep the cost of the housing 7 low, the second layer 74 does not have to be arranged on the entire surface of the first layer 72. That is, the second layer 74 may only partially cover the first layer 72. The second layer 74 partially or at least partially covers the bottom surface of the first layer 72 and / or partially or at least partially covers the top surface of the first layer 72. The bottom surface is the surface of the first layer 72 that faces the substrate 10 (the inside of the housing) when the housing 7 is arranged around the substrate 10, and the top surface is the surface of the first layer 72 that faces the outside of the housing 7 when the housing 7 is arranged around the substrate 10. Figure 5A , Figure 5B and Figure 5C In the example shown, the second layer 74 only partially covers the top surface of the first layer 72. Figure 6 In the example shown, the second layer 74 partially covers the top surface and partially covers the bottom surface of the first layer 72 .

[0033] like Figure 5A As schematically shown in FIG. 1 , the second layer 74 may be a flat layer. However, it is also possible that, similar to what has been discussed above, Figure 4 As described, the second layer 74 is formed into grooves and / or protrusions (see Figure 5B ) of the uneven layer 74. Figure 5C It is also possible that the first layer 72 is an uneven layer 72 forming grooves and / or protrusions, wherein the uneven first layer 72 is covered by a section of the (thin) second layer 74 at least in a section between two elements coupled to different potentials P1, P2. Figure 5DAccording to further alternative embodiments, it is even possible that the first layer 72 is omitted in those parts of the housing 7 where a higher CTI is required. That is, the first layer 72 may include at least one gap (or additional opening), each of the at least one gap being sealed by a section of the second layer 74, so that the second layer 74 forms at least one section of the housing 7. In this example, it is also possible that the second layer 74 is a flat layer (such as Figure 5D ) or an uneven layer (not specifically shown). In all the different examples, the distance d4 between the two elements coupled to the different potentials P1, P2 can be reduced even further. However, since the CTI of the second material is higher relative to the CTI of the first material, generally no grooves or protrusions or only very few grooves or protrusions may be required. By arranging the second layer 74 only in some sections of the housing 7, the advantages of the first material and the second material can be combined for the sections concerned, while keeping the overall cost of the housing 7 relatively low. FIG. 5A to FIG. 5D In the example shown, the second layer 74 is arranged only in a section of the housing 7 that is arranged between the first potential P1 and the second potential P2 , which is different from the first potential P1 .

[0034] Reference now Figure 6 , schematically shows a cross-sectional view of a power semiconductor module device 100 including a housing 7 according to an embodiment of the present disclosure. The power semiconductor module device 100 substantially corresponds to the power semiconductor module device described above. Figure 1 However, the housing 7 comprises a first layer 72 consisting of a first material having a first (relatively low) CTI and a second layer 74 partially covering the first layer 72, wherein the second layer 74 consists of a second material having a second CTI which is greater than the first CTI of the first material. Figure 6 The second layer 74 in the example of FIG. 4 covers the first layer 72 in the section arranged between two adjacent terminal elements 4. Figure 1 Compared to the arrangement in which the housing 7 comprises only a single layer of material, the distance d4 between the two terminal elements 4 can be smaller. Figure 6 The protrusions and grooves shown in the second layer 74 are optional.

[0035] Reference now Figure 7, schematically shows a further example of a power semiconductor module device 100. In this example, the second layer 74 covers a larger portion of the first layer 72 on both the top side and the bottom side of the first layer 72. That is, some sections of the first layer 72 are sandwiched between parts of the second layer 74. However, the second layer 74 does not cover the entire first layer 72. That is, at least some parts of the first layer 72 are not covered by the second layer 74. Optionally, the second layer 74 can also be arranged in one or more openings in the opening 722. That is, a portion of the second layer 74 can extend into the opening 722 and can be arranged between the terminal element 4 and the corresponding opening 722 through which the terminal element 4 extends. In this way, when the terminal element 4 extends through the opening 722, any gap or interval between the first layer 72 and the terminal element 4 can be sealed by the second layer 74. This can further increase electrical isolation. At the same time, the opening 722 is sealed by the second layer 74. In this way, for example, any contaminants, water vapor or corrosive gases can be prevented from entering the housing 7.

[0036] It should be noted that in many power semiconductor modules, the bottom surface of the substrate 10 (the surface facing away from the semiconductor body 20) is connected to ground potential. Therefore, the creepage distance between the terminal element 4 and the ground potential is usually of greatest concern. This is especially true for high power semiconductor modules with an isolation voltage of, for example, 12 kV or more. The same applies to the spring contacts, which are often used to press the power semiconductor module onto a cooling unit (usually done at the customer site) and are usually connected to ground potential.

[0037] When the housing 7 is mounted on the power semiconductor module device and at least one terminal element 4 extends through at least one of the openings 722, the first layer 72 may not be in direct contact with the at least one terminal element 4. For example, each of the openings 722 may have a circular, square, or any other suitable cross-section, and the terminal element 4 may extend centrally through the opening 722. On the other hand, the second layer 74 may be adjacent to and directly contact one or more of the terminal elements 4. In this way, each of the plurality of openings 4 may be sealed to prevent air, contaminants, water vapor, and corrosive gases from entering the interior of the housing 7. The second layer 74 may be a continuous layer or a structured layer.

[0038] For example, in order to even better protect the power semiconductor module device 100 from the influence of corrosive gases, the second layer 74 may also include a reactant or an additive. The reactant may be configured to react chemically with the corrosive gas or specifically with sulfur or sulfur-containing compounds in the corrosive gas. The corrosive gas may also be captured, adsorbed or absorbed by the reactant. By reacting chemically with the corrosive gas, the reactant further prevents harmful substances from reaching the (metal) parts inside the housing 7, and thereby protects the parts from corrosion. The reactant may be, for example, a powder of a third material distributed in the second material of the entire second layer 74. The third material may include any material (e.g., a metallic material) that reacts with the corrosive gas and, when exposed to the corrosive gas, may, for example, form a metal sulfide. The reactant may be substantially uniformly distributed in the second material of the entire second layer 74. It is also possible, for example, to add copper particles to the second material. The copper particles may be used as a sacrificial material, and, for example, will react with hydrogen sulfide before it can reach the interior of the housing 7.

[0039] As described above, the first layer 72 includes a first material, and the second layer 74 includes a second material different from the first material. According to an embodiment of the present disclosure, the first material can be a relatively rigid material. In this way, the housing 7 can provide sufficient protection to prevent mechanical damage. For example, when a semiconductor module including a housing is mounted to a cooling unit, the mechanical stability of the housing is also required. The housing is generally used to press the substrate and / or the base plate against the cooling unit. The housing providing sufficient mechanical stability allows the substrate to be in full contact with the cooling unit over the entire surface of the substrate to provide sufficient heat transfer between the substrate and the cooling unit. On the other hand, the second material can be a material that is softer than the first material. The second material can also include certain elastic properties. For example, this allows the terminal element 4 to pass through the second layer 74 and tightly close any gap between the first layer 72 and the terminal element 4. For example, the first layer 72 can include a thermoplastic material or any kind of hard plastic material or epoxy resin. For example, the second layer 74 can include at least one of a soft polymer, silicone, (thermoplastic) elastomer, polyurethane, acrylate or rubber. According to one example, the second layer 74 consists of or includes liquid silicone rubber (LSR). For example, different material hardnesses of the first material and the second material can also improve the vibration robustness of the power semiconductor module device 100. In addition, many rigid materials that can be used for the first layer 72 are very smooth and therefore may be difficult to handle manually. Since relatively soft materials have certain soft touch characteristics (especially when handled manually), they are generally easier to handle.

[0040] For example, the housing 7 can be produced using (2K) injection molding or manual assembly of separately produced injection molded or cast parts. According to one example, a method for producing the housing 7 includes: in a first step, forming a first layer 72 of a first material. The first layer 72 can, for example, have a rectangular or square cross-section and include a plurality of openings 722. According to one example, the plurality of openings 722 are distributed in a regular pattern over the plane of the first layer 72. However, this is only an example. The plurality of openings 722 can be distributed over the plane of the first layer 72 in any appropriate manner. For example, the first layer 72 can be formed by an injection molding process.

[0041] According to one example, the first layer 72 can remain in the molded object, and the second layer 74 is directly formed on the first layer 72 in the same molded object. The second layer 74 is formed to partially cover the first layer 72. For example, the second layer 74 can be arranged adjacent to the first layer, and can directly abut the first layer 72. When the first layer 72 and the second layer 74 are formed by a 2K injection molding process, the second layer 74 is generally bonded to the first layer 72 and may not be easily removed from the first layer 72. The second layer 74 can generally be bonded to the first layer, for example, by chemical bonding, mechanical interlocking and / or any other appropriate connection method. For example, depending on the materials used for the first layer 72 and the second layer 74, a chemical bond can be formed between the layers 72 and 74. According to one example, the second layer 74 has a certain adhesiveness so that it is bonded to the first layer 72 to a certain extent without any mechanical interlocking.

[0042] To form a power semiconductor module device, the top formed by the method according to an embodiment of the present disclosure may be connected to the sidewalls to form a housing 7, which is then arranged to surround at least one substrate 10. However, the sidewalls may also be formed during the same injection molding process as the top of the housing 7.

[0043] Before the terminal element 4 is inserted into the opening 722, the second layer 74 can completely cover the opening 722. According to one example, the thickness of the second layer 74 in the vertical direction y can be smaller within the range of the opening 722 than the thickness in the vertical direction y in those sections of the second layer 74 that cover the bottom surface of the first layer 72. In this way, a film covering the corresponding opening 722 can be formed. When the terminal element 4 is inserted through the opening 722, the terminal element 4 can easily penetrate this film. However, after the terminal element 4 is inserted, the opening 722 is still fully sealed. That is, the sealing between the terminal element 4 and the second layer 74 can be achieved by passing the terminal element 4 through the second layer 74 and the elastic behavior of the material of the second layer 74. When penetrating the second layer 74, the second end 42 of the terminal element 4 opens a small hole in the second layer 74. After this initial hole has been formed, the material of the second layer 74 moves elastically to allow the terminal element 4 to further advance through the hole. When the terminal element 4 is in its final position, the material of the second layer 74 forms a tight collar around the terminal element 4 due to its elastic properties. Optionally, the second layer 74 may have a specific structure (e.g., a predetermined breaking point) to achieve a fracture controlled by the terminal element 4. According to other examples, the terminal element 4 may also be molded into the housing 7 when the housing 7 is formed by an injection molding process.

Claims

1. A housing (7) for a power semiconductor module device (100), comprising side walls and a top, wherein: The top portion includes: a first layer (72) of a first material, the first layer (72) comprising a plurality of openings (722); and a second layer (74) of a second material different from the first material, wherein The second material has a higher comparative tracking index CTI than the comparative tracking index CTI of the first material, and at least one of the following: The second layer (74) partially covers at least one of a bottom surface of the first layer (72) and a top surface of the first layer (72), and The first layer (72) comprises at least one gap, each of the at least one gap being sealed by a section of the second layer (74), such that the second layer (74) forms at least one section of the housing (7).

2. The housing (7) according to claim 1, wherein: The second material is softer than the first material.

3. The housing (7) according to claim 1 or 2, wherein: The first material comprises at least one of a thermoplastic material, a plastic material and an epoxy resin, and The second material includes at least one of liquid silicone rubber, soft polymer, silicone, elastomer, thermoplastic elastomer, polyurethane, acrylate and rubber.

4. The housing (7) according to any one of the preceding claims, wherein Portions of the second layer (74) extend into at least some of the openings (722) to seal the respective openings (722).

5. The housing (7) according to any one of the preceding claims, wherein At least one of the following: The second layer (74) includes one or more protrusions and / or grooves extending in a vertical direction (y) perpendicular to the top surface and the bottom surface of the first layer (72), and The first layer (72) comprises one or more protrusions and / or grooves extending in the vertical direction (y), and wherein the one or more protrusions and / or grooves are covered by a section of the second layer (74).

6. The housing (7) according to any one of the preceding claims, wherein The second layer (74) is a structured layer comprising recesses between different sections of the layer.

7. The housing (7) according to any one of the preceding claims, wherein The second layer (74) is bonded to the first layer (72).

8. A power semiconductor module device (100), comprising: Semiconductor substrate (10); at least one semiconductor body (20), the at least one semiconductor body (20) being arranged on a top surface of the semiconductor substrate (10); as well as The housing (7) according to any one of claims 1 to 8, wherein the semiconductor substrate (10) on which the at least one semiconductor body (20) is arranged is arranged within the housing (7) or forms a bottom of the housing (7).

9. The power semiconductor module arrangement (100) according to claim 8, wherein: The second layer (74) covers a section of the housing (7) or forms a section of the housing (7), the section being arranged between a first potential (P1) and a second potential (P2), the second potential (P2) being different from the first potential (P1).

10. The power semiconductor module device (100) according to claim 9, further comprising a plurality of terminal elements (4), wherein: A first end (41) of each of the plurality of terminal elements (4) is mechanically and electrically coupled to the semiconductor substrate (10); The second end (42) of each of the plurality of terminal elements (4) protrudes through one of the openings (722) in the first layer (72) to the exterior of the housing (7); At least one terminal element of the plurality of terminal elements (4) is electrically coupled to the first potential (P1); At least one terminal element of the plurality of terminal elements (4) is electrically coupled to the second potential (P2); and The second layer (74) covers at least a section of the first layer (72) or forms a section of the housing (7), the section being arranged between the at least one terminal element (4) electrically coupled to the first potential (P1) and the at least one terminal element (4) electrically coupled to the second potential (P2).

11. A method for forming a top portion of a housing (7), the method comprising: forming a first layer (72) of a first material, the first layer (72) comprising a plurality of openings (722); as well as forming a second layer (74) of a second material different from the first material, wherein The second material has a higher comparative tracking index CTI than the comparative tracking index CTI of the first material, and at least one of the following: The second layer (74) partially covers at least one of a bottom surface of the first layer (72) and a top surface of the first layer (72), and The first layer (72) comprises at least one gap, each of the at least one gap being sealed by a section of the second layer (74), such that the second layer (74) forms at least one section of the housing (7).

12. The method according to claim 11, wherein: Forming the first layer (72) includes: forming the first layer (72) in a molded object; and Forming the second layer (74) includes forming the second layer (74) in the same molded article after forming the first layer (72).

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