Pre-forming unit of fan-out chip embedded packaging process and preparation method of pre-forming unit

Abstract

The invention relates to a preforming unit for a fan-out chip embedded packaging process and a preparation method thereof, comprising the following steps: a) preforming an integrated circuit crystal grain into a plurality of implementation units, each implementation unit comprising a chip with a different thickness, and each chip being respectively matched with a conductive column with a different height, and coating and covering the respective chips and the conductive columns by using an insulating colloid, and cutting the chips and the conductive columns into single bodies, namely performing units. Therefore, the surface-upward or surface-downward packaging process of the chip can be carried out according to actual requirements, and the complexity of subsequent chip packaging is simplified.

Description

Technical Field

[0001] The present invention relates to a chip packaging method, and in particular to a preformed unit and a preparation method thereof for a fan-out chip embedded packaging process that can simplify the process and improve transmission efficiency. Background Art

[0002] As semiconductor processes become more and more advanced, applications such as high-performance computing, 5G communications, the Internet of Things, AR / VR, etc. are growing rapidly. The demands for thin and light appearance, high data transmission rate, low power loss, and low cost have led to a significant increase in the application of advanced packaging processes.

[0003] As for the advanced packaging process of fan-out chips, it is different from the packaging of traditional chips. For example, when it needs to integrate heterogeneous chips of different thicknesses and materials, the face-up process cannot be implemented due to the different chip thicknesses, and only the face-down process can be implemented. Therefore, its application and implementation are quite limited. Summary of the invention

[0004] The main purpose of the present invention is to provide a preformed unit for a fan-out chip embedded packaging process and a preparation method thereof, which can simplify the complexity of packaging multiple chips, simplify the packaging process, and reduce the packaging cost.

[0005] In order to achieve the above-mentioned main purpose, firstly, the present invention provides a preforming unit for a fan-out chip embedded packaging process, comprising: preforming the integrated circuit grain into a plurality of implementation units, each implementation unit comprising a chip of different thicknesses, and each chip is respectively equipped with a conductive column of different heights, and an insulating colloid is used to wrap and cover each chip and conductive column, and then cut into a single body, namely a preforming unit.

[0006] Secondly, the present invention provides a preparation method for a fan-out chip embedded packaging process, comprising: a) preforming an integrated circuit die into a plurality of implementation units, each implementation unit comprising a plurality of chips of different thicknesses, and each chip is respectively equipped with a conductive column of different heights, using an insulating colloid to cover each chip and the conductive column, and cutting them into a single body, namely a preformed unit; then, b) a carrier is used to form a plurality of bearing areas for the above-mentioned preformed units to be pasted, and the plurality of preformed units contain the same or different chips and different conductive column heights; c) molded glue injection insulating layer to completely seal the preformed unit; d) performing grinding The process of manufacturing the conductive pillars of the preformed unit is as follows: (a) wiring the conductive pillars of each chip and connecting them to adjacent chips to form a complete wiring; (b) molding the insulating layer with glue again to cover each wiring and make exposed guide holes to complete the forward packaging process; (c) removing the carrier to complete the singulation operation; or (d) forming a plurality of carrying chambers with high conductive pillars on the carrier of (b) for pasting the preformed unit of (a), and continuing the processes of (c), (d) and (e) to complete the wiring of the conductive lines to the bottom, and adding another reverse packaging process; thereby, the present invention can meet actual needs for face-up or face-down packaging processes, thereby simplifying the complexity of subsequent chip packaging.

[0007] Furthermore, the present invention provides a method for preparing a fan-out chip embedded packaging process, comprising at least the following steps: a) preforming an integrated circuit die into an implementation unit, wherein the implementation unit comprises a plurality of chips of different thicknesses, and the aforementioned chips are respectively equipped with conductive pillars of different heights; b) a carrier, wherein a plurality of high conductive pillars are erected to form a plurality of supporting areas, and each high conductive pillar has a conductive pillar height higher than the aforementioned chip; c) coating the chips with a packaging colloid, so that the chips are respectively pasted and formed in the supporting areas; d) molding an insulating layer to make it complete Seal the high conductive pillars and the surrounding space of each chip filled with insulating glue so that the high conductive pillars and each chip are completely covered by the insulating layer; e) Perform grinding operation; f) Connect the conductive pillars of each chip with adjacent high conductive pillars to form a complete wiring; g) Molding glue and injecting insulating layer on it again to cover each wiring and make exposed guide holes; h) Remove the carrier and further grind the back of the chip until the back of the chip that is exposed first is exposed to the outside; i) Perform the above f) and g) processes to complete the subsequent chip packaging operations for the front and back sides.

[0008] Furthermore, the preparation method of the fan-out chip embedded packaging process of the present invention further includes a step j) of continuously manufacturing a heat dissipation layer on the exposed portion of the back side of the chip.

[0009] The detailed structure, characteristics, assembly or use of the preformed unit of the fan-out chip embedded packaging process and the preparation method thereof provided by the present invention will be described in the detailed description of the implementation method later. However, those skilled in the art should understand that the detailed description and the specific embodiments listed for implementing the present invention are only used to illustrate the present invention and are not used to limit the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 8 It is a schematic flow chart of a first embodiment of a preforming unit and a preparation method thereof for a fan-out chip embedded packaging process of the present invention.

[0011] Figures 9 to 20 It is a flow chart of a second embodiment of a preforming unit and a preparation method thereof for a fan-out chip embedded packaging process of the present invention.

[0012] Description of reference numerals:

[0013] [First embodiment]

[0014] A, B, C: Implementation units

[0015] A1, B1, C1: Chip

[0016] A2, B2, C2: Conductive columns

[0017] P: Insulating colloid

[0018] S: carrier

[0019] R: Insulating colloid

[0020] W: Metal wire

[0021] X: Insulation colloid

[0022] Y: Opening

[0023] [Second embodiment]

[0024] IC1, IC2, IC3: Chips

[0025] 10, 20, 30: Conductive columns

[0026] W1, W2, W3: load-bearing area

[0027] 80: Carrier

[0028] 70: High conductivity column

[0029] L: Insulation layer

[0030] R: Metal wire

[0031] S: Insulation layer

[0032] O: Exposed guide hole

[0033] R1: Metal wire

[0034] Z: Protective layer

[0035] O2: Guide hole

[0036] Q: Heat dissipation layer DETAILED DESCRIPTION

[0037] The applicant first explains that throughout the entire specification, including the embodiments described below and the claims of the patent application, the terms related to directions are based on the directions in the drawings. Secondly, in the embodiments and drawings to be described below, the same component numbers represent the same or similar components or their structural features.

[0038] First, please refer to FIGS. 1 to 8 of the first preferred embodiment. The preformed unit and the preparation method of the fan-out chip embedded packaging method of the first preferred embodiment of the present invention include the following preformed unit, production process or steps:

[0039] 1) The integrated circuit die is preformed into a plurality of implementation units A, B, and C. Each implementation unit includes a plurality of chips A1, B1, and C1 of different thicknesses, and each chip is respectively equipped with a conductive column A2, B2, and C2 of different heights. An insulating colloid P is used to cover each chip A1, B1, and C1 and the conductive column A2, B2, and C2 to form a preformed unit.

[0040] 2) A carrier S is provided to glue the preformed units in step 1) into a unit module.

[0041] 3) Molding an insulating colloid R onto the unit module of step 2) to form a package molding unit.

[0042] 4) Next, the package molding unit of step 3) is ground until the conductive pillars A2, B2, and C2 of each chip are exposed to the outside at the same time.

[0043] 5) Following step 4), connecting metal wires W are routed to connect adjacent preformed units.

[0044] 6) The connecting wire W in step 5) is molded again with an insulating colloid X and an opening Y is formed at an appropriate position.

[0045] 7) Removing the carrier S in step 6).

[0046] 8) Singulate the fan-out chips to complete the unit process for subsequent packaging.

[0047] Continuing to refer to FIGS. 9 to 20 of the second preferred embodiment, the fan-out chip packaging process of the second preferred embodiment of the present invention includes the following multiple processes:

[0048] 9) Preforming the integrated circuit die. An implementation unit is shown, which includes three chips IC1, IC2, and IC3 with different thicknesses, and the aforementioned chips are respectively equipped with conductive pillars 10, 20, and 30 with different heights.

[0049] 10) A carrier 80 is used to support a plurality of high conductive pillars 70 to form a plurality of supporting areas W1, W2, and W3. Each high conductive pillar 70 has a height higher than the conductive pillars of the front-end chips IC1, IC2, and IC3 of different heights.

[0050] 11) Paste the chips IC1, IC2, IC3 of different thicknesses in 9) in the pre-formed carrier areas W1, W2, W3 of 10) respectively. Please refer to the flow charts 12, 13, and 14 of the second embodiment, which include the following 3 steps:

[0051] 12) Molding glue to inject the insulating layer L, so that it is completely sealed and filled with insulating glue to fill the high conductive columns 10), 11) and the surrounding spaces of each chip IC1, IC2, IC3, so that the high conductive columns 11) and each chip IC1, IC2, IC3 are completely covered by the insulating layer.

[0052] 13) Perform a grinding operation, that is, grind downward toward the outside of the chip conductive pillars 10, 20, 30 and the high conductive pillars 70 of 12) until the high conductive pillars 70 and the conductive pillars 10, 20, 30 of each chip IC1, IC2, IC3 are exposed to the outside.

[0053] 14) Arrange metal wires R to connect the conductive pillars of each chip IC1, IC2, and IC3 with adjacent high-conductive pillars to form a complete circuit layout.

[0054] 15) The insulating layer S is molded again on 14) to first cover each metal wire R, and then an etching operation is performed at a specific position to produce an exposed guide hole O.

[0055] 16) The carrier 80 is removed, and the chip backside is further ground until the backside of the chip IC3 that is exposed first is exposed to the outside.

[0056] 17) Arrange the metal wire R1 again on the back side of each chip IC1, IC2, IC3 to form a predetermined interconnected metal wire.

[0057] 18) Perform a back insulating layer molding operation again to form a protection layer Z; then perform an etching operation to further form an exposed guide hole O2.

[0058] 19) Continue to make a heat dissipation layer Q on the exposed portion of the back side of the chip IC3.

[0059] 20) Cutting the chip modules completed from 9) to 19) from the wafer to form a predetermined number of fan-out embedded package preformed units J.

[0060] As described above, the two embodiments provided by the preformed unit and its preparation method of the fan-out chip embedded packaging process of the present invention are mainly to preform and package two or more chip units (thicknesses may be different), each with a conductive column (copper column) of different heights, into unit individuals of the same thickness. Next, a single-sided conductive design can be produced according to demand, or a conductive material pillar with controllable height can be further formed on the front of the chip to be packaged, and covered with an insulating layer exceeding the height of the conductive column, and then etched to form an exposed guide hole; similarly, after the back carrier is removed and the above process is repeated, another exposed guide hole that can be packaged can be formed on the back, and then cut to form a chip preformed unit for subsequent fan-out chips to select front or back packaging.

[0061] As described above, the preformed unit of the fan-out chip embedded packaging process of the present invention and its preparation method are often used in heterogeneous chip integration packaging. Through the application of the above process, the complexity of chip packaging will be effectively simplified and the packaging cost will be effectively reduced.

Claims

1. A preformed unit for a fan-out chip embedded packaging process, characterized in that: The method comprises: preforming integrated circuit crystal grains into a plurality of implementation units, each implementation unit comprises a plurality of chips with different thicknesses, and each chip is respectively matched with a conductive column with a different height, and using an insulating colloid to cover each chip and the conductive column to form a preformed unit.

2. A method for preparing a fan-out chip embedded packaging process, characterized in that: The method comprises: a) preforming an integrated circuit crystal into a plurality of implementation units, each implementation unit comprises a plurality of chips of different thicknesses, and each chip is respectively equipped with a conductive column of different heights, and using an insulating colloid to cover each chip and the conductive column to form a preformed unit; then, b) a carrier is used to form a plurality of bearing areas for the above-mentioned preformed units to be pasted; c) mold-pressing an insulating layer to completely seal the preformed unit; d) performing a grinding operation; e) wiring the conductive columns of each chip to connect with the adjacent chip to form a complete wiring; f) mold-pressing an insulating layer again to cover each wiring, and making an exposed guide hole to complete the forward packaging process; g) removing the carrier to complete the singulation operation.

3. The method for preparing the fan-out chip embedded packaging process according to claim 2, characterized in that: A plurality of carrying chambers are formed on the carrier b) with high conductive pillars for pasting the preformed units of a) and the processes c), d) and e) are continued to complete the wiring of the conductive lines to the bottom and add another reverse packaging process.

4. A method for preparing a fan-out chip embedded packaging process, characterized in that: It includes the following steps: a) preforming the integrated circuit die into a plurality of implementation units, each implementation unit comprising a plurality of chips of different thicknesses, and each chip is respectively equipped with a conductive column of different heights, and using an insulating colloid to cover each chip and the conductive column to form a preformed unit; b) pasting the preformed units in step a) on a carrier to form a unit module; c) molding the unit module of step b) with an insulating colloid to form a package molding unit; d) Next, the encapsulated molding units of step c) are further arranged with connecting wires as required to connect adjacent pre-molded units; e) using an insulating colloid to mold the connecting wires in step d) again and forming openings at appropriate locations for subsequent crystal growth; f) Remove the carrier in step b) and cut into pieces to complete the unit fan-out chip packaging.

5. The method for preparing the fan-out chip embedded packaging process according to claim 4, characterized in that: Further comprising the following steps: a) preforming the integrated circuit die into an implementation unit, wherein the implementation unit includes a plurality of chips of different thicknesses, and the aforementioned chips are respectively equipped with conductive pillars of different heights; b) using a carrier to vertically support a plurality of high conductive pillars to form a plurality of supporting areas, wherein each high conductive pillar has a height higher than that of the conductive pillar of the chip; c) wrapping the chip with a packaging colloid; pasting and preforming the plurality of chips of different thicknesses in a) in the carrying area of ​​b); d) Molding the insulating layer with glue to completely seal the insulating glue and fill the high conductive pillars in b) and c) and the surrounding space of each chip, so that the high conductive pillars in c) and each chip are completely covered by the insulating layer; e) performing a grinding operation, that is, grinding downward toward the outer edges of the chip conductive pillars and high conductive pillars in d) until the high conductive pillars and the conductive pillars of each chip are ground out; f) wiring the conductive pillars of each chip to connect with adjacent high conductive pillars to form a complete wiring; g) Molding the insulating layer again, first covering the wiring, and then etching at specific locations to make exposed guide holes; h) removing the carrier and further grinding the back of the chip until the back of the chip that was exposed first is exposed to the outside; i) wiring is performed again on the back side of each chip to form predetermined interconnected wiring; j) performing a back insulating layer molding operation again to form a protective layer; and then performing an etching operation to further form an exposed guide hole; k) Cutting the chip modules completed in steps a) to j) from the wafer to form a predetermined number of fan-out package preformed units.

6. The method for preparing the fan-out chip embedded packaging process according to claim 5, characterized in that: The method further comprises a step of continuously making a heat dissipation layer on the exposed portion of the back side of the chip between j) and k).

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