Battery management system

Abstract

The present invention describes a battery management system comprising: a sequence of four or more battery connections for connection to a series of batteries; a resistor associated with each of the battery connection terminals; and a sequence of three or more ADCs. Each ADC is associated with a pair of the battery connections and converts a difference between analog voltages at a first ADC input and a second ADC input of the ADC into a digital signal and provides the digital signal at an ADC output of the ADC. The battery management system further includes a digital processor that, for each ADC in the sequence: calculates an error voltage of the ADC based on: i) a digital signal of a previous ADC in the presence of the previous ADC in the sequence; and ii) a digital signal of the next ADC in the presence of the next ADC in the sequence; and providing a measured voltage output signal by subtracting the error voltage from the digital signal of the ADC.

Description

Technical Field

[0001] The present disclosure relates to a battery management system. Background Art

[0002] While battery chemistry is getting better, the voltage drop between a fully charged cell and an empty cell is getting smaller. In addition, for longevity and safety reasons, cells need to be protected from undercharging and overcharging. Therefore, great pressure falls on the accuracy of the battery management system (BMS) so that system autonomy can be maximized while keeping the application safe. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided a battery management system, comprising:

[0004] A sequence of four or more battery connection terminals for connecting to a series of batteries such that each battery is connected between a pair of the battery connection terminals, wherein:

[0005] a first battery connection terminal for connecting to a terminal of a battery at one end of the series of batteries;

[0006] The last battery connection terminal is for connecting to a terminal of a battery at the other end of the series of batteries; and

[0007] each other battery connection terminal is for connection to a node between two of the batteries in the series;

[0008] a resistor associated with each battery connection terminal;

[0009] A sequence of three or more ADCs, each ADC being associated with a pair of the battery connection terminals, each ADC having:

[0010] a first ADC input connected to one of the pair of battery connections via a resistor associated with the one battery connection;

[0011] a second ADC input connected to the other of the pair of battery connections via its associated resistor; and

[0012] ADC output terminal;

[0013] in:

[0014] each ADC configured to convert a difference between analog voltages at a first ADC input and a second ADC input of the ADC into a digital signal and to provide the digital signal at an ADC output of the ADC; and

[0015] A digital processor configured to, for each ADC in the sequence:

[0016] calculating an error voltage of the ADC based on: i) the digital signal of the previous ADC if there is one in the sequence; and ii) the digital signal of the next ADC if there is one in the sequence; and

[0017] A measured voltage output signal is provided by subtracting the error voltage from the digital signal of the ADC.

[0018] Advantageously, performing the compensation in the digital domain using a digital processor results in lower current consumption, smaller die size, and easy scalability from one technology to another.

[0019] In one or more embodiments, the digital processor is further configured to calculate the error voltage for each ADC in the sequence based on: iii) the digital signal of the ADC. In one or more embodiments, the digital processor is configured to calculate the error voltage for each intermediate ADC in the sequence by applying the following formula:

[0020] Error voltage = K x (V n+1 +V n-1 -2.V n )

[0021] in:

[0022] K is the timing value;

[0023] V n+1 is the value of the digital signal of the next ADC if the next ADC exists in the sequence;

[0024] V n-1 is the value of the digital signal of the previous ADC if the previous ADC exists in the sequence; and

[0025] V n is the value of the digital signal of the ADC.

[0026] In one or more embodiments, the digital processor is configured to calculate the error voltage by applying the following formula for the first ADC in the sequence:

[0027] Error voltage = K x (V n+1 -V n )

[0028] in:

[0029] K is the timing value;

[0030] V n+1 is the value of the digital signal of the next ADC in the sequence; and

[0031] V n is the value of the digital signal of the first ADC.

[0032] In one or more embodiments, the digital processor is configured to calculate the error voltage by applying the following formula for the last ADC in the sequence:

[0033] Error voltage = K x (V n-1 -V n )

[0034] in:

[0035] K is the timing value;

[0036] V n-1 is the value of the digital signal of the previous ADC in the sequence; and

[0037] V n is the value of the digital signal of the last ADC.

[0038] In one or more embodiments:

[0039] K=2.Rf clk .C in ;

[0040] R is the resistance value of the resistor associated with each battery connection terminal;

[0041] C in is the capacitance of the capacitor at each input terminal of each of the ADCs; and

[0042] f clk is the frequency of the clock associated with each ADC.

[0043] In one or more embodiments, the digital processor is configured to calculate the error voltage of the ADC for each ADC in the sequence by:

[0044] In case that the previous ADC exists in the sequence, comparing the digital signal of the previous ADC with a threshold value to generate a previous ADC in-use signal;

[0045] If the next ADC exists in the sequence, comparing the digital signal of the next ADC with a threshold value to generate a next ADC in-use signal;

[0046] combining the previous ADC in-use signal and the next ADC in-use signal to determine an error multiplier; and

[0047] The error multiplier is multiplied by a predetermined voltage value.

[0048] In one or more embodiments, the predetermined voltage value is an expected voltage value of one of the batteries.

[0049] In one or more embodiments, the digital processor is further configured to calculate the error voltage of the ADC for each ADC in the sequence by:

[0050] comparing the digital signal of the ADC with a threshold value to generate an ADC in-use signal; and

[0051] The previous ADC in-use signal, the next ADC in-use error signal, and the ADC in-use signal are combined to determine the error multiplier.

[0052] In one or more embodiments, the digital processor is further configured to, for each intermediate ADC:

[0053] The previous ADC in-use signal, the next ADC in-use error signal, and the ADC in-use signal are combined to determine the error multiplier according to the following equation:

[0054] Error multiplier=previous ADC in-use signal+next ADC in-use error signal−2×ADC in-use signal.

[0055] In one or more embodiments, the digital processor is further configured to, for the first and last ADCs in the sequence:

[0056] The previous ADC in-use signal, the next ADC in-use error signal, and the ADC in-use signal are combined to determine the error multiplier according to the following equation:

[0057] Error multiplier=previous ADC in-use signal+next ADC in-use error signal−ADC in-use signal.

[0058] In one or more embodiments, the digital processor is further configured to calculate, for each ADC in the sequence, the error voltage of the ADC by multiplying the error multiplier and the predetermined voltage value by a timing value K, wherein:

[0059] K=2.Rf clk .C in ;

[0060] R is the resistance value of the resistor associated with each battery connection terminal;

[0061] C in is the capacitance of the capacitor at each input of each of the ADCs; and

[0062] f clk is the frequency of the clock associated with each ADC.

[0063] In one or more embodiments, the digital processor is further configured to:

[0064] applying a gain correction voltage and / or an offset correction voltage to each digital signal of the sequence of ADCs to provide a corresponding plurality of corrected digital signals; and

[0065] All subsequent processing is performed on the corrected digital signal rather than the digital signal.

[0066] In one or more embodiments, the digital processor is configured to multiply each digital signal by the gain correction voltage.

[0067] In one or more embodiments, the digital processor is configured to subtract the offset correction voltage from each digital signal.

[0068] In one or more embodiments, the battery management system is configured to perform a calibration routine to determine values ​​of the gain correction voltage and / or the offset correction voltage.

[0069] In one or more embodiments, the battery management system is configured to perform the calibration routine by:

[0070] Setting the voltage difference between each pair of consecutive battery connection terminals in the sequence to a first calibration value, and recording the measured voltage output signal of each ADC as a first calibration output value;

[0071] setting the voltage difference between each pair of consecutive battery connection terminals in the sequence to a second calibration input value, and recording the measured voltage output signal of each ADC as a second calibration output value; and

[0072] The values ​​of the gain correction voltage and / or the offset correction voltage of each ADC are determined based on the first calibration value, the second calibration value, the first calibration output value associated with the ADC, and the second calibration output value associated with the ADC.

[0073] In one or more embodiments, determining the value of the gain correction voltage and / or the offset correction voltage includes solving the following simultaneous equations for each ADC:

[0074] V meas1 =γ channel .V X1 +o channel

[0075] V meas2 =γ channel .V X2 +o channel

[0076] in:

[0077] V X1 is the first calibration value;

[0078] V X2 is the second calibration value;

[0079] V meas1 is the first calibration output value;

[0080] V meas2 is the second calibration output value;

[0081] γ channel is the gain correction voltage; and

[0082] o channel is the offset correction voltage.

[0083] In one or more embodiments, the battery management system is configured to perform the calibration routine by determining the value of the timing value K by:

[0084] Setting the voltage difference between each pair of consecutive battery connection terminals in the sequence to a first calibration value, and recording the measured voltage output signal of each ADC as a first calibration output value;

[0085] setting the voltage difference between each pair of consecutive battery connection terminals in the sequence as a second calibration input value, and recording the measured voltage output signal of each ADC as a second calibration output value;

[0086] setting the voltage difference between a middle pair of battery terminals in the sequence to zero, while setting the voltage difference between adjacent pairs of battery terminals in the sequence to a first calibration value, and recording the measured voltage output signal of the ADC associated with the middle pair of battery terminals as a third calibration output value; and

[0087] The values ​​of the gain correction voltage and the offset correction voltage are determined using the following equations:

[0088]

[0089] in:

[0090] V X1 is the first calibration value;

[0091] V X2 is the second calibration value;

[0092] V meas1 is the first calibration output value;

[0093] V meas2 is the second calibration output value; and

[0094] V meas3 is the third calibration output value.

[0095] Although the present disclosure allows various modifications and alternative forms, the characteristics of the present disclosure have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments outside the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments within the spirit and scope of the appended claims are also covered.

[0096] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The following figures and detailed descriptions also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed descriptions in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0097] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0098] Figure 1 A battery management system (BMS) is shown that will be used to introduce the concept of measurement error;

[0099] Figure 2 An example embodiment of a BMS according to the present disclosure is shown;

[0100] Figure 3 Another example embodiment of a BMS according to the present disclosure is shown;

[0101] Figure 4 Another example embodiment of a BMS according to the present disclosure is shown;

[0102] Figure 5 will be used to describe the subsequent steps in the calibration routine of a BMS according to the present disclosure; and

[0103] Figure 6a and 6b Simulation results illustrating the advantages of the BMS of the present disclosure are shown. DETAILED DESCRIPTION

[0104] Figure 1 A BMS is shown that will be used to introduce the concept of measurement error, which can be obtained by Figures 2 to 5 The examples of the present disclosure shown in FIG.

[0105] Figure 1 The BMS has a sequence of four battery connection terminals: a first battery connection terminal C0 101; a second battery connection terminal C1 102; a third battery connection terminal C2 103; and a fourth battery connection terminal C3 104. The battery connection terminals 101-104 are used to connect to a series / string of batteries 105-107, such that each battery is connected between a different pair of battery connection terminals. Figure 1 103, and a third battery 107 is connected between the third battery connection terminal C2 103 and the fourth battery connection terminal C3 104. In this way, the first battery connection terminal C0 101 is used to connect to the end of the battery 105 at one end of the series of batteries. The last battery connection terminal C3 104 is used to connect to the end of the battery 107 at the other end of the series of batteries. Each other battery connection terminal C1 102, C2 103 is used to connect to a node between two batteries in the series / string of batteries 105-107.

[0106] It will be appreciated that in other examples, the BMS may have any number of battery connections for connecting to any suitable number of batteries.

[0107] Figure 1 Also shown in FIG. 1 are low pass filters 108-111 associated with each battery connection terminal 101-104. The low pass filters 108-111 each include a resistor 112-115 connected in series between a corresponding one of the battery connection terminals 101-104 and an ADC input terminal (as will be discussed below). Figure 1 In addition to or in place of the resistors 112-115 of the low-pass filters 108-111 shown in FIG, the BMS may include a battery cell balancing resistor (not shown) between each battery connection terminal 101-104 and the ADC input terminal. In addition, a low-pass filter with a different topology may be used instead of Figure 1For example, where the capacitor is connected to the IC terminal of the previous battery cell instead of to ground. Regardless of the circuit layout, as will be discussed below, it is the presence of resistors 112-115, battery connection terminals 101-104 and ADC input terminals that can cause the BMS to measure the voltage level of batteries 105-107 inaccurately.

[0108] Figure 1 Also shown is a sequence of three analog / digital converters (ADCs) 116-118, each associated with a pair of battery connection terminals. In this manner, each ADC 116-118 is used to measure the voltage level of a battery 105-107 connected between a pair of battery connection terminals. In this example: a first ADC 116 is used to measure the voltage level of a first battery 105; a second ADC 117 is used to measure the voltage level of a second battery 106; and a third ADC 118 is used to measure the voltage level of a third battery 107.

[0109] Each ADC 116-118 has a first ADC input, a second ADC input, and an ADC output. The first ADC input is connected to one of the pair of battery connections via an associated resistor of the battery connection terminal. The second ADC input is connected to the other of the pair of battery connections via an associated resistor of the other battery connection terminal. Each ADC 116-118 is configured to convert the difference between the analog voltages at the first and second ADC input terminals of the ADC (i.e., a differential voltage) into a digital signal 126-128 and provide the digital signal 126-128 at the ADC output terminal of the ADC.

[0110] Referring to the first ADC 116, its first ADC input terminal is connected to the first battery connection terminal C0 101 via a resistor 112 of a low pass filter 108 associated with the first battery connection terminal C0 101. A second ADC input terminal of the first ADC 116 is connected to the second battery connection terminal C1 102 via a resistor 113 of a low pass filter 109 associated with the second battery connection terminal C1 102. Therefore, the first battery connection terminal C0 101 and the second battery connection terminal C1 102 are a pair of battery connection terminals to which the first ADC 116 is connected. Each of the second ADC 117 and the third ADC 118 is similarly connected to a different pair of battery connection terminals, as shown in the figure.

[0111] Switched capacitor input circuits, such as sample-and-hold circuits or ADC input stages (such as Figure 1 ), which produces an average DC current when connected directly to the input. Figure 1 The average DC current is shown in FIG. 1 by dashed lines 119 , 120 and will be discussed in more detail below.

[0112] For example, for a switched capacitor ADC, this current sampling current is:

[0113] I p_n =2.f clk .C in .(V n+1 -V n )and

[0114] I m_n =2.f clk .C in .(V n -V n+1 ).

[0115] I p_n Current in Figure 1 It is shown as a dashed line 120. m_n Current in Figure 1 It is shown as a dotted line 119. n is the voltage at one of the battery connections to which the ADC is connected. V n+1 is the voltage at the other of the battery connections to which the ADC is connected. Therefore, V n+1 With V n The difference between φ and φ is the differential voltage presented across the two input terminals of ADC 116 - 118 .

[0116] If all differential voltages (V n+1 -V n ) is very similar, then most of the time, the current sampling current I p_n 120 and I m_n 119 have the same value and opposite sign. Therefore, the currents cancel each other.

[0117] However, if V n+1 and V n At a very different voltage level (for example, because the battery is bypassed by a short circuit in the busbar or BMS), the current sampling current I p_n 120 and I m_n 119 will not cancel each other, resulting in a significant voltage drop across the external resistor of the low pass filter. This voltage drop causes the ADC to be unable to accurately measure the voltage of the battery connected to the low pass filter. A similar problem exists for the ADC connected to the first and last battery terminals, because those battery terminals only receive the current sampling current I p_n 120 and I m_n A current sampling current is obtained in 119. Figure 1 In the embodiment, the first battery connection terminal C0 101 only receives the negative current sampling current I m_n119. Therefore, the voltage V across the resistor 112 associated with the first battery connection terminal C0 101 is error =I m_n *R drops. This voltage is considered an error voltage because it is effectively subtracted from the voltage of the first battery 105 in terms of what is provided to the first input of the first ADC 116 for measurement. Similarly, the last battery connection C3104 only receives the positive current sampling current I p_n 120, so that the voltage V across the resistor 112 associated with the last battery connection terminal C3 104 error =I p_n *R decreases.

[0118] The lower the input impedance of the analog front end of the BMS, the larger the differential current at the measurement input. Therefore, the differential current attributable to any external resistors associated with the BMS (e.g. Figure 1 As noted above, such external resistors may exist as part of an anti-aliasing filter, as a battery cell balancing resistor, etc.

[0119] It has been found that at least some of the measured currents are predictable, and in many applications, much of this measurement error is predictable and can therefore be compensated for by digital processing. At least some of the examples described herein relate to a BMS that achieves measurement error reduction that can be implemented on the same integrated circuit as the BMS with an associated calibration method. This can achieve accuracy of less than 500 μV in all expected application use cases (with a real number of battery cells, some of which can be bypassed by bus bars). For example, examples of the present disclosure use a digital signal processor to mathematically compensate for the error voltage dropped across an external resistor. As will be described below, such a digital signal processor may use the (V n+1 -V n ) and also in some examples, using 2.f which can be determined by ATE (automatic test equipment) calibration clk .C in The value of C in is the capacitance of the capacitor at each input of each ADC, and f clk is the frequency of the clock associated with each ADC.

[0120] Figure 2 An example embodiment of a BMS according to the present disclosure is shown. Figure 1 As shown in Figure 2 Features of the 200 series have been given corresponding reference numerals and will not need to be described again here.

[0121] Figure 2 The BMS includes a digital processor 221. The digital processor 221 provides a measured voltage output signal 223-225 for each of the ADCs 216-218. That is, the digital processor 221 provides:

[0122] A first measured voltage output signal 223 of the first ADC 216, such that the first measured voltage output signal 223 represents the voltage of the first battery connected between the first battery connection terminal C0 201 and the second battery connection terminal C1 202;

[0123] A second measured voltage output signal 224 of the second ADC 217, such that the second measured voltage output signal 224 represents the voltage of a second battery connected between the second battery connection terminal C1 202 and the third battery connection terminal C2 203;

[0124] A third measured voltage output signal 225 of the third ADC 218 , such that the third measured voltage output signal 225 represents the voltage of a third battery connected between the third battery connection terminal C2 203 and the fourth battery connection terminal C3 204 .

[0125] exist Figure 2 In the example, the first battery is shown as having V n0 =4V, and the third battery is shown to have a voltage of V n2 =4V. The second battery is shown as being shorted by the bus bar, so that the differential voltage between the second battery connection terminal C1 202 and the third battery connection terminal C2 203 is V n1 =0.5V.

[0126] With Figure 1 In the same way, Figure 2 The BMS has ADC 216-218 directly connected to the external low pass filter. The error on the low pass filter (as mentioned above in reference Figure 1 discussed) exists in the analog domain, but Figure 2 In the example, the error is compensated by digital processing in the digital processor 221. Therefore, it is beneficial that Figure 2 The solution can be easily transferred from one technology to another.

[0127] Taking into account different battery / cell voltages (busbar or cell configuration or mismatch), the error voltage in the digital signals 226-228 provided by the ADCs 216-218 due to the voltage drop across the external resistance depends on the voltage levels of the neighboring batteries / cells.

[0128]

[0129] V error=2.Rf clk .C in .(V n+1 +V n-1 -2.V n )

[0130] It should be noted that for a battery / battery cell at the beginning or end of a series of batteries (also referred to as a battery cell stack), the adjacent battery (where no battery is present) is given a value of 0V.

[0131] for Figure 1 For example,

[0132] The error of the first digital signal 226 provided at the output of the first ADC 216 is: V error =2.Rf clk .C in .(0.5+0-2×4)

[0133] The error of the second digital signal 227 provided at the output of the second ADC 217 is: V error =2.Rf clk .C in .(4+4-2×0.5)

[0134] The magnitude of these errors can be significant due to the different voltage levels of adjacent batteries / cells. Figure 2 In the example, the digital processor 221 calculates V for each ADC 216-218. error values ​​so that they can then be applied to the corresponding digital signals 226-228 to provide accurate measured voltage output signals 223-225.

[0135] For each ADC 216-218, the digital processor 221 calculates the ADC error voltage (V error ): i) the digital signal of the immediately preceding ADC if there is one in the sequence; and ii) the digital signal of the immediately succeeding ADC if there is one in the sequence. The digital processor 221 then provides the measured voltage output signals 223-225 by subtracting the error voltage from the digital signals 226-228 of the corresponding ADCs. For example, for the second ADC 217, the digital processor 221 calculates the error voltage (V error ): i) a digital signal 226 of a first ADC 216 in the sequence; and ii) a digital signal 228 of a third ADC 218 in the sequence.

[0136] In addition, Figure 2In the embodiment of the present invention, the digital processor 221 also calculates the error voltage (V) of each ADC based on the following terms: error ): iii) the digital signal of the ADC. Therefore, for the second ADC 217, the digital processor 221 also calculates the error voltage (V error ):iii) The digital signal 227 of the second ADC 217 in the sequence. This corresponds to the above including V n 、V n-1 and V n+1 V error The equation for .

[0137] More specifically, in Figure 2 In the example, the digital processor 221 calculates the error voltage V for each of the n ADCs by applying the following formula: error :

[0138] Error voltage = K x (V n+1 +V n-1 -2.V n )

[0139] Here

[0140] K is a timing value, which will be described below;

[0141] V n+1 is the value of the digital signal of the next ADC if the next ADC exists in the sequence;

[0142] V n-1 is the value of the digital signal of the previous ADC if the previous ADC exists in the sequence; and

[0143] V n is the value of the digital signal of the ADC.

[0144] Figure 2 The combination of addition blocks and multiplication blocks shown in the digital processor 221 of FIG. 2 represents an example of how this formula may be implemented, where K = 2.Rf clk .C in .

[0145] In some examples, this formula may be applied only to the middle ADCs in the sequence; that is, all ADCs that are neither the first nor the last ADC in the sequence. This is because the first and last ADCs do not have a previous or next ADC in the sequence. Therefore, it has been found that using slightly different formulas for the first and last ADCs can further improve the accuracy of the measured voltage output signals 223, 225 of these ADCs.

[0146] More specifically, for the first ADC 216 in the sequence, the digital processor 221 may calculate the error voltage V by applying the following formula: error :

[0147] Error voltage = K x (V n+1 -V n )

[0148] in:

[0149] K is the timing value;

[0150] V n+1 is the value of the digital signal 227 of the second ADC 217 in the sequence; and

[0151] V n is the value of the digital signal 226 of the ADC.

[0152] Additionally, for the last ADC 218 in the sequence, the digital processor 221 may calculate the error voltage V by applying the following formula: error :

[0153] Error voltage = K x (V n-1 -V n )

[0154] in:

[0155] K is the timing value;

[0156] V n-1 is the value of the digital signal 227 of the second to last ADC 217 in the sequence; and

[0157] V n is the value of the digital signal 228 of the ADC 218 .

[0158] for Figure 2 The circuit layout, the timing value K adopts the following value: K = 2.Rf clk .C in .in:

[0159] R is the resistance value of the resistor associated with each battery connection terminal;

[0160] C in is the capacitance of the capacitor at each input terminal of each of the ADCs; and

[0161] f clk is the frequency of the clock associated with each ADC.

[0162] However, it should be appreciated that for other circuit topologies, the timing value K may be implemented differently.

[0163] Figure 3 Another example embodiment of a BMS according to the present disclosure is shown.

[0164] Figure 2 The BMS is accurate but may require a fairly large die size in digital processing depending on the technology used. In many BMS use cases, all cell voltages will be at or close to 0V (when shorted by a bus bar or if the cell is an unused cell). A reasonable simplification can be made by comparing the measured voltage to a threshold to detect an unused cell or bus bar. For example, if the battery / cell voltage is below 1V, the battery / cell is considered to be unused or shorted by a bus bar.

[0165] Using this simplification, we can introduce a binary variable called is_used. Then, we can write:

[0166] V error =2.Rf clk .C in .(V.is_used n+1 +V.is_used n-1 -2.V.is_used n )

[0167] V error =2.Rf clk .C in .V.(is_used n+1 +is_used n-1 -2.is_used n )

[0168] Where V is the expected voltage value of the battery / cell connected to the BMS.

[0169] These equations are given by Figure 3 The digital processor 321 shown in FIG.

[0170] The benefit is that Figure 3 An embodiment of the digital processor 321 uses a ratio Figure 2 The digital processor shown in Figure 1 has fewer multipliers. Figure 3 In the equation, multiply by the term 2.Rf clk .C in .V can be centralized, and (is_used n+1 +is_used n-1 -2.is_used n ) is the sum of 3 binary variables. The possible values ​​are -2, -1, 0, 1, or 2. Therefore, Figure 3 Digital implementation ratio Figure 2The implementation is easier and more compact.

[0171] In this way, the digital processor 321 calculates the error voltage V of the ADC in the sequence by the following operation: error :

[0172] ● If there is a previous ADC in the sequence, compare the digital signal of the previous ADC with the threshold to generate a previous ADC in-use signal. The previous ADC in-use signal corresponds to the above is_used n-1 a variable and having a binary value of '1' if the digital signal is above a threshold value and having a binary value of '0' if the digital signal is less than the threshold value;

[0173] ● If there is a next ADC in the sequence, compare the digital signal of the next ADC with a threshold value to generate a next ADC in-use signal having a binary value. This next ADC in-use signal corresponds to the is_used signal described above. n+1 a variable and having a binary value of '1' if the digital signal is above a threshold value and having a binary value of '0' if the digital signal is less than the threshold value;

[0174] ● combining the previous ADC in-use signal and the next ADC in-use signal in order to determine an error multiplier. As discussed above, this combination may be the sum of a binary variable representing the magnitude of the expected error in the digital signal of the ADC under consideration; and

[0175] • Multiply the error multiplier by a predetermined voltage value. As discussed above, this predetermined voltage value corresponds to the expected voltage value V of the battery connected to the BMS.

[0176] To fully implement the V error The digital processor in this example also calculates the error voltage V for each ADC by the following operation error : Compare the ADC digital signal with the threshold to generate an ADC in-use signal. This ADC in-use signal corresponds to the above is_used n variable and has a binary value of '1' if the digital signal is above a threshold value and has a binary value of '0' if the digital signal is less than the threshold value.

[0177] The digital processor may then combine the previous ADC in-use signal, the next ADC in-use error signal, and the ADC in-use signal to determine the error multiplier in the same manner described above.

[0178] With reference Figure 2 In a similar manner as described, Figure 3The digital processor 321 may apply different equations for the first and last ADCs than the equations applied to the middle ADCs. In this way, different equations are applied to compensate the measured current of the first and last cells because they already have partial measured current compensation in their gain compensation:

[0179] V error =2.Rf clk .C in .(V n+1 +V n-1 -1.V n )

[0180] Where V (n+1) = 0 corresponds to the last / top cell, and V (n-1) = 0 corresponds to the first / bottom cell. Figure 4 is shown for the first ADC in the sequence.

[0181] Therefore, for the first and last ADCs in the sequence, the digital processor 321:

[0182] Combined with the previous ADC in use signal (is_used n-1 ), the next ADC uses the error signal (is_used n+1 ) and the ADC in use signal (is_used n ) to determine the error multiplier according to the following equation:

[0183] Error multiplier=previous ADC in-use signal+next ADC in-use error signal−ADC in-use signal.

[0184] And for each intermediate ADC, the digital processor 321:

[0185] Combined with the previous ADC in use signal (is_used n-1 ), the next ADC uses the error signal (is_used n+1 ) and the ADC in use signal (is_used n ) to determine the error multiplier according to the following equation:

[0186] Error multiplier=previous ADC in-use signal+next ADC in-use error signal−2×ADC in-use signal.

[0187] After the digital processor 321 has calculated the error multiplier of the ADC, the digital processor may calculate the error voltage of the ADC by multiplying the error multiplier and a predetermined voltage value (V) by a timing value K, where:

[0188] K=2.Rf clk.C in ;

[0189] R is the resistance value of the resistor associated with each battery connection terminal;

[0190] C in is the capacitance of the capacitor at each input terminal of each of the ADCs; and

[0191] f clk is the frequency of the clock associated with each ADC.

[0192] Whether it is implementation Figure 2 A complete digital correction is still Figure 3 A simplified digital correction is required to evaluate item 2.Rf for those examples clk .C in R is an external resistor that may be specified in the associated data sheet. Its variation is typically modest; for example, 1% initially (at t0) and 4% over lifetime. However, f clk and C in can vary a lot over process and temperature corners: ±25% or even more. However, for R and C in , the mismatch between channels is relatively negligible, and it can therefore be assumed that f clk is the same for all channels in the BMS. In this way, it will be assumed that 2.Rf clk .C in This is the same for all channels of the BMS chip.

[0193] Figure 4 Another exemplary embodiment of a BMS according to the present disclosure is shown. Figure 4 , the digital processor 421 further mitigates the gain error γ associated with the ADC channel and offset error o channel As will be discussed below, the gain error γ can be determined channel and offset error o channel as part of the calibration routine.

[0194] exist Figure 4 In the embodiment, the digital processor 421 applies a gain correction voltage and an offset correction voltage to each digital signal 426-428 of the ADC of the sequence to provide a corresponding plurality of corrected digital signals 436-438. Figure 4 As shown, digital processor 421 performs all subsequent processing (including reference processing) on ​​corrected digital signals 436-438 instead of digital signals 426-428. Figure 2 and 3In this example, digital processor 421 multiplies each digital signal 426-428 by a gain correction voltage and subtracts an offset correction voltage from each digital signal 426-428.

[0195] We will now turn to the calibration routine performed by or on the BMS to determine the values ​​of the gain correction voltage and the offset correction voltage.The calibration routine may be performed as an ATE calibration strategy.

[0196] As a first step, the calibration routine involves setting the voltage difference between each pair of consecutive battery connection terminals in the sequence to a first calibration value, and then recording the measured voltage output signal of each ADC as the first calibration output value. In this way, all channels are forced to be at the same voltage. The measured current error should be zero because all measured currents should compensate for each other except the first and last ADCs (which may also be referred to as the top and bottom channels). For the middle ADC / channel, we have:

[0197] V meas1 =γ channel .V X1 +o channel

[0198] in:

[0199] V meas1 is the first calibration output value; and

[0200] V X1 is the first calibration value.

[0201] Next, as a second step, the calibration routine involves setting the voltage difference between each pair of consecutive battery connection terminals in the sequence to a second calibration input value, and recording the measured voltage output signal of each ADC as the second calibration output value. In this way, all channels are forced to be at the same voltage, but at a different voltage from the first calibration value. For the middle ADC / channel, we now have:

[0202] V meas2 =γ channel .V X2 +o channel

[0203] in:

[0204] V meas2 is the second calibration output value; and

[0205] V X2 is the second calibration value.

[0206] Now, the BMS can determine the values ​​of the gain correction voltage and the offset correction voltage for each ADC based on the first calibration value, the second calibration value, the first calibration output value associated with the ADC, and the second calibration output value associated with the ADC. For example, these values ​​can be determined by solving the above two equations as simultaneous equations for each ADC. That is:

[0207] and

[0208]

[0209] However, for the first and last ADC (top and bottom channels):

[0210] V meas1 =γ channel .V X1 +o channel -2.Rf clk .C in .V X1

[0211] V meas2 =γ channel .V X2 +o channel -2.Rf clk .C in .V X2

[0212] therefore:

[0213] and

[0214]

[0215] The top and bottom channels do not have enough gain compensation.

[0216] Now go to Figure 5 , the subsequent steps in the calibration routine for determining the value of the timing value K will be described. In the above example, the timing value K is 2.Rf clk .C in This subsequent step assumes that 2.Rf clk .C in It is the same for all channels.

[0217] like Figure 5 As shown, the BMS sets the voltage difference between the middle pair of battery terminals in the sequence to zero; in this example, the middle pair of battery terminals are the second battery terminal C1 502 and the third battery terminal C2 503. At the same time, the BMS sets the voltage difference between the adjacent pairs of battery terminals in the sequence to the first calibration value. Therefore, all Vx are equal: For this cell, we see an impact on the current measurement.

[0218] The measured voltage output signal of the ADC associated with the middle pair of battery connection terminals is then recorded as the third calibration output value V meas3 In this way, one cell in the middle of the stack is forced to 0V while the other cells are at V X1 . For this particular battery cell we have:

[0219] V meas3 =o channel -V error

[0220] V error =2.Rf clk .C in .(V n+1 +V n-1 -2.V n )=4.Rf clk .C in .V X1

[0221]

[0222] Figure 6a and 6b Simulation results illustrating the advantages of the BMS of the present disclosure are shown. In the simulation, random battery cell voltages were used, artificial gain errors and offsets were added to an ideal ADC, and 500 sample measurements were taken. The measurement error for each battery cell is shown on the horizontal axis (in Figure 6a The unit is microvolt, while Figure 6b The unit is nanovolt in the graph). The number of samples is shown on the vertical axis.

[0223] Figure 6a Show Figure 1 Simulation results for a BMS with a digital processor that performs error correction; that is, a BMS without the presence of a digital processor that performs error correction. Figure 6b Show Figure 4 Simulation results for a BMS of FIG. 4 ; that is, a BMS including a digital processor that performs gain and offset calibration and mathematical compensation of measured current errors.

[0224] exist Figure 6a The standard deviation is 320μV. Figure 6b The standard deviation is 115nV. Therefore, Figure 6a and 6b Show Figure 4 The use of digital processors greatly improves the accuracy of battery cell voltage measurement.

[0225] One or more examples disclosed herein can compensate for analog defects in the digital domain. This is in contrast to performing compensation in the analog domain using, for example, a precharge circuit or buffer. Advantageously, performing compensation in the digital domain can result in lower current consumption, smaller die size, and excellent scalability from one technology to another. Furthermore, the operation can reduce / minimize the risk of compensation defects and drift.

[0226] Even if the battery cell voltages are different (e.g., in the case of bus bars), any voltage offsets produced by the sampled current on any input resistor can be compensated for by digital processing. A simplified compensation method is also described that simplifies the digital implementation and further reduces the die size. Finally, a calibration method that can be performed by automated test equipment (ATE) is also described.

[0227] Unless a specific order is explicitly stated, the instructions and / or flow chart steps in the above figures may be executed in any order. In addition, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification may be combined in a variety of ways to produce other examples, and should be understood within the context provided in this detailed description.

[0228] In some example embodiments, the instruction sets / method steps described above are implemented as functions and software instructions embodied as executable instruction sets that are implemented on a computer or machine programmed and controlled by the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or multiple components.

[0229] In other examples, the instruction sets / methods shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such one or more computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. A non-transitory machine or computer usable medium as defined herein does not include signals, but such a medium is capable of receiving and processing information from signals and / or other transient media.

[0230] Example embodiments of the materials discussed in this specification may be implemented in whole or in part through network, computer or data-based devices and / or services. These may include the cloud, the Internet, an intranet, a mobile device, a desktop, a processor, a lookup table, a microcontroller, a consumer device, an infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0231] In one example, one or more instructions or steps discussed herein are automated. The term automated or automatically (and similar variations thereof) means the use of computers and / or mechanical / electrical devices to control the operation of a device, system, and / or process without the need for human intervention, observation, effort, and / or decision making.

[0232] It should be understood that any components referred to as being coupled may be coupled or connected directly or indirectly. In the case of an indirect coupling, additional components may be disposed between the two components referred to as being coupled.

[0233] In this specification, example embodiments have been presented in terms of a selected set of details. However, one skilled in the art will appreciate that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A battery management system, characterized in that: include: A sequence of four or more battery connection terminals for connecting to a series of batteries such that each battery is connected between a pair of the battery connection terminals, wherein: a first battery connection terminal for connecting to a terminal of a battery at one end of the series of batteries; The last battery connection terminal is for connecting to a terminal of a battery at the other end of the series of batteries; and each other battery connection terminal is for connection to a node between two of the batteries in the series; a resistor associated with each battery connection terminal; A sequence of three or more ADCs, each ADC being associated with a pair of the battery connection terminals, each ADC having: a first ADC input connected to one of the pair of battery connections via a resistor associated with the one battery connection; a second ADC input connected to the other of the pair of battery connections via its associated resistor; and ADC output terminal; in: each ADC configured to convert a difference between analog voltages at a first ADC input and a second ADC input of the ADC into a digital signal and to provide the digital signal at an ADC output of the ADC; and A digital processor configured to, for each ADC in the sequence: calculating an error voltage of the ADC based on: i) the digital signal of the previous ADC if there is one in the sequence; and ii) the digital signal of the next ADC if there is one in the sequence; and A measured voltage output signal is provided by subtracting the error voltage from the digital signal of the ADC.

2. The battery management system according to claim 1, characterized in that: The digital processor is further configured to calculate, for each ADC in the sequence, the error voltage additionally based on: iii) the digital signal of the ADC.

3. The battery management system according to claim 1 or claim 2, characterized in that: The digital processor is configured to calculate the error voltage for each intermediate ADC in the sequence by applying the following formula: Error voltage = K x (V n+1 +V n-1 -2.V n ) in: K is the timing value; V n+1 is the value of the digital signal of the next ADC if the next ADC exists in the sequence; V n-1 is the value of the digital signal of the previous ADC if the previous ADC exists in the sequence; and V n is the value of the digital signal of the ADC.

4. A battery management system according to any of the preceding claims, characterized in that The digital processor is configured to calculate the error voltage for a first ADC in the sequence by applying the following formula: Error voltage = K x (V n+1 -V n ) in: K is the timing value; V n+1 is the value of the digital signal of the next ADC in the sequence; and and V n is the value of the digital signal of the first ADC.

5. A battery management system according to any of the preceding claims, characterised in that The digital processor is configured to calculate the error voltage for the last ADC in the sequence by applying the following formula: Error voltage = K x (V n-1 -V n ) in: K is the timing value; V n-1 is the value of the digital signal of the previous ADC in the sequence; and and V n is the value of the digital signal of the last ADC.

6. The battery management system according to any one of claims 3 to 5, characterized in that: K=2.R.f clk .C in ; R is the resistance value of the resistor associated with each battery connection terminal; C in is the capacitance of the capacitor at each input terminal of each of the ADCs; and f clk is the frequency of the clock associated with each ADC.

7. A battery management system according to any of the preceding claims, characterised in that The digital processor is configured to calculate, for each ADC in the sequence, the error voltage of the ADC by: In case that the previous ADC exists in the sequence, comparing the digital signal of the previous ADC with a threshold value to generate a previous ADC in-use signal; If the next ADC exists in the sequence, comparing the digital signal of the next ADC with a threshold value to generate a next ADC in-use signal; combining the previous ADC in-use signal and the next ADC in-use signal to determine an error multiplier; as well as The error multiplier is multiplied by a predetermined voltage value.

8. The battery management system according to claim 7, characterized in that: The digital processor is further configured to calculate, for each ADC in the sequence, the error voltage of the ADC by: comparing the digital signal of the ADC with a threshold value to generate an ADC in-use signal; and The previous ADC in-use signal, the next ADC in-use error signal, and the ADC in-use signal are combined to determine the error multiplier.

9. The battery management system according to claim 8, characterized in that: The digital processor is further configured to: for each intermediate ADC: The previous ADC in-use signal, the next ADC in-use error signal, and the ADC in-use signal are combined to determine the error multiplier according to the following equation: Error multiplier=previous ADC in-use signal+next ADC in-use error signal−2×ADC in-use signal.

10. The battery management system according to claim 9, characterized in that: The digital processor is further configured to, for the first and last ADCs in the sequence: The previous ADC in-use signal, the next ADC in-use error signal, and the ADC in-use signal are combined to determine the error multiplier according to the following equation: Error multiplier=previous ADC in-use signal+next ADC in-use error signal−ADC in-use signal.

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