Biphase buck converter circuit and current sharing method

Abstract

The invention discloses a biphase step-down converter circuit and a current sharing method, and belongs to the technical field of step-down converter circuits. A level conversion circuit and a leading edge blanking circuit are additionally arranged on the basis of a traditional biphase step-down converter circuit; the level conversion circuit receives a first power level driving signal sampled from the first step-down converter and the second step-down converter, obtains a second power level driving signal after level conversion, and inputs the second power level driving signal to the leading edge blanking circuit; the leading edge blanking circuit receives a second power level driving signal and generates a first level signal, when the second power level driving signal jumps at a rising edge and a falling edge, the first level signal is in a first level state, and when the second power level driving signal does not jumps at the rising edge and the falling edge, the first level signal is in a second level state; and the first level signal is an enable signal for opening and closing the current balancing module. According to the invention, large-current burrs generated when the high-side power tube is switched on and switched off can be filtered, and the sampling accuracy is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of buck converter circuits, and in particular, relates to a dual-phase buck converter circuit and a current balancing method. Background Art

[0002] In a dual-phase buck converter circuit, when two buck converters work and supply power at the same time, the supply current of the two buck converters cannot be evenly distributed, that is, the current is not balanced. For example, the load requires a current of 5A, but it is likely that the buck converter BUCK_A supplies 1A and the buck converter BUCK_B supplies 4A. Long-term operation will cause one of the BUCKs (buck converters) to age and be damaged faster, so a current-balancing circuit is needed.

[0003] A Chinese invention patent with publication number CN106257812A proposes a power management chip based on COT control of a two-phase Buck circuit with a current sharing function. In this solution, a current sharing method of a two-phase buck converter is included, but the current sharing method has two problems: ① There will be a short-term punch-through effect when the power tube is turned on and off, resulting in a very large current spike on the switch tube, which lasts for about 2ns. This makes the sampling current inaccurate when the power tube is turned on and off, causing inaccurate sampling voltage of the BUCK, and ultimately leads to inaccurate duty cycle of the power tube.

[0004] ② This current balancing method uses current sampling near the power tube to generate a sampling voltage, and sends the voltage to the current balancing module far away from the power tube. The voltage will collect a lot of interference signals on the layout routing, resulting in a certain voltage deviation and interference signal in the process of sending the voltage to the current balancing module and then to the input end of the BUCK comparator. Summary of the invention

[0005] The purpose of this application is to overcome the defects of the prior art and provide a dual-phase buck converter circuit and a current balancing method, which is intended to filter the large current glitches generated when the power tube is turned on and off, and to reduce the large parasitic interference and errors caused by the layout during longer routing.

[0006] The purpose of this application is achieved through the following technical solutions: A dual-phase buck converter circuit, the dual-phase buck converter circuit comprising a first buck converter, a second buck converter and a current balancing module, the first buck converter comprising a first pulse width modulation comparator, the second buck converter comprising a second pulse width modulation comparator, and further comprising: A level conversion circuit, wherein the level conversion circuit receives a first power level driving signal sampled from the first buck converter and the second buck converter, obtains a second power level driving signal after level conversion, and inputs the second power level driving signal to a leading edge blanking circuit; A leading edge blanking circuit, wherein the leading edge blanking circuit receives the second power level driving signal and generates a first level signal, wherein when the second power level driving signal transitions between a rising edge and a falling edge, the first level signal is in a first level state, and when the second power level driving signal does not transition between a rising edge and a falling edge, the first level signal is in a second level state; The first level signal is an enable signal for switching the current balancing module on and off.

[0007] Further, the first buck converter includes a first current sampling module, and the second buck converter includes a second current sampling module; The first current sampling module obtains a first sampling current and transmits it to the current balancing module; The second current sampling module obtains the second sampling current and transmits it to the current balancing module; The current balancing module evenly distributes the sum of the first sampling current and the second sampling current to the first pulse width modulation comparator and the second pulse width modulation comparator as a reference signal for current balancing.

[0008] Furthermore, the input end of the first pulse width modulation comparator is provided with a first resistor and a third resistor, and the input end of the second pulse width modulation comparator is provided with a second resistor and a fourth resistor; The first resistor and the second resistor are used to convert the reference signal into a voltage signal and then input it into a corresponding pulse width modulation comparator. The third resistor and the fourth resistor are used to convert the sampling current forwarded by the current balancing module into a voltage signal and then input it into a corresponding pulse width modulation comparator.

[0009] On the other hand, the present application also provides a current balancing method for a dual-phase buck converter circuit, wherein the dual-phase buck converter circuit includes a first buck converter, a second buck converter and a current balancing module, and the method includes: Sampling to obtain power level drive signals of high-side power tubes of the first buck converter and the second buck converter; Transmitting the power level driving signal to the leading edge blanking circuit after level conversion; The leading edge blanking circuit generates a first level signal according to the state of the power level driving signal, when the power level driving signal jumps at the rising edge and the falling edge, the first level signal is a low level, when the power level driving signal does not jump at the rising edge and the falling edge, the first level signal is a high level; When the first level signal is at a high level, current sharing is performed.

[0010] Further, the first buck converter includes a first current sampling module, the second buck converter includes a second current sampling module, and the method includes: Acquire a first sampling current of the first buck converter through a first current sampling module, and acquire a second sampling current of the second buck converter through a second current sampling module; When the first level signal is at a high level, the first sampling current and the second sampling current are transmitted to a current balancing module, the current balancing module calculates an average value of the first sampling current and the second sampling current to obtain a first reference current, the first sampling current and the first reference current are transmitted to a first buck converter, and the second sampling current and the first reference current are transmitted to a second buck converter; The first buck converter and the second buck converter receive the reference current and the corresponding sampling current, convert them into voltage signals and then perform current sharing.

[0011] Furthermore, the current sharing specifically includes: Converting the first reference current into a first voltage and connecting the first voltage to the non-inverting input terminal of the first pulse width modulation comparator and the second pulse width modulation comparator; Current sharing is achieved by adjusting the output duty ratios of the first pulse width modulation comparator and the second pulse width modulation comparator.

[0012] Furthermore, the step of adjusting the output duty cycle of the first pulse width modulation comparator and the second pulse width modulation comparator to complete current sharing specifically includes: Convert the first sampling current into a second voltage and input it into the inverting terminal of the first pulse width modulation comparator for comparison with the first voltage, and convert the second sampling current into a third voltage and input it into the inverting terminal of the second pulse width modulation comparator for comparison with the first voltage; When the second voltage is less than the first voltage, the first pulse width modulation comparator output duty cycle increases until the second voltage is equal to the first voltage, and the second pulse width modulation comparator output duty cycle decreases until the third voltage is equal to the first voltage; When the second voltage is greater than the first voltage, the first PWM comparator output duty cycle decreases until the second voltage is equal to the first voltage, and the second PWM comparator output duty cycle increases until the third voltage is equal to the first voltage.

[0013] The beneficial effects of this application are: (1) The present application adds a LEB circuit (leading edge blanking circuit) on the basis of the traditional two-phase buck converter circuit, which can make the power stage drive signal generate a low level when it jumps at the rising edge and the falling edge, and a high level in other cases, and use this signal as an enable signal for whether the sampling current is sent to the current balancing module. The sampling current is not allowed to be sent to the current balancing module during the low level time, and the sampling current is allowed to be sent to the current balancing module to participate in current balancing in other cases. In this way, at the moment when the high-side power tube is turned on and off, the current balancing module does not work, which can offset the error caused by the instantaneous large current generated by the high-side power tube and the low-side power tube to the subsequent sampling circuit and the current balancing module.

[0014] (2) The present application no longer directly sends the voltage signal to the pulse width modulation comparator, but first reduces signal interference by current transmission. After the power tube samples the current, it passes through the LEB circuit and then transmits the sampled current to the current balancing module. The current balancing module then forwards the sampled current and the reference current to the two pulse width modulation comparators. When the sampled current and the reference current reach the input end of the pulse width modulation comparator, they are converted into voltage signals through resistors, thereby reducing the large parasitic interference and errors caused by the long wiring process of the layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a circuit block diagram of a conventional two-phase buck converter circuit; Figure 2 4 is a circuit block diagram of a dual-phase buck converter circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0016] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0017] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0018] There are two problems with existing dual-phase buck converter circuits: ① There will be a short-term punch-through effect when the power tube is turned on and off, resulting in a very large current spike on the switch tube, which lasts for about 2ns. This makes the sampling current inaccurate when the power tube is turned on and off, causing inaccurate sampling voltage of the BUCK, and ultimately leads to inaccurate duty cycle of the power tube.

[0019] ② This current balancing method uses current sampling near the power tube to generate a sampling voltage, and sends the voltage to the current balancing module far away from the power tube. The voltage will collect a lot of interference signals on the layout routing, resulting in a certain voltage deviation and interference signal in the process of sending the voltage to the current balancing module and then to the input end of the BUCK comparator.

[0020] In order to solve the above technical problems, the following embodiments of the dual-phase buck converter circuit and current balancing method of the present application are proposed.

[0021] First, the cause of the problem needs to be analyzed. The embodiment of the present application simplifies the circuit diagram of the prior art solution. Figure 1 ,like Figure 1 The figure shows the circuit block diagram of the traditional two-phase buck converter circuit. Under this current balancing scheme, the sampling voltages Vsen_A and Vsen_B are formed by sampling the switch tube current close to the power tube and sent to the current balancing module, and then a current balancing voltage is output to the comparator to participate in the duty cycle adjustment of the two BUCKs, thereby achieving current balancing. Specifically: BUCK_A and BUCK_B are both common BUCK structures. BUCK_A_OSC and BUCK_B_OSC are the output voltages of the triangle wave oscillators of BUCK_A and BUCK_B respectively. BUCK_A_EA_OUT and BUCK_B_EA_OUT are the outputs of the error amplifiers EA of BUCK_A and BUCK_B respectively. OSC and EA_OUT are sent to the input of the pulse width modulation comparator for comparison to generate a square wave signal with a certain pulse width, which is then driven to turn on the high-side power tube and the low-side power tube to charge and discharge the power inductor and load capacitor, thereby achieving the purpose of power supply. BUCK_A_PWM and BUCK_B_PWM are the pulse width modulation comparators of BUCK_A and BUCK_B respectively, driver is the power stage driver, HS_A and HS_B are the high side power tubes of BUCK_A and BUCK_A respectively, namely HS. When charging, HS is turned on, and when discharging, HS is turned off. Ind is the power inductor, cap is the load capacitance, iload is the external current load, represented by a current source, and the current sampling module samples the current at a position close to the power tube and converts it into a sampling voltage Vsen, which is then sent to the current balancing module to obtain a current sharing voltage Vaverage, which is sent to the inverting input terminal of the PWM comparator and compared with the VREF current sharing reference voltage at the inverting terminal, and then participates in the adjustment of the duty cycle of the HS power tube to achieve the purpose of current sharing.

[0022] After analyzing the current sharing principle of the existing technology, this application proposes an improved solution, referring to Figure 2 ,like Figure 2The figure shows a circuit block diagram of a two-phase buck converter circuit according to an embodiment of the present application. It can be seen from the figure that the embodiment of the present application adds a leading edge blanking circuit LEB to the traditional two-phase BUCK current balancing circuit, and uses the output level signal of the leading edge blanking circuit LEB as an enable signal for opening and closing the current balancing module, thereby solving the error caused by the punch-through effect.

[0023] It should be noted that, since the voltage environment of the current of the sampling power tube is a high voltage environment, and the leading edge blanking circuit works in a low voltage environment, it is impossible to directly use the leading edge blanking circuit to solve the punch-through effect generated when the traditional two-phase buck converter is current-equalizing. For this reason, the embodiment of the present application also adds a level conversion circuit to adapt the leading edge blanking circuit to the bidirectional buck converter circuit.

[0024] In order to solve the above problem ①, the embodiment of the present application samples the driver signal of HS, converts the driver signal into a control signal under low voltage through a level conversion circuit, and then sends it to the leading edge blanking circuit LEB. LEB can allow the driver signal to generate a low level with a pulse width of 2ns when it jumps at the rising edge and the falling edge, and a high level in other cases. The signal is used as an enable signal for whether the sampling currents i1 and i2 generated by the current mirror 1 are sent to the current mirror 2. The sampling currents i1 and i2 of the current mirror 1 are not allowed to be sent to the current mirror 2 during the low level time of 2ns. In other cases, the sampling currents i1 and i2 of the current mirror 1 are allowed to be sent to the current mirror 2 to participate in current sharing. In this way, at the moment when the HS power tube is turned on and off, the current balancing module does not work, which can offset the error caused by the instantaneous large current generated by the high-side power tube HS and the low-side power tube LS to the subsequent sampling circuit and the current sharing module.

[0025] In order to solve the above problem ②, the embodiment of the present application reduces signal interference by sending current after sampling the current. After the power tube samples the current and the current passes through the leading edge blanking circuit LEB, the currents i1 and i2 are sent to the current mirror 2, and the current mirror 2 again divides the currents i1 and i2 and the two currents (i1+i2) / 2, which are sent to the resistors R3 and R4 at the input ports of BUCK_A and BUCK_B respectively, so as to reduce the large parasitic interference and errors caused by the layout in the long routing process.

[0026] In this embodiment, the current mirror 1 reduces the current of the high-side tubes HS_A and HS_B during charging by the ratio of N:1, and the currents are respectively i1 and i2. After i1 and i2 pass through the leading edge blanking circuit LEB, i1 and i2 are sent to the current mirror 2 for addition and then evenly distributed, that is, the current (i1+i2) / 2 is given to the resistors R1 of BUCK_A and BUCK_B to form a reference voltage V1, which is used as the reference voltage of the four-input pulse width modulation comparator. At the same time, i1 and i2 are respectively sent to the two BUCKs and compared with (i1+i2) / 2. Since iload=N*i1+N*i2 (N is the reduction factor), when iload is a constant, when i1>(i1+i2) / 2, then i2<(i1 +i2) / 2, at this time, it means that the load current N*i1 of BUCK_A is greater than the current sharing value, i.e., iload / 2, then the duty cycle of the output of the four-input PWM comparator of BUCK_A will decrease, thereby reducing the charging time of BUCK_A, thereby reducing the supply current of BUCK_A. At the same time, i2<(i1+i2) / 2, it means that the load current N*i2 of BUCK_B is less than the current sharing value, i.e., iload / 2, then the duty cycle of the output of the four-input PWM comparator of BUCK_B will increase, thereby increasing the charging time of BUCK_B, thereby increasing the supply current of BUCK_B, until i1≈i2≈(i1+i2) / 2, thereby achieving the effect of current sharing.

[0027] In the embodiment of the present application, the currents i1 and i2 of the power high-side tubes in BUCK_A and BUCK_B are sampled and compared with the current sharing current value (i1+i2) / 2. When the sampled current in the BUCK is greater than the current sharing current value, the charging time of the BUCK is reduced to ultimately reduce its own power supply current. Vice versa, when the sampled current in the BUCK is less than the current sharing current value, the on-time of the high-side power tube HS is increased, thereby increasing the power supply current of the BUCK, until the power supply currents of the two-phase BUCKs are substantially equal, i.e., iload1=iload2=iload / 2, and the circuit is stable to achieve the current sharing effect.

[0028] The current sharing principle of the embodiment of the present application is as follows: First, the high-side power transistor currents of BUCK_A and BUCK_B are simultaneously sampled by current mirror 1 and current mirror 2 respectively during the charging stage (not working during the discharging stage) and reduced by N times, namely currents i1 and i2. Currents i1 and i2 enter current mirror 2, where i1 and i2 are added together. Then, through current mirror 2, (i1 + i2) is halved to split out two branch currents with a magnitude of (i1 + i2) / 2. These currents are respectively passed through resistors R1 and R2 to ground to form voltages V1 = R1*(i1 + i2) / 2 = V2 = R2*(i1 + i2) / 2 (R1 = R2), which are connected to the non-inverting input terminals of the four-input pulse width modulation comparators of BUCK_A and BUCK_B as reference voltages. At the same time, currents i1 and i2 are replicated 1:1 through current mirrors and then flow to R3 and R4 in BUCK_A and BUCK_B respectively to form voltages V3 = i1*R3 and V4 = i2*R4 (R3 = R4 = R2 = R1), that is, they are then connected to the inverting input terminals of the four-input comparator and compared with V1 and V2 respectively.

[0029] ① When V3 < V1, that is, when i1*R3 < R1*(i1 + i2) / 2: For BUCK_A: Since R1 = R2 = R3 = R4, that is, when i1 < (i1 + i2) / 2, the output duty cycle of BUCK_A_PWM will increase at this time, which makes the conduction time of the high-side power transistor HS_A of BUCK_A longer, thereby increasing the power inductor current, and further increasing the supply current iload1 of BUCK_A until i1 = (i1 + i2) / 2, BUCK_A reaches the current sharing state, thus achieving the purpose of current sharing.

[0030] For BUCK_B: Since R1 = R2 = R3 = R4, that is, when i1 < (i1 + i2) / 2, then necessarily i2 > (i1 + i2) / 2, indicating that the supply current iload2 of BUCK_B at this time is greater than the average current iload / 2. Therefore, the voltage V4 = R4*i2 at the input terminal of BUCK_B is higher than V2 = R2*(i1 + i2) / 2. Thus, the duty cycle of the square wave signal output by the comparator of BUCK_B decreases, thereby reducing the conduction time of the power transistor of BUCK_B and further reducing the charging time of BUCK_B until V4 = R4*i2 = V2 = R2*(i1 + i2) / 2, that is, i2 = (i1 + i2) / 2, making BUCK_B reach the stable state, thus achieving the current sharing state. In this way, i2 = (i1 + i2) / 2, and BUCK_B finally reaches the current sharing state.

[0031] ② When V3 > V1, that is, when i1*R3 > R1*(i1 + i2) / 2 For BUCK_A: when V3>V1, that is, i1*R3>R1*(i1+i2) / 2; since R1=R2=R3=R4, that is, i1>(i1+i2) / 2, the duty cycle of the square wave signal output by BUCK_A_PWM is reduced, so that the conduction time of the high-side power tube HS_A of BUCK_A is shorter, thereby reducing the power inductor current, thereby reducing the supply current iload1 of BUCK_A, until i1=(i1+i2) / 2, it reaches stability, thereby achieving the purpose of current sharing.

[0032] For BUCK_B: When V3>V1, that is, i1*R3>R1*(i1+i2) / 2, and at this time i2<(i1+i2) / 2, the voltage at the input end V4=R4*i2 of BUCK_B is lower than V2=R2*(i1+i2) / 2 (R1=R2=R3=R4), the duty cycle of the square wave signal output by the comparator of BUCK_B increases, thereby increasing the conduction time of the BUCK_B power tube, thereby increasing the charging time of BUCK_B, until V4=R4*i2=V2=R2*(i1+i2) / 2, that is, i2=(i1+i2) / 2, making BUCK_B reach a stable state, thereby reaching a current sharing state. In this way, BUCK_A and BUCK_B, i1=i2=(i1+i2) / 2, finally reach a current sharing state.

[0033] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A dual-phase buck converter circuit, comprising a first buck converter, a second buck converter and a current balancing module, wherein the first buck converter comprises a first pulse width modulation comparator, and the second buck converter comprises a second pulse width modulation comparator, characterized in that: Also includes: A level conversion circuit, wherein the level conversion circuit receives a first power level driving signal sampled from the first buck converter and the second buck converter, obtains a second power level driving signal after level conversion, and inputs the second power level driving signal to a leading edge blanking circuit; A leading edge blanking circuit, wherein the leading edge blanking circuit receives the second power level driving signal and generates a first level signal, wherein when the second power level driving signal transitions between a rising edge and a falling edge, the first level signal is in a first level state, and when the second power level driving signal does not transition between a rising edge and a falling edge, the first level signal is in a second level state; The first level signal is an enable signal for switching the current balancing module on and off.

2. The dual-phase buck converter circuit according to claim 1, wherein: The first buck converter includes a first current sampling module, and the second buck converter includes a second current sampling module; The first current sampling module obtains a first sampling current and transmits it to the current balancing module; The second current sampling module obtains the second sampling current and transmits it to the current balancing module; The current balancing module evenly distributes the sum of the first sampling current and the second sampling current to the first pulse width modulation comparator and the second pulse width modulation comparator as a reference signal for current balancing.

3. The dual-phase buck converter circuit according to claim 2, wherein: The input end of the first pulse width modulation comparator is provided with a first resistor and a third resistor, and the input end of the second pulse width modulation comparator is provided with a second resistor and a fourth resistor; The first resistor and the second resistor are used to convert the reference signal into a voltage signal and then input it into a corresponding pulse width modulation comparator. The third resistor and the fourth resistor are used to convert the sampling current forwarded by the current balancing module into a voltage signal and then input it into a corresponding pulse width modulation comparator.

4. A current balancing method for a dual-phase buck converter circuit, the dual-phase buck converter circuit comprising a first buck converter, a second buck converter and a current balancing module, characterized in that: The method comprises: Sampling to obtain power level drive signals of high-side power tubes of the first buck converter and the second buck converter; Transmitting the power level driving signal to the leading edge blanking circuit after level conversion; The leading edge blanking circuit generates a first level signal according to the state of the power level driving signal, when the power level driving signal jumps at the rising edge and the falling edge, the first level signal is a low level, when the power level driving signal does not jump at the rising edge and the falling edge, the first level signal is a high level; When the first level signal is at a high level, current sharing is performed.

5. The current balancing method of the dual-phase buck converter circuit according to claim 4, characterized in that: The first buck converter includes a first current sampling module, the second buck converter includes a second current sampling module, and the method includes: Acquire a first sampling current of the first buck converter through a first current sampling module, and acquire a second sampling current of the second buck converter through a second current sampling module; When the first level signal is at a high level, the first sampling current and the second sampling current are transmitted to a current balancing module, the current balancing module calculates an average value of the first sampling current and the second sampling current to obtain a first reference current, the first sampling current and the first reference current are transmitted to a first buck converter, and the second sampling current and the first reference current are transmitted to a second buck converter; The first buck converter and the second buck converter receive the reference current and the corresponding sampling current, convert them into voltage signals and then perform current sharing.

6. The current balancing method of the dual-phase buck converter circuit according to claim 5, characterized in that: The current sharing specifically includes: Converting the first reference current into a first voltage and connecting the first voltage to the non-inverting input terminal of the first pulse width modulation comparator and the second pulse width modulation comparator; Current sharing is achieved by adjusting the output duty ratios of the first pulse width modulation comparator and the second pulse width modulation comparator.

7. The current balancing method of the dual-phase buck converter circuit according to claim 6, characterized in that: The step of adjusting the output duty ratio of the first pulse width modulation comparator and the second pulse width modulation comparator to complete current sharing specifically includes: Convert the first sampling current into a second voltage and input it into the inverting terminal of the first pulse width modulation comparator for comparison with the first voltage, and convert the second sampling current into a third voltage and input it into the inverting terminal of the second pulse width modulation comparator for comparison with the first voltage; When the second voltage is less than the first voltage, the first pulse width modulation comparator output duty cycle increases until the second voltage is equal to the first voltage, and the second pulse width modulation comparator output duty cycle decreases until the third voltage is equal to the first voltage; When the second voltage is greater than the first voltage, the first PWM comparator output duty cycle decreases until the second voltage is equal to the first voltage, and the second PWM comparator output duty cycle increases until the third voltage is equal to the first voltage.

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