Adaptive timing architecture

Abstract

Various implementations described herein relate to a device having an adaptive timing architecture with multi-level latches and buffers coupled in a delay line configuration. In some cases, each latch receives a delayed clock signal as a data input and provides a sampled output signal as a latched output based on the clock signal. Further, in some cases, each latch provides a delayed edge of the next clock cycle in order to extend the pulse width of the clock signal.

Description

Background Art

[0001] This section is intended to provide information relevant to understanding the various technologies described herein. As the title of this section implies, this is a discussion of related art and should in no way be considered prior art. Generally speaking, related art may or may not be considered prior art. Therefore, it should be understood that any statement in this section should be understood in this sense and is not intended to be any admission of prior art.

[0002] In various modern circuit architectures, conventional timing circuitry typically uses traditional logic circuitry, such as, for example, buffers and clock gates. In the case of using clock stretching to mitigate droop, one type of circuit that can be used is a digital clock divider that divides the input clock frequency by an integer when a droop is detected. Since the division factor can only be an integer value, if the stretch is triggered too frequently, the system performance may be greatly degraded. On the other hand, without the stretch, critical path delays may cause timing failures due to unexpected power supply drops (e.g., higher logic gate delays). Therefore, in some types of circuits, there is a need for small, energy and area efficient circuits that can provide clock stretching within a fractional division factor of the clock period. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The specific implementations of various technologies are described herein with reference to the accompanying drawings. However, it should be understood that the accompanying drawings only illustrate various specific implementations described herein and are not intended to limit the implementation of the various technologies described herein.

[0004] Figure 1 A diagram illustrating an adaptive timing architecture according to various implementations described herein.

[0005] Figure 2 Graphs showing adaptive timing waveforms according to various implementations described herein.

[0006] FIG. 3A to FIG. 3B Various diagrams of adaptive timing state machines are shown according to various implementations described herein.

[0007] Figure 4 Graphs showing adaptive timing waveforms according to various implementations described herein.

[0008] FIG. 5A to FIG. 5B Various diagrams of adaptive timing state machines are shown according to various implementations described herein.

[0009] FIG. 6A to FIG. 6C Various diagrams showing adaptive timing architectures and related circuitry according to various implementations described herein.

[0010] Figure 7A diagram illustrating an adaptive timing architecture with elastically stretched circuitry according to various implementations described herein. DETAILED DESCRIPTION

[0011] Various specific implementations described herein relate to flexible clock stretching schemes and / or techniques for various circuit-related architectural applications in physical design. In addition, in some specific implementations, the various flexible clock stretching schemes and techniques described herein provide a novel adaptive timing architecture with an adaptive timing block that reduces the frequency of the system circuit when a power sag is detected. The various adaptive timing schemes and / or techniques described herein use a delay line instead of a DLL as a time reference for the extended clock cycle, which enables the stretch to be based on gate delays instead of absolute fractions of the main clock cycle. In addition, since the delay line can be directly connected to the same power supply on which the sag occurs, the amount of stretch can therefore be directly proportional to the sag without any additional processing power. Therefore, the elastic stretching solution described herein can therefore be substantially low-power because the ADC required to detect the sag can be removed and the stretching state machine is substantially simple.

[0012] This article will Figures 1 to 7 Various implementations of the adiabatic step-by-step timing technique for various circuit applications are described in more detail in .

[0013] Figure 1 A schematic diagram 100 is shown of an adaptive timing architecture 104 according to various implementations described herein.

[0014] In various specific implementations, Figure 1 The adaptive timing architecture 104 in the present invention may refer to a flexible and stretchable timing architecture that can be implemented as a system or device having various integrated circuit (IC) components that are arranged and coupled together as some combination of assemblies or parts that provide physical circuit designs and related structures. In some cases, methods of designing, providing, and manufacturing the adaptive timing architecture 104 as an integrated system or device may involve using the various IC circuit components and / or structures described herein to implement manufacturing schemes and techniques associated therewith. In addition, the adaptive timing architecture 104 can be integrated with various computing circuit systems and related components on a single chip, and in addition, the adaptive timing architecture 104 can be implemented in embedded systems and / or devices for automobiles, mobile phones, computers, servers, and Internet of Things (IoT) applications (including remote server nodes).

[0015] like Figure 1As shown in , the adaptive timing architecture 104 may refer to a flexible extended timing architecture for various circuit-related applications. The adaptive timing architecture 104 may include multiple stages of latches (FF0, FF1, ..., FFN) and buffers (B0, B1, ..., BN) coupled in a delay line configuration, wherein the latches (FF0, FF1, ..., FFN) may include flip-flops (FF) or various types of similar circuits. In addition, each latch (FF0, FF1, ..., FFN) may receive a delayed clock signal (out <0> ,out <1> ,……,out <n>) as data input (D0, D1, ..., DN), and then provides a sampled output signal (sampout) based on a clock signal (ck) <0> 、sampout <1> ,……,sampout <n>) as latched outputs (Q0, Q1, ..., QN). In addition, each latch (FF0, FF1, ..., FFN) can provide a delayed edge of the next clock cycle to extend the pulse width (or pulse period) of the clock signal (ck). In some cases, Sampling Output signal(sampout ) can be used to capture the position of the clock pulse in the delay line, and therefore, sampout The position of the clock edge in the delay line is effectively captured (for each clock cycle). Furthermore, in various applications, the plurality of stages may include any number of stages, the latches (FF0, FF1, ..., FFN) may include any number of latches, and the buffers (B0, B1, ..., BN) may include any number of buffers. Furthermore, any type of latch may be used.

[0016] In various implementations, the latches (FF0, FF1, . . . , FFN) may provide a sampled output signal (sampout <0> 、sampout <1> ,……,sampout <n>) as a sampled output (sampout) so as to thereby generate a series of clock cycles of a clock signal (ck) having an extended pulse width (or an extended pulse period). The series of clock cycles may include a series of delayed edges for each corresponding clock cycle so as to extend the pulse width (or pulse period) of the clock signal (ck). In addition, each latch (FF0, FF1, . . . , FFN) may be based on the clock signal (ck) to sample the output signal (sampout) <0> ,……,sampout <n>), and each latch (FF0, FF1, ..., FFN) can provide the starting edge of the latched output (Q0, Q1, ..., QN) as a sampling output (sampout) so as to select a series of clock cycles and delayed clock edges that will extend the clock pulse width (or pulse period). In addition, a series of clock cycles of the clock signal (ck) refers to a series of multiple clock cycles of the clock signal (ck), and the series of multiple clock cycles includes repeated multiple clock cycles.

[0017] In various implementations, the multi-stage latches (FF0, FF1, ..., FFN) and buffers (B0, B1, ..., BN) may include a plurality of stages including a first stage having a first latch (FF0) and a first buffer (B0). The first buffer (B0) may receive a clock signal (ck) and convert a first delayed clock signal (out <0> ) is provided as a first data input (D0) to the first latch (FF0). In addition, the first latch (FF0) can receive a first delayed clock signal (out <0> ), and provides a first sampled output signal (sampout) based on a clock signal (ck) <0> ) as the first latched output (Q0).

[0018] In various implementations, the multiple stages of latches (FF0, FF1, ..., FFN) and buffers (B0, B1, ..., BN) may include a second stage having a second latch (FF1) and a second buffer (B1). The second buffer (B1) may receive the first delayed clock signal (out <0> ), and the second delayed clock signal (out <1> ) is provided as a second data input (D1) to the second latch (FF1). In addition, the second latch (FF1) can receive a second delayed clock signal (out <1> ), and then provides a second sampled output signal (sampout) based on the clock signal (ck) <1> ) as the second latched output (Q1).

[0019] In various implementations, the multiple stages of latches (FF0, FF1, ..., FFN) and buffers (B0, B1, ..., BN) may include a third stage having a third latch (FF2) and a third buffer (B2). The third buffer (B2) may receive the second delayed clock signal (out <1> ), and the third delayed clock signal (out <2> ) is provided as the third data input (D2) to the third latch (FF2). In addition, the third latch (FF2) can receive the third delayed clock signal (out <2> ), and then provides a third sampled output signal (sampout) based on the clock signal (ck) <2> ) as the third latched output (Q2).

[0020] In various implementations, the multiple stages of latches (FF0, FF1, ..., FFN) and buffers (B0, B1, ..., BN) may include a fourth stage having a fourth latch (FF3) and a fourth buffer (B3). In addition, the fourth buffer (B3) may receive a third delayed clock signal (out <2> ), and the fourth delayed clock signal (out <3> ) is provided as a fourth data input (D3) to a fourth latch (FF3). In addition, the fourth latch (FF3) can receive a fourth delayed clock signal (out <3> ), and then provides a fourth sampled output signal (sampout) based on the clock signal (ck) <3> ) as the fourth latched output (Q3).

[0021] In various implementations, the multiple stages of latches (FF0, FF1, ..., FFN) and buffers (B0, B1, ..., BN) may include multiple (N) additional stages, wherein each additional stage has an additional latch (FFN) and an additional buffer (BN). In addition, each additional buffer (BN) may receive a previously delayed clock signal (out) from a previous buffer (BN-1). <n-1>), and another delayed clock signal (out <n>) is provided as another data input (DN) to each additional latch (FFN). In addition, each additional latch (FFN) can receive a delayed clock signal (out <n>), and then provides another sampled output signal (sampout) based on the clock signal (ck) <n>) as the latched output (QN). In addition, in various applications, the buffers (B0, B1, . . . , BN) can be any type of delay element and / or gate for delaying the clock signal (ck), such as, for example, an AND gate, an OR gate, etc.

[0022] Figure 2 2 shows a signal diagram 200 of an adaptive timing waveform 204 according to various implementations described herein. In various applications, Figure 1 The adaptive timing architecture 104 in can be used to describe various transition states (0, 1) of the signal (or waveform) diagram 200.

[0023] like Figure 2 As shown in FIG. 2 , the waveform diagram 200 shows the Figure 1 In some cases, each rising edge signal within each timing period (tw0, tw1, ..., tw7) (as defined by each upward arrow) can refer to a single pulse within each timing period (tw0, tw1, ..., tw7) that can be used to trigger a rising edge pulse of the ck_out signal within each timing window (tw0, tw1, ..., tw7).

[0024] For example, in the timing window tw0, the delayed clock signal (ck=out <0> ) triggers the rising edge of the ck_out signal, and in the timing window tw1, the delayed clock signal (out <1> ) triggers the rising edge of the ck_out signal. In addition, in the timing window tw2, the delayed clock signal (out <2> ) triggers the rising edge of the ck_out signal, and in the timing window tw3, the delayed clock signal (out <3> ) triggers the rising edge of the ck_out signal. In addition, in the timing window tw4, the delayed clock signal (out <4> ) triggers the rising edge of the ck_out signal, and these multiple timing sequences of tw0 to tw4 can repeat themselves on the next timing window. For example, in timing window tw6, the delayed clock signal (ck=out <0> ) triggers the rising edge of the ck_out signal, and in the timing window tw7, the delayed clock signal (out <1> ) triggers the rising edge of the ck_out signal.

[0025] In some implementations, the adaptive timing waveform 204 can provide 4 edges in 1 Tck (ie, clock cycle timing period). However, any number (N) of edges for any number of clock cycle timing periods can be used to generate the ck_out signal.

[0026] FIG. 3A to FIG. 3B Various diagrams of adaptive timing state machines according to various implementations described herein are shown. In some implementations, FIG. 3A to FIG. 3B An example of an adaptive timing state machine diagram for stretching the ck_out signal is shown, where the clock is stretched by one clock edge, and there are 4 clock edges available in one clock cycle. However, the adaptive timing state machine diagram for stretching ck_out can be stretched by any number of clock edges, and the number of clock edges per clock cycle can also be arbitrary (depending on the delay line, voltage, clock frequency and / or temperature).

[0027] Figure 3A A state machine diagram 300A is shown for use with an adaptive timing architecture according to various implementations described herein. Figure 1 The adaptive timing architecture 104 in can be used to describe various transition states (0, 1, 2, 3, 4, N) of the state machine diagram 300A. In some cases, N can refer to a neutral state; however, the neutral state can refer to an idle state, which can be referred to as idle (I).

[0028] like Figure 3A As shown in, the state machine diagram 300A refers to an adaptive timing state machine diagram for extending a ck-out signal having 4 edges in 1 Tck using a plurality of transition logic states (including, for example, a first logic state (0), a second logic state (1), a third logic state (2), a fourth logic state (3), a fifth logic state (4), and an Nth logic state). In addition, the first logic state (0) may refer to a selected state for transitioning to the second logic state (1), and the second logic state (1) may refer to a selected state for transitioning to the third logic state (2). In addition, the third logic state (2) may refer to a selected state for transitioning to the fourth logic state (3), and the fourth logic state (3) may refer to a selected state for transitioning to the fifth logic state (4). In addition, the fifth logic state (4) may refer to a selected state for transitioning to the Nth logic state (N). In addition, the Nth logic state (N) may refer to a selected state for transitioning (or repeating) back to the first logic state (0).

[0029] Figure 3B A state machine diagram 300B is shown for use with an adaptive timing architecture according to various implementations described herein. Figure 1 The adaptive timing architecture 104 in FIG. 1 may be used to describe various transition states (0, 1, 2, 3, 4, N) in the state machine diagram 300B.

[0030] like Figure 3B As shown in, the state machine diagram 300B refers to an adaptive timing state machine diagram for extending a ck-out signal having 4 edges in 1 Tck without using a plurality of transition logic states (including, for example, a first logic state (0), a second logic state (1), a third logic state (2), a fourth logic state (3), a fifth logic state (4), and an Nth logic state). In addition, the first logic state (0) may refer to a selected state that transitions (or returns) back to itself. In addition, the second logic state (1) may refer to a selected state that transitions to the third logic state (2), and the third logic state (2) may refer to a selected state that transitions to the fourth logic state (3). The fourth logic state (3) may refer to a selected state that transitions to the fifth logic state (4), and the fifth logic state (4) may refer to a selected state that may transition to the Nth logic state (N) or the neutral (N) state. In addition, the Nth logic state (N) may refer to a selected state that transitions to the first logic state (0).

[0031] Figure 4 4 shows a signal diagram 400 of an adaptive timing waveform 404 according to various implementations described herein. In various applications, Figure 1 The adaptive timing architecture 104 in can be used to describe various transition states (0, 1) of the signal (or waveform) diagram 400.

[0032] like Figure 4 As shown in FIG. 4 , the waveform diagram 400 shows the Figure 1 In some cases, each rising edge signal within each timing period (tw0, tw1, ..., tw6) (as defined by each upward arrow) can refer to a single pulse within each timing period (tw0, tw1, ..., tw6) that can be used to trigger a rising edge pulse of the ck_out signal within each timing window (tw0, tw1, ..., tw6).

[0033] For example, in the timing window tw0, the delayed clock signal (ck=out <0> ) triggers the rising edge of the ck_out signal, and in the timing window tw1, the delayed clock signal (out <1> ) triggers the rising edge of the ck_out signal, and in the timing window tw2, the delayed clock signal (out <2> ) triggers the rising edge of the ck_out signal, and further, these multiple timing sequences of tw0 to tw2 may be repeated on the next timing window. For example, in timing window tw4, the delayed clock signal (out <0> ) triggers the rising edge of the ck_out signal, and in the timing window tw5, the delayed clock signal (out <1> ) triggers the rising edge of the ck_out signal, and in the timing window tw6, the delayed clock signal (out <2> ) triggers the rising edge of the ck_out signal, and these multiple timing sequences of tw4 to tw6 may repeat themselves in a similar manner on the next timing window.

[0034] In some implementations, the adaptive timing waveform 404 can provide 2 edges in 1 Tck (ie, clock cycle timing period). However, any number (N) of edges for any number of clock cycle timing periods can be used to generate the ck_out signal.

[0035] FIG. 5A to FIG. 5B Various diagrams of adaptive timing state machines are shown according to various implementations described herein.

[0036] Figure 5A A state machine diagram 500A is shown of an adaptive timing state machine 504A for use with an adaptive timing architecture according to various implementations described herein. Figure 1 The adaptive timing architecture 104 in can be used to describe the various transition states (0, 1, 2, N) of the state machine diagram 500A.

[0037] like Figure 5A As shown in , state machine diagram 500A includes an adaptive timing state machine diagram for extending a ck-out signal having 2 edges in 1 Tck using multiple transition logic states (including, for example, a first logic state (0), a second logic state (1), a third logic state (2), and an Nth logic state or a neutral (N) state). In various cases, the first logic state (0) may refer to a selected state for transitioning to the second logic state (1), and the second logic state (1) may refer to a selected state for transitioning to the third logic state (2). In addition, the third logic state (2) may refer to a selected state for transitioning to the Nth logic state (N). In addition, the Nth logic state (N) may refer to a selected state for transitioning (or repeating) back to the first logic state (0).

[0038] Figure 5B A state machine diagram 500B is shown of an adaptive timing state machine 504B for use with an adaptive timing architecture according to various implementations described herein. Figure 1 The adaptive timing architecture 104 in FIG. 5 can be used to describe the various transition states (0, 1, 2, N) of the state machine diagram 500B.

[0039] like Figure 5B As shown in , state machine diagram 500B includes an adaptive timing state machine diagram for extending a ck-out signal having 2 edges in 1 Tck without using multiple transition logic states (including (for example) a first logic state (0), a second logic state (1), a third logic state (2), and an Nth logic state). In various cases, the first logic state (0) may refer to a selected state that transitions (or returns) back to itself, and the second logic state (1) may refer to a selected state that transitions to the third logic state (2). In addition, the third logic state (2) may refer to a selected state that transitions to the Nth logic state (N). In addition, the Nth logic state (N) may refer to a selected state that transitions (or repeats) back to the first logic state (0).

[0040] FIG. 6A to FIG. 6C Various diagrams showing adaptive timing architectures and related circuitry according to various implementations described herein.

[0041] Fig. 6A Schematic diagram 600A shows an adaptive timing (elastic stretch) architecture 604A according to implementations described herein.

[0042] In some specific implementations, Fig. 6A The adaptive timing architecture 604A in the present invention may refer to a flexible and stretchable timing architecture that may be implemented as a system or device having various integrated circuit (IC) components that are arranged and coupled together as some combination of assemblies or parts that provide physical circuit designs and related structures. In some cases, methods of designing, providing, and manufacturing the adaptive timing architecture 604A as an integrated system or device may involve using the various IC circuit components and / or structures described herein to implement manufacturing schemes and techniques associated therewith. In addition, the adaptive timing architecture 604A may be integrated with various computing circuit systems and related components on a single chip, and in addition, the adaptive timing architecture 604A may be implemented in embedded systems and / or devices for automobiles, mobile phones, computers, servers, and Internet of Things (IoT) applications (including remote server nodes).

[0043] like Fig. 6A As shown in FIG. 6 , the adaptive timing architecture 604A may refer to a flexible and extended timing architecture for various circuit-related applications. The adaptive timing architecture 604A may include a delay line reset clock controller 614, a delay line-based drop detector and phase generator 618, a state machine controller 624, a phase selector 628, and a state calculator and synchronizer 634. Figure 6B Additional aspects, features, and circuitry related to the delay line based sag detector and phase generator 618 are described. Figure 6C Additional scopes, features, and circuitry associated with phase selector 628 are described.

[0044] In some specific implementations, the delay line reset clock controller 614 may refer to a clock controller that provides clock signals (ck0, ck1) and reset signals (rst0, rst1, ..., rstN) based on an enable signal (en), an input reset signal (reset), and an input clock signal (ckin). The delay line based sag detector and phase generator 618 may refer to a clock controller that can generate an output signal (O) based on the clock signals (ck0, ck1) and reset signals (rst0, rst1, ..., rstN) from the clock controller 614. <0> , O <1> ,……,O <n>) and the sampling signal (S <0> , S <1> ,……,S <n>) of the phase generator. The phase generator 618 may have multiple stages of latches and logic gates coupled in a delay line configuration. In addition, each latch may receive a delayed clock signal as a data input and provide a sampled output signal as a latched output based on the clock signal. In addition, each latch may provide a delayed edge of the next clock cycle to extend the pulse width (or pulse period) of the clock signal.

[0045] In some implementations, the state machine controller 624 may receive a sampling signal (S <0> , S <1> ,……,S <n>), receiving a sampling signal (St <0> 、St <1> ,……,St <n>) ) as a feedback signal, and then provides an output signal (Os) based on an enable signal (en), an input reset signal (reset), and an input clock signal (ckin) <0> , Os <1> 、……、Os <n>In addition, the phase selector 628 may receive an output signal (Os) from the state machine controller 624. <0> , Os <1> 、……、Os <n>), and then the sampling signal (St <0> 、St <1> ,……,St <n>) is provided to the state machine controller 624 (as a feedback signal). In addition, the state calculator and synchronizer 634 can receive an output signal (O) from the phase generator 618. <0> , O <1> ,……,O <n>), receiving a sampling signal (St <0> 、St <1> ,……,St <n>), and then provide a mask set signal (mask_set <n:0>) and mask reset signal (mask_reset <n:0>) as output.

[0046] Figure 6B Diagram 600B shows a delay line based droop detector and phase generator 618 according to various implementations described herein.

[0047] In some specific implementations, Figure 6B The detector-generator circuit system 618 in the present invention may refer to a flexible and stretchable timing architecture that can be implemented as a system or device having various integrated circuit (IC) components that are arranged and coupled together as some combination of assemblies or parts that provide physical circuit designs and related structures. In some cases, methods of designing, providing, and manufacturing the detector-generator circuit system 618 as an integrated system or device may involve using the various IC circuit components and / or structures described herein to implement manufacturing schemes and techniques associated therewith. In addition, the detector-generator circuit system 618 may be integrated with various computing circuit systems and related components on a single chip, and in addition, the detector-generator circuit system 618 may be implemented in embedded systems and / or devices for automobiles, mobile phones, computers, servers, and Internet of Things (IoT) applications (including remote server nodes).

[0048] like Figure 6B As shown in , the detector-generator circuit system 618 of the drop detector and phase generator 618 based on the delay line can refer to a flexible extended timing architecture for various circuit-related applications. The detector-generator circuit system 618 may include multiple stages of latches (FF0, FF1, ..., FFN) and logic gates (L0, L1, ..., LN) coupled in a delay line configuration, wherein the latches (FF0, FF1, ..., FFN) may include flip-flops (FF) or similar circuits of various types. In addition, each logic gate (L0, L1, ..., LN) may provide a delayed clock signal (O) based on a reset signal (rst0, rst1, ..., rstN). <0> , O <1> ,……,O <n>In addition, the signal (S ) can represent the latched value of the maximum position of the pulse in the delay line. In addition, each latch (FF0, FF1, ..., FFN) can provide the position of the pulse in the delay line so that clock stretch state calculation can be performed.

[0049] In various implementations, the latches (FF0, FF1, . . . , FFN) may provide a sampled output signal ( <0> , O <1> ,……,O <n>) as a sampled output (sampout) in order to calculate a required series of clock cycles of a clock signal (ck) to generate an extended signal period (or an extended pulse width). In addition, a series of clock cycles of a clock signal (ck) may refer to a series of multiple clock cycles of a clock signal (ck), the series of multiple clock cycles including repeated multiple (N) clock cycles. In addition, the series of clock cycles may have a series of delayed edges for each corresponding clock cycle in order to extend the pulse period (or pulse width) of the clock signal (ck). In addition, each latch (FF0, FF1, ..., FFN) may provide a corresponding sampled clock signal starting with a starting edge of a latched output (Q0, Q1, ..., QN) based on the clock signal (ck). In addition, each latch (FF0, FF1, ..., FFN) may provide a starting edge of a latched output (Q0, Q1, ..., QN) as a sampled output (sampout) in order to generate a series of clock cycles with an extended pulse width.

[0050] In various specific implementations, the multiple stages of latches (FF0, FF1, ..., FFN) and logic gates (L0, L1, ..., LN) may include a first stage having a first latch (FF0) and a first logic gate (L0). In addition, the first logic gate (L0) may receive a clock signal (ck), receive a first reset signal (rst0), and convert the first delayed clock signal (O <0> ) is provided as a first data input (D0) to the first latch (FF0). In addition, the first latch (FF0) can receive a first delayed clock signal (O <0> ), and provides a first sampled output signal (S) based on a clock signal (ck) <0> ) as the first latched output (Q0).

[0051] In various implementations, the multiple stages of latches (FF0, FF1, . . . , FFN) and logic gates (L0, L1, . . . , LN) may include a second stage having a second latch (FF1) and a second logic gate (L1). The second logic gate (L1) may receive the first delayed clock signal ( <0> ), receiving a second reset signal (rst1), and transmitting a second delayed clock signal (O <1> ) is provided as a second data input (D1) to a second latch (FF1). The second latch (FF1) can receive a second delayed clock signal ( <1> ), and provides a second sampled output signal (S) based on the clock signal (ck) <1> ) as the second latched output (Q1).

[0052] In various implementations, the multiple stages of latches (FF0, FF1, . . . , FFN) and logic gates (L0, L1, . . . , LN) may include a third stage having a third latch (FF2) and a third logic gate (L2). In addition, the third logic gate (L2) may receive the second delayed clock signal ( <1> ), receiving a third reset signal (rst2), and transmitting a third delayed clock signal (O <2> ) is provided to the third latch (FF2) as the third data input (D2). In addition, the third latch (FF2) can receive the third delayed clock signal (O <2> ), and provides a third sampled output signal (S) based on the clock signal (ck) <2> ) as the third latched output (Q2).

[0053] In various specific implementations, the multiple stages of latches (FF0, FF1, . . . , FFN) and logic gates (L0, L1, . . . , LN) may include a fourth stage having a fourth latch (FF(N-1)) and a fourth logic gate (L(N-1)). In addition, the fourth logic gate (L(N-1)) may receive a third delayed clock signal ( <2> ), receiving a fourth reset signal (rst(N-1)), and providing a fourth delayed clock signal (O(N-1)) as a fourth data input (D(N-1)) to a fourth latch (FF(N-1)). In addition, the fourth latch (FF(N-1)) may receive a fourth delayed clock signal (O <n-1>), and provides a fourth sampled output signal (S) based on the clock signal (ck) <n-1>) as the fourth latched output (Q(N-1)).

[0054] In various implementations, the multiple stages of latches (FF0, FF1, ..., FFN) and logic gates (L0, L1, ..., LN) may include multiple (N) additional stages, wherein each additional stage has an additional latch (FFN) and an additional logic gate (LN). In addition, each additional logic gate (LN) may receive another delayed clock signal (O) from the previous logic gate (L(N-1)). <n>), and the delayed clock signal (O <n>) is provided as another data input (DN) to each additional latch (FFN). In addition, each additional latch (FFN) can receive a delayed clock signal (O <n>), and provides a sampled output signal (S) based on a clock signal (ck) <n>) as the latched output (QN).

[0055] Figure 6C Schematic diagram 600C is shown of a phase selector 628 according to various implementations described herein.

[0056] In various specific implementations, Figure 6C The phase selector 628 in the embodiment may refer to a flexible extended timing architecture that may be implemented as a system or device having various integrated circuit (IC) components that are arranged and coupled together as some combination of assemblies or parts that provide a physical circuit design and related structures. In some cases, methods of designing, providing, and manufacturing the phase selector 628 as an integrated system or device may involve using the various IC circuit components and / or structures described herein to implement manufacturing schemes and techniques associated therewith. In addition, the phase selector 628 may be integrated with various computing circuit systems and related components on a single chip, and further, the phase selector 628 may be implemented in embedded systems and / or devices for automobiles, mobile phones, computers, servers, and Internet of Things (IoT) applications (including remote server nodes).

[0057] like Figure 6C As shown in FIG. 6 , the phase selector 628 may include a multi-stage latch (FF0, FF1, FF2, . . . , FF(M-1), FFM) that receives a sampling signal (Os <0> , Os <1> 、……、Os <n>) as data input signals (D0, D1, D2, ..., D(M-1), DM), receives a clock signal (ck0) as a clock input, and then provides a state signal (ST <0> , ST <1> , ST <2> ,……,ST <m-1>、ST <m>) as data output signals (Q0, Q1, Q2, ..., Q(M-1), QM). Fig. 6A As shown in FIG. 6 , the phase selector 628 may receive a sampling signal (S ) from the state machine controller 624. <0> , S <1> ,……,S <n>), and provides a status signal (ST <0> , ST <1> , ST <2> ,……,ST <m-1>、ST <m>) state calculator and synchronizer 634.

[0058] Figure 7 Schematic diagram 700 is shown of an adaptive timing architecture 704 with elastically extended circuitry according to implementations described herein.

[0059] In various specific implementations, Figure 7 The adaptive timing architecture 704 in the present invention may refer to a flexible and stretchable timing architecture that may be implemented as a system or device having various integrated circuit (IC) components that are arranged and coupled together as some combination of assemblies or parts that provide a physical circuit design and related structures. In some cases, methods of designing, providing, and manufacturing the adaptive timing architecture 704 as an integrated system or device may involve using the various IC circuit components and / or structures described herein to implement manufacturing schemes and techniques associated therewith. In addition, the adaptive timing architecture 704 may be integrated with various computing circuit systems and related components on a single chip, and in addition, the adaptive timing architecture 704 may be implemented in embedded systems and / or devices for automobiles, mobile phones, computers, servers, and Internet of Things (IoT) applications (including remote server nodes).

[0060] like Figure 7 As shown in FIG. 1 , the adaptive timing architecture 704 may refer to a flexible and extensible timing architecture for various circuit-related applications. The adaptive timing architecture 704 may include Fig. 6A The adaptive timing (flexible extension) architecture 604A, together with the pulser 714, the reset multiplexer 1, the set multiplexer 2, the output logic gate (LO) and the output flip-flop latch (FFO). In some applications, such as Figure 7 As shown in the figure, the mask reset signal (mask_reset <n:0>) can be used as a reset selection signal to output to reset multiplexer 1 and mask the set signal (mask_set <n:0>) can be output as a set selection signal to the set multiplexer 2. The pulse generator 714 can receive the O from the adaptive timing (flexible extension) architecture 604A. <n:0>signal, and then provides the mo[N:0] signal to the reset multiplexer 1 and the set multiplexer 2, wherein the reset multiplexer 1 is based on the mask set signal (mask_reset <n:0>) to provide the m1_out signal to the logic gate (LO), and wherein the set multiplexer 1 is based on the mask set signal (mask_set <n:0>>) to provide a set_edge signal to the clock input of the output latch (FFO). In addition, the output logic gate (LO) provides a reset_edge signal to the reset input of the output latch (FFO) based on the m1_out signal and the QO signal from the data output of the output latch (FFO). In addition, the data input (DO) of the output latch (FFO) can be coupled to the supply voltage (VDD).

[0061] It is contemplated that the subject matter of the claims is not limited to the specific implementations and illustrations provided herein, but rather includes modifications of those specific implementations according to the claims, including portions of specific implementations and combinations of elements of different specific implementations. It should be understood that in the development of any such specific implementation, as in any engineering or design project, many specific implementation-specific decisions should be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which may vary between different specific implementations. In addition, it should be understood that such development work may be complex and time consuming, but is nevertheless a routine task of design, manufacture, and production for a person of ordinary skill having the benefit of this disclosure.

[0062] Various implementations of an apparatus having an adaptive clocking architecture having multiple stages of latches and buffers coupled in a delay line configuration are described herein. In some cases, each latch may receive a delayed clock signal as a data input and provide a sampled output signal as a latched output based on the clock signal. In addition, in some cases, each latch may provide a delayed edge of the next clock cycle to extend the pulse width of the clock signal.

[0063] Various implementations of an adaptive timing architecture having a multi-stage latch and logic gate coupled with a delay line are described herein. In some cases, each logic gate may provide a delayed clock signal based on a reset signal. In addition, in some cases, each latch may receive a delayed clock signal as a data input and provide a sampled output signal in the delay line as a latched output based on the clock signal. In addition, in some cases, each latch may provide a delayed edge in the delay line of the next clock cycle to extend the pulse width of the clock signal.

[0064] Various specific implementations of a device having a clock controller that provides a clock signal and a reset signal based on an enable signal, an input reset signal, and an input clock signal are described herein. The device may have a phase generator that generates an output signal and a sampling signal based on a clock signal and a reset signal from a clock controller. In some cases, the phase generator may include a multi-stage latch and a logic gate coupled in a delay line configuration. In addition, in some cases, each latch may receive a delayed clock signal as a data input and provide a sampled output signal as a latched output based on the clock signal. In addition, each latch may provide a delayed edge of the next clock cycle in order to implement a state machine that calculates a delayed edge that will be used to extend the pulse width of the clock signal.

[0065] Reference has been made in detail to various specific implementations, examples of which are shown in the accompanying drawings and diagrams. In the following specific description, many specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other cases, well-known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the details of the embodiments.

[0066] It should also be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The first element and the second element are both elements, but they are not considered to be the same element.

[0067] The terms used in the description of the disclosure provided herein are for the purpose of describing a specific implementation, and are not intended to limit the disclosure provided herein. As used in the disclosure provided herein and the description of the appended claims, the singular forms "a", "a kind of" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. As used herein, the term "and / or" refers to and encompasses any and all possible combinations of one or more of the associated listed items. When used in this specification, the terms "include", "comprise" and / or "contain" specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups.

[0068] As used herein, the term "if" may be interpreted to mean "when" or "at" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined that..." or "if [the condition or event] is detected" may be interpreted to mean "upon determining that..." or "in response to determining that..." or "upon detecting [the condition or event]" or "in response to detecting [the condition or event]," depending on the context. The terms "up" and "down"; "upper" and "lower"; "upward" and "downward"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in conjunction with some specific implementations of the various techniques described herein.

[0069] While the foregoing is directed to various specific implementations of the related art described herein, other and additional specific implementations are contemplated based on the disclosure herein, which may be determined by the appended claims.

[0070] Although the subject matter is described herein in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as exemplary forms of implementing the claims. < / m> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A device comprising: an adaptive clocking architecture having multiple stages of latches and buffers coupled in a delay line configuration, wherein each latch receives a delayed clock signal as a data input and provides a sampled output signal as a latched output based on the clock signal, and Each latch provides a delayed edge of the next clock cycle to extend the pulse width of the clock signal.

2. The apparatus according to claim 1, wherein: Each latch provides the position of the sampled output signal as the latched output based on the clock signal, Each latch provides an upper limit value of the delayed edge of the next clock cycle to extend the pulse width of the clock signal, and The latch provides the sampled output signal as a sampled output to generate a series of clock cycles of the clock signal having a stretched pulse width.

3. The apparatus according to claim 2, wherein: The series of clock cycles has a series of delayed edges for each corresponding clock cycle so as to stretch the pulse width of the clock signal.

4. The apparatus according to claim 2, wherein: Each latch provides a corresponding sampled output signal position starting with a starting edge of the latched output based on the clock signal, and Each latch provides a starting edge value of the latched output as the sampled output to generate the series of clock cycles having the stretched pulse width.

5. The apparatus of claim 2, wherein the series of clock cycles of the clock signal refers to a series of multiple clock cycles of the clock signal, the series of multiple clock cycles comprising a repeated multiple clock cycles.

6. The apparatus of claim 1, wherein: The multi-stage latch and buffer comprises a plurality of stages including a first stage having a first latch and a first buffer, The first buffer receives the clock signal and provides a first delayed clock signal as a first data input to the first latch, and The first latch receives the first delayed clock signal and provides a first position of the sampled output signal as a first latched output based on the clock signal.

7. The apparatus of claim 6, wherein: The multi-stage latch and buffer includes a second stage having a second latch and a second buffer, The second buffer receives the first delayed clock signal and provides a second delayed clock signal as a second data input to the second latch, and The second latch receives the second delayed clock signal and provides a second position of the sampled output signal as a second latched output based on the clock signal.

8. The apparatus of claim 7, wherein: The multi-stage latch and buffer includes a third stage having a third latch and a third buffer, The third buffer receives the second delayed clock signal and provides a third delayed clock signal as a third data input to the third latch, and The third latch receives the third delayed clock signal and provides a third position of the sampled output signal as a third latched output based on the clock signal.

9. The apparatus according to claim 8, wherein: The multi-stage latch and buffer includes a fourth stage having a fourth latch and a fourth buffer, The fourth buffer receives the third delayed clock signal and provides a fourth delayed clock signal as a fourth data input to the fourth latch, and The fourth latch receives the fourth delayed clock signal and provides a fourth position of the sampled output signal as a fourth latched output based on the clock signal.

10. The apparatus of claim 9, wherein: The multi-stage latch and buffer includes a plurality of additional stages, wherein each additional stage has an additional latch and an additional buffer, Each additional buffer receives a delayed clock signal from a previous buffer and provides the delayed clock signal as another data input to each additional latch, and Each additional latch receives the delayed clock signal and provides the position of the sampled output signal as a latched output based on the clock signal.

11. A device comprising: an adaptive clocking architecture having multiple stages of latches and logic gates coupled in a delay line, Each logic gate provides a delayed clock signal based on a reset signal, wherein each latch receives the delayed clock signal as a data input and provides a sampled output signal in the delay line as a latched output based on the clock signal, and Each latch provides a delayed edge in the delay line of the next clock cycle so as to extend the pulse width of the clock signal.

12. The apparatus of claim 11, wherein: The latch provides the position of the sampled output signal in the delay line as a sampled output so as to generate a series of clock cycles of the clock signal having an extended signal period, and The series of clock cycles of the clock signal refers to a series of multiple clock cycles of the clock signal, and the series of multiple clock cycles includes repeated multiple clock cycles.

13. The apparatus of claim 12, wherein: The series of clock cycles has a series of delayed edges for each corresponding clock cycle so as to extend a pulse period of the clock signal.

14. The apparatus of claim 12, wherein: Each latch provides a corresponding sampled output signal starting with a starting edge of the latched output based on the clock signal, and Each latch provides the starting edge of the latched output as the sampled output to generate the series of clock cycles having the stretched pulse width.

15. The apparatus of claim 11, wherein: The multi-stage latch and logic gate comprises a first stage having a first latch and a first logic gate, The first logic gate receives the clock signal, receives a first reset signal, and provides a first delayed clock signal as a first data input to the first latch, and The first latch receives the first delayed clock signal and provides a position of a first sampled output signal as a first latched output based on the clock signal.

16. The apparatus of claim 15, wherein: The multi-stage latches and logic gates include a second stage having a second latch and a second logic gate, The second logic gate receives the first delayed clock signal, receives a second reset signal, and provides a second delayed clock signal as a second data input to the second latch, and The second latch receives the second delayed clock signal and provides a position of a second sampled output signal as a second latched output based on the clock signal.

17. The apparatus of claim 16, wherein: The multiple stages of latches and logic gates include a third stage having a third latch and a third logic gate, The third logic gate receives the second delayed clock signal, receives a third reset signal, and provides a third delayed clock signal as a third data input to the third latch, and The third latch receives the third delayed clock signal and provides a position of a third sampled output signal as a third latched output based on the clock signal.

18. The apparatus of claim 17, wherein: The multi-stage latches and logic gates include a fourth stage having a fourth latch and a fourth logic gate, The fourth logic gate receives the third delayed clock signal, receives a fourth reset signal, and provides a fourth delayed clock signal as a fourth data input to the fourth latch, and The fourth latch receives the fourth delayed clock signal and provides a position of a fourth sampled output signal as a fourth latched output based on the clock signal.

19. The apparatus of claim 18, wherein: The multi-stage latches and logic gates include a plurality of additional stages, wherein each additional stage has additional latches and additional logic gates, Each additional logic gate receives a delayed clock signal from a previous logic gate and provides the delayed clock signal as another data input to each additional latch, Each additional latch receives the delayed clock signal and provides a sampled output signal as a latched output based on the clock signal, and The state calculation depends on the output of the latch which provides the upper bound position of each edge in the delay line.

20. An apparatus comprising: a clock controller that provides a clock signal and a reset signal based on an enable signal, an input reset signal, and an input clock signal; and a phase generator that generates an output signal and a sampling signal based on the clock signal and the reset signal from the clock controller, wherein the phase generator comprises multiple stages of latches and logic gates coupled in a delay line configuration, wherein each latch receives a delayed clock signal as a data input and provides a sampled output signal as a latched output based on the clock signal, and Each latch provides a delayed edge for the next clock cycle in order to implement a state machine that calculates the delayed edge to be used to stretch the pulse width of the clock signal.

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