An adaptive DAC synchronization device and method suitable for high-speed data transmission modulation

Abstract

The application relates to an adaptive DAC synchronization device and method suitable for high-speed data transmission modulation. The method fixes the phase of the SYNC signal of one DAC chip, traverses and adjusts the phase of the SYNC signal of another DAC chip, and simultaneously carries out phase discrimination on the output clock phase of the DAC chip, so as to find the phase difference between the SYNC signals when the output clocks of the two DAC chips are synchronized, output the SYNC signals of the two DAC chips according to the phase difference, and thus realize the sampling clock synchronization of the two DAC chips.

Description

TECHNICAL FIELD

[0001] The application relates to an adaptive DAC synchronization implementation method suitable for high-speed data transmission modulation and belongs to the field of satellite data processing and transmission. BACKGROUND

[0002] To meet the demand of downlink of satellite oceanic load data, a high-order modulation mode with a higher rate needs to be used for downlink of satellite data. The data rate of the high-speed data transmission modulation is as high as 2.4 GHz. High-speed DAC devices will complete the key digital / analog conversion function. In engineering implementation, two high-speed DACs need to simultaneously complete high sampling rate digital / analog conversion. How to ensure the data synchronization between the two high-speed DAC chips under high sampling rate becomes a key problem, and the synchronization performance directly affects the modulation performance.

[0003] Patent CN201710283876.5 discloses a quadrature modulator output DAC synchronization circuit based on double-loop frequency synthesis. The DAC synchronization circuit comprises an I-path frequency synthesizer, a Q-path frequency synthesizer, an I-path DAC, a Q-path DAC and a variable delay module. The I-path frequency synthesizer generates a sampling clock required by the I-path DAC. The I-path DAC performs 1 / N frequency division processing on the I-path DAC sampling clock. One path is sent to an I-path and a Q-path of a quadrature modulator, so that the I-path and the Q-path data of the quadrature modulator are processed and output in synchronization with the I-path frequency division clock. Another path is output to the Q-path frequency synthesizer after phase delay. The Q-path frequency synthesizer takes the I-path frequency division clock as a reference signal, performs phase detection, low-pass filtering and N times frequency multiplication on the Q-path frequency division clock output by the Q-path DAC, and generates a Q-path DAC sampling clock. Thus, the problem of different synchronization of I / Q high-speed DAC output data of a satellite high-reliability modulator is solved. The method adopts an external frequency synthesizer and a variable delay module to realize synchronization detection of the DAC and phase shift of the DAC clock. The method is not suitable for high-rate devices, consumes large hardware resources and has poor scalability. SUMMARY

[0004] The application solves the technical problem of overcoming the shortcomings of the prior art and providing an adaptive DAC synchronization device and method suitable for high-speed data transmission modulation, and solves the synchronization problem of the DAC under a high-rate transmission mode.

[0005] The application solves the technical problem by providing an adaptive DAC synchronization device suitable for high-speed data transmission modulation, which is used for realizing data synchronization between two DAC chips. The two DAC chips share a sampling clock, and the sampling clock is frequency-divided to obtain an output clock. The synchronization device comprises a phase detection module, a phase delay module and a synchronization control module.

[0006] The phase detection module is used to detect the phase of the output clocks CLKD of the two DAC chips and output a phase detection status word. When the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection status word is a preset value.

[0007] The synchronization control module is used for data sampling of the DAC chips; setting the frequency division coefficient of the output clock of the two DAC chips; generating a first synchronization control signal and a second synchronization control signal, wherein the first synchronization control signal is connected to the SYNC signal terminal of the first DAC chip; the second synchronization control signal is connected to the SYNC signal terminal of the second DAC chip; fixing the phase of the first synchronization control signal, traversing the phase delay of the second synchronization control signal, observing the status word output by the phase detection module when the phase of the second synchronization control signal changes relative to the phase of the first synchronization control signal, determining the phase delay of the second synchronization control signal that minimizes the phase difference between the two DAC chips based on the phase delay of the second synchronization control signal corresponding to the preset value output by the phase detection module, keeping the first synchronization control signal unchanged, and outputting the second synchronization control signal according to the phase delay, wherein the two DAC chips are synchronously sampled under the pulse drive of the first synchronization control signal and the second synchronization control signal respectively.

[0008] Preferably, the synchronization control module is implemented using a state machine method. The state machine includes six states, ST1 to ST6, initialized to ST1. The specific operations of the state machine are as follows:

[0009] ST1: Configure and reset the sampling clocks of the two DAC chips, then enter state ST2; ST2: Generate a synchronization control signal. The synchronization control signal is delayed by 16 units of phase by the first global delay unit to obtain the first synchronization control signal; the synchronization control signal is delayed by 0 units of phase by the second global delay unit to obtain the second synchronization control signal; then enter state ST3;

[0010] ST3: Reset the phase detection module, and then enter state ST4;

[0011] ST4: Monitor and record the phase detection status word generated by the phase detector, increment the phase delay of the second synchronization control signal by 1, and determine whether the phase delay is greater than or equal to the preset threshold. If yes, enter state ST5; otherwise, return to state ST3.

[0012] ST5: Extract and calculate the intermediate value of the phase delay corresponding to the second synchronization control signal when the phase detection status word is the preset value, and enter state ST6;

[0013] ST6: Keep the phase delay of the first synchronization control signal unchanged, select the phase delay of the second synchronization control signal as the intermediate value calculated in state ST5, and re-output the first synchronization control signal and the second synchronization control signal.

[0014] Preferably, the phase detection module comprises eight D flip-flops, a PLL module, a phase detection result output module.

[0015] Four D flip-flops are used to latch the state of the output clock of the first DAC chip, and are denoted as flip-flop A1, flip-flop A2, flip-flop A3 and flip-flop A4, respectively.

[0016] The other four D flip-flops are used to latch the state of the output clock of the second DAC chip, and are denoted as flip-flop B1, flip-flop B2, flip-flop B3 and flip-flop B4, respectively.

[0017] The PLL module generates four phase-different and frequency-same phase detection clocks according to an external input clock signal, and the phases of the four phase detection clocks are 22.5°, 67.5°, 112.5° and 157.5°, respectively, and are denoted as a first phase detection clock, a second phase detection clock, a third phase detection clock and a fourth phase detection clock.

[0018] The phase detection result output module outputs the data bits of the phase detection state word from high to low according to the outputs of the flip-flop A1, the flip-flop A2, the flip-flop A3, the flip-flop A4, the flip-flop B1, the flip-flop B2, the flip-flop B3 and the flip-flop B4.

[0019] Preferably, the preset threshold is less than or equal to The preset value is 0xFF.

[0020] Preferably, the intermediate value of the phase delay corresponding to the second synchronization control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronization control signal.

[0021] Preferably, each unit phase delay is 78ps.

[0022] Another technical scheme of the application is an adaptive DAC synchronization method suitable for high-speed data transmission modulation.

[0023] The adaptive DAC synchronization method suitable for high-speed data transmission modulation comprises the following steps:

[0024] S1, configure and reset the sampling clock of the two DAC chips, and then enter step S2;

[0025] S2, generate a synchronization control signal, and after the synchronization control signal is delayed by 16 unit phases through a first global delay unit, a first synchronization control signal is obtained; the synchronization control signal is delayed by 0 unit phases through a second global delay unit, and a second synchronization control signal is obtained; enter step S3; the first synchronization control signal is connected to the SYNC signal end of the first DAC chip; the second synchronization control signal is connected to the SYNC signal end of the second DAC chip;

[0026] S3, phase detect the output clock of the first DAC chip and the second DAC chip, and output a phase detection state word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection state word is a preset value;

[0027] S4, monitor and record the phase detection state word generated by the phase detector, delay the phase of the second synchronization control signal by 1, and judge whether the phase delay is greater than or equal to the preset threshold; if yes, enter step S5; otherwise, return to step S3;

[0028] S5, extract and calculate the middle value of the phase delay corresponding to the second synchronization control signal when the phase detection state word is the preset value, and enter state S6;

[0029] S6, fix the phase delay of the first synchronization control signal unchanged, select the middle value calculated in state S5 as the phase delay of the second synchronization control signal, and re-output the first synchronization control signal and the second synchronization control signal.

[0030] Preferably, the middle value of the phase delay corresponding to the second synchronization control signal is the average value of the phase delay corresponding to the second synchronization control signal, which is obtained by rounding down.

[0031] Preferably, the preset threshold is less than or equal to The preset value is 0xFF.

[0032] The beneficial effects of the present application compared with the prior art are:

[0033] (1) The present application uses FPGA+DAC architecture, which not only solves the selection problem caused by the device and does not need to use other hardware resources, but also is suitable for other mainstream FPGAs and DACs in the application scenario of high sampling rate DAC synchronization.

[0034] (2), the state machine module of the application utilizes a small amount of FPGA internal resources, without using other hardware resources, reduces human intervention, ensures the reliability of DAC synchronization, and utilizes the flexibility of programming in the FPGA to be applicable to more different scenarios.

[0035] (3), the application can avoid the problem of multiple unsuccessful resets caused by fixed reset signal phase, shorten the synchronization time, and realize fast adaptive synchronization.

[0036] (4), the application is applicable to high sampling rate DAC devices, and the sampling rate can be as high as 2.4GHz. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 for the FPGA and DAC connection diagram of the embodiment of the application;

[0038] Figure 2 for the adaptive DAC synchronization implementation method block diagram suitable for high-speed data transmission modulation of the embodiment of the application;

[0039] Figure 3 for the FPGA processing state machine flow chart of the embodiment of the application. DETAILED DESCRIPTION

[0040] The application will be further described below in combination with embodiments.

[0041] The DAC chip realizes digital-to-analog conversion of baseband data in high-speed data transmission modulation, and converts the baseband data signal into an analog signal; the external interface of the DAC chip mainly includes a data interface (DATA), a clock output signal (CLKD) and a reset synchronization signal (SYNC); the data interface (DATA) is parallel data output from the FPGA to the DAC; the clock output signal is a clock output from the DAC to the FPGA after the sampling clock is divided; the reset synchronization signal SYNC, when a pulse signal is input to the SYNC pin of the DAC, the clock output signal CLKD of the DAC will stop for a certain time and then restart.

[0042] In order to perform high-speed modulation data transmission, the application proposes an adaptive DAC synchronization device and implementation method suitable for high-speed data transmission modulation, by fixing the phase of the SYNC signal of one of the DAC chips, adjusting the phase of the SYNC signal of the other DAC chip, and simultaneously phase detecting the output clock phase of the DAC chip, finding the phase difference between the SYNC signals when the output clocks of the two DAC chips are synchronized, outputting the SYNC signals of the two DAC chips according to the phase difference, so as to realize the sampling clock synchronization of the two DAC chips.

[0043] As Figure 1As shown, the adaptive DAC synchronization device for high-speed data transmission modulation provided by the application is used to realize data synchronization between two DAC chips, the adaptive DAC synchronization device is realized by FPGA, two DAC chips share a sampling clock, and the sampling clock is divided to obtain an output clock, and the output clock is fed back to the FPGA.

[0044] The adaptive DAC synchronization device comprises a phase discrimination module, a phase delay module and a synchronization control module.

[0045] The phase discrimination module is used to discriminate the output clock CLKD of the two DAC chips and output a phase discrimination state word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase discrimination state word is a preset value.

[0046] The synchronization control module is used for data sampling of the DAC chips; the division coefficients of the output clocks of the two DAC chips are set; a first synchronization control signal and a second synchronization control signal are generated, the first synchronization control signal is connected to the SYNC signal end of the first DAC chip, the second synchronization control signal is connected to the SYNC signal end of the second DAC chip; the phase of the first synchronization control signal is fixed, the phase delay of the second synchronization control signal is traversed, the state word output by the phase discrimination module is observed when the phase of the second synchronization control signal changes relative to the phase of the first synchronization control signal, the phase delay amount of the second synchronization control signal corresponding to the preset value output by the phase discrimination module is determined, the phase delay amount of the second synchronization control signal that makes the phase difference between the two DAC chips minimum is determined, the first synchronization control signal is kept unchanged, and the second synchronization control signal is output according to the phase delay amount, and the two DAC chips are synchronously sampled under the pulse driving of the first synchronization control signal and the second synchronization control signal.

[0047] Preferably, the synchronization control module is realized by the method of a state machine, the state machine module mainly completes the whole DAC synchronization method and realizes the control of the process, the state machine comprises six states, namely ST1-ST6, and is initialized as ST1.

[0048] As shown in the figure, Figure 3 The specific operation of the state machine is as follows:

[0049] ST1: the application mode and the sampling clock of the two DAC chips are configured and reset, and then state ST2 is entered; the sampling clock configuration includes configuration of the division ratio and the like.

[0050] ST2: the synchronization control signal is generated, the synchronization control signal is delayed by 16 unit phases after passing through a first global delay unit to obtain a first synchronization control signal; the synchronization control signal is delayed by 0 unit phases after passing through a second global delay unit to obtain a second synchronization control signal; and state ST3 is entered.

[0051] ST3: reset the phase detection module, then enter state ST4;

[0052] ST4: monitor and record the phase detection state word generated by the phase detector, then enter state ST5;

[0053] ST5: delay the phase of the second synchronization control signal by 1, determine whether the phase delay is greater than or equal to a preset threshold, if yes, enter state ST6; otherwise, return to state ST3;

[0054] ST6: extract and calculate the intermediate value of the phase delay of the second synchronization control signal when the phase detection state word is a preset value, enter state ST7;

[0055] ST7: fix the phase delay of the first synchronization control signal unchanged, select the phase delay of the second synchronization control signal as the intermediate value calculated in state ST6, and re-output the first synchronization control signal and the second synchronization control signal.

[0056] In some embodiments of the present application, the phase detection module includes eight D flip-flops, a PLL module, and a phase detection result output module.

[0057] Four D flip-flops are used to latch the state of the output clock of the first DAC chip, and are denoted as flip-flop A1, flip-flop A2, flip-flop A3, and flip-flop A4, respectively.

[0058] The other four D flip-flops are used to latch the state of the output clock of the second DAC chip, and are denoted as flip-flop B1, flip-flop B2, flip-flop B3, and flip-flop B4, respectively.

[0059] The PLL module generates four phase-different and frequency-same phase detection clocks according to an external input clock signal, and the phases of the four phase detection clocks are 22.5°, 67.5°, 112.5°, and 157.5°, respectively, denoted as first phase detection clock, second phase detection clock, third phase detection clock, and fourth phase detection clock. The first phase detection clock is connected to the clock terminals of flip-flop A1 and flip-flop B1; the second phase detection clock is connected to the clock terminals of flip-flop A2 and flip-flop B2; the third phase detection clock is connected to the clock terminals of flip-flop A3 and flip-flop B3; and the fourth phase detection clock is connected to the clock terminals of flip-flop A4 and flip-flop B4.

[0060] The phase detection result output module outputs the data bits of the phase detection state word from high to low according to the outputs of flip-flop A1, flip-flop A2, flip-flop A3, flip-flop A4, flip-flop B1, flip-flop B2, flip-flop B3, and flip-flop B4. When the output clocks of the first DAC chip and the second chip are synchronized, the outputs of the four D flip-flops are the same, so when the phase detection state word is 0xFF, it can indicate that the output clocks of the first DAC chip and the second chip are synchronized.

[0061] Preferably, the preset threshold is less than or equal to The preset value is 0xFF.

[0062] The intermediate value of the phase delay corresponding to the second synchronization control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronization control signal.

[0063] The JFM7K325T-C series FPGA of Fudan Microelectronics Co., Ltd. is adopted, wherein the global delay unit of the FPGA has a unit phase delay of 78ps.

[0064] The GDA12SL3GMCCRH series DAC of Zhongdian 24 is adopted, and the DAC is also applicable to other mainstream FPGAs and DACs.

[0065] Based on the above device, the application provides an adaptive DAC synchronization method suitable for high-speed data transmission modulation, and the method is suitable for the design of a satellite-borne high-speed data transmission modulator and other data transmission devices requiring high-speed high-order modulation.

[0066] As shown in Figure 2 The method comprises the following steps:

[0067] S1, the sampling clock of the two DAC chips is configured and reset, and then step S2 is entered;

[0068] S2, a synchronization control signal is generated, the synchronization control signal is delayed by 16 unit phases through a first global delay unit to obtain a first synchronization control signal, and the synchronization control signal is delayed by 0 unit phases through a second global delay unit to obtain a second synchronization control signal; step S3 is entered; the first synchronization control signal is connected to the SYNC signal end of the first DAC chip; and the second synchronization control signal is connected to the SYNC signal end of the second DAC chip;

[0069] S3, the output clock of the first DAC chip and the second DAC chip is phase-detected, and a phase detection state word is output; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection state word is a preset value;

[0070] S4, the phase detection state word generated by the phase detector is monitored and recorded, the phase delay of the second synchronization control signal is increased by 1, and it is judged whether the phase delay is greater than or equal to the preset threshold; if yes, step S5 is entered; otherwise, step S3 is returned;

[0071] S5, the intermediate value of the phase delay corresponding to the second synchronization control signal when the phase detection state word is the preset value is extracted and calculated, and step S6 is entered.

[0072] S6, fixing the phase delay of the first synchronization control signal, selecting the phase delay of the second synchronization control signal as the intermediate value calculated in state S5, and re-outputting the first synchronization control signal and the second synchronization control signal.

[0073] Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the technical solutions of the present application shall fall within the protection scope of the technical solutions of the present application.

Claims

1. An adaptive DAC synchronization device suitable for high speed data modem, for realizing data synchronization between two DAC chips, the two DAC chips sharing a sampling clock and dividing the sampling clock to obtain an output clock; characterized in that The phase discriminator module, the phase delay module, and the synchronization control module are included. The phase discriminator module is configured to perform phase discrimination on the output clock CLKD of the two DAC chips and output a phase discrimination state word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase discrimination state word is a preset value. The synchronization control module is configured to sample data of the DAC chips. The frequency division coefficients of the output clocks of the two DAC chips are set; a first synchronization control signal and a second synchronization control signal are generated; the first synchronization control signal is connected to the SYNC signal end of the first DAC chip; the second synchronization control signal is connected to the SYNC signal end of the second DAC chip; the phase of the first synchronization control signal is fixed, the phase delay of the second synchronization control signal is traversed, and the state word output by the phase discriminator module when the phase of the second synchronization control signal changes relative to the phase of the first synchronization control signal is observed; the phase delay amount of the second synchronization control signal corresponding to the preset value output by the phase discriminator module is determined as the phase delay amount of the second synchronization control signal that minimizes the phase difference between the two DAC chips; the first synchronization control signal remains unchanged, and the second synchronization control signal is output according to the phase delay amount; the two DAC chips are synchronously sampled under the pulse driving of the first synchronization control signal and the second synchronization control signal.

2. The adaptive DAC synchronization device for high speed data modem according to claim 1, wherein, The synchronization control module is implemented by using a state machine method, and the state machine includes six states, namely ST1-ST6, and is initialized as ST1; the specific operation of the state machine is as follows: ST1: The sampling clocks of the two DAC chips are configured and reset, and then the state ST2 is entered; ST2: the synchronization control signal is generated; the synchronization control signal is delayed by 16 unit phases through a first global delay unit to obtain the first synchronization control signal; the synchronization control signal is delayed by 0 unit phases through a second global delay unit to obtain the second synchronization control signal; and the state ST3 is entered; ST3: The phase discriminator module is reset, and then the state ST4 is entered; ST4: The phase discrimination state word generated by the phase discriminator is monitored and recorded; the phase delay of the second synchronization control signal is increased by 1; and it is determined whether the phase delay is greater than or equal to a preset threshold; if yes, the state ST5 is entered; otherwise, the state ST3 is returned; ST5: The intermediate value of the phase delay of the second synchronization control signal corresponding to the preset value of the phase discrimination state word is extracted and calculated, and the state ST6 is entered; ST6: The phase delay of the first synchronization control signal is fixed; the phase delay of the second synchronization control signal is selected as the intermediate value calculated in the state ST5; and the first synchronization control signal and the second synchronization control signal are re-output.

3. The adaptive DAC synchronization device for high speed data modem according to claim 1, wherein, The phase discriminator module includes eight D flip-flops, a PLL module, and a phase discrimination result output module. Four D flip-flops are configured to latch the state of the output clock of the first DAC chip and are denoted as flip-flop A1, flip-flop A2, flip-flop A3, and flip-flop A4. The other four D flip-flops are configured to latch the state of the output clock of the second DAC chip and are denoted as flip-flop B1, flip-flop B2, flip-flop B3, and flip-flop B4. The PLL module generates four phase-different and frequency-same phase-discriminating clocks according to an external input clock signal, the phases of the four phase-discriminating clocks are 22.5°, 67.5°, 112.5° and 157.5°, and the four phase-discriminating clocks are recorded as a first phase-discriminating clock, a second phase-discriminating clock, a third phase-discriminating clock and a fourth phase-discriminating clock; the first phase-discriminating clock is connected to the clock end of the flip-flop A1 and the flip-flop B1; the second phase-discriminating clock is connected to the clock end of the flip-flop A2 and the flip-flop B2; the third phase-discriminating clock is connected to the clock end of the flip-flop A3 and the flip-flop B3; and the fourth phase-discriminating clock is connected to the clock end of the flip-flop A4 and the flip-flop B4. The phase-discriminating result output module outputs the data bits of the phase-discriminating state word from high to low according to the outputs of the flip-flop A1, the flip-flop A2, the flip-flop A3, the flip-flop A4, the flip-flop B1, the flip-flop B2, the flip-flop B3 and the flip-flop B4.

4. The adaptive DAC synchronization device for high speed data modem according to claim 3, wherein, The preset threshold is less than or equal to The preset value is 0xFF.

5. The adaptive DAC synchronization device for high speed data modem according to claim 2, wherein, The intermediate value of the phase delay corresponding to the second synchronization control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronization control signal.

6. The adaptive DAC synchronization device for high speed data modem according to claim 2, wherein, Each unit phase delay is 78 ps.

7. An adaptive DAC synchronization method suitable for high speed data transmission modulation, characterized in that By fixing the phase of the SYNC signal of one of the DAC chips, the phase of the SYNC signal of the other DAC chip is adjusted, and the output clock phase of the DAC chip is phase-discriminated, and the state word output by the phase-discriminating module is observed when the phase of the second synchronization control signal changes relative to the phase of the first synchronization control signal, and the phase delay amount of the second synchronization control signal corresponding to the preset value of the phase-discriminating module is determined, so as to determine the phase delay amount of the second synchronization control signal that makes the phase difference between the two DAC chips minimum, keep the first synchronization control signal unchanged, and output the second synchronization control signal according to the phase delay amount, and the two DAC chips are synchronously sampled under the pulse driving of the first synchronization control signal and the second synchronization control signal.

8. The adaptive DAC synchronization method for high speed data transmission modulation according to claim 7, characterized in that The method comprises the following steps: S1, configuring and resetting the sampling clock of the two DAC chips, and then entering step S2; S2, generating a synchronization control signal, the synchronization control signal is delayed by 16 unit phase delays through a first global delay unit to obtain a first synchronization control signal, and the synchronization control signal is delayed by 0 unit phase delays through a second global delay unit to obtain a second synchronization control signal; entering step S3; the first synchronization control signal is connected to the SYNC signal end of the first DAC chip; and the second synchronization control signal is connected to the SYNC signal end of the second DAC chip; S3, phase-discriminating the output clock of the first DAC chip and the second DAC chip, and outputting a phase-discriminating state word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase-discriminating state word is a preset value; S4, monitoring and recording the phase-discriminating state word generated by the phase discriminator, increasing the phase delay of the second synchronization control signal by 1, and determining whether the phase delay is greater than or equal to the preset threshold; if yes, entering step S5; Otherwise, returning to step S3; S5, extracting and calculating the intermediate value of the phase delay corresponding to the second synchronization control signal when the phase-discriminating state word is the preset value, and entering state S6; S6, fixing the phase delay of the first synchronization control signal unchanged, selecting the intermediate value of the phase delay of the second synchronization control signal calculated in state S5 as the phase delay of the second synchronization control signal, and re-outputting the first synchronization control signal and the second synchronization control signal.

9. The adaptive DAC synchronization method for high speed data transmission modulation according to claim 7, wherein, The intermediate value of the phase delay corresponding to the second synchronization control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronization control signal.

10. The adaptive DAC synchronization method for high speed data transmission modulation according to claim 7, wherein, The preset threshold is less than or equal to The preset value is 0xFF.

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