A semiconductor static memory and its fabrication method

Abstract

This application discloses a semiconductor static memory and its fabrication method, relating to the semiconductor field. The semiconductor static memory includes a substrate and embedded power rails and complementary field-effect transistors (SRAMs) disposed on the substrate. A first and a second embedded power rail are disposed parallel to each other at both ends of the substrate. The first SRAM is formed by stacking a first pull-down transistor and a first pull-up transistor sequentially from bottom to top. The second SRAM is formed by stacking a first transfer transistor and a second transfer transistor sequentially from bottom to top. Both the first and second transfer transistors are n-type. The third SRAM is formed by stacking a second pull-down transistor and a second pull-up transistor sequentially from bottom to top. This application enables a reduction in standard cell area and improves the integration density of the SRAM.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a semiconductor static memory and a method for its fabrication. Background Technology

[0002] As integrated circuits continue to develop, the method of maintaining Moore's Law by continuously shrinking transistor size faces severe challenges such as declining gate control capability and quantum confinement effects. Complementary Field Effect Transistors (CFETs) achieve a significant increase in integration density by vertically stacking two transistors, thereby extending Moore's Law.

[0003] Static Random Access Memory (SRAM) is widely used in mobile phones, computers, wearable devices and automotive electronics due to its advantages such as high speed, no need for refresh, and low power consumption, and its proportion in the overall chip area is getting larger and larger.

[0004] For existing 6T SRAM standard cells, the presence of two n-type PG devices means that the overall 6T SRAM is not an N / P Complementary Metal Oxide Semiconductor (CMOS) structure. Therefore, the two cross-coupled inverters of the SRAM can only be implemented using two CFET structures, while the two PG devices are implemented using the top or bottom devices of each of the two CFET structures. Furthermore, unused devices in these two CFETs need to be removed or disabled to ensure the normal operation of the PG devices. Therefore, the existing 6T SRAM layout occupies the area of ​​four CFETs, making it impossible to achieve a reduction in the area of ​​the standard cell. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor static memory and its fabrication method, which can reduce the area of ​​standard cells and improve the integration density of SRAM.

[0006] To achieve the above objectives, this application provides the following solution:

[0007] In a first aspect, this application provides a semiconductor static memory, comprising: a substrate and a buried power rail and a complementary field-effect transistor disposed on the substrate;

[0008] The embedded power rail includes a first embedded power rail and a second embedded power rail.

[0009] The first and second embedded power rails are arranged parallel to each other at both ends of the substrate; one end of the complementary field-effect transistor is connected to the first embedded power rail; the other end of the complementary field-effect transistor is connected to the second embedded power rail.

[0010] The complementary field-effect transistor includes: a first complementary field-effect transistor, a second complementary field-effect transistor, and a third complementary field-effect transistor arranged at intervals;

[0011] The first complementary field-effect transistor is obtained by stacking the first pull-down transistor and the first pull-up transistor from bottom to top;

[0012] The second complementary field-effect transistor is obtained by stacking the first transfer transistor and the second transfer transistor from bottom to top; both the first transfer transistor and the second transfer transistor are of type n.

[0013] The third complementary field-effect transistor is obtained by stacking the second pull-down transistor and the second pull-up transistor sequentially from bottom to top.

[0014] Optionally, the semiconductor static memory further includes: metal interconnects;

[0015] The metal connecting wire includes: a bottom metal wire and a top metal wire;

[0016] The gate of the first complementary field-effect transistor is connected to the bottom metal line, which is connected to the bottom drain of the second complementary field-effect transistor and the drain of the third complementary field-effect transistor, respectively. The bottom drain of the second complementary field-effect transistor is the drain of the first transmission transistor. The drain of the third complementary field-effect transistor is a common drain structure defined by the drain of the second pull-down transistor and the drain of the second pull-up transistor. The gate of the first complementary field-effect transistor is a common gate structure defined by the gate of the first pull-down transistor and the gate of the first pull-up transistor.

[0017] The drain of the first complementary field-effect transistor is connected to the top metal line, which is connected to the top source of the second complementary field-effect transistor and the gate of the third complementary field-effect transistor, respectively; the top source of the second complementary field-effect transistor is the source of the second transmission transistor; the gate of the third complementary field-effect transistor is a common gate structure determined by the gate of the second pull-down transistor and the gate of the second pull-up transistor.

[0018] Optionally, the semiconductor static memory further includes: buried power rail vias;

[0019] The buried power rail through hole is in interconnection with the embedded power rail.

[0020] The buried power rail through-hole includes: a bottom through-hole, a middle through-hole, and a top through-hole;

[0021] The bottom metal line connects the bottom source of the first complementary field-effect transistor and the bottom via; the bottom source of the first complementary field-effect transistor is the source of the first pull-down transistor.

[0022] The intermediate via connects the top drain of the first complementary field-effect transistor and the bottom drain of the first complementary field-effect transistor to form a common drain structure; the intermediate via is also connected to the bottom metal line; the top drain of the first complementary field-effect transistor is the drain of the first pull-up transistor; the bottom drain of the first complementary field-effect transistor is the drain of the first pull-down transistor.

[0023] The top via is connected to the top drain of the second complementary field-effect transistor and the top source of the first complementary field-effect transistor, respectively; the top via is also connected to the middle via and the bottom metal line, respectively, to form an interconnect structure; the top source of the first complementary field-effect transistor is the source of the first pull-up transistor.

[0024] Optionally, the material of the buried power rail through hole is tungsten or ruthenium.

[0025] Secondly, this application provides a method for fabricating a semiconductor static memory, the method being used to fabricate the aforementioned semiconductor static memory, the method comprising:

[0026] Silicon-germanium and silicon are alternately epitaxially grown on a substrate to obtain a silicon-germanium stacked structure;

[0027] A fin-shaped structure is obtained by etching downwards from the top surface of the silicon-germanium stacked structure to a predetermined position inside the substrate at a set interval using a self-aligned dual imaging technique. The fin-shaped structure includes a groove region and a protrusion region.

[0028] A buried power rail structure is obtained by photolithography deposition based on the fin structure; the buried power rail structure includes: a substrate, a buried power rail, and a photolithographically processed fin structure; the buried power rail includes a first buried power rail and a second buried power rail; the first buried power rail and the second buried power rail are arranged parallel to each other at both ends of the substrate.

[0029] Using etching and deposition processes, a virtual gate pattern of a predetermined thickness is deposited and covered on the buried power rail structure at a location perpendicular to the raised area to obtain a virtual gate structure; the virtual gate pattern extends from the top to the bottom of the raised area.

[0030] In a direction perpendicular to the protruding region, a deposition process is used to deposit material on both sides of the virtual gate structure to obtain the outer wall;

[0031] Using the outer wall as a reference, the protruding area is etched to obtain the source and drain etched structure;

[0032] Based on the source and drain etching structure, etching and deposition processes are performed according to a set method to obtain the inner wall structure.

[0033] On the inner wall structure, a drain-source epitaxial structure is obtained based on an epitaxial growth process; the drain-source epitaxial structure includes: the source and drain of a first pull-up transistor, the source and drain of a first pull-down transistor, the source and drain of a first transmission transistor, the source and drain of a second transmission transistor, the source and drain of a second pull-down transistor, and the source and drain of a second pull-up transistor.

[0034] An etching process is used to etch the virtual gate pattern based on the drain-source epitaxial structure, and then gate metal is deposited to obtain a metal gate structure.

[0035] The metal gate structure is etched and cut according to the set interval to obtain a gate cut structure; the gate cut structure includes a first complementary field-effect transistor, a second complementary field-effect transistor, and a third complementary field-effect transistor; the first complementary field-effect transistor includes a first pull-down transistor and a first pull-up transistor stacked sequentially from bottom to top; the second complementary field-effect transistor includes a first transmission transistor and a second transmission transistor stacked sequentially from bottom to top; the third complementary field-effect transistor includes a second pull-down transistor and a second pull-up transistor stacked sequentially from bottom to top.

[0036] Optionally, a buried power rail structure is obtained by photolithographic deposition based on the fin structure, specifically including:

[0037] An isolation oxide layer of a set thickness is filled in the groove area of ​​the fin structure, and a mask pattern is defined based on photolithography. At both ends of the filled structure and perpendicular to the protruding area, a set depth is etched into the substrate to obtain the buried power rail groove.

[0038] A buried power rail structure is obtained by depositing metallic material in the groove of the buried power rail using a deposition process.

[0039] Optionally, based on the source / drain etching structure, etching and deposition processes are performed according to a set method to obtain the inner wall structure, specifically including:

[0040] Based on the source and drain etching structure, the silicon and germanium on both sides of the outer wall are etched to a set etching depth to obtain the inner wall cavity structure.

[0041] Based on the cavity structure of the inner sidewall, the material is filled using deposition and etching processes to obtain the inner sidewall structure.

[0042] Optionally, the gate metal may be tungsten or aluminum.

[0043] Optionally, the method for fabricating the semiconductor static memory further includes:

[0044] On the gate dicing structure, photolithographic deposition is used to conceal power rail vias;

[0045] The metal interconnects are determined based on the buried power rail vias using photolithography deposition.

[0046] Optionally, High-K gate technology is used to deposit gate metal to obtain a metal gate structure.

[0047] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0048] This application provides a semiconductor static memory and its fabrication method. The method involves parallelly arranging a first and a second buried power rail at opposite ends of a substrate, followed by spaced-apart first complementary field-effect transistors (CFETs), second CFETs, and third CFETs. The first CFET is formed by stacking a first pull-down transistor and a first pull-up transistor sequentially from bottom to top. The second CFET is formed by stacking a first transfer transistor and a second transfer transistor sequentially from bottom to top. Both the first and second transfer transistors are n-type. The third CFET is formed by stacking a second pull-down transistor and a second pull-up transistor sequentially from bottom to top. This structural arrangement enables a reduction in the area of ​​standard cells, improving the integration density of the SRAM. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a circuit diagram of a standard SRAM cell.

[0051] Figure 2 This is a schematic diagram of a typical CFET structure;

[0052] Figure 3 This is a schematic diagram of a silicon-germanium stacked structure;

[0053] Figure 4 This is a schematic diagram of a fin-shaped structure;

[0054] Figure 5 Schematic diagram of STI filling structure;

[0055] Figure 6 Schematic diagram of the trench structure for burying the power rail;

[0056] Figure 7 Schematic diagram of the structure for burying the power rail;

[0057] Figure 8 This is a schematic diagram of a virtual gate structure;

[0058] Figure 9 This is a schematic diagram of the outer wall structure of the gate.

[0059] Figure 10 This is a schematic diagram of the source and drain etching structure;

[0060] Figure 11 This is a schematic diagram of the cavity structure of the inner wall;

[0061] Figure 12 This is a schematic diagram of the inner wall structure;

[0062] Figure 13 This is a schematic diagram of the source-drain epitaxial structure and its perspective when rotated 90° clockwise around the z-axis.

[0063] Figure 14 This is a schematic diagram of a metal gate structure;

[0064] Figure 15 This is a schematic diagram of the gate cutting structure;

[0065] Figure 16 A schematic diagram of the structure for burying the power rail through-hole and the perspective of rotating 90° clockwise around the z-axis.

[0066] Figure 17 This is a schematic diagram of the underlying metal interconnect structure and the viewpoint of rotating 120° clockwise around the z-axis.

[0067] Figure 18 This is a schematic diagram of the structure with a central through hole and the viewpoint of rotating 120° clockwise around the z-axis.

[0068] Figure 19 This is a schematic diagram of the top-layer metal interconnect structure;

[0069] Figure 20 This is a schematic diagram of the structure of a semiconductor static memory.

[0070] Figure 21 This is a schematic diagram of the viewpoint of a semiconductor static memory rotated 120° clockwise around the z-axis. Detailed Implementation

[0071] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0072] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0073] The circuit diagram of a standard SRAM cell is as follows: Figure 1 As shown, a standard SRAM cell consists of six transistors (N1, N2, N3, N4, P1, and P2) connected by interconnects. P1 and P2 are PMOS transistors, used as pull-up transistors in the SRAM. N2 and N3 are NMOS transistors, used as pull-down transistors in the SRAM. N1 and N4 are also NMOS transistors, used as transfer transistors in the SRAM.

[0074] The top transistor of the first complementary field-effect transistor CFET1 mentioned in this application corresponds to... Figure 1 The N2 transistor in the CFET1 corresponds to the bottom transistor. Figure 1 The P1 transistor in the middle. The top transistor of the second complementary field-effect transistor CFET2 corresponds to... Figure 1 The N4 transistor in the CFET2 corresponds to the bottom transistor. Figure 1 The N1 transistor in the middle. The top transistor of the third complementary field-effect transistor CFET3 corresponds to... Figure 1 The N3 transistor in the CFET3 corresponds to the bottom transistor of the CFET3. Figure 1 The P2 transistor in the middle.

[0075] CFETs typically consist of NMOS and PMOS stacked vertically to form an N / P complementary structure. A typical CFET structure is as follows: Figure 2 As shown, the structure mainly includes a silicon substrate 201, a common metal gate 202, a channel 203 for the top transistor, a source epitaxial layer 204 for the top transistor, a drain epitaxial layer 205 for the top transistor, a channel 207 for the bottom transistor, a source epitaxial layer 208 for the bottom transistor, and a drain epitaxial layer 206 for the bottom transistor. The top transistor is typically an NMOS, and the bottom transistor is a PMOS, but designers can also design their own. The empty areas of the entire CFET structure 200 are filled with interlayer dielectric. However, the asymmetry in the number of N / P transistors in a standard SRAM cell hinders the reduction in standard cell area brought about by the CFET structure.

[0076] In one exemplary embodiment, this application provides a semiconductor static memory, which includes a substrate and embedded power rails and complementary field-effect transistors disposed on the substrate.

[0077] The embedded power rail includes a first embedded power rail and a second embedded power rail; the first embedded power rail and the second embedded power rail are arranged parallel to each other at both ends of the substrate; one end of the complementary field-effect transistor is connected to the first embedded power rail; the other end of the complementary field-effect transistor is connected to the second embedded power rail.

[0078] The complementary field-effect transistor includes a first complementary field-effect transistor, a second complementary field-effect transistor, and a third complementary field-effect transistor arranged at intervals.

[0079] The first complementary field-effect transistor is obtained by stacking the first pull-down transistor and the first pull-up transistor sequentially from bottom to top.

[0080] The second complementary field-effect transistor is obtained by stacking the first transfer transistor and the second transfer transistor from bottom to top; both the first transfer transistor and the second transfer transistor are of type n.

[0081] The third complementary field-effect transistor is obtained by stacking the second pull-down transistor and the second pull-up transistor from bottom to top.

[0082] In one embodiment, the semiconductor static memory further includes: metal interconnects.

[0083] The metal interconnects include a bottom metal line and a top metal line; the gate of the first complementary field-effect transistor (CFPT) is connected to the bottom drain of the second CFPT and the drain of the third CFPT via the bottom metal line; the bottom drain of the second CFPT is the drain of the first transfer transistor; the drain of the third CFPT is a common-drain structure defined by the drains of the second pull-down transistor and the second pull-up transistor. The gate of the first CFPT is a common-gate structure defined by the gates of the first pull-down transistor and the first pull-up transistor.

[0084] The drain of the first complementary field-effect transistor uses a top metal line, which is connected to the top source of the second complementary field-effect transistor and the gate of the third complementary field-effect transistor, respectively; the top source of the second complementary field-effect transistor is the source of the second transfer transistor; the gate of the third complementary field-effect transistor is a common gate structure determined by the gate of the second pull-down transistor and the gate of the second pull-up transistor.

[0085] In one embodiment, the semiconductor static memory further includes: buried power rail vias; the material for burying the power rail vias is tungsten or ruthenium.

[0086] The buried power rail through-holes are interconnected with the embedded power rails; the buried power rail through-holes include: bottom through-holes, middle through-holes and top through-holes.

[0087] The bottom metal line connects the bottom source of the first complementary field-effect transistor (CFPT) and the bottom via; the bottom source of the first CFPT is the source of the first pull-down transistor; the middle via connects the top drain of the first CFPT and the bottom drain of the first CFPT to form a common drain structure; the middle via is also connected to the bottom metal line; the top drain of the first CFPT is the drain of the first pull-up transistor; the bottom drain of the first CFPT is the drain of the first pull-down transistor.

[0088] The top via is connected to the top drain of the second complementary field-effect transistor and the top source of the first complementary field-effect transistor, respectively; the top via is also connected to the middle via and the bottom metal line, respectively, to form an interconnect structure; the top source of the first complementary field-effect transistor is the source of the first pull-up transistor.

[0089] In one exemplary embodiment, a method for fabricating a semiconductor static memory is provided. This method includes:

[0090] Silicon-germanium and silicon are epitaxially grown alternately on a substrate to obtain a silicon-germanium stacked structure.

[0091] Using a self-aligned dual imaging technique, a fin structure is obtained by etching downwards from the top surface of the silicon-germanium stacked structure to a predetermined position inside the substrate based on a set interval; the fin structure includes a groove region and a protrusion region.

[0092] A buried power rail structure is obtained by photolithography deposition based on the fin structure. The buried power rail structure includes a substrate, a buried power rail, and a photolithographically processed fin structure. The buried power rail includes a first buried power rail and a second buried power rail. The first buried power rail and the second buried power rail are arranged parallel to each other at both ends of the substrate.

[0093] Using etching and deposition processes, a virtual gate pattern of a set thickness is deposited and covered on the power rail structure at the location perpendicular to the raised area to obtain a virtual gate structure; the virtual gate pattern extends from the top to the bottom of the raised area.

[0094] In a direction perpendicular to the protruding region, material is deposited on both sides of the virtual gate structure using a deposition process to obtain the outer wall.

[0095] Using the outer wall as a reference, the raised area is etched to obtain the source and drain etched structure.

[0096] Based on the source and drain etching structure, etching and deposition processes are performed according to the set method to obtain the inner wall structure.

[0097] On the inner wall structure, a drain-source epitaxial structure is obtained based on the epitaxial growth process; the drain-source epitaxial structure includes: the source and drain of the first pull-up transistor, the source and drain of the first pull-down transistor, the source and drain of the first transmission transistor, the source and drain of the second transmission transistor, the source and drain of the second pull-down transistor, and the source and drain of the second pull-up transistor.

[0098] An etching process is used to etch the virtual gate pattern based on the drain-source epitaxial structure, followed by gate metal deposition to obtain a metal gate structure. The gate metal is either tungsten or aluminum.

[0099] As an alternative implementation, a metal gate structure is obtained by using High-K gate technology to deposit gate metal.

[0100] The metal gate structure is etched and cut at predetermined intervals to obtain a gate-cut structure. The gate-cut structure includes a first complementary field-effect transistor (CFPT), a second complementary field-effect transistor (CFPT), and a third complementary field-effect transistor (CFPT). The first CFPT includes a first pull-down transistor and a first pull-up transistor stacked sequentially from bottom to top. The second CFPT includes a first transmission transistor and a second transmission transistor stacked sequentially from bottom to top. The third CFPT includes a second pull-down transistor and a second pull-up transistor stacked sequentially from bottom to top.

[0101] In one embodiment, a buried power rail structure is obtained by photolithographic deposition based on a fin-shaped structure, specifically including:

[0102] An isolation oxide layer of a set thickness is filled in the groove area of ​​the fin-shaped structure, and a mask pattern is defined based on photolithography. At both ends of the filled structure and perpendicular to the raised area, a set depth is etched into the substrate to obtain the buried power rail groove.

[0103] By using a deposition process, metallic material is deposited in the groove of the buried power rail to obtain the buried power rail structure.

[0104] In one embodiment, based on the source / drain etching structure, etching and deposition processes are performed according to a predetermined method to obtain the inner wall structure, specifically including:

[0105] Based on the source-drain etching structure, the silicon-germanium on both sides of the outer wall is etched to a set etching depth to obtain the inner wall cavity structure.

[0106] Based on the cavity structure of the inner sidewall, the material is filled using deposition and etching processes to obtain the inner sidewall structure.

[0107] In one embodiment, the method for fabricating a semiconductor static memory further includes:

[0108] On the gate dicing structure, photolithography is used to deposit buried power rail vias; metal interconnects are determined based on the buried power rail vias using photolithography.

[0109] Based on the SRAM pull-up and pull-down transistors being constructed using a CFET structure (CFET1 consisting of P1 and N2 stacked vertically, and CFET3 consisting of P2 and N3 stacked vertically), this invention also uses two NMOS transfer transistors (N1 and N4) stacked vertically to obtain a CFET structure (CFET2). By designing metal interconnects, the area of ​​the SRAM standard cell is reduced.

[0110] The specific steps of the implementation method are as follows:

[0111] 1. Silicon-germanium 2 and silicon 3 are alternately epitaxially grown on a designated wafer substrate, i.e., substrate 1, to form a silicon-germanium stacked structure 100, such as... Figure 3 As shown, the thickness and quantity of silicon germanium 2 and silicon 3 can be designed according to requirements to obtain device designs with different performance characteristics.

[0112] 2. Based on the silicon-germanium stacked structure 100, the silicon-germanium stacked structure 100 is etched using a self-aligned dual imaging technique to obtain the fin structure 101, such as... Figure 4 As shown.

[0113] 3. Based on the fin structure 101, a shallow trench isolation oxide (STI) layer 4 is filled on the silicon substrate, i.e., substrate 1, to obtain the STI-filled structure 102, as shown below. Figure 5 As shown. The shallow trench isolation oxide layer 4 surrounds the portion of the substrate 1 below the silicon germanium 2. The shallow trench isolation oxide layer 4 can be made of silicon nitride, silicon oxide, silicon oxynitride, etc., and can be deposited by a deposition process.

[0114] 3. Based on the fin structure 101, a mask pattern is defined using photolithography, and then the STI filling structure 102 is etched to a certain depth on the silicon substrate 1 to obtain the buried power rail trench structure 103, as shown below. Figure 6 As shown, this depth can be designed by the designer according to the etching process capabilities.

[0115] 4. Based on the buried power rail trench structure 103, a first buried power rail 5 and a second buried power rail 6 are deposited using a deposition process, resulting in the buried power rail structure 104, as shown below. Figure 7 As shown. The first embedded power rail 5 and the second embedded power rail 6 are connected to high-level (VDD) wiring in the overall interconnect layout of the chip. The first embedded power rail 5 and the second embedded power rail 6 can be made of metals such as tungsten and molybdenum.

[0116] 5. Based on the buried power rail structure 104, the pattern of the virtual gate 7 is defined using photolithography. Then, using etching and deposition processes, the virtual gate 7 is deposited and covers the substrate 1 of the buried power rail structure 104 and the surrounding fin-stacked silicon-germanium 2 and silicon 3, resulting in the virtual gate structure 105. Figure 8 As shown.

[0117] 6. Based on the virtual gate structure 105, outer walls 8 are deposited on both sides of the virtual gate 7 using a deposition process to obtain the gate outer wall structure 106, as shown below. Figure 9 As shown. The material of the outer wall 8 can be silicon nitride, silicon oxide, etc.

[0118] 7. Based on the gate outer wall structure 106, using the virtual gate 7 and outer wall 8 as a hard mask, the substrate 1, silicon germanium 2, and silicon 3 not covered by the virtual gate 7 and outer wall 8 are etched away through an etching process. The etching depth is designed by the designer, but the bottom layer of silicon germanium 2 must be completely etched away, up to the level of the shallow trench isolation oxide layer 4, finally forming the source / drain etching structure 107, as shown below. Figure 10 As shown.

[0119] 8. Based on the source / drain etching structure 107, a selective etching process is used to laterally etch all exposed silicon-germanium 2 on both sides of the outer wall 8 in the y-direction. The etching depth is designed by the designer and can reach the thickness of the outer wall, finally forming the inner wall cavity structure 108, such as... Figure 11 As shown.

[0120] 9. Based on the inner wall cavity structure 108, the inner wall is filled into the inner wall cavity through deposition and etching processes to form the inner wall structure 109, as shown below. Figure 12 As shown. The material of the inner wall can be silicon nitride, silicon oxide, etc. Note that it needs to be different from the material of the outer wall 8 to facilitate selective etching away the excess parts.

[0121] 10. Based on the inner wall structure 109, source and drain electrodes are epitaxially grown on the surfaces of all exposed silicon 3 on both sides of the outer wall 8 using a selective epitaxial growth process, resulting in a source / drain epitaxial structure 110, as shown below. Figure 13 As shown. The source and drain electrodes of all silicon 3 epitaxially grown on the surface are: drain 10 and source 16 of the top transistor of CFET1, drain 13 and source 19 of the bottom transistor of CFET1, drain 11 and source 17 of the top transistor of CFET2, drain 14 and source 20 of the bottom transistor of CFET2, drain 18 and source 12 of the top transistor of CFET3, and drain 21 and source 15 of the bottom transistor of CFET3.

[0122] 11. Based on the source-drain epitaxial structure 110, the dummy gate 7 is first etched away using an etching process, then all exposed silicon-germanium 2 is selectively etched, and then a metal gate 22 is deposited using High-K gate technology to obtain the metal gate structure 111, as shown below. Figure 14 As shown. The gate metal can be tungsten, aluminum, etc., and is designed by the designer.

[0123] 12. Based on the metal gate structure 111, the metal gate 22 and the outer wall 8 are etched using an etching process to form the gate dicing structure 112, such as... Figure 15 As shown, the metal gate 22 is divided into three parts, corresponding to the metal gate 22-1 of CFET1, the metal gate 22-2 of CFET2, and the metal gate 22-3 of CFET3, respectively.

[0124] 13. Based on the gate dicing structure 112, the buried power rail vias and the mask for the buried power rail vias are defined by photolithography. Then, through etching and deposition processes, the first bottom via 23 and the second bottom via 24 are formed, resulting in the buried power rail via structure 113. The first bottom via 23 forms an interconnection contact with the second buried power rail 6, and the second bottom via 24 forms an interconnection contact with the first buried power rail 5. Figure 16 As shown. The material used to cover the power rail through-holes can be tungsten, ruthenium, etc., and the designer can decide for themselves.

[0125] 14. Based on the buried power rail via structure 113, a mask is used to define the first bottom layer metal interconnect 25, the second bottom layer metal interconnect 26, the third bottom layer metal interconnect 27, and the fourth bottom layer metal interconnect 28 through photolithography. Then, through etching and deposition processes, the first bottom layer metal interconnect 25, the second bottom layer metal interconnect 26, the third bottom layer metal interconnect 27, and the fourth bottom layer metal interconnect 28 are formed, resulting in the bottom layer metal interconnect structure 114, as shown below. Figure 17As shown. The first bottom metal interconnect 25 sequentially connects the drain 13 of the bottom transistor of CFET1, the drain 14 of the bottom transistor of CFET2, and the metal gate 22-3 of CFET3. The second bottom metal interconnect 26 connects the source 15 of the bottom transistor of CFET3 and the first bottom via 23, electrically connecting the source 15 of the bottom transistor of CFET3 to the second buried power rail 6. The third bottom metal interconnect 27 connects the source 20 of the bottom transistor of CFET2 and extends a certain length along the positive y-axis of the coordinate axis. This length is set by the designer, provided that it meets the set rules. The fourth bottom metal interconnect 28 connects the source 19 of the bottom transistor of CFET1 and the second bottom via 24, electrically connecting the source 19 of the bottom transistor of CFET1 to the buried power rail 5. The bottom metal lines include: the first bottom metal interconnect 25, the second bottom metal interconnect 26, the third bottom metal interconnect 27, and the fourth bottom metal interconnect 28.

[0126] 15. Based on the underlying metal interconnect structure 114, the mask pattern for the intermediate vias is defined by photolithography; then, through etching and deposition processes, the first intermediate via 29, the second intermediate via 30, and the third intermediate via 31 are formed, resulting in the intermediate via structure 115. The intermediate via structure is as follows: Figure 18 As shown. The intermediate through holes include: a first intermediate through hole 29, a second intermediate through hole 30, and a third intermediate through hole 31.

[0127] The first intermediate via 29 connects the drain 10 of the top transistor of CFET1 and the drain 13 of the bottom transistor of CFET1, forming a common-drain structure of CFET1, and is connected to the first bottom metal interconnect 25. The second intermediate via 30 connects the drain 18 of the top transistor of CFET3 and the drain 21 of the bottom transistor of CFET3, forming a common-drain structure of CFET3. The third intermediate via 31 connects to the third bottom metal interconnect 27.

[0128] 16. Based on the intermediate via structure 115, a mask for the top-layer metal interconnect 32 is defined by photolithography. Then, the top-layer metal interconnect 32 is formed through photolithography and deposition processes, resulting in the top-layer metal interconnect structure 116, as shown below. Figure 19 As shown. The top metal interconnect 32 is sequentially connected to the metal gate 22-1 of CFET1, the source 17 of the top transistor of CFET2, the drain 18 of the top transistor of CFET3, and the intermediate via 30.

[0129] 17. Based on the top metal interconnect structure 116, top vias, namely the first top via 33, the second top via 34, the third top via 35, the fourth top via 36, ​​and the fifth top via 37, are defined by photolithography. Then, the first top via 33, the second top via 34, the third top via 35, the fourth top via 36, ​​and the fifth top via 37 are formed by etching and deposition processes, resulting in the top via structure 117, as shown below. Figure 20 and Figure 21 As shown. The first top via 33 connects to the drain 11 of the top transistor of CFET2, and the second top via 34 connects to the source 12 of the top transistor of CFET3. The third top via 35 connects to the third intermediate via 31, and the third top via 35, the third intermediate via 31, and the third bottom metal interconnect 27 form an electrical interconnect structure. The fourth top via 36 connects to the metal gate 22-2 of CFET2, and the fifth top via 37 connects to the source 16 of the top transistor of CFET1.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A semiconductor static memory, characterized in that, The semiconductor static memory includes: a substrate and a buried power rail and a complementary field-effect transistor disposed on the substrate; The embedded power rail includes a first embedded power rail and a second embedded power rail. The first and second embedded power rails are arranged parallel to each other at both ends of the substrate; one end of the complementary field-effect transistor is connected to the first embedded power rail; the other end of the complementary field-effect transistor is connected to the second embedded power rail. The complementary field-effect transistor includes: a first complementary field-effect transistor, a second complementary field-effect transistor, and a third complementary field-effect transistor arranged at intervals; The first complementary field-effect transistor is obtained by stacking the first pull-down transistor and the first pull-up transistor from bottom to top; The second complementary field-effect transistor is obtained by stacking the first transfer transistor and the second transfer transistor from bottom to top; both the first transfer transistor and the second transfer transistor are of type n. The third complementary field-effect transistor is obtained by stacking the second pull-down transistor and the second pull-up transistor sequentially from bottom to top.

2. The semiconductor static memory according to claim 1, characterized in that, The semiconductor static memory further includes: metal interconnects; The metal connecting wire includes: a bottom metal wire and a top metal wire; The gate of the first complementary field-effect transistor is connected to the bottom metal line, which is connected to the bottom drain of the second complementary field-effect transistor and the drain of the third complementary field-effect transistor, respectively. The bottom drain of the second complementary field-effect transistor is the drain of the first transmission transistor. The drain of the third complementary field-effect transistor is a common drain structure defined by the drain of the second pull-down transistor and the drain of the second pull-up transistor. The gate of the first complementary field-effect transistor is a common gate structure defined by the gate of the first pull-down transistor and the gate of the first pull-up transistor. The drain of the first complementary field-effect transistor is connected to the top metal line, which is connected to the top source of the second complementary field-effect transistor and the gate of the third complementary field-effect transistor, respectively; the top source of the second complementary field-effect transistor is the source of the second transmission transistor; the gate of the third complementary field-effect transistor is a common gate structure determined by the gate of the second pull-down transistor and the gate of the second pull-up transistor.

3. The semiconductor static memory according to claim 2, characterized in that, The semiconductor static memory further includes: buried power rail vias; The buried power rail through hole is in interconnection with the embedded power rail. The buried power rail through-hole includes: a bottom through-hole, a middle through-hole, and a top through-hole; The bottom metal line connects the bottom source of the first complementary field-effect transistor and the bottom via; the bottom source of the first complementary field-effect transistor is the source of the first pull-down transistor. The intermediate via connects the top drain of the first complementary field-effect transistor and the bottom drain of the first complementary field-effect transistor to form a common drain structure; the intermediate via is also connected to the bottom metal line; the top drain of the first complementary field-effect transistor is the drain of the first pull-up transistor; the bottom drain of the first complementary field-effect transistor is the drain of the first pull-down transistor. The top via is connected to the top drain of the second complementary field-effect transistor and the top source of the first complementary field-effect transistor, respectively; the top via is also connected to the middle via and the bottom metal line, respectively, to form an interconnect structure; the top source of the first complementary field-effect transistor is the source of the first pull-up transistor.

4. The semiconductor static memory according to claim 3, characterized in that, The material of the buried power rail through hole is tungsten or ruthenium.

5. A method for fabricating a semiconductor static memory, characterized in that, The method for fabricating the semiconductor static memory is used to fabricate the semiconductor static memory according to any one of claims 1-4, wherein the method for fabricating the semiconductor static memory includes: Silicon-germanium and silicon are alternately epitaxially grown on a substrate to obtain a silicon-germanium stacked structure; A fin-shaped structure is obtained by etching downwards from the top surface of the silicon-germanium stacked structure to a predetermined position inside the substrate at a set interval using a self-aligned dual imaging technique. The fin-shaped structure includes a groove region and a protrusion region. A buried power rail structure is obtained by photolithography deposition based on the fin structure; the buried power rail structure includes: a substrate, a buried power rail, and a photolithographically processed fin structure; the buried power rail includes a first buried power rail and a second buried power rail; the first buried power rail and the second buried power rail are arranged parallel to each other at both ends of the substrate. Using etching and deposition processes, a virtual gate pattern of a predetermined thickness is deposited and covered on the buried power rail structure at a location perpendicular to the raised area to obtain a virtual gate structure; the virtual gate pattern extends from the top to the bottom of the raised area. In a direction perpendicular to the protruding region, a deposition process is used to deposit material on both sides of the virtual gate structure to obtain the outer wall; Using the outer wall as a reference, the protruding area is etched to obtain the source and drain etched structure; Based on the source and drain etching structure, etching and deposition processes are performed according to a set method to obtain the inner wall structure. On the inner wall structure, a drain-source epitaxial structure is obtained based on an epitaxial growth process; the drain-source epitaxial structure includes: the source and drain of a first pull-up transistor, the source and drain of a first pull-down transistor, the source and drain of a first transmission transistor, the source and drain of a second transmission transistor, the source and drain of a second pull-down transistor, and the source and drain of a second pull-up transistor. An etching process is used to etch the virtual gate pattern based on the drain-source epitaxial structure, and then gate metal is deposited to obtain a metal gate structure. The metal gate structure is etched and cut according to the set interval to obtain a gate cut structure; the gate cut structure includes a first complementary field-effect transistor, a second complementary field-effect transistor, and a third complementary field-effect transistor; the first complementary field-effect transistor includes a first pull-down transistor and a first pull-up transistor stacked sequentially from bottom to top; the second complementary field-effect transistor includes a first transmission transistor and a second transmission transistor stacked sequentially from bottom to top; the third complementary field-effect transistor includes a second pull-down transistor and a second pull-up transistor stacked sequentially from bottom to top.

6. The method for fabricating a semiconductor static memory according to claim 5, characterized in that, Based on the aforementioned fin-shaped structure, photolithographic deposition is performed to obtain a buried power rail structure, specifically including: An isolation oxide layer of a set thickness is filled in the groove area of ​​the fin structure, and a mask pattern is defined based on photolithography. At both ends of the filled structure and perpendicular to the protruding area, a set depth is etched into the substrate to obtain the buried power rail groove. A buried power rail structure is obtained by depositing metallic material in the groove of the buried power rail using a deposition process.

7. The method for fabricating a semiconductor static memory according to claim 5, characterized in that, Based on the source / drain etching structure, etching and deposition processes are performed according to a predetermined method to obtain the inner wall structure, specifically including: Based on the source and drain etching structure, the silicon and germanium on both sides of the outer wall are etched to a set etching depth to obtain the inner wall cavity structure. Based on the cavity structure of the inner sidewall, the material is filled using deposition and etching processes to obtain the inner sidewall structure.

8. The method for fabricating a semiconductor static memory according to claim 5, characterized in that, The gate metal is made of tungsten or aluminum.

9. The method for fabricating a semiconductor static memory according to claim 5, characterized in that, The method for fabricating the semiconductor static memory further includes: Photolithographic deposition is performed on the gate dicing structure to conceal power rail vias; The metal interconnects are determined based on the buried power rail vias using photolithography deposition.

10. The method for fabricating a semiconductor static memory according to claim 5, characterized in that, A metal gate structure is obtained by depositing gate metal using High-K gate technology.

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