Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a stack structure comprising a plurality of initial support layers and a plurality of initial sacrificial layers in a thickness direction of the stack structure; forming a plurality of initial lower electrodes through the stack structure and in contact with the substrate; an initial top support layer of a top layer of the stack structure is located between and above the plurality of initial lower electrodes; forming a mask layer above the initial top support layer, the mask layer and the initial lower electrodes comprising the same material; patterning the initial top support layer based on the mask layer to form a plurality of openings in the initial top support layer; continuing to etch the stack structure comprising the initial lower electrodes along the plurality of openings, and removing the plurality of initial sacrificial layers; the remaining initial lower electrodes form lower electrodes, the remaining mask layer forms a strengthening layer, and the remaining initial support layers form support layers, wherein a top support layer of the support layers is located between and protrudes from the plurality of lower electrodes.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor structure commonly used in electronic devices. It contains multiple memory cells, each of which includes a transistor and a capacitor. As DRAM feature sizes continue to shrink, the capacitance of the capacitors is often increased by increasing the height of the capacitor columns to improve storage density. When the feature size decreases below a certain value, forming capacitor columns with high aspect ratios presents more process challenges. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.

[0004] In a first aspect, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0005] Providing a substrate; forming a stacked structure consisting of a plurality of initial support layers and a plurality of initial sacrificial layers alternating in a thickness direction of the substrate;

[0006] forming a plurality of initial lower electrodes arranged in an array; the plurality of initial lower electrodes pass through the stacked structure and contact the substrate; wherein the initial top support layer of the top layer of the stacked structure is located between the plurality of initial lower electrodes and is located above the plurality of initial lower electrodes;

[0007] forming a mask layer above the initial top supporting layer, wherein the mask layer and the initial bottom electrode comprise the same material;

[0008] The initial top supporting layer is patterned based on the mask layer to form a plurality of openings in the initial top supporting layer, and the stacked structure including the initial lower electrodes is continuously etched along the plurality of openings to remove the plurality of initial sacrificial layers; the remaining initial lower electrodes constitute the lower electrodes, the remaining mask layers form the strengthening layers, and the remaining initial supporting layers constitute the supporting layers, wherein the top supporting layer in the supporting layers is located between the plurality of lower electrodes and protrudes from the plurality of lower electrodes.

[0009] In some embodiments, in the step of patterning the initial top supporting layer based on the mask layer, an etching selectivity ratio between the initial top supporting layer and the mask layer is greater than or equal to 15.

[0010] In some embodiments, forming the stacked structure and forming the plurality of initial bottom electrodes arranged in an array includes:

[0011] In the thickness direction of the substrate, overlappingly depositing a first initial supporting layer, a first initial sacrificial layer, a second initial supporting layer, a second initial sacrificial layer, a third initial supporting layer, a third initial sacrificial layer and a fourth initial supporting layer to form the stacked structure;

[0012] Selectively etching the stacked structure to form a plurality of capacitor holes penetrating the plurality of initial support layers and the plurality of initial sacrificial layers, wherein the plurality of capacitor holes are arranged in an array;

[0013] forming the plurality of initial lower electrodes in the plurality of capacitor holes respectively;

[0014] A fifth initial supporting layer is formed on surfaces of the plurality of initial lower electrodes and the fourth initial supporting layer, wherein the fifth initial supporting layer and the fourth initial supporting layer together constitute an initial top supporting layer of the top layer in the stacked structure.

[0015] In some embodiments, the size of the fifth initial supporting layer in the thickness direction of the substrate is less than or equal to the size of the fourth initial supporting layer in the thickness direction of the substrate, and the size of the fifth initial supporting layer in the thickness direction of the substrate is less than or equal to 50 nm.

[0016] In some embodiments, the mask layer is multi-layered, and forming the mask layer above the initial top supporting layer includes:

[0017] forming a first initial mask layer and a second initial mask layer in sequence on the initial top supporting layer; the first initial mask layer is made of the same material as the initial bottom electrode, and the second initial mask layer is made of the same material as the initial sacrificial layer;

[0018] A patterned photoresist layer is formed on the second initial mask layer, and the second initial mask layer and the first initial mask layer are sequentially etched through the patterned photoresist layer to form the mask layer.

[0019] In some embodiments, during the step of removing the initial sacrificial layer,

[0020] An etching selectivity ratio between the first preliminary mask layer and the second preliminary mask layer is greater than or equal to 20.

[0021] In some embodiments, the thickness of the first initial mask layer is less than or equal to 20 nm.

[0022] In some embodiments, in the step of continuing to etch the stacked structure including the initial lower electrode along the plurality of openings to remove the plurality of initial sacrificial layers,

[0023] The multiple initial sacrificial layers are removed by a wet method using a mixture of ammonium bifluoride, ammonium fluoride and water.

[0024] In some embodiments, the step of removing the plurality of initial sacrificial layers by wet method using a mixture of ammonium bifluoride, ammonium fluoride and water further includes:

[0025] Use a mixture of ammonia, hydrogen peroxide and water.

[0026] In some embodiments, the method for preparing a semiconductor structure further includes:

[0027] forming a dielectric layer along the plurality of openings on surfaces of the lower electrode, the support layer, and the strengthening layer;

[0028] forming an upper electrode on a surface of the dielectric layer; and,

[0029] A filling layer is filled in the gaps between the upper electrodes.

[0030] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, including:

[0031] A substrate and a plurality of support layers spaced apart along a thickness direction of the substrate;

[0032] a plurality of lower electrodes arranged in an array, the plurality of lower electrodes passing through the plurality of supporting layers and contacting the substrate, wherein a top supporting layer among the plurality of supporting layers is located between the plurality of lower electrodes and protrudes from the plurality of lower electrodes;

[0033] A strengthening layer is located on the top supporting layer, and the strengthening layer and the lower electrode contain the same material.

[0034] In some embodiments, the lower electrode is a cylindrical electrode or a columnar electrode.

[0035] In some embodiments, the semiconductor structure further comprises:

[0036] a dielectric layer continuously disposed on surfaces of the plurality of lower electrodes, the plurality of support layers, and the strengthening layer;

[0037] an upper electrode continuously disposed on a surface of the dielectric layer; and

[0038] The filling layer fills the gaps between the upper electrodes.

[0039] In some embodiments, in the top supporting layer, a thickness of a first portion protruding from the lower electrodes is less than or equal to a thickness of a second portion located between the lower electrodes, and a thickness of the first portion is less than or equal to 50 nm.

[0040] In some embodiments, the thickness of the strengthening layer is less than or equal to 20 nm.

[0041] The present disclosure provides a semiconductor structure and a method for preparing the same. In the present disclosure, the mask layer and the lower electrode contain the same material, which can not only improve the bowl-shaped defect problem caused by the top support layer, but also utilize the high etching selectivity between the top support layer and the lower electrode. As the capacitor size continues to decrease, the capacitance density or height and the thickness of the top support layer continue to increase, the high etching selectivity between the top support layer and the mask layer can be ensured, thereby achieving a balance between the opening size (i.e., the critical size) of the support layer and the sacrificial layer residue, thereby improving the reliability of the capacitor structure formed. In addition, since the mask layer and the lower electrode contain the same material, and the material of the lower electrode is usually a metal material with greater stress, the stress of the mask layer is also greater and the ability to resist deformation is stronger. In this way, the mask layer forms a strengthening layer, which increases the height and strength of the supporting layer, thereby improving the support for the capacitor structure. That is, the top support layer located between the multiple lower electrodes and protruding from the multiple lower electrodes, and the strengthening layer located on the top support layer can produce a better support effect on the lower electrode, so that the stability of the formed capacitor structure is enhanced. In addition, the mask layer and the lower electrode contain the same material, which can also avoid contamination of the lower electrode in the stacked structure during the process of patterning the initial top support layer based on the mask layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0043] Figure 1 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0044] Figures 2 to 22 A schematic diagram of the structure during the preparation of the semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0046] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0047] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0048] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the present disclosure necessarily has the first element, component, region, layer, or part.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] As the requirements for the capacitance value of the storage unit increase, the size of the capacitor column continues to shrink, and the height of the capacitor column and the thickness of the top silicon nitride carbide layer in the support structure continue to increase. Continuing to use the top silicon nitride carbide layer as a hard mask layer to etch multiple silicon nitride carbide layers in the support structure will lead to greater process challenges.

[0051] First, when the lower silicon carbide nitride layer in the supporting structure is etched using the top silicon carbide nitride layer as a hard mask, the top silicon carbide nitride layer will be consumed at the same time. Therefore, when the thickness of the top silicon carbide nitride layer is not enough, it is difficult to obtain sufficient over-etching of the sacrificial oxide layer, resulting in the inability to open the supporting structure, thereby causing the sacrificial oxide layer to remain.

[0052] Secondly, when the top silicon carbide nitride layer is made thicker, it becomes more difficult to open it during etching, and in order to obtain sufficient over-etching of the sacrificial oxide layer, it is difficult to maintain the remaining thickness of the top silicon carbide nitride layer, thereby exposing the top of the lower electrode layer to the wet etching solution for removing the sacrificial oxide layer, causing the interior of the lower electrode layer to be etched, which can easily cause problems such as bending of the lower electrode layer.

[0053] Thirdly, due to the unevenness of ion sputtering during the etching process, the upper part of the top silicon nitride carbide layer on the opening side will be etched more and the lower part will be etched less. Therefore, the top silicon nitride carbide layer is prone to bowl-shaped defects, which affects the supporting role of the top silicon nitride carbide layer on the lower electrode layer and the capacitor structure.

[0054] As can be seen from the above, on the one hand, it is difficult to balance the opening size of the top silicon carbide nitride layer and the problem of over-etching the sacrificial oxide layer. On the other hand, there is a problem that the support structure does not provide sufficient support for the lower electrode layer and the capacitor structure, which easily causes the capacitor structure to bend or tilt.

[0055] Based on this, the embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof. In the embodiment of the present disclosure, since the mask layer and the lower electrode contain the same material, not only can the bowl-shaped defect problem caused by the top support layer be improved, but also the high etching selectivity between the top support layer and the lower electrode can be used to ensure the high etching selectivity between the top support layer and the mask layer as the capacitor size continues to decrease and the capacitance density or height and the thickness of the top support layer continue to increase. Thus, a balance between the opening size (i.e., the critical size) of the support layer and the sacrificial layer residue can be achieved at the same time, thereby improving the reliability of the capacitor structure finally formed. In addition, since the mask layer and the lower electrode contain the same material, and the material of the lower electrode is usually a metal material with greater stress, the stress of the mask layer is also greater and the ability to resist deformation is stronger. In this way, the mask layer forms a strengthening layer, which increases the height and strength of the supporting layer, thereby improving the supporting effect on the capacitor structure. That is, the top support layer located between the multiple lower electrodes and protruding from the multiple lower electrodes, and the strengthening layer located on the top support layer can produce a better supporting effect on the lower electrode, so that the stability of the formed capacitor structure is enhanced. In addition, the mask layer and the lower electrode contain the same material, which can also avoid contamination of the lower electrode in the stacked structure during the process of patterning the initial top support layer based on the mask layer.

[0056] The semiconductor structure and the manufacturing method thereof in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0057] An embodiment of the present disclosure provides a method for preparing a semiconductor structure. Figure 1 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure is provided. Figures 2 to 22 This is a schematic diagram of the structure of the semiconductor structure provided in the embodiment of the present disclosure during the preparation process. Figures 1 to 22 The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0058] like Figure 1 As shown, the method for preparing a semiconductor structure includes the following steps 101 to 104:

[0059] First, please refer to Figure 2 , perform step 101, provide a substrate 30; and form a stacked structure 31 consisting of a plurality of initial support layers and a plurality of initial sacrificial layers alternating in a thickness direction of the substrate 30.

[0060] In some embodiments, step 101 may be implemented by the following steps:

[0061] Provide Figure 2 The base 30 is shown;

[0062] In some embodiments, the substrate 30 includes, but is not limited to, a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a semiconductor material substrate (such as a germanium silicon substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator substrate, etc.

[0063] It should be noted that the substrate 30 may further include a plurality of conductive pads (not shown) arranged in an array, and the initial lower electrode 32 formed subsequently is located above the conductive pads.

[0064] During implementation, support materials and sacrificial materials are alternately deposited on the surface of the substrate 30 along the thickness direction of the substrate 30 to form a Figure 2 The stacked structure 31 is formed by a first initial supporting layer 311 , a first initial sacrificial layer 312 , a second initial supporting layer 313 , a second initial sacrificial layer 314 , a third initial supporting layer 315 , a third initial sacrificial layer 316 and a fourth initial supporting layer 317 .

[0065] In the embodiment of the present disclosure, one or more deposition processes selected from physical vapor deposition, chemical vapor deposition, or atomic layer deposition can be used to form a first initial support layer 311, a first initial sacrificial layer 312, a second initial support layer 313, a second initial sacrificial layer 314, a third initial support layer 315, a third initial sacrificial layer 316, and a fourth initial support layer 317. The supporting materials used to form the first initial support layer 311, the second initial support layer 313, the third initial support layer 315, and the fourth initial support layer 317 include, but are not limited to, nitrides, such as SiCN and SIN. Due to the high hardness of SiCN, it can provide a good support for the subsequent initial lower electrode and capacitor structure. The sacrificial materials used to form the first initial sacrificial layer 312, the second initial sacrificial layer 314, and the third initial sacrificial layer 316 can include, but are not limited to, oxides, such as undoped silicon oxide, doped silicon oxide, such as borophosphosilicate glass (BPSG).

[0066] It should be noted that in the disclosed embodiment, the stacked structure 31 includes four supporting layers and three sacrificial layers. In other embodiments, the stacked structure 31 may include fewer or more supporting layers and sacrificial layers. The type and number of film layers included in the stacked structure 31 may vary depending on the height of the capacitor structure and are not specifically limited here.

[0067] Next, please refer to Figure 5 , execute step 102 to form a plurality of initial lower electrodes 32 arranged in an array; the plurality of initial lower electrodes 32 pass through the stacked structure 31 and contact the substrate 30; wherein the initial top support layer 319 of the top layer of the stacked structure 31 is located between the plurality of initial lower electrodes 32 and also located above the plurality of initial lower electrodes 32.

[0068] In some embodiments, please refer to Figures 3 to 5 , step 102 can be implemented by the following steps:

[0069] The stacked structure 31 is selectively etched to form a plurality of initial support layers and a plurality of initial sacrificial layers. Figure 3 The capacitor holes 321 shown in FIG. 3 are arranged in an array (eg, Figure 4 );

[0070] In some embodiments, the capacitor hole 321 may be formed by an anisotropic etching process, such as a plasma etching process.

[0071] Next, the following structures are formed in the plurality of capacitor holes 321: Figure 5 A plurality of initial lower electrodes 32 are shown;

[0072] Specifically, the initial lower electrode 32 can be formed by one or more deposition processes including physical vapor deposition, chemical vapor deposition or atomic layer deposition, wherein the material of the initial lower electrode 32 may include but is not limited to titanium nitride (TiN), titanium (Ti), tungsten nitride (WN), tungsten (W), platinum (Pt), silver (Ag), or palladium (Pd), for example, titanium nitride, which has good conductivity and low resistance, and can maintain an ideal etching selectivity ratio with silicon nitride during the etching process.

[0073] On the surfaces of the plurality of preliminary lower electrodes 32 and the fourth preliminary supporting layer 317, a Figure 5 The fifth initial support layer 318 shown, the fifth initial support layer 318 and the fourth initial support layer 317 together constitute the Figure 5 An initial top support layer 319 is shown.

[0074] In the embodiment of the present disclosure, the initial top supporting layer 319 is not only located between the initial lower electrodes 32 , but also located above the initial lower electrodes 32 , so that the initial top supporting layer 319 has a stronger supporting effect on the initial lower electrodes 32 .

[0075] In some embodiments, the fifth initial supporting layer 318 may be formed by one or more deposition processes including physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The material of the fifth initial supporting layer 318 may include, but is not limited to, SiCN.

[0076] In some embodiments, the material of the fifth initial supporting layer 318 may be the same as that of the fourth supporting layer 317 , so that the initial top supporting layer 319 can better support the initial bottom electrode 32 .

[0077] In some embodiments, a dimension of the fifth preliminary supporting layer 318 in the thickness direction of the substrate 30 is smaller than or equal to a dimension of the fourth preliminary supporting layer 317 in the thickness direction of the substrate 30 .

[0078] In the disclosed embodiment, since the subsequent etching of multiple support layers to form the opening does not use the fifth initial supporting layer 318 as a mask, but rather uses the subsequently formed mask layer 36 as a mask, the fifth initial supporting layer 318, protected by the subsequently formed mask layer 36, is not gradually consumed during etching. This allows for relatively precise control of the size of the fifth initial supporting layer 318 in the thickness direction of the substrate 30. Therefore, the size of the fifth initial supporting layer 318 in the thickness direction of the substrate 30 can be less than or equal to the size of the fourth initial supporting layer 317 in the thickness direction of the substrate 30. For example, the size of the fifth initial supporting layer 318 in the thickness direction of the substrate 30 can be less than or equal to 50 nm, and can be, for example, 45 nm, 40 nm, 30 nm, or 25 nm. This ensures that the fifth initial supporting layer 318 effectively supports the initial lower electrode 32 while also making it easier to open the initial top supporting layer 319 during the subsequent process of forming the opening therein, reducing process complexity and achieving a balance between the opening size and the extent of initial sacrificial layer removal.

[0079] In addition, the fifth initial supporting layer 318 can also insulate and isolate the initial lower electrode 32 from the subsequently formed mask layer 36 to avoid short circuit between the ultimately formed lower electrode 322 made of the same material.

[0080] Next, please refer to Figure 6 and Figure 7 , step 103 is performed to form a mask layer 36 above the initial top support layer 319 , where the mask layer 36 and the initial bottom electrode 32 contain the same material.

[0081] In the embodiment of the present disclosure, the mask layer 36 and the initial lower electrode 32 contain the same material, which can not only improve the bowl-shaped defect problem caused by the top initial top support layer 319, but also utilize the high etching selectivity between the initial top support layer 319 and the initial lower electrode 32. As the capacitor size continues to decrease, the capacitance density / height and the thickness of the top support layer continue to increase, the high etching selectivity between the initial top support layer 319 and the mask layer 36 can be guaranteed, thereby achieving a balance between the opening size of the initial top support layer 319 and the sacrificial layer residue, thereby improving the reliability of the capacitor structure finally formed. In addition, the mask layer 36 and the initial lower electrode 32 contain the same material, which can also avoid contamination of the initial lower electrode 32 located in the stacked structure 31 during the process of patterning the top initial support layer 319 based on the mask layer 36. Furthermore, the material of the initial lower electrode 32 is usually a metal material with high stress, so the stress of the mask layer 36 is also high and the ability to resist deformation is strong. In this way, the mask layer forms a strengthening layer, which increases the height and strength of the supporting layer, thereby improving the supporting effect on the capacitor structure. That is, the initial top supporting layer 319 located between the multiple initial lower electrodes 32 and protruding from the multiple initial lower electrodes 32 plus the strengthening layer located on the initial top supporting layer 319 can provide better support for the initial lower electrode 32, so that during the process, the stability of the initial lower electrode 32 is significantly enhanced, and the stability of the capacitor structure formed subsequently is enhanced.

[0082] In some embodiments, please refer to Figure 6 and Figure 7 Step 103 can be implemented by the following steps: the mask layer 36 can be a single layer or multiple layers, for example, multiple layers, and the following layers are sequentially formed on the initial top support layer 319: Figure 9 The first initial mask layer 361 and the second initial mask layer 362 are shown; the first initial mask layer 361 is made of the same material as the initial lower electrode 32, and the second initial mask layer 362 is made of the same material as the initial sacrificial layer;

[0083] In some embodiments, one or more deposition processes including physical vapor deposition, chemical vapor deposition, or atomic layer deposition can be used to form a first initial mask layer 361 and a second initial mask layer 362, wherein the first initial mask layer 361 is made of the same material as the initial lower electrode 32. Specifically, the electrode material is used as a hard mask material on the top support layer, so the deposition equipment for depositing the upper electrode of the capacitor can be used to deposit the mask material, thereby increasing the effective utilization of the equipment and avoiding contamination problems in subsequent processes.

[0084] The second initial mask layer 362 is made of the same material as the initial sacrificial layer, for example, an oxide. When the mask is made of titanium nitride, for example, it has excellent adhesion to the oxide, resulting in improved bonding between the first initial mask layer 361 and the second initial mask layer 362. Furthermore, the oxide layer acts as an anti-reflective layer, eliminating reflections from the exposure light source, preventing deformation or dimensional deviations in the photoresist pattern, and ensuring the correct transfer of the mask pattern. Furthermore, the first initial mask layer 361 can be deposited using the same equipment used to form the initial lower electrode 32, and the second initial mask layer 362 can be deposited using the same equipment used to form the initial sacrificial layer. This improves the effective utilization of the equipment.

[0085] In some embodiments, the thickness of the first initial mask layer 361 is less than or equal to 20 nm. For example, it can be 18 nm, 15 nm, 12 nm, or 10 nm. This avoids the problem of difficulty in opening the first initial mask layer 361 due to its excessive thickness during subsequent etching of the first initial mask layer 361 to form the first mask layer. In the disclosed embodiment, the formed first mask layer is located above the initial top support layer 319, which is equivalent to further increasing the height of the support layer, thereby ensuring better support for the initial lower electrode 32.

[0086] On the second preliminary mask layer 362, a Figure 6 The patterned photoresist layer 39 is formed, and the second initial mask layer 362 and the first initial mask layer 361 are sequentially etched through the patterned photoresist layer 39 to form a Figure 7 The second mask layer 38 and the first mask layer (ie, the strengthening layer 37 ) are shown, and the second mask layer 38 and the first mask layer constitute the mask layer 36 .

[0087] Of course, in some other embodiments, the mask layer 36 may be a single layer. When the mask 36 is a single layer, the first mask layer constitutes the mask layer 36 .

[0088] In some embodiments, the sequential etching of the second preliminary mask layer 362 and the first preliminary mask layer 361 may be performed using an anisotropic etching process, such as a plasma etching process.

[0089] In some embodiments, in the subsequent step of removing the initial sacrificial layer, the etching selectivity ratio between the second mask layer 38 and the first mask layer is greater than or equal to 20, for example, 22, 25, 30, or 35.

[0090] In the embodiment of the present disclosure, since the second mask layer 38 is made of the same material as the initial sacrificial layer, and the first mask layer is made of the same material as the initial lower electrode 32, in the step of removing the initial sacrificial layer, the etching selectivity ratio between the second mask layer 38 and the first mask layer is greater than or equal to 20. On the one hand, the second mask layer 38 is removed in the process of removing the initial sacrificial layer with little effect on the first mask layer, and multiple initial supporting layers can be patterned based on the first mask layer subsequently; on the other hand, the initial lower electrode 32 is affected very little in the process of removing the initial sacrificial layer.

[0091] Finally, please refer to Figure 8 and Figure 9 , perform step 104, pattern the initial top support layer 319 based on the mask layer 36 to form the following in the initial top support layer 319 Figure 8 The multiple openings 331 are shown, and the stacked structure 31 including the initial lower electrode is further etched along the multiple openings 331 to remove the multiple initial sacrificial layers; the remaining initial lower electrode structure 32 forms the lower electrode 322, the remaining mask layer 36 forms the strengthening layer 37, and the remaining initial supporting layer forms the supporting layer 33. The top supporting layer in the supporting layer 33 is located between the multiple lower electrodes 322 and protrudes from the multiple lower electrodes 322.

[0092] It should be noted that each opening 331 overlaps with at least one initial lower electrode 32. Figure 9 FIG. 3 is a top view along the top surface of the fourth initial supporting layer 317 .

[0093] In the embodiment of the present disclosure, a dry etching process, such as a plasma etching process, can be used to form the first openings 331. Each opening 331 overlaps with three initial lower electrodes 32. This allows the initial sacrificial layer to be removed more efficiently through the openings 331 while ensuring that the initial support layer provides sufficient support for the initial lower electrodes 32. It is understood that, depending on actual needs, the number of initial lower electrodes 32 overlapping with each opening 331 can also be other values, such as one, two, or four or more, and is not specifically limited here.

[0094] In some embodiments, in the step of patterning the initial top supporting layer 319 based on the mask layer 36, the etching selectivity ratio between the initial top supporting layer 319 and the mask layer 36 is greater than or equal to 15, for example, it can be 17, 20, 22 or 25.

[0095] In the embodiment of the present disclosure, the electrode material is used as the mask material throughout the process of etching the stacked structure. By increasing the etching selectivity of the mask layer 36 and the initial top support layer 319 during the etching process, not only can the bowl-shaped defect problem caused by the top initial top support layer 319 be improved, but also as the capacitor size continues to decrease and the capacitor density / height and the thickness of the top support layer continue to increase, the balance of the critical size, residual thickness and over-etching of the initial top support layer 319 can be achieved, thereby ensuring the control of the residual and critical sizes of the initial top support layer 319 and improving the reliability of the finally formed capacitor structure.

[0096] In some embodiments, in step 104 , the initial sacrificial layers may be removed by wet processing using a mixture of ammonium bifluoride, ammonium fluoride, and water.

[0097] Specifically, the third initial sacrificial layer 316 is removed through the first opening 331 (see Figure 10 );

[0098] It should be noted that when the third initial sacrificial layer 316 is removed, the second mask layer 38 is removed at the same time.

[0099] Based on the first mask layer, a second opening 332 is formed in the third initial supporting layer 315 to expose the second initial sacrificial layer 314 (see Figure 11 );

[0100] The second initial sacrificial layer 314 is removed through the second opening 332 (refer to Figure 12 );

[0101] Based on the first mask layer, a third opening 333 (refer to FIG. 3 ) is formed in the second preliminary supporting layer 313 to expose the first preliminary sacrificial layer 312. Figure 13 );

[0102] The first initial sacrificial layer 312 is removed through the third opening 333; the remaining initial lower electrode 32 constitutes the lower electrode 322, and the remaining initial support layer constitutes the support layer 33 (refer to Figure 14 ).

[0103] In the embodiment of the present disclosure, a dry etching process, such as a plasma etching process, can be used to form the second opening 332 and the third opening 333. The first initial sacrificial layer 312, the second initial sacrificial layer 314, and the third initial sacrificial layer 316 are removed by wet removal using a mixture of ammonium bifluoride, ammonium fluoride, and water (LAL solution). The mass percentages of ammonium bifluoride, ammonium fluoride, and water in the LAL solution are, for example, 8-12%: 9-15%: 73-83% respectively.

[0104] In the disclosed embodiment, after wet removal of the multiple initial sacrificial layers, no additional process is required to remove the first mask layer, thereby simplifying the process, reducing costs, and increasing yield. The first mask layer forms a strengthening layer 37, which also provides good support for the subsequently formed capacitor structure.

[0105] In some embodiments, please refer to Figure 15 The method for preparing the semiconductor structure further includes: forming a dielectric layer 323 along the plurality of openings on the surfaces of the lower electrode 322, the support layer 33, and the strengthening layer 37; forming an upper electrode 324 on the surface of the dielectric layer 323; and filling a filling layer 325 in the gaps between the upper electrodes 324.

[0106] In the embodiment of the present disclosure, one or more deposition processes including physical vapor deposition, chemical vapor deposition, or atomic layer deposition can be used to form the dielectric layer 323, the upper electrode 324, and the filling layer 325. The material of the dielectric layer 323 can include, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, zirconium oxide, or a combination thereof. The material of the upper electrode 324 can include, but is not limited to, titanium nitride (TiN), titanium (Ti), tungsten nitride (WN), tungsten (W), platinum (Pt), silver (Ag), or palladium (Pd). The material of the filling layer 325 can include, but is not limited to, polysilicon or silicon germanium. The lower electrode 322, the dielectric layer 323, the upper electrode 324, and the filling layer 325 together constitute a complete capacitor structure.

[0107] In some embodiments, as Figures 16 to 20 As shown, in the step of wet-processing the multiple initial sacrificial layers using a mixture of ammonium bifluoride, ammonium fluoride and water, a mixture of ammonia water, hydrogen peroxide and water (SC1) is used to etch the electrode material.

[0108] In some embodiments, please refer to Figures 16 to 21 , step 104 can be implemented by the following steps:

[0109] The third initial sacrificial layer 316 is removed through the first opening 331; and the initial lower electrode 32 located between the fourth initial support layer 317 and the third initial support layer 315 is partially etched simultaneously (see Figure 16 and Figure 17 ).

[0110] In the embodiment of the present disclosure, since the initial lower electrode 32 located between the fourth initial supporting layer 317 and the third initial supporting layer 315 is partially etched, the process window for subsequently etching the third initial supporting layer 315 to form the second opening 332 is increased, thereby reducing the difficulty of the process.

[0111] In some embodiments, please refer to Figure 16In the process of performing the above-mentioned step 104 of patterning the initial top supporting layer 319 based on the mask layer 36 to form multiple openings 331 in the initial top supporting layer 319, some impurities such as the mask layer material 362, such as titanium-based polymers, may remain on the sidewalls of the initial top supporting layer 319.

[0112] In the embodiment of the present disclosure, during the process of wet-etching the third initial sacrificial layer 316 using a mixed solution of LAL solution and SC1 solution, due to the isotropic characteristics of the wet etching process, the mask layer material 362 remaining on the sidewall of the initial top support layer 319 can be removed simultaneously during the wet etching (see Figure 17 ), thereby preventing the first mask layer and the initial lower electrode 32 from being short-circuited by the residual mask layer material 362. In addition, the side of the first mask layer exposed to the etching solution will also be partially etched, thereby pushing the first mask layer outward (please refer to Figure 17 ), thereby further reducing the risk of short circuit between the first mask layer and the initial lower electrode 32.

[0113] Based on the first mask layer, a second opening 332 is formed in the third initial supporting layer 315 to expose the second initial sacrificial layer 314 (see Figure 18 );

[0114] The second initial sacrificial layer 314 is removed through the second opening 332; and the initial lower electrode 32 located between the third initial support layer 315 and the second initial support layer 313 is partially etched simultaneously (see Figure 19 ).

[0115] In the embodiment of the present disclosure, since the initial lower electrode 32 located between the third initial supporting layer 315 and the second initial supporting layer 313 is partially etched, the process window for subsequently etching the second initial supporting layer 313 to form the third opening 333 is increased, thereby reducing the difficulty of the process.

[0116] Based on the first mask layer, a third opening 333 (refer to FIG. 3 ) is formed in the second preliminary supporting layer 313 to expose the first preliminary sacrificial layer 312. Figure 20 );

[0117] The first initial sacrificial layer 312 is removed through the third opening 333; and the initial lower electrode 32 located between the second initial support layer 313 and the first initial support layer 311 is partially etched simultaneously; the remaining initial lower electrode 32 constitutes the lower electrode 322, and the remaining initial support layer constitutes the support layer 33 (please refer to Figure 21 ).

[0118] In the embodiment of the present disclosure, a dry etching process, such as a plasma etching process, can be used to form the second opening 332 and the third opening 333. The steps of removing the first initial sacrificial layer 312, the second initial sacrificial layer 314, and the third initial sacrificial layer 316 are performed by wet removal using a LAL solution and an SC1 solution. The mass percentage ratios of ammonium bifluoride, ammonium fluoride, and water in the LAL solution are, for example, 8-12%:9-15%:73-83% respectively. The mass percentage ratios of ammonia water, hydrogen peroxide, and water in the SC1 solution can be, for example, 0.8-3%:3.2-10%:10-90%. In the embodiment of the present disclosure, SC1 (etching solution) is added during the wet removal of oxide to etch the electrode material, and the control of the wet etching time can greatly improve the size from the top to the bottom of the capacitor, while increasing the critical size in the subsequent capacitor etching process and increasing the process window for downward etching in the capacitor etching process. In addition, by adding SC1 (etching solution) to etch the electrode material during the wet removal of oxide, not only can impurities that may remain on the side walls of the top support layer be removed, but also because of the isotropic characteristics of wet etching, the mask material will be pushed outward, thereby reducing the risk of capacitor short circuit.

[0119] In the embodiment of the present disclosure, all the initial sacrificial layers are removed while the initial lower electrode 32 is partially etched. By controlling parameters such as the etching solution and etching time in the wet etching process, the size of the etched first initial electrode layer 32 from top to bottom can be better controlled, so that the morphology of the finally formed lower electrode 322 is better.

[0120] It should be noted that in the embodiment of the present disclosure, the capacitor hole can be made larger in the step of initially etching the stacked structure to form the capacitor hole, and then an initial lower electrode 32 with a larger size can be formed in the capacitor hole, so that after the initial lower electrode 32 is partially etched simultaneously during the removal of the initial sacrificial layer, the size of the formed lower electrode 322 can reach the expected target size.

[0121] In the disclosed embodiment, after wet removal of the multiple initial sacrificial layers, no additional process is required to remove the first mask layer and form the strengthening layer 37, thereby simplifying the process, reducing costs, and increasing production yields. The first mask layer also provides good support for the subsequently formed capacitor structure.

[0122] In some embodiments, please refer to Figure 22 The method for preparing the semiconductor structure further includes: forming a dielectric layer 323 along the plurality of openings on the surfaces of the lower electrode 322, the support layer 33, and the strengthening layer 37; forming an upper electrode 324 on the surface of the dielectric layer 323; and filling a filling layer 325 in the gaps between the upper electrodes 324.

[0123] It should be noted that the process of forming the dielectric layer 323, the upper electrode 324 and the filling layer 325 can be understood with reference to the above embodiment and will not be repeated here. The lower electrode 322, the dielectric layer 323, the upper electrode 324 and the filling layer 325 together constitute a complete capacitor structure.

[0124] In the disclosed embodiment, a metal hard mask (corresponding to the first mask layer described above) is used to increase the selectivity between the hard mask and silicon carbide (corresponding to the initial top support layer 319 described above), thereby improving the etching selectivity and achieving effective control of the remaining thickness of the top silicon carbide and the over-etching of the initial sacrificial layer in more advanced processes. The introduction of the metal hard mask also avoids the consumption of the top silicon carbide, thereby achieving precise control of the critical dimensions. In addition, the metal hard mask remains on the top support layer, which increases the strength of the support layer and its support for the capacitor, thereby improving the bending problem.

[0125] In another embodiment of the present disclosure, a semiconductor structure is provided. Figure 15 and Figure 22 , which shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 15 and Figure 22 As shown, the semiconductor structure includes:

[0126] A substrate 30 and a plurality of support layers 33 spaced apart along a thickness direction of the substrate 30;

[0127] A plurality of lower electrodes 322 arranged in an array, the plurality of lower electrodes 322 passing through the plurality of support layers 33 and contacting the substrate 30 , wherein a top support layer 330 of the plurality of support layers 33 is located between the plurality of lower electrodes 322 and protrudes from the plurality of lower electrodes 322 ;

[0128] The strengthening layer 37 is located on the top supporting layer 330 . The strengthening layer 37 and the bottom electrode 322 are made of the same material.

[0129] In the embodiment of the present disclosure, the strengthening layer 37 and the lower electrode 322 are made of the same material. The material of the lower electrode 322 is generally a metal material with high stress. Therefore, the stress of the strengthening layer 37 is also high and the deformation resistance is strong. In this way, the top support layer 330 located between the multiple lower electrodes 322 and protruding from the multiple lower electrodes 322, and the strengthening layer 37 located above the top support layer 330 can provide better support for the lower electrodes 322, thereby enhancing the stability of the formed capacitor structure. In actual processing, since the strengthening layer 37 and the lower electrode 322 are made of the same material, not only can the bowl-shaped defect problem caused by the top support layer 330 be improved, but also the high etching selectivity between the top support layer 330 and the lower electrode 322 can be maintained as the capacitor size continues to decrease and the capacitance density / height and the thickness of the top support layer 330 continue to increase. Thus, a balance can be achieved between the opening size of the top support layer 330 and the sacrificial layer residue, thereby improving the reliability of the final capacitor structure.

[0130] In some embodiments, the substrate 30 includes, but is not limited to, a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a semiconductor material substrate (such as a germanium silicon substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator substrate, etc.

[0131] It should be noted that the substrate 30 may further include a plurality of conductive pads (not shown) arranged in an array, and the lower electrode 322 is located above the conductive pads.

[0132] In some embodiments, the supporting material of the supporting layer 33 includes but is not limited to nitride, such as SiCN. Since SiCN material has a high hardness, the supporting layer 33 can provide good support for the lower electrode 322 and the capacitor structure.

[0133] It should be noted that, in the embodiment of the present disclosure, the support layer 33 has five layers. In other embodiments, the support layer 33 may also include fewer or more layers to effectively support a capacitor structure with a larger aspect ratio.

[0134] In some embodiments, the materials of the lower electrode 322 and the strengthening layer 37 may include but are not limited to titanium nitride (TiN), titanium (Ti), tungsten nitride (WN), tungsten (W), platinum (Pt), silver (Ag), or palladium (Pd).

[0135] In some embodiments, the lower electrode 322 is a cylindrical electrode or a columnar electrode.

[0136] In the embodiment of the present disclosure, the lower electrode 322 can be a tubular electrode or a columnar electrode. When the lower electrode 322 is a tubular electrode, a tubular capacitor can be formed subsequently, thereby increasing the capacitance value. When the lower electrode 322 is a columnar electrode, a columnar capacitor can be formed subsequently. Compared with a double-sided capacitor, the area of ​​the columnar capacitor is smaller, thereby increasing the integration and achieving miniaturization.

[0137] In some embodiments, please refer to Figure 15 and Figure 22 The semiconductor structure also includes: a dielectric layer 323, which is continuously located on the surfaces of multiple lower electrodes 322, multiple support layers 33, and the strengthening layer 37; an upper electrode 324, which is continuously located on the surface of the dielectric layer 323; and a filling layer 325, which fills the gaps between the upper electrodes 324.

[0138] In the disclosed embodiment, the material of dielectric layer 323 may include, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, zirconium oxide, or a combination thereof. The material of top electrode 324 may include, but is not limited to, titanium nitride (TiN), titanium (Ti), tungsten nitride (WN), tungsten (W), platinum (Pt), silver (Ag), or palladium (Pd). The material of filling layer 325 may include, but is not limited to, polysilicon. Bottom electrode 322, dielectric layer 323, top electrode 324, and filling layer 325 together form a complete capacitor structure.

[0139] In some embodiments, please refer to Figure 15 and Figure 22 In the top supporting layer 330 , the thickness of the first portion 341 protruding from the lower electrodes 322 is less than or equal to the thickness of the second portion 342 located between the lower electrodes 322 .

[0140] In the embodiment of the present disclosure, the thickness of the first portion 341 can be less than or equal to the thickness of the second portion 342. For example, the thickness of the first portion 341 is less than or equal to 50 nm, and can be, for example, 45 nm, 40 nm, 30 nm, or 25 nm. In this way, while ensuring that the first portion 341 can effectively support the lower electrode 322 and achieve insulation isolation between the lower electrode 322 and the strengthening layer 37, it also makes it easier to open the top supporting layer 330 during the process of forming the opening in the top supporting layer 330, reducing the process difficulty. In other words, a balance can be achieved between the opening size and the degree of removal of the initial sacrificial layer.

[0141] In some embodiments, the thickness of the strengthening layer 37 is less than or equal to 20 nm, for example, 18 nm, 15 nm, 12 nm, or 10 nm.

[0142] In some embodiments, please refer to Figure 22The projection of the strengthening layer 37 in the plane where the base 30 is located is located within the projection area of ​​the first portion 341 of the top support layer 330 in the plane where the base 30 is located.

[0143] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0144] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0145] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure consisting of a plurality of initial support layers and a plurality of initial sacrificial layers alternating in the thickness direction of the substrate; forming a plurality of initial lower electrodes arranged in an array; The plurality of initial lower electrodes pass through the stacked structure and contact the substrate; The stacked structure is formed, and the plurality of initial lower electrodes arranged in an array are formed, including: in the thickness direction of the substrate, overlappingly depositing a first initial supporting layer, a first initial sacrificial layer, a second initial supporting layer, a second initial sacrificial layer, a third initial supporting layer, a third initial sacrificial layer, and a fourth initial supporting layer to form the stacked structure; selectively etching the stacked structure to form a plurality of capacitor holes penetrating the plurality of initial supporting layers and the plurality of initial sacrificial layers, wherein the plurality of capacitor holes are arranged in an array; forming the plurality of initial lower electrodes in the plurality of capacitor holes; and forming a fifth initial supporting layer on the surfaces of the plurality of initial lower electrodes and the fourth initial supporting layer, wherein the fifth initial supporting layer and the fourth initial supporting layer together constitute an initial top supporting layer. forming a mask layer above the initial top supporting layer, wherein the mask layer and the initial bottom electrode comprise the same material; The initial top supporting layer is patterned based on the mask layer to form a plurality of openings in the initial top supporting layer, and the stacked structure including the initial lower electrodes is continuously etched along the plurality of openings to remove the plurality of initial sacrificial layers; the remaining initial lower electrodes constitute the lower electrodes, the remaining mask layers form the strengthening layers, and the remaining initial supporting layers constitute the supporting layers, wherein the top supporting layer in the supporting layers is located between the plurality of lower electrodes and protrudes from the plurality of lower electrodes.

2. The preparation method according to claim 1, characterized in that In the step of patterning the initial top supporting layer based on the mask layer, An etching selectivity ratio between the initial top supporting layer and the mask layer is greater than or equal to 15.

3. The preparation method according to claim 1, characterized in that The size of the fifth initial supporting layer in the thickness direction of the substrate is smaller than or equal to the size of the fourth initial supporting layer in the thickness direction of the substrate, and the size of the fifth initial supporting layer in the thickness direction of the substrate is smaller than or equal to 50 nm.

4. The preparation method according to any one of claims 1 to 3, characterized in that The mask layer is multi-layered, and forming the mask layer above the initial top supporting layer includes: forming a first initial mask layer and a second initial mask layer in sequence on the initial top supporting layer; the first initial mask layer is made of the same material as the initial bottom electrode, and the second initial mask layer is made of the same material as the initial sacrificial layer; A patterned photoresist layer is formed on the second initial mask layer, and the second initial mask layer and the first initial mask layer are sequentially etched through the patterned photoresist layer to form the mask layer.

5. The preparation method according to claim 4, characterized in that In the step of removing the initial sacrificial layer, An etching selectivity ratio between the first preliminary mask layer and the second preliminary mask layer is greater than or equal to 20.

6. The preparation method according to claim 4, characterized in that The thickness of the first initial mask layer is less than or equal to 20 nm.

7. The preparation method according to any one of claims 1 to 3, characterized in that In the step of continuing to etch the stacked structure including the initial lower electrode along the plurality of openings to remove the plurality of initial sacrificial layers, The multiple initial sacrificial layers are removed by a wet method using a mixture of ammonium bifluoride, ammonium fluoride and water.

8. The preparation method according to claim 7, characterized in that The step of removing the plurality of initial sacrificial layers by wet method using a mixture of ammonium bifluoride, ammonium fluoride and water further includes: Use a mixture of ammonia, hydrogen peroxide and water.

9. The preparation method according to claim 1, characterized in that Also includes: forming a dielectric layer along the plurality of openings on surfaces of the lower electrode, the support layer, and the strengthening layer; forming an upper electrode on a surface of the dielectric layer; as well as, A filling layer is filled in the gaps between the upper electrodes.

10. A semiconductor structure, characterized in that include: A substrate and a plurality of support layers spaced apart along a thickness direction of the substrate; a plurality of lower electrodes arranged in an array, the plurality of lower electrodes passing through the plurality of supporting layers and contacting the substrate; A strengthening layer is located on the top supporting layer, and the strengthening layer and the lower electrode contain the same material; the semiconductor structure is prepared by the preparation method according to any one of claims 1 to 9.

11. The semiconductor structure according to claim 10, wherein: The lower electrode is a cylindrical electrode or a columnar electrode.

12. The semiconductor structure according to claim 10, wherein: Also includes: a dielectric layer continuously disposed on surfaces of the plurality of lower electrodes, the plurality of support layers, and the strengthening layer; an upper electrode continuously disposed on the surface of the dielectric layer; as well as, The filling layer fills the gaps between the upper electrodes.

13. The semiconductor structure according to claim 10, wherein: In the top supporting layer, a thickness of a first portion protruding from the lower electrodes is less than or equal to a thickness of a second portion located between the lower electrodes, and a thickness of the first portion is less than or equal to 50 nm.

14. The semiconductor structure according to claim 10, wherein: The thickness of the strengthening layer is less than or equal to 20 nm.

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