Semiconductor structure and preparation method thereof
By forming grooves around the base of the semiconductor structure and building groove transistors therein, leakage current problems caused by size reduction in DRAM components are solved, and electrical characteristics and production efficiency are improved.
Patent Information
- Application Number
- CN202311065597.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-05
- Filing Date
- 2023-08-23
- Publication Date
- 2025-01-07
AI Technical Summary
As DRAM components shrink, the size and spacing of signal lines become smaller and smaller, and leakage current becomes a key issue, affecting electrical characteristics, quality and cost.
A semiconductor structure is designed in which a peripheral portion of the substrate forms grooves and a groove transistor is formed in these grooves, extending to the outer trench through a character line nitriding layer to form an outer trench transistor, improving channel length and width to reduce leakage current.
By reducing the size of the semiconductor structure and improving the design of groove transistors, leakage current is effectively reduced, electrical characteristics and production efficiency are improved.
Smart Images
Figure CN119277769A_ABST
Abstract
Description
Technical Field
[0001] This application claims priority to U.S. patent application No. 18 / 218,215 (i.e., the priority date is "July 5, 2023"), the contents of which are incorporated herein by reference in their entirety.
[0002] The present disclosure relates to a semiconductor structure and a method for preparing the same, and in particular to a semiconductor structure including a recessed transistor and a method for preparing the same. Background Art
[0003] Semiconductor structures are used in a variety of electronic applications, and the size of semiconductor structures continues to shrink to meet current application requirements. However, various problems arise during the process of shrinking the size and affect the final electrical characteristics, quality, cost and yield. A typical memory component (such as a dynamic random access memory (DRAM) component) includes signal lines, such as word lines and bit lines that intersect the word lines. As DRAM components shrink, the size and / or spacing of the signal lines become smaller and smaller, and leakage current will become a critical issue.
[0004] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention
[0005] One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a component and at least one recessed transistor. The component includes a substrate and a plurality of word lines. The substrate includes an array portion and a peripheral portion surrounding the array portion. The plurality of word lines are disposed in the array portion. The peripheral portion is free of word lines. The peripheral portion of the substrate defines at least one recessed groove. The at least one recessed transistor is disposed in the at least one recessed groove of the peripheral portion of the substrate.
[0006] Another aspect of the present disclosure provides a method for preparing a semiconductor structure. The method includes: providing a component, wherein the component includes a substrate and a plurality of word lines, the substrate includes an array portion and a peripheral portion surrounding the array portion, the plurality of word lines are arranged in the array portion, and the peripheral portion has no word lines; forming at least one groove in the peripheral portion of the substrate; and forming at least one groove transistor in the at least one groove in the peripheral portion of the substrate.
[0007] Another aspect of the present disclosure provides a method for preparing a semiconductor structure. The method includes: providing a device, wherein the device includes a substrate, a plurality of word lines, and a word line nitride layer, wherein the word line nitride layer covers a top surface of the substrate and extends to the plurality of word lines; forming at least one outer trench extending through the word line nitride layer and extending to the substrate; and forming at least one recessed transistor in the at least one outer trench.
[0008] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purposes as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] A more complete understanding of the disclosure of this application may be obtained when referring to the detailed description and claims taken in conjunction with the drawings, and:
[0010] Figure 1 is a cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.
[0011] Figure 2 is a cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.
[0012] Figure 3 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0013] Figure 4 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0014] Figure 5 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0015] Figure 6 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0016] Figure 7 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0017] Figure 8is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0018] Fig. 9 2 is a cross-sectional view illustrating one or more stages of a method for preparing a semiconductor structure according to some embodiments of the present disclosure.
[0019] Fig.10 2 is a cross-sectional view illustrating one or more stages of a method for preparing a semiconductor structure according to some embodiments of the present disclosure.
[0020] Fig.11 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0021] Fig.12 2 is a cross-sectional view illustrating one or more stages of a method for preparing a semiconductor structure according to some embodiments of the present disclosure.
[0022] Fig.13 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0023] Fig.14 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0024] Fig.15 is a cross-sectional view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.
[0025] Fig.16 is a flow chart illustrating a method for preparing a semiconductor structure according to some embodiments of the present disclosure.
[0026] The reference numerals are described as follows:
[0027] 1: Character line
[0028] 1a: First character line
[0029] 1b: Second character line
[0030] 4: Base
[0031] 5: Groove transistor
[0032] 5a: First groove transistor
[0033] 5b: Second groove transistor
[0034] 7: Semiconductor structure
[0035] 7': Component
[0036] 7a: Semiconductor Structure
[0037] 41: Array part
[0038] 42: Peripheral part
[0039] 43: First Surface
[0040] 44: Outer groove
[0041] 44a: First outer groove
[0042] 44b: Second outer groove
[0043] 45: Groove
[0044] 45a: First groove
[0045] 45b: Second groove
[0046] 46: Isolation materials
[0047] 47: Groove
[0048] 47a: First groove
[0049] 47b: Second groove
[0050] 51: Insulation layer
[0051] 51a: First insulation layer
[0052] 51b: Second insulation layer
[0053] 52: Gate conductor
[0054] 52a: First gate conductor
[0055] 52b: Second gate conductor
[0056] 53: Polysilicon layer
[0057] 53a: first polysilicon layer
[0058] 53b: Second polysilicon layer
[0059] 61: Overlay
[0060] 62: Isolation layer
[0061] 63: Conductive materials
[0062] 63a: first conductive material
[0063] 63b: Second conductive material
[0064] 64: Polysilicon layer
[0065] 64a: first polysilicon layer
[0066] 64b: second polysilicon layer
[0067] 65: Character line nitride layer
[0068] 65a: Part I
[0069] 65b: Part 2
[0070] 72: Shallow Trench Isolation (STI)
[0071] 80: Mask layer
[0072] 82: Photoresist layer
[0073] 84: Sacrificial Layer
[0074] 461: Accommodating groove
[0075] 521: First Surface
[0076] 522: Bottom
[0077] 611: First surface
[0078] 613: Opening
[0079] 621: First Surface
[0080] 623: Opening
[0081] 651: Opening
[0082] 651a: First opening
[0083] 651b: Second opening
[0084] 653: First Surface
[0085] 821: The remainder
[0086] 8211: Top
[0087] 821a: First remainder
[0088] 821b: Second remainder
[0089] 841: Top
[0090] 843: Opening
[0091] 843a: First opening
[0092] 843b: Second opening 900: Preparation method S901: Step S902: Step S903: Step
[0093] W1: Width
[0094] W2: Width DETAILED DESCRIPTION
[0095] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally be done by one of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numerals.
[0096] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers or parts, these elements, components, regions, layers or parts are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part without departing from the teaching of the concept of the present invention.
[0097] The terms used herein are only used to describe specific embodiments and are not intended to be limited to the concepts of the present invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly indicates. It should be further understood that the terms "comprise" and "include", when used in this specification, indicate the presence of the features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.
[0098] Figure 1 2 is a cross-sectional view illustrating a semiconductor structure 7 of some embodiments of the present disclosure. In some embodiments, the semiconductor structure 7 may be a semiconductor element including a circuit such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).
[0099] In addition, the semiconductor structure 7 can be or include a part of an integrated circuit (IC) chip, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable integrated circuit components, or combinations thereof.
[0100] The semiconductor structure 7 may include an element 7' and at least one recessed transistor 5. The element 7' may include a substrate 4, a plurality of word lines 1, a capping layer 61, an isolation layer 62, a conductive material 63, a polysilicon layer 64, and a word line nitride layer 65. The substrate 4 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.
[0101] In some embodiments, Figure 1 As shown, the substrate 4 may have a first surface 43 (e.g., a top surface). The substrate 4 may include an array portion 41 (or an array region) and a peripheral portion 42 (or a peripheral region) surrounding the array portion 41. The word lines 1 are arranged in the array portion 41, and the peripheral portion 42 does not have word lines 1. That is, the array portion 41 includes all word lines 1 that can be arranged in an array. The peripheral portion 42 does not include the word lines 1. The peripheral portion 42 may be an area outside the word line 1 distribution area.
[0102] The substrate 4 may define a plurality of grooves 45 and at least one recess 47. The grooves 45 and the at least one recess 47 are recessed from the first surface 43 of the substrate 4. The grooves 45 may be located within the array portion 41. The recess 47 may be located in the peripheral portion 42 and outside the array portion 41. Therefore, the array portion 41 of the substrate 4 may define the grooves 45, and the peripheral portion 42 of the substrate 4 may define the recess 47.
[0103] The trench 45 may include a plurality of first trenches 45a and a plurality of second trenches 45b. The depth of the first trench 45a may be greater than the depth of the second trench 45b. The isolation material 46 may be disposed in the first trench 45a and may define a receiving trench 461. In some embodiments, the isolation material 46 may include an oxide or the like and may be embedded in the substrate 4.
[0104] The capping layer 61 may be disposed on the first surface 43 of the substrate 4 and may cover the first surface 43. In some embodiments, the capping layer 61 may include nitride, etc. The capping layer 61 may have a first surface 611 (e.g., a top surface). The capping layer 61 may define a plurality of openings 613 to expose the second trench 45b, the receiving trench 461, and the at least one recess 47.
[0105] The isolation layer 62 may be disposed on the first surface 611 of the cover layer 61 and may cover the first surface 611. In some embodiments, the isolation layer 62 may include, for example, an oxide. The isolation layer 62 may have a first surface 621 (e.g., a top surface). The isolation layer 62 may define a plurality of openings 623 to expose at least one recess 47. In addition, the isolation layer 62 may extend into the second trench 45b and the receiving trench 461. Therefore, the isolation layer 62 may be disposed on the sidewalls of the second trench 45b and the sidewalls of the receiving trench 461.
[0106] In some embodiments, the conductive material 63 may be a metal material, etc. The metal material may include tungsten, etc. The conductive material 63 may include a first conductive material 63a and a second conductive material 63b. The first conductive material 63a may be disposed on the isolation layer 62 in the receiving groove 461. The second conductive material 63b may be disposed on the isolation layer 62 in the second groove 45b.
[0107] In some embodiments, the polysilicon layer 64 may include a first polysilicon layer 64a and a second polysilicon layer 64b. The first polysilicon layer 64a may be disposed on the first conductive material 63a in the receiving groove 461. The second polysilicon layer 64b may be disposed on the second conductive material 63b in the second groove 45b. Figure 1 As shown, the thickness of the first polysilicon layer 64a may be substantially equal to the thickness of the second polysilicon layer 64b. The elevation of the first polysilicon layer 64a may be the same as the elevation of the second polysilicon layer 64b. In some embodiments, the thickness of the first polysilicon layer 64a may be less than the thickness of the first conductive material 63a. The thickness of the second polysilicon layer 64b may be less than the thickness of the second conductive material 63b.
[0108] The wordline nitride layer 65 may be disposed on the first surface 621 of the isolation layer 62 and may cover the first surface 621 of the isolation layer 62. Therefore, the wordline nitride layer 65 may cover the array portion 41 and the peripheral portion 42 (e.g., the first surface 43 of the substrate 4). The wordline nitride layer 65 may have a first surface 653 (e.g., a top surface). The wordline nitride layer 65 may define a plurality of openings 651 to expose at least one recess 47. In addition, the wordline nitride layer 65 may extend into the second trench 45b and the receiving trench 461. For example, the first portion 65a of the wordline nitride layer 65 may extend into the receiving trench 461 to contact the first polysilicon layer 64a. The second portion 65b of the wordline nitride layer 65 may extend into the second trench 45b to contact the second polysilicon layer 64b.
[0109] like Figure 1 As shown, the word line 1 may include a plurality of first word lines 1a and a plurality of second word lines 1b. The first word line 1a may be disposed in the receiving groove 461 and may include a first conductive material 63a, a first polysilicon layer 64a, and a first portion 65a of a word line nitride layer 65. The second word line 1b may be disposed in the second groove 45b and may include a second conductive material 63b, a second polysilicon layer 64b, and a second portion 65b of a word line nitride layer 65. The word line nitride layer 65 may extend to the word line 1. For example, the first portion 65a of the word line nitride layer 65 may extend to the first word line 1a. The second portion 65b of the word line nitride layer 65 may extend into the second word line 1b.
[0110] The at least one groove 47 of the peripheral portion 42 of the base 4 may include a plurality of grooves 47. Figure 1 As shown, the groove 47 may include at least one first groove 47a and at least one second groove 47b. The width W1 of the first groove 47a may be different from the width W2 of the second groove 47b. For example, the width W1 of the first groove 47a may be smaller than the width W2 of the second groove 47b.
[0111] In addition, the wordline nitride layer 65 may define at least one opening 651 corresponding to the at least one groove 47 of the peripheral portion 42. The opening 651 may extend through the wordline nitride layer 65 and may include a first opening 651a and a second opening 651b. The first opening 651a may correspond to the first groove 47a, and the second opening 651b may correspond to the second groove 47b. In some embodiments, the opening 651 of the wordline nitride layer 65, the groove 47 of the peripheral portion 42, the opening 613 of the cover layer 61, and the opening 623 of the isolation layer 62 may collectively form at least one outer trench 44 recessed from the first surface 653 of the wordline nitride layer 65. The outer trench 44 may include a first outer trench 44a and a second outer trench 44b. For example, the first opening 651a, the first groove 47a, the opening 613 of the cover layer 61, and the opening 623 of the isolation layer 62 may collectively form a first outer trench 44a recessed from the first surface 653 of the wordline nitride layer 65. Furthermore, the second opening 651 b , the second recess 47 b , the opening 613 of the capping layer 61 , and the opening 623 of the isolation layer 62 may collectively form a second outer trench 44 b recessed from the first surface 653 of the word line nitride layer 65 .
[0112] The recess transistor 5 may be disposed in the outer trench 44. Therefore, the recess transistor 5 may be disposed in the peripheral portion 42 of the substrate 4. The recess transistor 5 may include an insulating layer 51, a polysilicon layer 53, and a gate conductor 52. The insulating layer 51 may be disposed on the sidewalls of the outer trench 44. The polysilicon layer 53 may be disposed on the insulating layer 51 in the recess 47 of the peripheral portion 42 of the substrate 4. Therefore, the insulating layer 51 may be disposed between the polysilicon layer 53 and the peripheral portion 42 of the substrate 4. The gate conductor 52 may be disposed on the polysilicon layer 53 and the insulating layer 51. Therefore, the gate conductor 52 may be disposed in the opening 651 of the word line nitride layer 65. The insulating layer 51 may be disposed between the gate conductor 52 and the word line nitride layer 65. Therefore, the recess transistor 5 may be disposed in the recess 47 of the peripheral portion 42 of the substrate 4 and the opening 651 of the word line nitride layer 65.
[0113] like Figure 1 As shown, the bottom surface 522 of the gate conductor 52 may be higher than the first surface 43 (e.g., the top surface) of the substrate 4. In some embodiments, the bottom surface 522 of the gate conductor 52 may be higher than the first surface 611 (e.g., the top surface) of the capping layer 61. The bottom surface 522 of the gate conductor 52 may be lower than the first surface 621 (e.g., the top surface) of the isolation layer 62. In addition, the top surface 521 of the gate conductor 52 may be lower than the first surface 653 (e.g., the top surface) of the word line nitride layer 65, and may be higher than the first surface 621 (e.g., the top surface) of the isolation layer 62.
[0114] In some embodiments, the insulating layer 51 may include a first insulating layer 51a and a second insulating layer 51b. The polysilicon layer 53 may include a first polysilicon layer 53a and a second polysilicon layer 53b. The gate conductor 52 may include a first gate conductor 52a and a second gate conductor 52b. The first insulating layer 51a may be disposed on the sidewall of the first outer trench 44a. The first polysilicon layer 53a may be disposed on the first insulating layer 51a in the first groove 47a of the peripheral portion 42 of the substrate 4. Therefore, the first insulating layer 51a may be disposed between the first polysilicon layer 53a and the peripheral portion 42 of the substrate 4. The first gate conductor 52a may be disposed on the first polysilicon layer 53a and the first insulating layer 51a. Therefore, the first gate conductor 52a may be disposed in the first opening 651a of the word line nitride layer 65. The first insulating layer 51a may be disposed between the first gate conductor 52a and the word line nitride layer 65. The first insulating layer 51a, the first polysilicon layer 53a, and the first gate conductor 52a may together form a first recess transistor 5a. The first recess transistor 5a may be disposed in the first outer trench 44a and may have a width W1.
[0115] The second insulating layer 51b may be disposed on the sidewall of the second outer trench 44b. The second polysilicon layer 53b may be disposed on the second insulating layer 51b in the second groove 47b of the peripheral portion 42 of the substrate 4. Therefore, the second insulating layer 51b may be disposed between the second polysilicon layer 53b and the peripheral portion 42 of the substrate 4. The second gate conductor 52b may be disposed on the second polysilicon layer 53b and the second insulating layer 51b. Therefore, the second gate conductor 52b may be disposed in the second opening 651b of the word line nitride layer 65. The second insulating layer 51b may be disposed between the second gate conductor 52b and the word line nitride layer 65. The second insulating layer 51b, the second polysilicon layer 53b and the second gate conductor 52b may together form a second groove transistor 5b. The second groove transistor 5b may be disposed in the second outer trench 44b and may have a width W2. Therefore, the groove transistor 5 may include a plurality of groove transistors 5a, 5b having different widths W1, W2.
[0116] exist Figure 1 In the illustrated embodiment, the groove transistor 5 (e.g., including the first groove transistor 5a and the second groove transistor 5b) is recessed from the first surface 653 (e.g., the top surface) of the word line nitride layer 65, so the size (e.g., thickness) of the semiconductor structure 7 can be reduced. In addition, since the channel length of the groove transistor 5 (e.g., including the first groove transistor 5a and the second groove transistor 5b) is relatively long, the groove transistor 5 (e.g., including the first groove transistor 5a and the second groove transistor 5b) can improve the leakage problem. In addition, the widths W1 and W2 of the groove transistor 5 (e.g., including the first groove transistor 5a and the second groove transistor 5b) can be reduced.
[0117] Figure 2 FIG. 1 is a cross-sectional view illustrating a semiconductor structure 7a according to some embodiments of the present disclosure. The semiconductor structure 7a may be similar to Figure 1 The semiconductor structure 7 may further include at least one shallow trench isolation (STI) 72 .
[0118] like Figure 2 As shown, the semiconductor structure 7a further includes a plurality of STIs 72 embedded in the substrate 4. The top surface of the STI 72 may be substantially coplanar with the first surface 43 of the substrate 4. The STI 72 may be disposed between the recess transistors 5 (e.g., including the first recess transistor 5a and the second recess transistor 5b) to provide isolation between the recess transistors 5.
[0119] Figures 3 to 15 The method for preparing the semiconductor structure 7 according to some embodiments of the present disclosure is illustrated. Figure 3 , providing element 7'. Figure 3 The element 7' can be connected with Figure 1 The elements 7' are the same or similar.
[0120] The element 7' may include a substrate 4, a plurality of word lines 1, a capping layer 61, an isolation layer 62, a conductive material 63, a polysilicon layer 64, and a word line nitride layer 65. The substrate 4 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other IV-IV, III-V, or II-VI semiconductor materials.
[0121] The substrate 4 may have a first surface 43 (e.g., a top surface). The substrate 4 may include an array portion 41 (or an array region) and a peripheral portion 42 (or a peripheral region) surrounding the array portion 41. The word lines 1 are disposed in the array portion 41, and the peripheral portion 42 has no word lines 1. That is, the array portion 41 includes all word lines 1 that can be arranged in an array. The peripheral portion 42 does not include the word lines 1. The peripheral portion 42 may be a region outside the word line 1 distribution region.
[0122] The substrate 4 may define a plurality of grooves 45. The grooves 45 are recessed from the first surface 43 of the substrate 4. The grooves 45 may be located within the array portion 41. Therefore, the array portion 41 of the substrate 4 may define the grooves 45. The grooves 45 may include a plurality of first grooves 45a and a plurality of second grooves 45b. The depth of the first grooves 45a may be greater than the depth of the second grooves 45b. The isolation material 46 may be disposed in the first grooves 45a and may define a receiving groove 461. In some embodiments, the isolation material 46 may include an oxide or the like and may be embedded in the substrate 4.
[0123] The capping layer 61 may be disposed on the first surface 43 of the substrate 4 and may cover the first surface 43. In some embodiments, the capping layer 61 may include nitride, etc. The capping layer 61 may have a first surface 611 (eg, a top surface). The capping layer 61 may define a plurality of openings 613 to expose the second trench 45b and the receiving trench 461.
[0124] The isolation layer 62 may be disposed on the first surface 611 of the cover layer 61 and may cover the first surface 611. In some embodiments, the isolation layer 62 may include an oxide or the like. The isolation layer 62 may have a first surface 621 (e.g., a top surface). In addition, the isolation layer 62 may extend into the second trench 45b and the receiving trench 461. Therefore, the isolation layer 62 may be disposed on the sidewalls of the second trench 45b and the sidewalls of the receiving trench 461.
[0125] In some embodiments, the conductive material 63 may be a metal material, etc. The metal material may include tungsten, etc. The conductive material 63 may include a first conductive material 63a and a second conductive material 63b. The first conductive material 63a may be disposed on the isolation layer 62 in the receiving groove 461. The second conductive material 63b may be disposed on the isolation layer 62 in the second groove 45b.
[0126] In some embodiments, the polysilicon layer 64 may include a first polysilicon layer 64a and a second polysilicon layer 64b. The first polysilicon layer 64a may be disposed on the first conductive material 63a in the receiving trench 461. The second polysilicon layer 64b may be disposed on the second conductive material 63b in the second trench 45b.
[0127] The word line nitride layer 65 may be disposed on the first surface 621 of the isolation layer 62 and may cover the first surface 621 of the isolation layer 62. Therefore, the word line nitride layer 65 may cover the array portion 41 and the peripheral portion 42 (e.g., the first surface 43 (e.g., the top surface) of the substrate 4). The word line nitride layer 65 may have a first surface 653 (e.g., the top surface). In addition, the word line nitride layer 65 may extend into the second trench 45b and the receiving trench 461. For example, the first portion 65a of the word line nitride layer 65 may extend into the receiving trench 461 to contact the first polysilicon layer 64a. The second portion 65b of the word line nitride layer 65 may extend into the second trench 45b to contact the second polysilicon layer 64b.
[0128] like Figure 3As shown, the word line 1 may include a plurality of first word lines 1a and a plurality of second word lines 1b. The first word line 1a may be disposed in the receiving groove 461 and may include a first conductive material 63a, a first polysilicon layer 64a, and a first portion 65a of a word line nitride layer 65. The second word line 1b may be disposed in the second groove 45b and may include a second conductive material 63b, a second polysilicon layer 64b, and a second portion 65b of a word line nitride layer 65. The word line nitride layer 65 may extend to the word line 1. For example, the first portion 65a of the word line nitride layer 65 may extend to the first word line 1a. The second portion 65b of the word line nitride layer 65 may extend into the second word line 1b.
[0129] Reference Figure 4 The mask layer (e.g., hard mask) 80 may be formed or disposed on the first surface 653 (e.g., top surface) of the word line nitride layer 65 by, for example, deposition. Alternatively, the mask layer (e.g., hard mask) 80 may be formed or disposed on the array portion 41 and the peripheral portion 42 of the substrate 4 (e.g., the first surface 43 of the substrate 4).
[0130] Reference Figure 5 , a photoresist layer 82 may be formed or disposed on the mask layer 80 .
[0131] Reference Figure 6 , the photoresist layer 82 may be patterned to include a plurality of remaining portions 821 spaced apart from each other. For example, the remaining portion 821 may include a first remaining portion 821a and a second remaining portion 821b spaced apart from each other. In some embodiments, the remaining portion 821 may be trimmed. Each remaining portion 821 may have a top surface 8211.
[0132] Reference Figure 7 , a sacrificial layer 84 may be formed or disposed on the mask layer 80 to cover the remaining portion 821 of the patterned photoresist layer 82. The sacrificial layer 84 may include an oxide, and its manufacturing technology may include deposition, etc. In some embodiments, the thickness of the sacrificial layer 84 may be greater than the thickness of the patterned photoresist layer 82. Therefore, the sacrificial layer 84 may cover a plurality of top surfaces 8211 of the remaining portion 821 of the patterned photoresist layer 82.
[0133] Reference Figure 8 The sacrificial layer 84 may be thinned to expose the top surface 8211 of the remaining portion 821 of the patterned photoresist layer 82 by, for example, etching. Meanwhile, the top surface 841 of the sacrificial layer 84 may be substantially coplanar with the top surface 8211 of the remaining portion 821 of the patterned photoresist layer 82.
[0134] Reference Fig. 9, the remaining portion 821 of the patterned photoresist layer 82 can be removed by, for example, stripping, thereby forming a plurality of openings 843 in the sacrificial layer 84. The size and position of the openings 843 of the sacrificial layer 84 can correspond to the size and position of the remaining portion 821 of the patterned photoresist layer 82. For example, the openings 843 of the sacrificial layer 84 can include a first opening 843a corresponding to the first remaining portion 821a and a second opening 843b corresponding to the second remaining portion 821b. In addition, the openings 843 of the sacrificial layer 84 (for example, including the first opening 843a and the second opening 843b) expose a portion of the mask layer 80.
[0135] Reference Fig.10 , portions of the word line nitride layer 65, portions of the isolation layer 62, portions of the cover layer 61, and portions of the peripheral portion 42 may be removed simultaneously to form a plurality of outer trenches 44 according to the openings 843 of the sacrificial layer 84. The outer trenches 44 may extend through the word line nitride layer 65, the isolation layer 62, and the cover layer 61, and extend to the peripheral portion 42 of the substrate 4. For example, the outer trenches 44 may include a first outer trench 44a corresponding to the first opening 843a and a second outer trench 44b corresponding to the second opening 843b.
[0136] Reference Fig.11 , the sacrificial layer 84 and the mask layer 80 can be removed. Fig.11 As shown, the first outer trench 44a may be recessed from the first surface 653 of the wordline nitride layer 65, and may include a first opening 651a of the wordline nitride layer 65, a first recess 47a of the peripheral portion 42, an opening 613 of the cover layer 61, and an opening 623 of the isolation layer 62. The second outer trench 44b may be recessed from the first surface 653 of the wordline nitride layer 65, and may include a second opening 651b of the wordline nitride layer 65, a second recess 47b of the peripheral portion 42, an opening 613 of the cover layer 61, and an opening 623 of the isolation layer 62. Thus, the recess 47 (e.g., including the first recess 47a and the second recess 47b) may be formed in the peripheral portion 42 of the substrate 4.
[0137] Reference Figures 12 to 15 , the recessed transistor 5 may be formed in the outer trench 44 and in the recessed groove 47 of the peripheral portion 42 of the substrate 4. Fig.12 , the insulating layer 51 may be formed or disposed on the sidewalls of the outer trench 44. Alternatively, the insulating layer 51 may be formed or disposed on the sidewalls of the recess 47, the sidewalls of the opening 613 of the capping layer 61, the sidewalls of the opening 623 of the isolation layer 62, and the sidewalls of the opening 651 of the word line nitride layer 65.
[0138] For example, the insulating layer 51 may include a first insulating layer 51a and a second insulating layer 51b. The first insulating layer 51a may be disposed on the sidewall of the first outer trench 44a. That is, the first insulating layer 51a may be disposed on the sidewall of the first recess 47a of the peripheral portion 42 and on the sidewall of the first opening 651a of the word line nitride layer 65. In addition, the second insulating layer 51b may be disposed on the sidewall of the second outer trench 44b. That is, the second insulating layer 51b may be disposed on the sidewall of the second recess 47b of the peripheral portion 42 and on the sidewall of the second opening 651b of the word line nitride layer 65.
[0139] Reference Fig.13 The polysilicon layer 53 may be formed or disposed on the first surface 653 of the word line nitride layer 65 (i.e., on the first surface 43 (e.g., the top surface) of the substrate 4), and may be deposited to fill the outer trench 44. Thus, the polysilicon layer 53 may be formed or disposed on the insulating layer 51 in the outer trench 44 and in the recess 47 of the peripheral portion 42.
[0140] Reference Fig.14 , a portion of the polysilicon layer 53 disposed on the first surface 653 of the wordline nitride layer 65 (i.e., disposed on the first surface 43 (e.g., top surface) of the substrate 4) can be removed by, for example, etching. In some embodiments, the upper portion of the polysilicon layer 53 disposed in the outer trench 44 can also be removed. Therefore, the upper surface of the polysilicon layer 53 can be lower than the first surface 653 (e.g., top surface) of the wordline nitride layer 65. In some embodiments, the top surface of the polysilicon layer 53 can be lower than the first surface 621 (e.g., top surface) of the isolation layer 62. The top surface of the polysilicon layer 53 can be higher than the first surface 43 (e.g., top surface) of the substrate 4. The top surface of the polysilicon layer 53 can be higher than the first surface 611 (e.g., top surface) of the capping layer 61.
[0141] Meanwhile, the polysilicon layer 53 may include a first polysilicon layer 53a and a second polysilicon layer 53b spaced apart from each other. The first polysilicon layer 53a may be disposed on the first insulating layer 51a in the first groove 47a of the peripheral portion 42 of the substrate 4. Therefore, the first insulating layer 51a may be disposed between the first polysilicon layer 53a and the peripheral portion 42 of the substrate 4. The second polysilicon layer 53b may be disposed on the second insulating layer 51b in the second groove 47b of the peripheral portion 42 of the substrate 4. Therefore, the second insulating layer 51b may be disposed between the second polysilicon layer 53b and the peripheral portion 42 of the substrate 4.
[0142] Reference Fig.15The gate conductor 52 may be formed or disposed on the first surface 653 of the word line nitride layer 65 (i.e., on the first surface 43 (e.g., the top surface) of the substrate 4), and may be deposited to fill the outer trench 44. Thus, the gate conductor 52 may be formed or disposed on the polysilicon layer 53 in the outer trench 44 and in the recess 47 of the peripheral portion 42.
[0143] Reference Figure 1 , the portion of the gate conductor 52 disposed on the first surface 653 of the word line nitride layer 65 (i.e., the portion disposed on the first surface 43 (e.g., the top surface) of the substrate 4) can be removed by, for example, etching. In some embodiments, the upper portion of the gate conductor 52 disposed in the outer trench 44 can also be removed. Therefore, the first surface 521 (e.g., the top surface) of the gate conductor 52 can be lower than the first surface 653 (e.g., the top surface) of the word line nitride layer 65. In some embodiments, the first surface 521 (e.g., the top surface) of the gate conductor 52 can be higher than the first surface 621 (e.g., the top surface) of the isolation layer 62. In addition, the bottom surface 522 of the gate conductor 52 can be higher than the first surface 43 (e.g., the top surface) of the substrate 4. In some embodiments, the bottom surface 522 of the gate conductor 52 can be higher than the first surface 611 (e.g., the top surface) of the capping layer 61. The bottom surface 522 of the gate conductor 52 can be lower than the first surface 621 (e.g., the top surface) of the isolation layer 62. The insulating layer 51 , the polysilicon layer 53 and the gate conductor 52 may together form a recessed transistor 5 disposed in the outer trench 44 .
[0144] Meanwhile, the gate conductor 52 may include a first gate conductor 52a and a second gate conductor 52b spaced apart from each other. The first gate conductor 52a may be disposed on the first polysilicon layer 53a and the first insulating layer 51a. Therefore, the first gate conductor 52a may be disposed in the first opening 651a of the word line nitride layer 65. The first insulating layer 51a may be disposed between the first gate conductor 52a and the word line nitride layer 65. The first insulating layer 51a, the first polysilicon layer 53a, and the first gate conductor 52a may together form a first recessed transistor 5a. The first recessed transistor 5a may be disposed in the first outer trench 44a.
[0145] The second gate conductor 52b may be disposed on the second polysilicon layer 53b and the second insulating layer 51b. Therefore, the second gate conductor 52b may be disposed in the second opening 651b of the word line nitride layer 65. The second insulating layer 51b may be disposed between the second gate conductor 52b and the word line nitride layer 65. The second insulating layer 51b, the second polysilicon layer 53b and the second gate conductor 52b may together form a second recess transistor 5b. The second recess transistor 5b may be disposed in the second outer trench 44b.
[0146] Therefore, we get Figure 1 The semiconductor structure 7 is shown.
[0147] Fig.16 is a flow chart illustrating a method 900 for preparing a semiconductor structure according to some embodiments of the present disclosure.
[0148] In some embodiments, the preparation method 900 may include step S901, providing a device, wherein the device includes a substrate and a plurality of word lines, the substrate includes an array portion and a peripheral portion surrounding the array portion, the plurality of word lines are arranged in the array portion, and the peripheral portion has no word lines. Figure 3 As shown, a component 7' is provided. The component 7' includes a substrate 4 and a plurality of word lines 1. The substrate 4 includes an array portion 41 and a peripheral portion 42 surrounding the array portion 41. The plurality of word lines 1 are disposed in the array portion 41. The peripheral portion 42 has no word lines.
[0149] In some embodiments, the preparation method 900 may include step S902, forming at least one groove in the peripheral portion of the substrate. Fig.11 As shown, at least one groove 47 is formed in the peripheral portion 42 of the base 4 .
[0150] In some embodiments, the preparation method 900 may include step S903, forming at least one recessed transistor in the at least one recessed portion of the peripheral portion of the substrate. Figure 1 As shown, at least one recessed transistor 5 is formed in at least one recessed groove 47 of the peripheral portion 42 of the substrate 4 .
[0151] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes may be implemented in different ways, and other processes, or combinations thereof may be used to replace many of the above processes.
[0152] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.
Claims
1. A semiconductor structure comprising: A device comprising a substrate and a plurality of word lines, wherein the substrate comprises an array portion and a peripheral portion surrounding the array portion, wherein the plurality of word lines are disposed in the array portion and the peripheral portion is free of word lines, wherein the peripheral portion of the substrate defines at least one groove; and At least one recessed transistor is disposed in the at least one recessed portion of the peripheral portion of the substrate. 2 . The semiconductor structure of claim 1 , wherein the at least one recess transistor comprises a plurality of recess transistors having different widths. 3 . The semiconductor structure of claim 1 , wherein the at least one trench transistor comprises a plurality of trench transistors, and the semiconductor structure further comprises at least one shallow trench isolation (STI) disposed between the trench transistors.
4. The semiconductor structure of claim 1 , wherein the element further comprises a word line nitride layer covering the array portion and the peripheral portion of the substrate and extending to the plurality of word lines, wherein the word line nitride layer defines at least one opening corresponding to the at least one recess of the peripheral portion, and the at least one recess transistor is further disposed in the at least one opening of the word line nitride layer.
5. The semiconductor structure of claim 1 , wherein the at least one recessed transistor comprises: a polysilicon layer disposed in the at least one groove of the peripheral portion of the substrate; an insulating layer disposed between the polysilicon layer and the peripheral portion of the substrate; and A gate conductor is disposed on the polysilicon layer. The semiconductor structure as claimed in claim 5 , wherein a bottom surface of the gate conductor is higher than a top surface of the substrate.
7. A semiconductor structure as described in claim 5, wherein the element further includes a word line nitride layer covering the array portion and the peripheral portion of the substrate and extending to the plurality of word lines, wherein the word line nitride layer defines at least one opening corresponding to the at least one groove of the peripheral portion, the gate conductor is disposed in the at least one opening of the word line nitride layer, and the insulating layer is further disposed between the gate conductor and the word line nitride layer. 8 . The semiconductor structure as claimed in claim 7 , wherein a top surface of the gate conductor is lower than a top surface of the word line nitride layer.
9. A method for preparing a semiconductor structure, comprising: A device is provided, wherein the device comprises a substrate and a plurality of word lines, the substrate comprises an array portion and a peripheral portion surrounding the array portion, the plurality of word lines are arranged in the array portion, and the peripheral portion has no word lines; forming at least one groove in the peripheral portion of the substrate; and At least one recess transistor is formed in the at least one recess of the peripheral portion of the substrate.
10. The method for preparing a semiconductor structure according to claim 9, wherein forming at least one groove in the peripheral portion of the substrate comprises: forming a mask layer on the peripheral portion of the substrate; forming a sacrificial layer on the mask layer, wherein the sacrificial layer includes a plurality of openings to expose portions of the mask layer; as well as According to the opening of the sacrificial layer, a portion of the periphery of the substrate is removed to form the at least one groove.
11. The method for preparing a semiconductor structure according to claim 10, wherein forming the sacrificial layer on the mask layer comprises: forming a patterned photoresist layer on the mask layer, wherein the patterned photoresist layer includes a plurality of remaining portions spaced apart from each other; forming the sacrificial layer on the mask layer to cover the remaining portions of the patterned photoresist layer; as well as The remaining portions of the patterned photoresist layer are removed to form the openings of the sacrificial layer.
12. The method for manufacturing a semiconductor structure according to claim 11, wherein in the step of forming the sacrificial layer on the mask layer to cover the plurality of remaining portions of the patterned photoresist layer, the sacrificial layer covers a plurality of top surfaces of the plurality of remaining portions of the patterned photoresist layer, and the method further comprises: The sacrificial layer is thinned to expose top surfaces of the remaining portions of the patterned photoresist layer. 13 . The method for fabricating a semiconductor structure as claimed in claim 12 , wherein after the step of thinning the sacrificial layer, a top surface of the sacrificial layer is substantially coplanar with the top surfaces of the remaining portions of the patterned photoresist layer.
14. The method for preparing a semiconductor structure according to claim 9, wherein forming the at least one recess transistor in the at least one recess in the peripheral portion of the substrate comprises: forming an insulating layer on a side wall of the at least one groove of the peripheral portion of the substrate; forming a polysilicon layer on the insulating layer in the at least one groove of the peripheral portion of the substrate; and A gate conductor is formed on the polysilicon layer.
15. The method for preparing a semiconductor structure as claimed in claim 14, wherein in the step of forming the polysilicon layer on the insulating layer, the polysilicon layer further covers a top surface of the substrate, and the method further comprises: A portion of the polysilicon layer on the top surface of the substrate is removed.