Semiconductor device

Abstract

A semiconductor device includes a circuit region: a first global wiring extending over the circuit region, the first global wiring being at least partially divided into a first main wiring and a first branch wiring over the circuit region; and a second global wiring disposed adjacent to the first global wiring and extending parallel to the first global wiring, the second global wiring being at least partially divided into a second main wiring and a second branch wiring over the circuit region. The first branch wire extends between the second main wire and the second branch wire. The second branch wire extends between the first main wire and the first branch wire.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Recently, in semiconductor devices such as dynamic random access memory (DRAM), it is desired to increase memory capacity, and the number of memory elements placed in memory chips is increasing. For this reason, the number of circuits for driving memory elements is also increasing, and therefore the power consumption in the circuit area is rising. In addition, in some cases, design constraints may cause difficulties in freely arranging the wiring for supplying power. Therefore, in some cases, it is difficult to evenly supply power to the circuit area arranged in the memory chip. Summary of the invention

[0003] In one aspect, the present disclosure relates to a device comprising: a circuit area: a first global wiring, which extends above the circuit area, and the first global wiring is at least partially divided into a first main wiring and a first branch wiring above the circuit area; and a second global wiring, which is arranged adjacent to the first global wiring and extends parallel to the first global wiring, and the second global wiring is at least partially divided into a second main wiring and a second branch wiring above the circuit area; wherein the first branch wiring extends between the second main wiring and the second branch wiring; and wherein the second branch wiring extends between the first main wiring and the first branch wiring.

[0004] In another aspect, the present disclosure relates to a device, comprising: a circuit area: a first global wiring, which extends above the circuit area, and the first global wiring is at least partially divided into a first branch wiring, a second branch wiring and a first main wiring therebetween above the circuit area; a second global wiring, which is arranged adjacent to the first global wiring in one side of the first global wiring and extends parallel to the first global wiring, and the second global wiring is at least partially divided into a third branch wiring, a fourth branch wiring and a second main wiring therebetween above the circuit area; a third global wiring, which is arranged adjacent to the first global wiring in the other side of the first global wiring and extends parallel to the first global wiring, and the third global wiring is at least partially divided into a fifth branch wiring, a sixth branch wiring and a third main wiring therebetween above the circuit area; wherein the first branch wiring extends between the second main wiring and the fourth branch wiring; and wherein the second branch wiring extends between the third main wiring (144A) and the fifth branch wiring.

[0005] In another aspect, the present disclosure relates to a device comprising: a circuit area: a first global wiring, which extends above the circuit area, and the first global wiring is arranged in a first wiring layer; a second global wiring, which is arranged adjacent to the first global wiring and extends parallel to the first global wiring, and the second global wiring is arranged in the first wiring layer; a first branch wiring, which has a first branch portion branching from the first global wiring and a first connection portion connected to the first global wiring through the first branch wiring, and the first branch wiring extends parallel to the first global wiring at least above the circuit area; a second branch wiring, which has a second branch portion branching from the second global wiring and a second connection portion connected to the second global wiring through the second branch wiring, and the second branch wiring extends parallel to the second global wiring at least above the circuit area; wherein the first branch wiring extends between the second global wiring and the second branch wiring; and wherein the second branch wiring extends between the first global wiring and the first branch wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a plan view illustrating a schematic configuration of a semiconductor device according to the embodiment.

[0007] Figure 2 is a plan view illustrating a schematic configuration of a semiconductor device according to the embodiment.

[0008] Figure 3 is a plan view illustrating a schematic configuration of a semiconductor device according to the embodiment.

[0009] Figure 4 is a longitudinal sectional view illustrating a schematic configuration of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0010] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show specific aspects and various embodiments of the present disclosure by way of illustration. The detailed description provides sufficient details to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural changes, logical changes, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0011] Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. In the description of the embodiment, common or related elements and substantially the same elements are indicated by the same symbols, and their description will be reduced or omitted. In the figures cited below, the size and size ratio of each unit of each of the figures do not necessarily match the actual size and size ratio in the embodiment. In addition, in the following description, the Y direction is a direction at right angles to the X direction. The Z direction is a direction at right angles to the XY plane defined as the plane of the semiconductor substrate and is referred to as the vertical direction.

[0012] Hereinafter, a semiconductor device according to an embodiment will be described. In the following description, a dynamic random access memory (DRAM) is described as an example. Examples of DRAM include synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, double data rate 2 (DDR2) SDRAM, and double data rate 3 (DDR3) SDRAM. Figure 1 An example of a floor plan layout on a single DRAM chip is schematically illustrated.

[0013] like Figure 1 , the semiconductor device 1 is generally rectangular in shape with the long edge extending in the X direction. As described later, the semiconductor device 1 is formed on a semiconductor substrate. The semiconductor device 1 has a circuit area 12 having a plurality of power pads 11 along one long edge. The power pads 11 are connected by bonding in a back-end process of a process for manufacturing the semiconductor device 1 and are electrically connected to a memory controller when the semiconductor device 1 is incorporated into a computer system. A power line for driving the semiconductor device 1 is connected to the power pads 11.

[0014] The semiconductor device 1 is provided with a plurality of memory banks 16. The memory banks 16 are arranged in a matrix on a semiconductor substrate. The memory banks 16 contain a plurality of memory cells. A column decoder 18 and a row decoder 20 are arranged around the memory banks 16. The column decoder 18 and the row decoder 20 generate control signals for controlling operations such as writing, reading, and refreshing data in the memory cells.

[0015] In the center of the Y direction of the semiconductor device 1, the bank logic 24, the error correction code (ECC) / bus buffer 26, and the data sense amplifier 28 are arranged to extend in the X direction. The ECC / bus buffer 26 and the data sense amplifier 28 have high power consumption. The area where the ECC / bus buffer 26 and the data sense amplifier 28 with high power consumption are arranged is designated as the circuit area 12. An area where a circuit different from the circuit area 12 is arranged is provided in an area adjacent to the circuit area 12.

[0016] The semiconductor device 1 includes a plurality of global interconnects 14. Figure 11, the global wirings 14 are arranged parallel to each other in the X direction and extend in the Y direction. The global wirings 14 are each connected to the power pad 11 so that the length of the semiconductor device 1 extends in the Y direction and extends to the edge on the side opposite to the power pad 11 in the Y direction. Unillustrated wirings in the same layer as the global wirings 14 and the local wirings 22 arranged in different layers may be arranged between adjacent global wirings 14. For this reason, a layout extending in the Y direction is adopted for the global wirings 14.

[0017] Next, refer to Figure 2 , 3 and 4 describe the detailed configuration of the global wiring 14. Figure 2 1 is a schematic plan view illustrating an enlarged view of the region where the global wiring 14 overlaps the circuit region 12. Figure 2 As illustrated in FIG. 1 , a plurality of global wirings 14 are arranged. The global wirings 14 are each connected to a different power pad 11 and are connected at a different potential.

[0018] exist Figure 2 , in the order from the left side of the figure, the plurality of global wirings 14 are illustrated as a first global wiring 141, a second global wiring 142, a third global wiring 143, a fourth global wiring 144, and a fifth global wiring 145. The plurality of global wirings 14 extend in the Y direction so as to overlap with the circuit area 12 and cross over the circuit area 12. The first global wiring 141, the second global wiring 142, the third global wiring 143, the fourth global wiring 144, and the fifth global wiring 145 are included in the same wiring layer.

[0019] A plurality of sub-global wirings 30 extending in the X direction are arranged above the circuit region 12. Figure 2 , the plurality of sub-global wires 30 are illustrated as a first sub-global wire 301 , a second sub-global wire 302 , a third sub-global wire 303 , a fourth sub-global wire 304 , and a fifth sub-global wire 305 .

[0020] As described below, each of the global wirings 14 has a main wiring and a branch wiring. Figure 2As described in the above, the global wiring 14 (141, 142, 143, 144, 145) includes main wiring 141A, 142A, 143A, 144A, and 145A, respectively. In addition, the global wiring 14 (141, 142, 143, 144, 145) includes branch wiring 141B, 142B and 142C, 143B and 143C, 144B and 144C, and 145B and 145C, respectively. Each of the global wirings 14 (141, 142, 143, 144, 145) is at least partially divided into main wirings 141A, 142A, 143A, 144A and 145A and branch wirings 141B, 142B, 142C, 143B, 143C, 144B, 144C, 145B and 145C over the circuit area 12.

[0021] Main wirings 141A, 142A, 143A, 144A, and 145A are connected to the global wiring 14 at connection portions 38 and 39. Branch wirings 141B, 142B, 142C, 143B, 143C, 144B, 144C, 145B, and 145C are branched from the global wiring 14 at branch portion 40. The global wiring 14 (141, 142, 143, 144, 145) does not have a branch wiring on another area adjacent to the circuit area 12.

[0022] The first global wiring 141 and the fifth global wiring 145 are connected to the same potential. The second global wiring 142 and the fourth global wiring 144 are connected to the same potential. The global wirings 141 and 145 are connected to a potential different from that of the global wirings 142, 143, and 144. The global wirings 142 and 144 are connected to a potential different from that of the third global wiring 143.

[0023] The main wiring 141A and the branch wiring 141B of the first global wiring 141 are connected to the sub-global wirings 301 and 305 via contact plugs C1, C2, C3, and C4. The main wiring 145A and the branch wiring 145B of the fifth global wiring 145 are connected to the sub-global wirings 301 and 305 via contact plugs C17, C18, C19, and C20. The first sub-global wiring 301 and the fifth sub-global wiring 305 are connected to the same potential.

[0024] The main line 142A and branch lines 142B and 142C of the second global line 142 are connected to the third sub-global line 303 via contact plugs C5, C6 and C7. The main line 144A and branch lines 144B and 144C of the fourth global line 144 are connected to the third sub-global line 303 via contact plugs C14, C15 and C16.

[0025] The main wiring 143A and branch wirings 143B and 143C of the third global wiring 143 are connected to the second sub-global wiring 302 and the fourth sub-global wiring 304 through contact plugs C8, C9, C10, C11, C12 and C13. The second sub-global wiring 302 and the fourth sub-global wiring 304 are connected to the same potential.

[0026] The main wirings 141A, 142A, 143A, 144A, 145A and the branch wirings 141B, 142B, 142C, 143B, 143C, 144B, 144C, 145B are each provided with at least one contact plug. This arrangement allows voltage to be supplied to the circuit area 12 through each of the sub-global wirings 30 .

[0027] Between the main wiring 141A and the branch wiring 141B of the first global wiring 141, a branch wiring 142B adjacent to the second global wiring 142 is arranged. Between the main wiring 142A and the branch wiring 142B of the second global wiring 142, a branch wiring 141B adjacent to the first global wiring 141 is arranged. Between the main wiring 142A and the branch wiring 142C of the second global wiring 142, a branch wiring 143B adjacent to the third global wiring 143 is arranged.

[0028] The branch wire 142C adjacent to the second global wire 142 is disposed between the main wire 143A and the branch wire 143B of the third global wire 143. The branch wire 144B adjacent to the fourth global wire 144 is disposed between the main wire 143A and the branch wire 143C of the third global wire 143.

[0029] Between the main wiring 144A and the branch wiring 144B of the fourth global wiring 144, the branch wiring 143C adjacent to the third global wiring 143 is arranged. Between the main wiring 144A and the branch wiring 144C of the fourth global wiring 144, the branch wiring 145B adjacent to the fifth global wiring 145 is arranged. Between the main wiring 145A and the branch wiring 145B of the fifth global wiring 145, the branch wiring 144C adjacent to the fourth global wiring 144 is arranged.

[0030] In this way, a distance sufficient to accommodate adjacent branch connections 142B, 142C, 143B, 143C, 144B, 144C, 145B is set between the main connection 141A, 142A, 143A, 144A, 145A of each of the global connections 14 and the branch connections 141B, 142B, 142C, 143B, 143C, 144B, 144C, 145B corresponding to each of the global connections 14.

[0031] Figure 3 Yes Description Figure 214 is a diagram of a second global wiring 142 among the plurality of global wirings 14 illustrated in FIG. The global wirings 141, 142, 143, 144, 145 have substantially the same configuration. Therefore, the description about the second global wiring 142 is also applicable to the global wirings 141, 143, 144, 145. Each of the tips 42 of the branch wirings 141B, 142B, 142C, 143B, 143C, 144B, 144C, 145B is coupled to the corresponding global wiring 141, 142, 143, 144, 145 by means of the corresponding supplementary wiring 32.

[0032] like Figure 3 , the branch wires 142B and 142C of the second global wire 142 branch from the main wire 142A at the branch portion 40. The main wire 142A is connected to the branch wires 142B and 142C at the branch portion 40. The branch portion 40 is positioned on the frame on one side of the circuit area 12 in the Y direction.

[0033] exist Figure 3 In the embodiment, the branch portion 40 is disposed on the near side closer to the circuit region 12 in the Y direction. The branch wiring 142B and the branch wiring 142C extend in the Y direction and are Figure 3 In the embodiment, the tip 42 thereof is arranged on the far side further in the Y direction than the circuit area 12. The tip 42 is positioned on the border on the other side of the circuit area 12 in the Y direction.

[0034] On both sides of the circuit area 12 are branch portions 40 and tips 42. The tips 42 of the branch wiring 142B and the tips 42 of the branch wiring 142C are coupled to the second global wiring 142 via the supplementary wiring 32.

[0035] The global wirings 141, 143, 144, 145 also have a structure similar to the second global wiring 142 described above. That is, the branch wirings 141B, 141C, 143B, 143C, 144B, 144C, 145B branch from the global wirings 141, 143, 144, 145 at the branch portions 40 corresponding to each. The tip 42 and the branch portions 40 corresponding to each of the branch wirings 141B, 141C, 143B, 143C, 144B, 144C, 145B are located on both sides of the circuit area 12.

[0036] Next, refer to Figure 4 The structure around the supplementary wiring 32 is described. Figure 4 , the second global wiring 142 and the branch wiring 142B are coupled at the tip 42 via the supplementary wiring 32. The tip 42 of the second global wiring 142 and the branch wiring 142B is connected via the contact plug 34. The contact plug 34 may be formed as a component of the second global wiring 142.

[0037] Below the first global wiring 141 and the second global wiring 142, for example, five wiring layers, namely, the first layer M1, the second layer M2, the third layer M3, the fourth layer M4, and the fifth layer M5 are provided. The first layer M1, the second layer M2, the third layer M3, the fourth layer M4, and the fifth layer M5 are provided in the insulating film 52 provided on the top of the semiconductor substrate 50. The first global wiring 141 and the second global wiring 142 are provided on the top of the insulating film 52.

[0038] The fifth layer M5 is located in the uppermost layer among the wiring layers disposed in the layer below the wiring layer in which the first global wiring 141 and the second global wiring 142 are disposed. The supplementary wiring 32 is included in the fifth layer M5. The supplementary wiring 32 is disposed in a wiring layer different from the first global wiring 141 and the second global wiring 142. Figure 4 An example in which the supplementary wiring 32 is formed in the fifth layer M5 is described, but the configuration is not necessarily limited thereto.

[0039] like Figure 4 14, the branch wiring 141B of the first global wiring 141 adjacent to the second global wiring 142 is disposed above the supplementary wiring 32. The first global wiring 141 and the second global wiring 142 are formed in the same wiring layer. Therefore, in order to place the branch wiring 141B between the main wiring 142A and the branch wiring 142B, the branch wiring 141B must be extended beyond the second global wiring 142. In an embodiment, by forming the supplementary wiring 32 in a wiring layer different from the global wiring 14, the branch wiring 141B can pass over the supplementary wiring 32, thereby allowing the branch wiring 141B to be placed between the main wiring 142A and the branch wiring 142B.

[0040] As described above, the second global wiring 142 is divided into a plurality of branches over the circuit region 12. For this reason, the contact plugs C5, C6, and C7 can be dispersed in the X direction. Therefore, the contact plugs connected to the sub-global wiring 30 can be more uniformly arranged, and the variation of the voltage supplied to the sub-global wiring 30 can be suppressed. The second global wiring 142 is not divided into a plurality of branches in the region outside the circuit region 12.

[0041] Tips 42 of the branch wirings 142B and 142C are coupled to the second global wiring 142 by means of the supplementary wiring 32. For this reason, a voltage drop in the branch wirings 142B and 142C can be suppressed, and thus a variation in a voltage supplied to the sub-global wiring 30 can be suppressed.

[0042] The global wirings 141, 143, 144, 145 also have substantially the same configuration as the second global wiring 142 described above. In other words, the global wirings 141, 142, 143, 144, 145 are divided into a plurality of branches over the circuit area 12. For this reason, the contact plugs C1 to C20 can be dispersed in the X direction. Therefore, the contact plugs connected to the sub-global wiring 30 can be arranged more uniformly, and the variation of the voltage supplied to the sub-global wiring 30 can be suppressed. With this arrangement, the driving variation of the circuit connected to the sub-global wiring 30 is suppressed, thereby achieving a more stable device operation. Note that the global wirings 141, 142, 143, 144, 145 are not divided into a plurality of branches in the area outside the circuit area 12.

[0043] Likewise, in the global wirings 141, 142, 143, 144, 145, the tip 42 of each of the branch wirings 141B, 142B, 142C, 143B, 143C, 144B, 144C, and 145C is coupled to the global wirings 141, 142, 143, 144, 145 by means of the corresponding supplementary wiring 32. For this reason, a voltage drop in the branch wirings 141B, 142B, 142C, 143B, 143C, 144B, 144C, and 145C can be suppressed, and thus a variation in the voltage supplied to the sub-global wiring 30 can be suppressed. With this arrangement, a driving variation of the circuit coupled to the sub-global wiring 30 is suppressed, thereby achieving a more stable device operation.

[0044] As described above, DRAM is described as an example of a semiconductor device according to an embodiment, but the above description is only an example and is not intended to be limited to DRAM. Memory devices other than DRAM, such as (for example) static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory can also be applied as semiconductor devices. In addition, devices other than memory, such as (for example) logic ICs such as microprocessors and application-specific integrated circuits (ASICs), can also be applied as semiconductor devices according to the aforementioned embodiments.

[0045] Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the explicitly disclosed embodiments to other alternative embodiments and / or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the present disclosure. It is also contemplated that various combinations or sub-combinations may be made to the specific features and aspects of the embodiments and that they still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with one another to form different modes of the disclosed embodiments. Therefore, it is desired that the scope of at least some of the present disclosure should not be limited by the above-mentioned specific disclosed embodiments.

Claims

1. A device comprising: Circuit area: A first global wiring extending above the circuit area, wherein the first global wiring is at least partially divided into a first main wiring and a first branch wiring above the circuit area; and a second global wiring arranged adjacent to the first global wiring and extending parallel to the first global wiring, the second global wiring being at least partially divided into a second main wiring and a second branch wiring above the circuit region; wherein the first branch connection extends between the second main connection and the second branch connection; and The second branch connection extends between the first main connection and the first branch connection.

2. The apparatus of claim 1, wherein voltages different from each other are supplied to the first global wiring and the second global wiring.

3. The apparatus of claim 1, wherein the first global wiring and the second global wiring do not have branch wiring over a region adjacent to the circuit region. 4 . The apparatus according to claim 1 , wherein each of the first main wiring and the first branch wiring of the first global wiring is disposed in a first wiring layer. 5 . The apparatus according to claim 1 , wherein each of the second main wiring and the second branch wiring of the second global wiring is disposed in a first wiring layer. 6 . The apparatus according to claim 1 , wherein each of the first main wiring of the first global wiring, the first branch wiring, the second main wiring of the second global wiring, and the second branch wiring is disposed in a first wiring layer. 7 . The apparatus according to claim 6 , wherein the first branch wiring has a tip, and the tip is coupled to the first global wiring by means of a supplementary wiring provided in a second wiring layer different from the first wiring layer. 8 . The apparatus according to claim 1 , wherein at least one contact plug is disposed on each of the first and second main wirings and the first and second branch wirings to supply a voltage to the circuit area.

9. A device comprising: Circuit area: A first global wiring extending above the circuit area, wherein the first global wiring is at least partially divided into a first branch wiring, a second branch wiring and a first main wiring therebetween above the circuit area; a second global wiring arranged adjacent to the first global wiring in one side of the first global wiring and extending parallel to the first global wiring, the second global wiring being at least partially divided into a third branch wiring, a fourth branch wiring and a second main wiring therebetween over the circuit region; a third global wiring, which is arranged adjacent to the first global wiring in the other side of the first global wiring and extends parallel to the first global wiring, the third global wiring being at least partially divided into a fifth branch wiring, a sixth branch wiring and a third main wiring therebetween over the circuit region; The first branch connection extends between the second main connection and the fourth branch connection; and The second branch connection extends between the third main connection (144A) and the fifth branch connection.

10. The apparatus of claim 9, wherein voltages different from one another are supplied to the first global wiring, the second global wiring, and the third global wiring.

11. The apparatus of claim 9, wherein the first global wiring, the second global wiring, and the third global wiring do not have branch wiring over a region adjacent to the circuit region. 12 . The apparatus according to claim 9 , wherein each of the first main wiring, the first branch wiring, and the second branch wiring of the first global wiring is disposed in a first wiring layer. 13 . The apparatus according to claim 9 , wherein each of the second main wiring, the third branch wiring, and the fourth branch wiring of the second global wiring is disposed in a first wiring layer.

14. The apparatus according to claim 9, wherein each of the third main wiring, the fifth branch wiring, and the sixth branch wiring of the third global wiring is disposed in a first wiring layer.

15. The apparatus according to claim 9, wherein each of the first main wiring, the first branch wiring, the second branch wiring, the second main wiring, the third branch wiring, the fourth branch wiring, the third main wiring, the fifth branch wiring and the sixth branch wiring is arranged in a first wiring layer.

16. The apparatus according to claim 15, wherein the first branch wiring, the second branch wiring, the third branch wiring, the fourth branch wiring, the fifth branch wiring, and the sixth branch wiring respectively have a tip, wherein each of the tips of the first branch wiring and the second branch wiring is coupled to the first global wiring by means of a first supplementary wiring in a second wiring layer different from the first wiring layer; wherein each of the tips of the third branch wiring and the fourth wiring is coupled to the second global wiring by means of a second supplementary wiring in the second wiring layer; and Wherein each of the tips of the fifth branch wiring and the sixth wiring is coupled to the third global wiring by means of a third supplementary wiring in the second wiring layer.

17. The device according to claim 9, wherein at least one contact plug is arranged on the first main wiring, the second main wiring and the third main wiring and each of the first branch wiring, the second branch wiring, the third branch wiring, the fourth branch wiring, the fifth branch wiring and the sixth branch wiring to supply a corresponding voltage to the circuit area.

18. An apparatus comprising: Circuit area: A first global wiring extending above the circuit area, wherein the first global wiring is disposed in a first wiring layer; a second global wiring arranged adjacent to the first global wiring and extending parallel to the first global wiring, the second global wiring being disposed in the first wiring layer; a first branch wiring having a first branch portion branching from the first global wiring and a first connection portion connected to the first global wiring through the first branch wiring, the first branch wiring extending parallel to the first global wiring at least above the circuit region; a second branch wiring having a second branch portion branching from the second global wiring and a second connection portion connected to the second global wiring through the second branch wiring, the second branch wiring extending parallel to the second global wiring at least above the circuit region; wherein the first branch connection extends between the second global connection and the second branch connection; and The second branch connection extends between the first global connection and the first branch connection.

19. The apparatus of claim 18, further comprising: a first supplementary wiring that couples the first global wiring and the first branch wiring in the first connection portion and is disposed in a second wiring layer different from the first wiring layer; The second branch wiring is arranged to overlap with the first supplementary wiring.

20. The apparatus according to claim 18, further comprising a second supplementary wiring, the second supplementary wiring coupling the second global wiring and the second branch wiring in the second connection portion and disposed in a second wiring layer different from the first wiring layer; The first branch wiring is arranged to overlap with the second supplementary wiring.

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