Semiconductor structure, memory and manufacturing method thereof

Abstract

The present disclosure relates to a semiconductor structure, a memory and a preparation method thereof. The semiconductor structure includes a first conductive structure, a second conductive structure, a third conductive structure, a channel layer and an isolation layer. The first conductive structure extends along a first direction; the second conductive structure and the third conductive structure extend along a second direction, and the second conductive structure and the third conductive structure are alternately arranged at intervals in the first direction; the channel layer extends along the first direction, and the channel layer surrounds the first conductive structure; the isolation layer extends along the second direction, and the isolation layer is located between the second conductive structure and the third conductive structure, and the isolation layer is in contact with the channel layer; wherein the channel layer has a plurality of protrusions extending in the second direction, and the second conductive structure and the third conductive structure are respectively in contact with the corresponding protrusions; the second direction is perpendicular to the first direction. The semiconductor structure can reduce the overall height of the semiconductor structure, increase storage density, and improve product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure, a memory and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, multi-plane technology used for stacked memory cells can enable semiconductor devices to achieve smaller device sizes and larger storage capacities, thereby producing different three-dimensional (3D) flash memory structures, such as three-dimensional or non-(3D NOR) flash memory and three-dimensional and non-(3D NAND) flash memory.

[0003] In the related art, the 3D NOR using a vertical word line structure has a coupling effect and a short channel effect due to the reduced spacing between the source contact area and the drain contact area, making it difficult to reduce the interlayer distance and achieve a higher storage density. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure, a memory and a method for manufacturing the same, which can at least reduce the height of a three-dimensional NOR flash memory while increasing the storage density.

[0005] According to various embodiments of the present disclosure, on the one hand, a semiconductor structure is provided, including a first conductive structure, a second conductive structure, a third conductive structure, a channel layer and an isolation layer, wherein the first conductive structure extends along a first direction; the second conductive structure and the third conductive structure extend along a second direction, and the second conductive structure and the third conductive structure are alternately arranged at intervals in the first direction; the channel layer extends along the first direction, and the channel layer surrounds the first conductive structure; the isolation layer extends along the second direction, and the isolation layer is located between the second conductive structure and the third conductive structure, and the isolation layer is in contact with the channel layer; wherein the channel layer has a plurality of protrusions extending in the second direction, and the second conductive structure and the third conductive structure are in contact with the corresponding protrusions, respectively; the second direction is perpendicular to the first direction.

[0006] In the semiconductor structure of the above embodiment, a plurality of protrusions extending in the second direction are provided on the channel layer surrounding the first conductive structure, and the second conductive structure and the third conductive structure are provided to be in contact and connected with the corresponding protrusions, respectively. The channel region of each layer is provided as a U-shaped channel with two protrusions, thereby increasing the channel length without increasing the spacing between cells. Therefore, the semiconductor structure of this embodiment provides protrusions in the channel region, which can reduce the layer height of the film layer and the isolation layer where the stacked second conductive structure and the third conductive structure are located, thereby reducing the overall height of the semiconductor structure, increasing the storage density, and improving the product yield.

[0007] In some embodiments, the protrusion includes at least two parts located on opposite sides of the first conductive structure along the second direction, ensuring that the channel regions on both sides of the first conductive structure can reduce the layer height of the film layer and the isolation layer where the stacked second conductive structure and the third conductive structure are located, thereby reducing the overall height of the semiconductor structure, increasing storage density, and improving product yield.

[0008] In some embodiments, the protrusion surrounds the outer wall of the first conductive structure, so that the channel region of the first conductive structure in the three-dimensional semiconductor structure has the protrusion as a whole in a three-dimensional angle, ensuring that the three-dimensional semiconductor structure as a whole can reduce the height and increase the storage density.

[0009] In some embodiments, in the direction along the first direction toward the bottom surface of the first conductive structure, the lengths of the second conductive structures and the third conductive structures of different layers along the second direction increase successively. The stepped conductive structure enables the conductive structures located at different steps to be connected to their corresponding bit lines through a simple structure, thereby simplifying the process flow and reducing production costs.

[0010] In some embodiments, the channel layer circumferentially surrounds the first conductive structure; the semiconductor structure further includes a barrier layer circumferentially surrounding the sidewalls of the first conductive structure and covering the bottom surface of the first conductive structure.

[0011] In some embodiments, the semiconductor structure further includes a charge storage layer, which circumferentially surrounds the sidewalls of the blocking layer and covers the bottom surface of the blocking layer. The charge storage layer and the blocking layer work together to enable the semiconductor structure to have a storage function.

[0012] In some embodiments, the charge storage layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer circumferentially surrounds the outer wall of the blocking layer and covers the bottom surface of the blocking layer; the second dielectric layer circumferentially surrounds the outer wall of the first dielectric layer and covers the bottom surface of the first dielectric layer; the third dielectric layer circumferentially surrounds the outer wall of the second dielectric layer and covers the bottom surface of the second dielectric layer; the first dielectric layer and the third dielectric layer are made of the same material, and the first dielectric layer and the second dielectric layer are made of different materials.

[0013] According to various embodiments of the present disclosure, on the other hand, a memory is provided, comprising a substrate and an array structure located on the substrate, the array structure comprising the semiconductor structures of any of the above-mentioned embodiments arranged in an array; the first conductive structures in the array structure all extend along a first direction and are arranged in rows and columns along a second direction and a third direction; the second direction intersects with the third direction and is both perpendicular to the first direction; the semiconductor structures adjacent along the third direction are insulated from each other, and the second conductive structures or third conductive structures of the semiconductor structures adjacent along the second direction in the same layer are electrically connected; the second conductive structures or third conductive structures of the semiconductor structures adjacent along the first direction in different layers are insulated from each other.

[0014] In the memory of the above embodiment, a plurality of protrusions extending in the second direction are provided on the channel layer surrounding the first conductive structure through a semiconductor structure, and a second conductive structure and a third conductive structure are provided to be in contact and connected with the corresponding protrusions, respectively. The channel region of each layer is provided as a U-shaped channel with two protrusions, which increases the channel length without increasing the spacing between cells. Therefore, the memory of this embodiment provides protrusions in the channel region through multiple semiconductor structures, which can reduce the layer height of the film layer and the isolation layer where the stacked second conductive structure and the third conductive structure are located, thereby reducing the overall height of the memory, increasing the storage density, and improving the product yield.

[0015] In some embodiments, in the direction away from the substrate along the first direction, the second conductive structure and the third conductive structure located in different layers on the periphery of the array structure have lengths that decrease successively along the second direction and form steps. The stepped conductive structure enables the conductive structures located at different steps to be connected to their corresponding bit lines through a simple structure, thereby simplifying the process flow and reducing production costs.

[0016] In some embodiments, the memory further includes a word line extension and / or a bit line contact plug. The word line extension is located on the array structure and is arranged corresponding to the first conductive structure; the bit line contact plug is located on the periphery of the array structure and is arranged corresponding to the second conductive structure and the third conductive structure. The contact plug corresponding to each conductive structure can connect each conductive structure with the corresponding structure in the subsequent process, thereby facilitating the preparation of the subsequent structure.

[0017] In some embodiments, in the direction away from the substrate along the first direction, the heights of the bit line contact plugs corresponding to the protrusions of different layers decrease successively, corresponding to the above-mentioned stepped second conductive structure and third conductive structure, so that the top surfaces of the bit line contact plugs are flush, which facilitates subsequent structure preparation.

[0018] According to various embodiments of the present disclosure, on the other hand, a method for preparing a memory is provided, comprising: providing a substrate; sequentially forming isolation layers and sacrificial layers alternately stacked along a first direction on the substrate; forming an array structure, the array structure comprising a first conductive structure, a second conductive structure, a third conductive structure and a channel layer, the first conductive structure being arranged in rows and columns along the second direction and the third direction, the first conductive structure penetrating the isolation layer and the sacrificial layer along the first direction, the second conductive structure and the third conductive structure being alternately arranged in the first direction and spaced apart by the isolation layer; the channel layer extending along the first direction and surrounding the first conductive structure; the channel layer having a plurality of protrusions extending in the second direction, the second conductive structure and the third conductive structure being respectively in contact with and connected to the corresponding protrusions.

[0019] In the method for preparing the memory of the above embodiment, a plurality of protrusions extending in the second direction are provided on the channel layer surrounding the first conductive structure through a semiconductor structure, and a second conductive structure and a third conductive structure are provided to be in contact and connected with the corresponding protrusions, respectively. The channel region of each layer is provided as a U-shaped channel with two protrusions, which increases the channel length without increasing the spacing between cells. Therefore, the semiconductor structure of this embodiment can reduce the layer height of the film layer and the isolation layer where the stacked second conductive structure and the third conductive structure are located by providing protrusions in the channel region through each semiconductor structure, thereby reducing the overall height of the memory, increasing the storage density, and improving the product yield.

[0020] In some embodiments, forming an isolation layer and a sacrificial layer includes: forming functional layers alternately stacked along a first direction on a substrate, the functional layers including isolation material layers and sacrificial material layers stacked along the first direction; forming a patterned mask layer on the top isolation material layer, the patterned mask layer defining an array area for forming an array structure; etching the isolation material layer and the sacrificial material layer located at the periphery of the array area based on the patterned mask layer, the lengths of the remaining functional layers of different layers along the second direction successively decrease in a direction away from the substrate along the first direction, forming a stacked structure including a stepped structure; the remaining isolation material layers are used to constitute the isolation layers, and the remaining sacrificial material layers are used to constitute the sacrificial layers.

[0021] In some embodiments, forming the array structure also includes: forming first grooves arranged in rows and columns along the second direction and the third direction in the array area, the first grooves penetrating the isolation layer and the sacrificial layer along the first direction and exposing a portion of the substrate; etching back the sacrificial layer at least along the second direction through the first grooves to obtain first grooves isolated from each other by the isolation layer; the connected first grooves and the first grooves are used to form a first through hole; forming a channel layer on the inner side wall of the first through hole, the channel layer including a protrusion located in the first groove; forming a charge storage layer on the side surface of the channel layer and the bottom surface of the first through hole; forming a blocking layer on the side surface of the charge storage layer and the bottom surface of the charge storage layer; and forming a first conductive structure in the first through hole.

[0022] In some embodiments, the stepped structure is covered with a dielectric layer; forming the array structure further includes: after filling the first conductive structure in the first through hole, forming isolation trenches spaced along the third direction and extending along the second direction in the stacked structure; the isolation trenches are located between adjacent channel layers along the third direction; removing the sacrificial layer through the isolation trenches to obtain a second groove located between the protrusions of the channel layers adjacent along the second direction; forming a second conductive structure and a third conductive structure in the second groove; the second conductive structure and the third conductive structure are located at the periphery of the array structure, and in the direction away from the substrate along the first direction, the lengths of the second conductive structures and the third conductive structures of different layers along the second direction decrease successively and form steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0025] Figure 2 A schematic structural diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0026] Figure 3 This is a schematic structural diagram of a semiconductor structure provided in yet another embodiment of the present disclosure;

[0027] Figure 4 This is a schematic structural diagram of a semiconductor structure provided in yet another embodiment of the present disclosure;

[0028] Figure 5 A schematic structural diagram of a memory provided in one embodiment of the present disclosure;

[0029] Figure 6 A schematic structural diagram of a memory provided in another embodiment of the present disclosure;

[0030] Figure 7 A schematic flow chart of a method for preparing a memory provided in one embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of the three-dimensional structure of a substrate and a functional layer provided in some embodiments of the present disclosure;

[0032] Figure 9 In some embodiments of the present disclosure, Figure 8 A schematic diagram of a three-dimensional structure obtained after forming a first mask layer, a second mask layer and a third mask layer stacked in sequence from top to bottom on the structure shown;

[0033] Figure 10 In some embodiments of the present disclosure, Figure 9 A schematic diagram of a three-dimensional structure obtained after forming a patterned mask layer and a patterned photoresist layer PR1 on the structure shown;

[0034] Figure 11 In some embodiments of the present disclosure, Figure 10 Schematic diagram of the three-dimensional structure obtained after forming a stepped structure on the structure shown;

[0035] Figure 12 In some embodiments of the present disclosure, Figure 11 A schematic diagram of a three-dimensional structure obtained after a filling layer is formed on the structure shown;

[0036] Figure 13 In some embodiments of the present disclosure, Figure 12 A schematic diagram of a three-dimensional structure obtained after forming a patterned photoresist layer PR2 on the structure shown;

[0037] Figure 14 In some embodiments of the present disclosure, Figure 13 A schematic diagram of a three-dimensional structure obtained after forming a first through hole on the structure shown;

[0038] Figure 15 In some embodiments of the present disclosure, Figure 14 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0039] Figure 16 In some embodiments of the present disclosure, Figure 14 A schematic diagram of a three-dimensional structure obtained after forming a channel material layer on the structure shown;

[0040] Figure 17 In some embodiments of the present disclosure, Figure 16 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0041] Figure 18 In some embodiments of the present disclosure, Figure 16 A schematic diagram of a three-dimensional structure obtained after forming a patterned photoresist layer PR3 on the structure shown;

[0042] Figure 19 In some embodiments of the present disclosure, Figure 18 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0043] Figure 20 In some embodiments of the present disclosure, Figure 18 A schematic diagram of a three-dimensional structure obtained after a charge storage layer and a blocking layer are formed on the structure shown;

[0044] Figure 21 In some embodiments of the present disclosure, Figure 20 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0045] Figure 22 In some embodiments of the present disclosure, Figure 20 A schematic diagram of a three-dimensional structure obtained after forming a first conductive structure on the structure shown;

[0046] Figure 23 In some embodiments of the present disclosure, Figure 22 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0047] Figure 24 In some embodiments of the present disclosure, Figure 22 A schematic diagram of a three-dimensional structure obtained after forming a first capping layer on the structure shown;

[0048] Figure 25 In some embodiments of the present disclosure, Figure 24 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0049] Figure 26 In some embodiments of the present disclosure, Figure 24 A schematic diagram of a three-dimensional structure obtained after forming a patterned photoresist layer PR4 on the structure shown;

[0050] Figure 27 In some embodiments of the present disclosure, Figure 26 A schematic diagram of a three-dimensional structure obtained after forming a second groove on the structure shown;

[0051] Figure 28 In some embodiments of the present disclosure, Figure 27 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0052] Figure 29 In some embodiments of the present disclosure, Figure 27 A schematic diagram of a three-dimensional structure obtained after a conductive contact layer is formed on the structure shown;

[0053] Figure 30 In some embodiments of the present disclosure, Figure 29 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0054] Figure 31 In some embodiments of the present disclosure, Figure 29 A schematic diagram of a three-dimensional structure obtained after a conductive layer is formed on the structure shown;

[0055] Figure 32 In some embodiments of the present disclosure, Figure 29 A schematic diagram of a three-dimensional structure obtained after forming a capping layer on the structure shown;

[0056] Figure 33 In some embodiments of the present disclosure, Figure 32 A schematic diagram of a three-dimensional structure obtained after a conductive layer is formed on the structure shown;

[0057] Figure 34In some embodiments of the present disclosure, Figure 33 A schematic diagram of a three-dimensional structure obtained after forming a patterned photoresist layer PR5 on the structure shown;

[0058] Figure 35 In some embodiments of the present disclosure, Figure 34 The structure shown is an enlarged schematic diagram of a local cross section along the ox direction;

[0059] Figure 36 In some embodiments of the present disclosure, Figure 34 FIG. 1 is a schematic diagram of a three-dimensional structure obtained after forming a bit line contact plug and a word line extension on the structure shown.

[0060] Description of reference numerals:

[0061] 100, semiconductor structure; 11, first conductive structure; 12, second conductive structure; 13, third conductive structure; 20, channel layer; 21, protrusion; 30, isolation layer; 40, blocking layer; 50, charge storage layer; 51, first dielectric layer; 52, second dielectric layer; 53, third dielectric layer; 200, memory; 71, bit line contact plug; 72, word line extension; 101, substrate; 102, functional layer; 1021, isolation material layer; 1022, sacrificial material layer ; 1023, sacrificial layer; 103, patterned mask layer; 1031, first mask layer; 1032, second mask layer; 1033, third mask layer; 105, filling layer; 107, first through hole; 1071, first trench; 1072, first groove; 22, channel material layer; 60, capping layer; 61, first capping layer; 62, second capping layer; 110, isolation trench; 111, second groove; 112, conductive layer; 113, conductive contact layer; 115, plug trench. DETAILED DESCRIPTION

[0062] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0064] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0065] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0066] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0068] Please refer to Figure 1 The current mainstream NOR flash memory is mainly a two-dimensional structure. However, when the size of the two-dimensional NOR flash memory is reduced, the channel size will be reduced. However, when the channel size is reduced to a certain extent, the charge retention mechanism of the NOR flash memory will be uncertain, resulting in problems such as the read, write or erase operation results of the memory not being consistent with the actual state.

[0069] Please refer to Figure 2 In order to improve the integration of NOR flash memory, researchers adopted a 3D NOR structure with a vertical word line structure. The distance between the source contact area and the drain contact area determines the channel length H. If the channel length H is too small, it will lead to coupling effects between cells and short channel effects. Therefore, the cell height cannot be reduced, and it is difficult to achieve higher storage density.

[0070] Based on this, the present disclosure provides a semiconductor structure, a memory and a method for manufacturing the same, which can at least reduce the height of a three-dimensional NOR flash memory while increasing the storage density.

[0071] For example, as shown in the following figure, the ox direction is parallel to the second direction, the oy direction is parallel to the third direction, and the oz direction is parallel to the first direction. The first direction can be perpendicular to the top surface of the substrate, the second direction can be parallel to the top surface of the substrate, and the third direction can be parallel to the top surface of the substrate and intersect with the second direction.

[0072] Please refer to Figure 3According to one aspect of the present disclosure, a semiconductor structure 100 is provided, comprising a first conductive structure 11, a second conductive structure 12, a third conductive structure 13, a channel layer 20, and an isolation layer 30, wherein the first conductive structure 11 extends along a first direction; the second conductive structure 12 and the third conductive structure 13 extend along a second direction, and the second conductive structure 12 and the third conductive structure 13 are alternately arranged in the first direction; the channel layer 20 extends along the first direction, and the channel layer 20 surrounds the first conductive structure 11; the isolation layer 30 extends along the second direction, and the isolation layer 30 is located between the second conductive structure 12 and the third conductive structure 13, and the isolation layer 30 is in contact with and connected to the channel layer 20; wherein the channel layer 20 has a plurality of protrusions 21 extending in the second direction, and the second conductive structure 12 and the third conductive structure 13 are in contact with and connected to the corresponding protrusions 21, respectively; the second direction is perpendicular to the first direction, the first direction may be the oy direction, and the second direction may be the ox direction. The material of the channel layer 20 includes but is not limited to at least one of doped single crystal silicon, polycrystalline silicon, and indium gallium zinc oxide (IGZO).

[0073] As an example, please refer to Figure 3 The semiconductor structure 100 of this embodiment provides a plurality of protrusions 21 extending in the second direction on the channel layer 20 surrounding the first conductive structure 11, and provides the second conductive structure 12 and the third conductive structure 13 to be in contact with the corresponding protrusions 21, respectively. The channel region of each layer is configured as a U-shaped channel with two protrusions 21, thereby increasing the channel length without increasing the spacing between cells. Therefore, the semiconductor structure 100 of this embodiment provides the protrusions 21 in the channel region, which can reduce the layer height of the film layer and the isolation layer 30 where the stacked second conductive structure 12 and the third conductive structure 13 are located, thereby reducing the overall height of the semiconductor structure 100, increasing the storage density, and improving the product yield.

[0074] In some embodiments, please refer to Figure 3 The protrusion 21 includes at least two parts located on opposite sides of the first conductive structure 11 along the second direction, so that the channel regions on both sides of the first conductive structure 11 have the protrusion 21, ensuring that the channel regions on both sides of the first conductive structure 11 can reduce the layer height of the film layer and the isolation layer 30 where the stacked second conductive structure 12 and the third conductive structure 13 are located, thereby reducing the overall height of the semiconductor structure 100, increasing the storage density, and improving the product yield.

[0075] In some embodiments, please refer to Figure 3The protrusion 21 surrounds the outer wall of the first conductive structure 11, so that the channel region of the first conductive structure 11 in the three-dimensional semiconductor structure 100 has the protrusion 21 as a whole in a three-dimensional angle, ensuring that the three-dimensional semiconductor structure 100 as a whole can reduce the height and increase the storage density.

[0076] As an example, see Figure 2 and Figure 4 The actual channel length h of this embodiment is the channel length H plus the length 2L of the two protrusions 21, that is, h=H+2L, but the channel length in the related art is only H. The actual channel length of the semiconductor structure 100 of this embodiment is effectively increased compared with the channel length in the related art.

[0077] In some embodiments, please refer to Figure 3 In the direction along the first direction toward the bottom surface of the first conductive structure 11, the lengths of the second conductive structures 12 and the third conductive structures 13 of different layers along the second direction increase successively to form a stepped conductive structure. The second conductive structure 12 can be a source contact area, and the third conductive structure 13 can be a drain contact area. The stepped conductive structure allows the drain contact areas located at different steps to be connected to their corresponding bit lines through a simple structure, and the source contact areas located at different steps can also be connected to their corresponding source contact area lines through a simple structure, thereby simplifying the process flow and reducing production costs.

[0078] In some embodiments, please refer to Figure 3 The channel layer 20 circumferentially surrounds the first conductive structure 11; the semiconductor structure 100 further includes a barrier layer 40, which circumferentially surrounds the sidewalls of the first conductive structure 11 and covers the bottom surface of the first conductive structure 11. The barrier layer 40 may include a high-k dielectric layer, for example, k≥3.9, and the material of the high-k dielectric layer includes aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, praseodymium oxide, and combinations thereof.

[0079] In some embodiments, please refer to Figure 3 The semiconductor structure 100 further includes a charge storage layer 50, which circumferentially surrounds the sidewalls of the blocking layer 40 and covers the bottom surface of the blocking layer 40. The charge storage layer 50 and the blocking layer 40 work together to enable the semiconductor structure 100 to have a storage function.

[0080] In some embodiments, please refer to Figure 3The charge storage layer 50 includes a first dielectric layer 51, a second dielectric layer 52, and a third dielectric layer 53. The first dielectric layer 51 circumferentially surrounds the outer wall of the barrier layer 40 and covers the bottom surface of the barrier layer 40; the second dielectric layer 52 circumferentially surrounds the outer wall of the first dielectric layer 51 and covers the bottom surface of the first dielectric layer 51; the third dielectric layer 53 circumferentially surrounds the outer wall of the second dielectric layer 52 and covers the bottom surface of the second dielectric layer 52; the material of the first dielectric layer 51 includes silicon oxide, hafnium oxide, silicon hafnium oxide, aluminum hafnium oxide, zirconium hafnium oxide, zirconium oxide, yttrium oxide, and a combination thereof; the material of the second dielectric layer 52 includes silicon nitride, hafnium nitride, silicon hafnium nitride, aluminum hafnium nitride, zirconium hafnium nitride, zirconium nitride, yttrium nitride, and a combination thereof. The first dielectric layer 51 and the third dielectric layer 53 are made of the same material, while the first dielectric layer 51 and the second dielectric layer 52 are made of different materials.

[0081] Please refer to Figure 5 Another aspect of the present disclosure provides a memory 200, comprising a substrate 101 and an array structure located on the substrate 101, the array structure comprising any of the semiconductor structures 100 described above arranged in an array; the first conductive structures 11 in the array structure all extend along a first direction and are arranged in rows and columns along a second direction and a third direction; the second direction intersects with the third direction and is perpendicular to the first direction; the semiconductor structures 100 adjacent along the third direction are insulated from each other, and the second conductive structures 12 or the third conductive structures 13 of the semiconductor structures 100 adjacent along the second direction in the same layer are electrically connected; the second conductive structures 12 or the third conductive structures 13 of the semiconductor structures 100 adjacent along the first direction in different layers are insulated from each other, and the third direction may be the oz direction.

[0082] As an example, please refer to Figure 5 The memory 200 of this embodiment includes the above-mentioned semiconductor structures 100 arranged in an array. A plurality of protrusions 21 extending in the second direction are provided on the channel layer 20 surrounding the first conductive structure 11 through the semiconductor structure 100, and the second conductive structure 12 and the third conductive structure 13 are provided to contact and connect with the corresponding protrusions 21 respectively. The channel region of each layer is configured as a U-shaped channel with two protrusions 21. While increasing the channel length, the spacing between cells will not be increased. Therefore, the memory 200 of this embodiment can reduce the layer height of the film layer and the isolation layer 30 where the stacked second conductive structure 12 and the third conductive structure 13 are located by providing the protrusions 21 in the channel region through each semiconductor structure 100, thereby reducing the overall height of the memory 200, increasing the storage density, and improving the product yield.

[0083] In some embodiments, please refer to Figure 5In the direction away from the substrate 101 along the first direction, the second conductive structure 12 and the third conductive structure 13 located in different layers on the periphery of the array structure have lengths that decrease successively along the second direction and form steps. The second conductive structure 12 can be a source contact area, and the third conductive structure 13 can be a drain contact area. The stepped conductive structure allows the drain contact areas located at different steps to be connected to their corresponding bit lines through a simple structure, and the source contact areas located at different steps can also be connected to their corresponding source contact area lines through a simple structure, thereby simplifying the process flow and reducing production costs.

[0084] In some embodiments, please refer to Figure 5 and Figure 6 The memory 200 further includes a word line extension 72 and / or a bit line contact plug 71. The word line extension 72 is located on the array structure and is arranged corresponding to the first conductive structure 11; the bit line contact plug 71 is located on the periphery of the array structure and is arranged corresponding to the second conductive structure 12 and the third conductive structure 13. The contact plug corresponding to each conductive structure can connect each conductive structure with the corresponding structure in the subsequent process, thereby facilitating the subsequent structure preparation.

[0085] In some embodiments, please refer to Figure 5 and Figure 6 In the direction away from the substrate 101 along the first direction, the heights of the bit line contact plugs 71 corresponding to the protrusions 21 of different layers decrease successively, corresponding to the above-mentioned stepped second conductive structure 12 and third conductive structure 13, so that the top surfaces of the bit line contact plugs 71 are flush, which is convenient for subsequent structure preparation.

[0086] Please refer to Figure 7 Another aspect of the present disclosure provides a method for preparing a memory, comprising:

[0087] Step S102: providing a substrate;

[0088] Step S104: forming isolation layers and sacrificial layers alternately stacked along a first direction on the substrate in sequence;

[0089] Step S106: forming an array structure, the array structure including a first conductive structure, a second conductive structure, a third conductive structure and a channel layer, the first conductive structure being arranged in rows and columns along the second direction and the third direction, the first conductive structure penetrating the isolation layer and the sacrificial layer along the first direction, the second conductive structure and the third conductive structure being alternately arranged in the first direction and spaced apart by the isolation layer; the channel layer extending along the first direction and surrounding the first conductive structure; the channel layer having a plurality of protrusions extending in the second direction, the second conductive structure and the third conductive structure being respectively in contact with and connected to the corresponding protrusions.

[0090] As an example, please refer to Figure 7In the method for preparing the memory of this embodiment, a plurality of protrusions extending in a second direction are provided on a channel layer surrounding a first conductive structure through a semiconductor structure, and a second conductive structure and a third conductive structure are provided to contact and connect with the corresponding protrusions, respectively. The channel region of each layer is configured as a U-shaped channel with two protrusions. This increases the channel length without increasing the spacing between cells. Therefore, the semiconductor structure of this embodiment, by providing protrusions in the channel region of each semiconductor structure, can reduce the layer height of the film layer and isolation layer where the stacked second and third conductive structures are located, thereby reducing the overall height of the memory, increasing storage density, and improving product yield.

[0091] It should be understood that although Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0092] As an example, see Figure 8 In step S102, the substrate 101 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 101 can be a single-layer structure or a multi-layer structure. For example, the substrate 101 can be a silicon (Si) substrate 101, a silicon germanium (SiGe) substrate 101, a silicon germanium carbon (SiGeC) substrate 101, a silicon carbide (SiC) substrate 101, a gallium arsenide (GaAs) substrate 101, an indium arsenide (InAs) substrate 101, an indium phosphide (InP) substrate 101, or other III / V semiconductor substrates 101 or II / VI semiconductor substrates 101. Alternatively, for example, the substrate 101 can be a layered substrate 101 including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Those skilled in the art can select the type of substrate 101 according to the type of transistor formed on the substrate 101, so the type of substrate 101 should not limit the scope of protection of the present disclosure.

[0093] In some embodiments, please refer to Figures 8-12 In step S104, the isolation layer 30 and the sacrificial layer 1023 are formed, including:

[0094] Step S1041 : forming functional layers 102 alternately stacked along a first direction on the substrate 101 , wherein the functional layers 102 include isolation material layers 1021 and sacrificial material layers 1022 stacked along the first direction;

[0095] Step S1042: forming a patterned mask layer 103 on the top isolation material layer 1021, wherein the patterned mask layer 103 defines an array region for forming an array structure;

[0096] Step S1043: Based on the patterned mask layer 103, the isolation material layer 1021 and the sacrificial material layer 1022 are etched at the periphery of the array area, and the lengths of the remaining functional layers 102 in different layers along the second direction decrease successively in the direction away from the substrate 101 along the first direction, forming a stacked structure including a stepped structure; the remaining isolation material layer 1021 is used to constitute the isolation layer 30, and the remaining sacrificial material layer 1022 is used to constitute the sacrificial layer 1023.

[0097] As an example, please refer to Figures 8-12 In step S1041, a deposition process is used to form isolation material layers 1021 and sacrificial material layers 1022 alternately stacked along a first direction on the substrate 101. The isolation material layers 1021 include oxide, and the sacrificial material layers 1022 include polysilicon. The sacrificial material layers 1022 may be formed of a material having a large etching selectivity with the isolation material layers 1021, so that the sacrificial material layers 1022 can be more effectively removed in subsequent processes without damaging the isolation material layers 1021. The deposition process may include, but is not limited to, at least one of a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a high-density plasma deposition (HDP) process, a plasma-enhanced deposition process, and a spin-on dielectric (SOD) process.

[0098] As an example, please refer to Figures 8-12 In step S1042, a deposition process can be used to stack a third mask layer 1033, a second mask layer 1032 and a first mask layer 1031 in sequence on the top surface of the top isolation material layer 1021. The material of the first mask layer 1031 may include silicon oxide; the material of the second mask layer 1032 may include silicon nitride. The material of the first mask layer 1031 and the third mask layer 1033 can be the same, and the material of the first mask layer 1031 and the second mask layer 1032 is different.

[0099] As an example, please refer to Figures 8-12In step S1042, a first photoresist material layer can be coated on the top surface of the first mask layer 1031. After a series of steps such as exposure, development, photolithography, and etching, a patterned mask layer 103 and a patterned photoresist layer PR1 covering the patterned mask layer 103 are obtained. The patterned mask layer 103 has an opening pattern for defining the position and shape of the array region. In step S1043, the portions of the isolation material layer 1021 and the sacrificial material layer 1022 located outside the array region are etched based on the patterned mask layer 103. By repeating the "Trim+Etch" process, the lengths of the remaining functional layers 102 in the second direction of different layers are sequentially reduced in a direction away from the top surface of the substrate 101 along the first direction, forming a stacked structure including a stair step (SS). The remaining isolation material layer 1021 is used to form the isolation layer 30, and the remaining sacrificial material layer 1022 is used to form the sacrificial layer 1023.

[0100] As an example, please refer to Figures 8-12 After forming the stacked structure including the step structure, the method further includes forming a filling layer 105 by a deposition process to fill the step structure, and then polishing the top surface of the filling layer 105 and the top surface of the patterned mask layer 103 by a chemical mechanical polishing (CMP) process so that the top surface of the patterned mask layer 103 is flush with the top surface of the filling layer 105.

[0101] In some embodiments, please refer to Figure 13-Figure 23 , forming an array structure in step S106, further comprising:

[0102] Step S1061 : forming first trenches 1071 arranged in rows and columns along the second direction and the third direction in the array region. The first trenches 1071 penetrate the isolation layer 30 and the sacrificial layer 1023 along the first direction and expose a portion of the substrate 101 .

[0103] Step S1062 : etching back the sacrificial layer 1023 at least along the second direction through the first trench 1071 to obtain first grooves 1072 isolated from each other by the isolation layer 30 ; the connected first trenches 1071 and first grooves 1072 are used to form the first through hole 107 ;

[0104] Step S1063 : forming a channel layer 20 on the inner sidewall of the first through hole 107 , wherein the channel layer 20 includes a protrusion 21 located in the first groove 1072 ;

[0105] Step S1064 : forming a charge storage layer 50 on the side surface of the channel layer 20 and the bottom surface of the first through hole 107 ;

[0106] Step S1065 : forming a blocking layer 40 on the side surface of the charge storage layer 50 and the bottom surface of the charge storage layer 50 ;

[0107] Step S1066 : forming a first conductive structure 11 in the first through hole 107 .

[0108] As an example, please refer to Figure 13-Figure 23 In step S1061, a second photoresist material layer can be coated on the top surface of the patterned mask layer 103. After a series of steps such as exposure, development, photolithography, and etching, a patterned photoresist layer PR2 is formed. The patterned photoresist layer PR2 has an opening pattern for defining the position and shape of the first trench 1071. Then, an etching process is used to etch the array area using the patterned photoresist layer PR2 with the opening pattern as a mask, forming first trenches 1071 arranged in rows and columns along the second direction and the third direction in the array area. The first trenches 1071 penetrate the isolation layer 30 and the sacrificial layer 1023 along the first direction and expose a portion of the substrate 101. The etching process may include, but is not limited to, a dry etching process and / or a wet etching process. The dry etching process may include, but is not limited to, at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high concentration plasma etching (HDP).

[0109] As an example, please refer to Figure 13-Figure 23 In step S1062, an etching process can be used to etch back the sacrificial layer 1023 at least along the second direction through the first trench 1071 to obtain a first groove 1072 isolated from each other by the isolation layer 30; the connected first trench 1071 and the first groove 1072 are used to form a first through hole 107. As an example, please continue to refer to Figure 13-Figure 23In step S1063, a deposition process can be used to deposit a channel material layer 22 on the top surface of the filling layer 105, the top surface of the patterned mask layer 103, the inner sidewalls of the first trench 1071, and within the first recess 1072. The material of the channel layer 22 can be at least one of indium gallium zinc oxide (IGZO), doped single-crystal silicon, and polycrystalline silicon. A patterned photoresist layer PR3 is formed on the top surface of the channel material layer 22. The patterned photoresist layer PR3 has an opening pattern that defines the position and shape of the first trench 1071. An etching process is then used to etch the array area perpendicular to the top surface of the substrate based on the patterned photoresist layer PR3 with the opening pattern, removing the channel material layer 22 covering the top surface of the substrate 101. The remaining channel material layer 22 is used to form a channel layer 20 with a smooth inner surface. The channel layer 20 includes a protrusion 21 located within the first recess 1072. The channel material layer 22 is etched so that the inner surface of the formed channel layer 20 is smooth to avoid tip discharge, and the thickness of the channel layer 20 is set to a preset thickness, which can be 5nm-15nm. For example, the preset thickness can be 5nm, 7nm, 9nm, 11nm, 13nm or 15nm, etc.

[0110] As an example, please refer to Figure 13-Figure 23 In step S1064, a deposition process may be used to sequentially deposit a conformally covering third dielectric layer 53, a second dielectric layer 52, and a first dielectric layer 51 on the side surfaces of the channel layer 20 and the bottom surface of the first through hole 107 to form the charge storage layer 50. The material of the first dielectric layer 51 includes silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, hafnium zirconium oxide, zirconium oxide, yttrium oxide, and combinations thereof; the material of the second dielectric layer 52 includes silicon nitride, hafnium nitride, hafnium silicon nitride, hafnium aluminum nitride, hafnium zirconium nitride, zirconium nitride, yttrium nitride, and combinations thereof. The first dielectric layer 51 and the third dielectric layer 53 are made of the same material, while the first dielectric layer 51 and the second dielectric layer 52 are made of different materials.

[0111] As an example, please refer to Figure 13-Figure 23 In step S1065, a deposition process may be used to form a barrier layer 40 on the side surfaces and bottom surface of the charge storage layer 50. The barrier layer 40 may include a high-k dielectric layer, for example, with k ≥ 3.9. The material of the high-k dielectric layer includes aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, praseodymium oxide, and combinations thereof. For example, the material of the barrier layer 40 may be aluminum oxide. Thus, the first dielectric layer 51, the second dielectric layer 52, the third dielectric layer 53, and the barrier layer 40 together form an oxide-nitride-oxide-Al2O3 (ONOA) structure.

[0112] As an example, please refer to Figure 13-Figure 23 In step S1066, a deposition process may be used to form a first conductive structure 11 in the first through hole 107, and then a CMP process may be used to remove the blocking layer 40, the charge storage layer 50 and the channel layer 20 located on the top surface of the patterned mask layer 103 and the top surface of the filling layer 105.

[0113] In some embodiments, please refer to Figures 24-31 , the stepped structure is covered with a dielectric layer 1032; the array structure is formed in step S106, further comprising:

[0114] Step S1067: After filling the first conductive structure 11 in the first through hole 107 , forming isolation trenches 110 spaced apart along the third direction and extending along the second direction in the stacked structure; the isolation trenches 110 are located between adjacent channel layers 20 along the third direction;

[0115] Step S1068 : removing the sacrificial layer 1023 through the isolation trench 110 to obtain a second groove 111 located between the protrusions 21 of the channel layer 20 adjacent to each other along the second direction;

[0116] Step S1069: forming a second conductive structure 12 and a third conductive structure 13 in the second groove 111; the second conductive structures 12 and the third conductive structures 13 located at the periphery of the array structure, in the direction away from the substrate 101 along the first direction, the lengths of the second conductive structures 12 and the third conductive structures 13 of different layers along the second direction decrease successively and form steps.

[0117] As an example, please refer to Figures 24-31 In step S1067, a deposition process is used to first deposit a first cap layer 61 on the top surface of the filling layer 105 and the top surface of the patterned mask layer 103, and a patterned photoresist layer PR4 is formed on the top surface of the first cap layer 61. The patterned photoresist layer PR4 has an opening pattern for defining the position and shape of the isolation trench 110. Then, an etching process is used to etch the first cap layer 61, the patterned mask layer 103 and the stacked structure based on the patterned photoresist layer PR4 with the opening pattern, and isolation trenches 110 are formed in the stacked structure. The isolation trenches 110 are spaced apart along the third direction and extend along the second direction. The isolation trenches 110 are located between adjacent channel layers 20 along the third direction. The material of the first cap layer 61 can be selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and combinations thereof.

[0118] As an example, please refer to Figures 24-31 In step S1068 , an etching process may be used to remove the sacrificial layer 1023 through the isolation trench 110 to obtain a second groove 111 located between the protrusions 21 of the channel layer 20 adjacent to each other along the second direction.

[0119] In some embodiments, please refer to Figures 24-31 In step S1069 , the second conductive structure 12 and the third conductive structure 13 are formed in the second groove 111 , including:

[0120] Step S10691 : forming a conductive contact layer 113 on the side surface of the protruding portion of the channel layer 20 exposed by the second groove 111 ;

[0121] Step S10692 : forming a conductive layer 112 in the second groove 111 , electrically connected to the conductive contact layer 113 , wherein the conductive layer 112 and the conductive contact layer 113 are used to form the second conductive structure 12 and the third conductive structure 13 ;

[0122] Step S10693: forming an isolation structure in the second grooves 111 adjacent to each other along the second direction.

[0123] As an example, please refer to Figures 24-31 In step S10691, a deposition process can be used to form a conductive contact layer 113 on the side surface of the protruding portion of the channel layer 20 exposed by the second groove 111, and then a deposition process can be used to form a conductive layer 112 electrically connected to the conductive contact layer 113 in the second groove 111. The conductive layer 112 and the conductive contact layer 113 are used to jointly constitute the second conductive structure 12 and the third conductive structure 13. The material of the conductive contact layer 113 includes cobalt silicide, and the material of the conductive layer 112 can be selected from copper, tungsten, aluminum, copper alloy and combinations thereof.

[0124] In some embodiments, please refer to Figure 32-Figure 36 , forming an array structure in step S106, further comprising:

[0125] Step S1071 : After forming the second conductive structure 12 and the third conductive structure 13 , a bit line contact plug 71 is formed directly above the stepped structure.

[0126] Step S1072 : forming a word line extension 72 on the stacked structure in the array region.

[0127] As an example, please refer to Figure 32-Figure 36Step S1071 includes removing the conductive layer 112 on the top surface of the first capping layer 61 by an etching process, depositing a second capping layer 62 on the top surface of the first capping layer 61 by a deposition process to form a capping layer 60, and polishing the top surface of the capping layer 60 by a CMP process. A patterned photoresist layer PR5 is formed on the top surface of the capping layer 60, which is flush with the top surface. The patterned photoresist layer PR5 has an opening pattern for defining the position and shape of the plug trench 115. An etching process is then used to etch the capping layer 60 and the filling layer 105 based on the patterned photoresist layer PR5 having the opening pattern, forming the plug trench 115 directly above the stepped structure and on the stacked structure in the array region. A metal layer is deposited in the plug trench 115 by a deposition process, forming a bit line contact plug 71 directly above the stepped structure and a word line extension 72 on the stacked structure in the array region. The top surface of the capping layer 60 is then polished by a CMP process. The material of the bit line contact plug 71 can be selected from copper, tungsten, aluminum, copper alloy and combinations thereof, the material of the word line extension 72 can be selected from copper, tungsten, aluminum, copper alloy and combinations thereof, and the material of the second cap layer 62 can be selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and combinations thereof.

[0128] Please note that for the sake of simplicity of the specification, in the structural schematic diagrams given in the embodiments below, except for the schematic diagrams of the corresponding three-dimensional structure obtained separately, other structural schematic diagrams of different perspectives of structures related to the inventive points of the embodiments of the present disclosure can be referenced to each other.

[0129] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0130] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0131] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a first conductive structure extending along a first direction; a second conductive structure and a third conductive structure extending along a second direction, wherein the second conductive structure and the third conductive structure are alternately arranged in the first direction; a channel layer extending along the first direction, wherein the channel layer surrounds the first conductive structure; an isolation layer extending along the second direction, the isolation layer being located between the second conductive structure and the third conductive structure, the isolation layer being in contact with and connected to the channel layer; The channel layer has a plurality of protrusions extending in the second direction, and the second conductive structure and the third conductive structure are respectively in contact with and connected to corresponding protrusions; The second direction is perpendicular to the first direction.

2. The semiconductor structure according to claim 1, wherein: The protrusion includes at least two parts located on two opposite sides of the first conductive structure along the second direction.

3. The semiconductor structure according to claim 2, wherein: The protrusion surrounds an outer sidewall of the first conductive structure.

4. The semiconductor structure according to claim 2 or 3, characterized in that: In a direction along the first direction toward the bottom surface of the first conductive structure, the lengths of the second conductive structures and the third conductive structures of different layers along the second direction increase sequentially.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The channel layer circumferentially surrounds the first conductive structure; The semiconductor structure further comprises: The barrier layer circumferentially surrounds the sidewalls of the first conductive structure and covers the bottom surface of the first conductive structure.

6. The semiconductor structure according to claim 5, wherein: Also includes: The charge storage layer circumferentially surrounds the sidewalls of the blocking layer and covers the bottom surface of the blocking layer.

7. The semiconductor structure according to claim 6, wherein: The charge storage layer comprises: a first dielectric layer circumferentially surrounding the outer side wall of the barrier layer and covering the bottom surface of the barrier layer; a second dielectric layer circumferentially surrounding the outer side wall of the first dielectric layer and covering the bottom surface of the first dielectric layer; a third dielectric layer circumferentially surrounding the outer side wall of the second dielectric layer and covering the bottom surface of the second dielectric layer; The first dielectric layer and the third dielectric layer are made of the same material, and the first dielectric layer and the second dielectric layer are made of different materials.

8. A memory, characterized in that: comprising a substrate and an array structure located on the substrate, wherein the array structure comprises the semiconductor structure according to any one of claims 1 to 7 arranged in an array; The first conductive structures in the array structure all extend along the first direction and are arranged in rows and columns along the second direction and the third direction; the second direction intersects the third direction and is perpendicular to the first direction; The semiconductor structures adjacent to each other along the third direction are insulated from each other, and the second conductive structures or the third conductive structures of the semiconductor structures adjacent to each other along the second direction in the same layer are electrically connected; The second conductive structures or the third conductive structures of the semiconductor structures adjacent to each other along the first direction in different layers are insulated from each other.

9. The memory according to claim 8, wherein: In a direction away from the substrate along the first direction, the second conductive structures and the third conductive structures located in different layers at the periphery of the array structure have lengths that decrease in sequence along the second direction and form steps.

10. The memory according to claim 9, wherein: Also includes: a word line extension portion, located on the array structure and arranged corresponding to the first conductive structure; and / or The bit line contact plug is located at the periphery of the array structure and is arranged corresponding to the second conductive structure and the third conductive structure.

11. The memory according to claim 9, wherein: In a direction away from the substrate along the first direction, the heights of the bit line contact plugs corresponding to the protrusions of different layers decrease sequentially.

12. A method for preparing a memory, characterized in that: include: providing a substrate; forming isolation layers and sacrificial layers alternately stacked along a first direction on the substrate in sequence; forming an array structure, the array structure comprising a first conductive structure, a second conductive structure, a third conductive structure, and a channel layer, wherein the first conductive structure is arranged in rows and columns along a second direction and a third direction, the first conductive structure penetrates the isolation layer and the sacrificial layer along the first direction, and the second conductive structure and the third conductive structure are alternately arranged in the first direction and separated by the isolation layer; The channel layer extends along the first direction and surrounds the first conductive structure; The channel layer has a plurality of protrusions extending in the second direction, and the second conductive structure and the third conductive structure are respectively in contact with and connected to corresponding protrusions.

13. The preparation method according to claim 12, characterized in that Forming the isolation layer and the sacrificial layer includes: forming functional layers alternately stacked along the first direction on the substrate, the functional layers comprising isolation material layers and sacrificial material layers stacked along the first direction; forming a patterned mask layer on the top isolation material layer, wherein the patterned mask layer defines an array area for forming the array structure; Based on the etching of the isolation material layer and the sacrificial material layer located at the periphery of the array area using the patterned mask layer, the lengths of the remaining functional layers of different layers along the second direction decrease successively in the direction away from the substrate along the first direction, forming a stacked structure including a stepped structure; the remaining isolation material layer is used to constitute the isolation layer, and the remaining sacrificial material layer is used to constitute the sacrificial layer.

14. The preparation method according to claim 13, characterized in that The forming of the array structure further comprises: forming first trenches arranged in rows and columns along the second direction and the third direction in the array region, wherein the first trenches penetrate the isolation layer and the sacrificial layer along the first direction and expose a portion of the substrate; The sacrificial layer is etched back at least along the second direction through the first trench to obtain first grooves isolated from each other by the isolation layer; the first trench and the first groove that are connected are used to form a first through hole; forming a channel layer on an inner sidewall of the first through hole, wherein the channel layer includes the protrusion located in the first groove; forming a charge storage layer on the side surface of the channel layer and the bottom surface of the first through hole; forming a blocking layer on the side surface of the charge storage layer and the bottom surface of the charge storage layer; The first conductive structure is formed in the first through hole.

15. The preparation method according to claim 14, characterized in that The stepped structure is covered with a dielectric layer; the array structure is further comprised of: After the first conductive structure is filled in the first through hole, isolation trenches are formed in the stacked structure, which are spaced apart along the third direction and extend along the second direction; the isolation trenches are located between the channel layers adjacent to each other along the third direction; removing the sacrificial layer through the isolation trench to obtain a second groove located between protrusions of the channel layer adjacent to each other along the second direction; The second conductive structure and the third conductive structure are formed in the second groove; the second conductive structure and the third conductive structure are located at the periphery of the array structure, and the lengths of the second conductive structures and the third conductive structures of different layers along the second direction decrease successively in the direction away from the substrate along the first direction and form steps.

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