Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes: a plate layer; conductive layers spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer, extending different lengths in a second direction perpendicular to the first direction, and forming a stepped region; the gap filling insulating layer is positioned on the step region; and a vertical structure penetrating through the gap filling insulating layer and the conductive layer in the step region and extending in the first direction, and wherein the vertical structure extends in the first direction, the gap filling insulating layer includes voids disposed symmetrically about at least one of the vertical structures or a center of the step region in a third direction perpendicular to the first direction and the second direction.

Description

Technical Field

[0001] The disclosed subject matter generally relates to a semiconductor device having improved reliability and mass productivity and a data storage system including the semiconductor device having improved reliability and mass productivity. Background Art

[0002] In data storage systems, the demand for large-capacity semiconductor data storage devices has been growing. Therefore, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device including a three-dimensionally arranged storage cell instead of a two-dimensionally arranged storage cell has been proposed. Summary of the invention

[0003] According to some implementations of the present disclosure, a semiconductor device includes: a first semiconductor structure, the first semiconductor structure includes a substrate, a circuit device located on the substrate, and a circuit interconnection line located on the circuit device; and a second semiconductor structure, the second semiconductor structure is located on the first semiconductor structure, wherein the second semiconductor structure includes: a plate layer; a gate electrode, the gate electrodes are spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, extend different lengths in a second direction perpendicular to the first direction, and form a stepped region; a gap-filling insulating layer, the gap-filling insulating layer fills a region between the gate electrodes spaced apart from each other in the second direction in the stepped region; a channel structure, the channel structure penetrates at least a portion of the gate electrode and extends in the first direction; and a contact plug, the contact plug penetrates the gap-filling insulating layer and the gate electrode in the stepped region and extends in the first direction, wherein the gap-filling insulating layer extends along a side surface of the gate electrode and a side surface of the contact plug, and includes a gap spaced apart from the contact plug and the gate electrode.

[0004] According to some implementations of the present disclosure, a semiconductor device includes: a board layer; a conductive layer, the conductive layers on the board layer are spaced apart from each other along a first direction perpendicular to an upper surface of the board layer, extend different lengths in a second direction perpendicular to the first direction, and form a stepped region; a gap-filling insulating layer, the gap-filling insulating layer is located on the stepped region; and a vertical structure, the vertical structure penetrates the gap-filling insulating layer and the conductive layer in the stepped region and extends in the first direction, and wherein the gap-filling insulating layer includes gaps symmetrically arranged about the center of at least one of the vertical structures or the stepped region in a third direction perpendicular to the first direction and the second direction.

[0005] According to some implementations of the present disclosure, a data storage system includes: a semiconductor memory device, the semiconductor memory device including: a first semiconductor structure, the first semiconductor structure including a circuit device; a second semiconductor structure, the second semiconductor structure is located on a surface of the first semiconductor structure; and an input / output pad, the input / output pad is electrically connected to the circuit device; and a controller, the controller is electrically connected to the semiconductor memory device through the input / output pad and is configured to control the semiconductor memory device, wherein the second semiconductor structure includes: a plate layer; a gate electrode, the gate electrodes are spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, extend different lengths in a second direction perpendicular to the first direction, and form a stepped region; a gap-filling insulating layer, the gap-filling insulating layer is located on the stepped region; and a contact plug, the contact plug penetrates the gap-filling insulating layer and the stepped region and extends in the first direction, and wherein the gap-filling insulating layer includes a gap therein that is spaced apart from the contact plug and the gate electrode.

[0006] According to some implementations of the present disclosure, a method for manufacturing a semiconductor device includes: forming a mold structure by alternately stacking sacrificial insulating layers and interlayer insulating layers on a board layer; forming a step region having a step structure by partially removing the mold structure; forming a gap-filling sacrificial layer filling the step region; forming a vertical sacrificial layer penetrating the gap-filling sacrificial layer and the mold structure; removing the gap-filling sacrificial layer; and forming a gap-filling insulating layer including a void therein in the region from which the gap-filling sacrificial layer is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a top view illustrating a semiconductor device according to some implementations of the present disclosure;

[0009] Figure 2A and Figure 2B is a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0010] FIG. 3A to FIG. 4B is an enlarged view illustrating a portion of a semiconductor device according to some implementations of the present disclosure;

[0011] Figure 5A and Figure 5B is a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0012] Fig. 6A and Figure 6B are respectively a top view and a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0013] Figure 7 is a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0014] Figure 8 is a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0015] Fig. 9 is a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0016] Fig. 10A and Fig. 10B is a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0017] Fig.11 is a cross-sectional view illustrating a semiconductor device according to some implementations of the present disclosure;

[0018] Fig.12 is a flow chart illustrating a method of manufacturing a semiconductor device according to some implementations of the present disclosure;

[0019] FIG. 13A to FIG. 13O is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some implementations of the present disclosure;

[0020] Fig.14 is a diagram illustrating a data storage system including a semiconductor device according to some implementations of the present disclosure;

[0021] Fig.15 is a perspective view illustrating a data storage system including a semiconductor device according to some implementations of the present disclosure; and

[0022] Fig.16 is a cross-sectional view illustrating a semiconductor package according to some implementations of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, implementations of the present disclosure will be described below with reference to the accompanying drawings.

[0024] Figure 1 is a top view illustrating a semiconductor device according to some implementations.

[0025] Figure 2A and Figure 2B are respectively along Figure 1Schematic diagrams taken along lines II′ and II-II′ in FIG. 1 are cross-sectional views of a semiconductor device according to some implementations.

[0026] FIG. 3A to FIG. 4B is an enlarged view illustrating a portion of a semiconductor device according to some implementations. Figure 3A It's a picture. Figure 2A A magnified view of area "A" in Figure 3B It's a picture. Figure 2A A magnified view of area "B" in Figure 4A It's a picture. Figure 2A A magnified view of area "C" in FIG. Figure 4B It's a picture. Figure 2A Magnified view of area "D" in FIG.

[0027] refer to Figures 1 to 4B , the semiconductor device 100 includes a peripheral circuit region PERI and a memory cell region CELL, the peripheral circuit region PERI is a first semiconductor structure including a substrate 201, and the memory cell region CELL is a second semiconductor structure including a board layer 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. In some implementations, on the contrary, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

[0028] The peripheral circuit region PERI includes a substrate 201 , an impurity region 205 and a device isolation layer 210 located in the substrate 201 , a circuit device 220 disposed on the substrate 201 , a peripheral region insulating layer 290 , a circuit contact plug 270 , and a circuit interconnection line 280 .

[0029] The substrate 201 may have an upper surface extending in the X direction and the Y direction. In the substrate 201, the active region may be defined by the device isolation layer 210. An impurity region 205 including impurities may be provided in a portion of the active region. The substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0030] The circuit devices 220 may include planar transistors. Each circuit device 220 includes a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The impurity regions 205 may be disposed on both sides of the circuit gate electrode 225 in the substrate 201 as source / drain regions.

[0031] The peripheral region insulating layer 290 may be disposed on the circuit device 220 on the substrate 201. The peripheral region insulating layer 290 may include a plurality of insulating layers formed in different processes. The peripheral region insulating layer 290 may be formed of an insulating material.

[0032] The circuit contact plug 270 and the circuit interconnection line 280 may form a circuit interconnection structure electrically connected to the circuit device 220 and the impurity region 205. The circuit contact plug 270 may have a cylindrical shape, and the circuit interconnection line 280 may have a line shape. An electrical signal may be applied to the circuit device 220 through the circuit contact plug 270 and the circuit interconnection line 280. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit interconnection line 280 may be connected to the circuit contact plug 270, may have a line shape, and may be arranged in multiple layers. The circuit contact plug 270 and the circuit interconnection line 280 may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may also include a diffusion barrier layer (barrier). In some implementations, the number of layers of the circuit contact plug 270 and the number of layers of the circuit interconnection line 280 may vary.

[0033] The memory cell region CELL has a first region R1 and a second region R2, and includes: a source structure SS; a gate electrode 130, which is stacked on the source structure SS and forms a step region GP in the second region R2; an interlayer insulating layer 120, which is alternately stacked with the gate electrode 130; a first channel structure CH and a second channel structure SCH, which are arranged as a stack structure GS penetrating the gate electrode 130 in the first region R1; a first isolation region MS, which extends by penetrating the gate electrode 130; a second isolation region US, which penetrates a portion of the gate electrode 130 arranged on the upper portion; a gap-filling insulating layer 150, which covers an end of the gate electrode 130 and fills the step region GP, ​​for example, the gap-filling insulating layer 150 fills a region between a plurality of gate electrodes 130 spaced apart from each other in the X direction in a plurality of step regions GP; and a contact plug 170, which is connected to the gate electrode 130 and extends vertically in the second region R2.

[0034] The memory cell region CELL includes a horizontal sacrificial layer 110 arranged below the gate electrode 130 in the second region R2, a substrate insulating layer 121 arranged to penetrate the plate layer 101, a side surface insulating layer arranged around the contact plug 170, a first unit insulating layer 152 of a stacked structure GS covering the gate electrode 130, a second unit insulating layer 154 covering the side surface of the contact plug 170, a third unit insulating layer 156 located on the gap-filling insulating layer 150, a horizontal insulating layer 158 located on the third unit insulating layer 156, an upper insulating layer 190 located on the horizontal insulating layer 158, and a stud 180 located on the second channel structure SCH and the contact plug 170.

[0035] In the memory cell region CELL, in the first region R1, the gate electrodes 130 may be vertically stacked and the first channel structure CH may be provided, and the memory cell may be provided in the first region R1. In the second region R2, the gate electrodes 130 may extend to different lengths and may form a step region GP, ​​and the second region R2 may be configured to electrically connect the memory cell to the peripheral circuit region PERI. The second region R2 may be provided on at least one end of the first region R1 in at least one direction (e.g., X direction).

[0036] The source structure SS includes a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 sequentially stacked in the first region R1. However, in some implementations, the number of conductive layers included in the source structure SS may vary.

[0037] The plate layer 101 may have a plate shape and may be used as at least a portion of a common source line of the semiconductor device 100. The plate layer 101 may have an upper surface extending in the X direction and the Y direction. The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The plate layer 101 may also include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer such as a polysilicon layer or an epitaxial layer.

[0038] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked on the upper surface of the plate layer 101 in the first region R1. The first horizontal conductive layer 102 may not extend to the second region R2, while the second horizontal conductive layer 104 may extend to the second region R2. For example, the first horizontal conductive layer 102 may be used as a part of a common source line of the semiconductor device 100, and may be used as a common source line together with the plate layer 101. Figure 4B As illustrated, the first horizontal conductive layer 102 may surround the channel layer 140 and be directly connected to the channel layer 140 .

[0039] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material such as polysilicon. In this case, at least the first horizontal conductive layer 102 may be a layer doped with impurities having the same conductivity as that of the plate layer 101, and the second horizontal conductive layer 104 may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102.

[0040] The horizontal sacrificial layer 110 may be disposed on the board layer 101 at the same height as that of the first horizontal conductive layer 102 in at least a portion of the second region R2. The horizontal sacrificial layer 110 includes first horizontal sacrificial layers 111 and second horizontal sacrificial layers 112 alternately stacked on the second region R2 of the board layer 101. The horizontal sacrificial layer 110 may be a layer remaining after a portion thereof is replaced with the first horizontal conductive layer 102 during a manufacturing process.

[0041] The horizontal sacrificial layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 may include different insulating materials. For example, the first horizontal sacrificial layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal sacrificial layer 112 may be formed of a material different from the material of the interlayer insulating layer 120.

[0042] The substrate insulating layer 121 may be disposed to penetrate the plate layer 101, the horizontal sacrificial layer 110, and the second horizontal conductive layer 104 in a portion of the second region R2. The substrate insulating layer 121 may be further disposed in the first region R1, and, for example, may be disposed in a region in which a through-path extending from the memory cell region CELL to the peripheral circuit region PERI is disposed. The upper surface of the substrate insulating layer 121 may be coplanar with the upper surface of the second horizontal conductive layer 104. The substrate insulating layer 121 may include an insulating material such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0043] The gate electrodes 130 may be stacked vertically on the plate layer 101 and spaced apart from each other, and a portion thereof may form a stacked structure GS together with the interlayer insulating layer 120. The gate electrode 130 includes a first upper gate electrode 130U1 included in a string selection transistor, a second upper gate electrode 130U2 included in an erase transistor, a storage gate electrode 130M included in a plurality of memory cells, a first lower gate electrode 130L1 included in an erase transistor, and a second lower gate electrode 130L2 forming a ground selection transistor. The number of storage gate electrodes 130M included in a memory cell may be determined according to the capacity of the semiconductor device 100. The first upper gate electrode 130U1 and the second lower gate electrode 130L2 may also be referred to as an upper selection gate electrode and a lower selection gate electrode, respectively. In some implementations, each of the number of the first upper gate electrodes 130U1, the number of the second upper gate electrodes 130U2, the number of the first lower gate electrodes 130L1, and the number of the second lower gate electrodes 130L2 may be 1 to 4 or more. Each of the first upper gate electrode 130U1 , the second upper gate electrode 130U2 , the first lower gate electrode 130L1 , and the second lower gate electrode 130L2 may have a structure that is the same as or different from that of the memory gate electrode 130M.

[0044] In some implementations, the positions of the first upper gate electrode 130U1 and the second upper gate electrode 130U2 may be interchanged, or the positions of the first lower gate electrode 130L1 and the second lower gate electrode 130L2 may be interchanged. In some implementations, the second upper gate electrode 130U2 and / or the first lower gate electrode 130L1 may not be provided. In some implementations, a dummy gate electrode may be additionally provided.

[0045] The gate electrodes 130 may be vertically stacked and spaced apart from each other on the first region R1, may extend to different lengths from the first region R1 to the second region R2, and may form step structures ST1 and ST2 in a step region GP. However, the first upper gate electrode 130U1 may extend to a relatively short length and may not form the step region GP. Figure 2A As illustrated, the gate electrode 130 may have a shape removed from the upper portion of the step region GP to a predetermined depth, and the step region GP may have different depths. The step region GP may have a shape in which its depth may increase in a direction away from the first region R1 along the X direction, but the implementation is not limited thereto. The gate electrode 130 may form a dummy structure between the step regions GP. The height of the uppermost surface of the dummy structure may be the same, but the implementation is not limited thereto. In some implementations, the height of the uppermost surface of the dummy structure may decrease in a direction away from the first region R1 along the X direction.

[0046] The gate electrode 130 may form a first step structure ST1 and a second step structure ST2 in a symmetrical or asymmetrical form in each step region GP in the X direction. The first step structure ST1 may have a step structure relatively adjacent to the first region R1 and having a height reduced in the X direction. The second step structure ST2 may be a step structure disposed at a position spaced apart from the first region R1 and having a height increased in the X direction. For example, in each step region GP, ​​the slope of the first step structure ST1 may be equal to or less than the slope of the second step structure ST2.

[0047] In some implementations, the specific shape of the step region GP and the specific shapes of the first and second step structures ST1 and ST2 and the number of gate electrodes 130 included in the first and second step structures ST1 and ST2 are not limited to Figure 2A In some implementations, the gate electrode 130 may be provided to have a step structure in the Y direction.

[0048] Using the first stepped structure ST1 and the second stepped structure ST2, the gate electrodes 130 may have contact regions 130P, respectively, wherein the lower gate electrode 130 may extend longer than the upper gate electrode 130 and may be exposed upward from the interlayer insulating layer 120. The gate electrodes 130 may be connected to the contact plugs 170 in the contact regions 130P as end regions, respectively. The gate electrode 130 excluding the first upper gate electrode 130U1 may have an increased thickness in the contact region 130P.

[0049] The gate electrode 130 may include a metal material such as tungsten (W), or may include polysilicon or a metal silicide material. For example, the first upper gate electrode 130U1 may include polysilicon, and the other gate electrodes 130 may include a metal material. In some implementations, the gate electrode 130 may also include a diffusion barrier layer, and for example, the diffusion barrier layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0050] The interlayer insulating layer 120 may be disposed between the gate electrodes 130 except the first upper gate electrode 130U1. Similar to the gate electrodes 130, the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of the plate layer 101 and may extend in the X direction. The interlayer insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride.

[0051] The first channel structure CH may penetrate the gate electrode 130 other than the first upper gate electrode 130U1, may extend in the Z direction, and may be connected to the plate layer 101. The first channel structure CH may form a memory cell string together with the second channel structure SCH, and may be spaced apart from each other while forming rows and columns on the plate layer 101 in the first region R1. The first channel structure CH may be arranged to form a lattice pattern on the XY plane or to be formed in a zigzag pattern in one direction. The first channel structure CH may have a columnar shape and may have an inclined side surface whose width decreases toward the plate layer 101. At least a portion of the first channel structure CH (including the first channel structure CH disposed on the end of the first region R1) may be a dummy channel structure.

[0052] like Figure 4A and Figure 4BAs illustrated, each first channel structure CH includes a first channel layer 140 disposed in a lower channel hole, a first gate dielectric layer 145, a first channel filling insulating layer 147, and a first channel pad 149. The first channel layer 140 may be formed in a ring shape surrounding the first channel filling insulating layer 147 inside, or in some implementations, the first channel layer 140 may have a columnar shape such as a cylindrical shape or a prism shape without the first channel filling insulating layer 147. The first channel layer 140 may be connected to the first horizontal conductive layer 102 in a lower portion. The first channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon.

[0053] The first gate dielectric layer 145 may be disposed between the gate electrode 130 and the first channel layer 140. Although not specifically illustrated, the first gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the first channel layer 140. The tunneling layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-κ dielectric material, or a combination thereof. In some implementations, at least a portion of the first gate dielectric layer 145 may extend in a horizontal direction along the gate electrode 130. The first channel pad 149 may be disposed on an upper end of the first channel structure CH. The first channel pad 149 may include, for example, doped polysilicon.

[0054] The second channel structures SCH may penetrate the first upper gate electrode 130U1 , may extend in the Z direction, and may be connected to the first channel structures CH, respectively. The second channel structures SCH may be disposed on the first channel structures CH, respectively, and may be horizontally shifted from the first channel structures CH, but some implementations are not limited thereto.

[0055] like Figure 4AAs illustrated, each second channel structure SCH includes a second channel layer 160 disposed in an upper channel hole, a connection pad 161, a second gate dielectric layer 165, a second channel filling insulating layer 167, and a second channel pad 169. The second channel layer 160 may be formed in a ring shape surrounding the second channel filling insulating layer 167. The second channel layer 160 may be connected to the connection pad 161 in a lower portion, and may be electrically connected to the first channel layer 140 of the first channel structure CH through the connection pad 161. The connection pad 161 may be disposed below the second channel layer 160 and may be partially recessed into the first channel pad 149. In some implementations, the connection pad 161 and the second channel layer 160 may be integrated with each other.

[0056] The description of the materials of the first channel layer 140, the first gate dielectric layer 145, the first channel filling insulating layer 147, and the first channel pad 149 described above may be respectively applicable to the description of the materials of the second channel layer 160, the second gate dielectric layer 165, the second channel filling insulating layer 167, and the second channel pad 169. The connection pad 161 may include a conductive material, such as polysilicon.

[0057] The first isolation region MS may penetrate at least a portion of the gate electrode 130 and may extend in the X direction. Figure 1 As shown, the first isolation regions MS may be arranged parallel to each other. Figure 2B As shown, the first isolation region MS may penetrate the gate electrode 130 stacked on the plate layer 101, may further penetrate the first horizontal conductive layer 102 and the second horizontal conductive layer 104, and may be connected to the plate layer 101. The first isolation region MS may be arranged to penetrate the gate electrode 130 except the first upper gate electrode 130U1. A portion of the isolation region MS may extend along the first region R1 and the second region R2 as an integrated region, and another portion may extend only to a portion of the second region R2, or may be intermittently arranged in the first region R1 and the second region R2. However, in some implementations, the arrangement form of the first isolation region MS and the number of the first isolation region MS are not limited to Figure 1 An example is shown in the figure.

[0058] A gate isolation insulating layer 105 may be disposed in each first isolation region MS. The gate isolation insulating layer 105 may have a shape whose width may decrease toward the plate layer 101 due to a high aspect ratio. The gate isolation insulating layer 105 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0059] like Figure 1As illustrated, the second isolation region US may extend in the X direction between the first isolation regions MS adjacent to each other. The second isolation region US may be disposed in a portion of the second region R2 and the first region R1. The second isolation region US may penetrate the first upper gate electrode 130U1 disposed in the uppermost portion of the gate electrode 130. The second isolation region US may divide the first upper gate electrode 130U1 in the Y direction.

[0060] The gap-filling insulating layer 150 may cover the end of the gate electrode 130 except the first upper gate electrode 130U1 and may fill the step region GP. The gap-filling insulating layer 150 may extend with a substantially constant thickness along the end of the gate electrode 130 and the side surface of the contact plug 170. The gap-filling insulating layer 150 may extend with a substantially constant thickness along the gate electrode 130 and the contact plug 170 in the step region GP.

[0061] The gap-fill insulating layer 150 may have a void VD therein. The void VD may include a gas and may also be referred to as an air gap. The void VD may be spaced apart from the stack structure GS and the contact plug 170. The void VD may be spaced apart from the gate electrode 130. The void VD may be disposed between the contact plugs 170 and between the contact plug 170 and the stack structure GS. The void VD may also be disposed between the contact plug 170 and the first isolation region MS. Figure 2B As shown, in the cross section in the Y direction, the voids VD may be symmetrically disposed on both sides of the contact plug 170 with the contact plug 170 as the center. In the cross section in the Y direction, the voids VD may be symmetrically disposed about the center of the step region GP. The gap-filling insulating layer 150 may be formed by replacing the gap-filling sacrificial layer 116 (refer to Fig.13D ) is formed so that the gap VD can be set therein, which will be referred to below FIG. 13A to FIG. 13O This is described in more detail.

[0062] The void VD may include a lower region having a stepped shape corresponding to the shape of the step region GP. In the lower region, the void VD may have a stepped shape of the step region GP or a step structure thereof may be relaxed or relieved when corresponding to the stepped shape of the step region GP. The thickness of the gap filling insulating layer 150 surrounding the void VD may be substantially constant, and the thickness may vary in some implementations. Therefore, the size of the void VD may vary. In some implementations, when the distance between the contact plugs 170 is relatively short or the thickness of the gap filling insulating layer 150 is relatively large, the void VD may not exist between some contact plugs 170.

[0063] The first unit insulating layer 152 may be a capping insulating layer that conformally covers the stacked structure GS. The first unit insulating layer 152 may cover the side surfaces of the gate electrode 130 and the side surfaces of the interlayer insulating layer 120 included in the stacked structure GS, and may cover the upper surface of the stacked structure GS, for example, the upper surface of the second upper gate electrode 130U2. The first unit insulating layer 152 may be in contact with the gap-filling insulating layer 150.

[0064] The second unit insulating layer 154 may cover a portion of a side surface of the contact plug 170. Specifically, the second unit insulating layer 154 may be interposed between the side surface of the contact plug 170 and the gap-filling insulating layer 150. The second unit insulating layer 154 may be disposed on the first unit insulating layer 152, and may be disposed below the third unit insulating layer 156 in the Z direction. An inner side surface of the second unit insulating layer 154 may contact the contact plug 170, and an outer side surface of the second unit insulating layer 154 may contact the gap-filling insulating layer 150. The second unit insulating layer 154 may be an oxide layer formed by an oxidation process.

[0065] The third unit insulating layer 156 may be disposed on the gap-filling insulating layer 150 and the stacked structure GS and may extend horizontally in the first region R1 and the second region R2. The third unit insulating layer 156 may support the mold structure including the interlayer insulating layer 120 during the manufacturing process. Figure 3A As illustrated, the third unit insulating layer 156 includes an opening OP spaced apart from the contact plug 170. The opening OP may be filled with the gap-filling insulating layer 150. In some implementations, the size of the opening OP and the arrangement of the opening OP may vary. In some implementations, the third unit insulating layer 156 may not be provided.

[0066] The first cell insulating layer 152 , the second cell insulating layer 154 , and the third cell insulating layer 156 may include an insulating material, and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0067] The horizontal insulating layer 158 may be disposed between the first channel structure CH and the second channel structure SCH, and may extend horizontally in the first region R1 and the second region R2. The horizontal insulating layer 158 may be disposed between the first upper gate electrode 130U1 and the second upper gate electrode 130U2. The horizontal insulating layer 158 may be used as an etching stop layer when forming the second channel structure SCH, and may also be used when forming the connection pad 161.

[0068] The horizontal insulating layer 158 may include an insulating material and may include a material different from those of the gap-fill insulating layer 150, the third unit insulating layer 156, and the upper insulating layer 190. The horizontal insulating layer 158 may include a nitride and may include, for example, at least one of SiN, SiON, SiCN, and SiOCN.

[0069] An upper insulating layer 190 may be disposed to cover the contact plug 170 on the horizontal insulating layer 158. The upper insulating layer 190 may be formed of an insulating material, and may also include a plurality of insulating layers.

[0070] The contact plug 170 may be connected to the contact region 130P disposed in the uppermost portion of the gate electrode 130 in the step region GP of the second region R2. Figure 1 The arrangement form in the top view in FIG. 1 may vary. The contact plug 170 may penetrate at least a portion of the upper insulating layer 190 and the gap-filling insulating layer 150, and may be respectively connected to the contact region 130P of the gate electrode 130 exposed upward. The contact plug 170 may penetrate the gate electrode 130 below the contact region 130P, may penetrate the second horizontal conductive layer 104, the horizontal sacrificial layer 110, and the board layer 101, and may be connected to the circuit interconnection line 280 in the peripheral circuit region PERI. The contact plug 170 may be spaced apart from the gate electrode 130 disposed below the contact region 130P by the side surface insulating layer 125. The contact plug 170 may be spaced apart from the board layer 101, the horizontal sacrificial layer 110, and the second horizontal conductive layer 104 by the substrate insulating layer 121. However, in some implementations, the contact plug 170 may be arranged not to penetrate the gate electrode 130. In this case, the contact plug 170 may be respectively connected to the contact region 130P of the gate electrode 130 exposed upward. In some implementations, each contact plug 170 may further include a landing region whose width may extend below the substrate insulating layer 121 .

[0071] The contact plug 170 may be spaced apart from the void VD in the gap-filling insulating layer 150. The contact plug 170 may penetrate the gap-filling insulating layer 150 without penetrating or contacting the void VD. Therefore, the contact plug 170 may have a stable pillar shape without defects such as distortion and twisting.

[0072] like Figure 3AAs illustrated, each contact plug 170 may have a bent portion BE whose width may be discontinuously changed under the horizontal insulating layer 158. The bent portion BE may be disposed in the third unit insulating layer 156 and may vary within a range disposed under a lower surface of the horizontal insulating layer 158. In some implementations, the contact plug 170 may not have the bent portion BE.

[0073] like Figure 3B As shown, each contact plug 170 may have a horizontally extending form in the contact region 130P. The contact plug 170 includes a vertical extension portion 170V extending in the Z direction and a horizontal extension portion 170H extending horizontally from the vertical extension portion 170V and contacting the gate electrode 130. The horizontal extension portion 170H may be arranged along the circumference of the vertical extension portion 170V, and its entire side surface may be surrounded by the gate electrode 130. The length from the side surface of the vertical extension portion 170V to the end of the horizontal extension portion 170H may be less than the length from the side surface of the vertical extension portion 170V to the outer side surface of the side surface insulating layer 125. The contact plug 170 may be spaced apart from the gate electrode 130 (i.e., the gate electrode 130 not electrically connected) disposed below the contact region 130P by the side surface insulating layer 125.

[0074] The contact plug 170 may include at least one of the following conductive materials: for example, tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some implementations, the contact plug 170 may include a barrier layer extending along side and bottom surfaces, or may have an air gap therein.

[0075] The side surface insulating layer 125 may be disposed to surround the side surface of each contact plug 170 below the contact region 130P. The side surface insulating layers 125 may be spaced apart from each other in the Z direction around each contact plug 170. The side surface insulating layer 125 may be disposed at a height substantially the same as that of the gate electrode 130. The side surface insulating layer 125 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0076] The short column 180 may be included in a cell interconnect structure electrically connected to a memory cell in the memory cell region CELL. The short column 180 may be connected to the second channel structure SCH and the contact plug 170, and may be electrically connected to the first channel structure CH and the second channel structure SCH and the gate electrode 130. The short column 180 may have a plug shape, but the implementation is not limited thereto. In some implementations, the short column 180 may have a line shape. In some implementations, the number of plugs included in the cell interconnect structure and the number of interconnect lines may vary. The short column 180 may include a metal, for example, tungsten (W), copper (Cu) or aluminum (Al).

[0077] Figure 5A and Figure 5B is a cross-sectional view illustrating a semiconductor device according to some implementations, the cross-sectional view illustrated corresponds to Figure 2A .

[0078] refer to Figure 5A In the semiconductor device 100a, in each step region GP, ​​the slope of the first step structure ST1 may be smaller than the slope of the second step structure ST2. The step shape of the first step structure ST1 may be relatively gentle, while the step shape of the second step structure ST2 may be relatively steep.

[0079] Likewise, in some implementations, in the first stepped structure ST1, the gate electrode 130 may be connected to the contact plug 170, and in the second stepped structure ST2, the gate electrode 130 may form a dummy region or a dummy structure that is not connected to the contact plug 170. The relative inclinations of the first stepped structure ST1 and the second stepped structure ST2 and the arrangement positions of the contact plugs 170 may be independently combined with other implementations.

[0080] refer to Figure 5B The semiconductor device 100b includes a first stacked structure GS1 and a second stacked structure GS2, respectively arranged in the lower part and the upper part, a first gap-filling insulating layer 150L and a second gap-filling insulating layer 150U, a first lower unit insulating layer 152L and a first upper unit insulating layer 152U, a second lower unit insulating layer 154L and a second upper unit insulating layer 154U, and a third lower unit insulating layer 156L and a third upper unit insulating layer 156U.

[0081] In some implementations, the number of stacked structures GS1 and GS2 stacked in the Z direction may vary. For example, in some implementations, the gate electrodes 130 may form three or more stacked structures. The number of gate electrodes 130 included in the first stacked structure GS1 and the number of gate electrodes 130 included in the second stacked structure GS2 may be the same or different.

[0082] The gate electrode 130 may have a shape in which a predetermined depth is removed from the upper portion of one of the first stacked structure GS1 and the second stacked structure GS2 in the step region GP. The step region GP may be arranged not to overlap each other in the Z direction. On the step region GP of the first stacked structure GS1, at least a portion of the gate electrode 130 included in the upper second stacked structure GS2 may extend horizontally. In some implementations, the arrangement type, arrangement order, and depth of the step region GP may vary. In some implementations, the gate electrode 130 may not be arranged on the step region GP.

[0083] The first channel structure CH includes a lower channel structure CH1 and an upper channel structure CH2 vertically stacked. The first channel structure CH may have a form in which the lower channel structure CH1 and the upper channel structure CH2 are connected to each other, and may have a bent portion due to a width difference in a connection region.

[0084] The contact plugs 170 may have a shape corresponding to the channel structure CH. Each of the contact plugs 170 may include a lower region and an upper region penetrating the first and second stack structures GS1 and GS2, respectively.

[0085] The first gap-filling insulating layer 150L, ​​the first lower unit insulating layer 152L, the second lower unit insulating layer 154L, and the third lower unit insulating layer 156L may be disposed on the first stacked structure GS1. The second gap-filling insulating layer 150U, the first upper unit insulating layer 152U, the second upper unit insulating layer 154U, and the third upper unit insulating layer 156U may be disposed on the second stacked structure GS2. The first gap-filling insulating layer 150L may fill the step region GP of the first stacked structure GS1, and the second gap-filling insulating layer 150U may fill the step region GP of the second stacked structure GS2. In addition to the above differences, reference FIG. 2A to FIG. 3B The description described may also be applied to the first lower cell insulation layer 152L and the first upper cell insulation layer 152U, the second lower cell insulation layer 154L and the second upper cell insulation layer 154U, and the third lower cell insulation layer 156L and the third upper cell insulation layer 156U.

[0086] Fig. 6A and Figure 6B Along the Fig. 6A FIG. 4 shows a top view and a cross-sectional view of a semiconductor device according to some implementations, as shown in FIG.

[0087] refer to Fig. 6A and Figure 6B , in the semiconductor device 100c, the memory cell region CELL further includes a support structure DH.

[0088] like Fig. 6A As shown, the support structure DH may be disposed on the corner of each contact region 130P in the second region R2. The support structure DH may be disposed so that four support structures DH may surround the contact plug 170. However, in some implementations, the arrangement type and size of the support structure DH may vary. For example, in some implementations, the support structure DH may be disposed on the end of the gate electrode 130.

[0089] The support structure DH may be disposed below the horizontal insulating layer 158 and may support the molded structure including the interlayer insulating layer 120 during the process of manufacturing the semiconductor device 100c. The support structure DH may be referred to as a vertical structure together with the contact plug 170 and / or the first channel structure CH. The support structure DH may penetrate the stacked structure GS, the second horizontal conductive layer 104, and the horizontal sacrificial layer 110, and the lower end of the support structure DH may be disposed in the plate layer 101. The upper end of the support structure DH may be disposed at a height substantially the same as the height of the upper end of the first channel structure CH, but the implementation is not limited thereto. The support structure DCH may include an insulating material, and may include, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0090] The gap-filling insulating layer 150 has a void VD disposed between the support structures DH. The void VD may be isolated from the support structure DH. In a cross section not shown, the void VD may be further disposed between the stacked structure GS and the support structure DH and between the contact plug 170 and the support structure DH. In some implementations, the void VD may be further disposed between the support structure DH and the first isolation region MS.

[0091] Figure 7 is a cross-sectional view illustrating a semiconductor device according to some implementations, Figure 7 The diagram in can correspond to Figure 2B The area shown in the figure.

[0092] refer to Figure 7 , in the semiconductor device 100 d , the stack structure GS includes a wall region WS.

[0093] The wall region WS may be disposed on both side surfaces of the first isolation region MS in the Y direction. The wall region WS may have a form in which the entirety of the gate electrode 130 below the second upper gate electrode 130U2 may be stacked, and the gate electrode 130 included in the wall region WS may be connected to the gate electrode 130 included in the step region GP. Therefore, the length of the step region GP in the Y direction may be less than the length between adjacent first isolation regions MS in the Y direction. In some implementations, the relative lengths of the wall region WS and the first isolation region MS in the Y direction may vary.

[0094] Figure 8 is a cross-sectional view illustrating a semiconductor device according to some implementations.

[0095] refer to Figure 8 , the semiconductor device 100e includes a first semiconductor structure S1 and a second semiconductor structure S2 bonded to each other by a wafer bonding method.

[0096] refer to Figures 1 to 2BThe description of the peripheral circuit region PERI described in the aforementioned implementation may be applicable to the first semiconductor structure S1. However, the first semiconductor structure S1 further includes a first bonding path 295, a first bonding metal layer 298, and a first bonding insulating layer 299 as a bonding structure. The first bonding path 295 may be disposed above the uppermost circuit interconnection line 280 and may be connected to the circuit interconnection line 280. At least a portion of the first bonding metal layer 298 may be connected to the first bonding path 295 on the first bonding path 295. The first bonding metal layer 298 may be connected to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 may provide an electrical connection path together with the second bonding metal layer 198 according to the bonding between the first semiconductor structure S1 and the second semiconductor structure S2. A portion of the first bonding metal layer 298 may be provided for bonding without being connected to the lower circuit interconnection line 280. The first bonding path 295 and the first bonding metal layer 298 may include a conductive material such as copper (Cu). The first bonding insulating layer 299 may be disposed around the first bonding metal layer 298. The first bonding insulating layer 299 may also serve as a diffusion barrier layer of the first bonding metal layer 298 , and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0097] For the second semiconductor structure S2, unless otherwise indicated, refer to Figures 1 to 4B The description of the memory cell region CELL described in the aforementioned implementation may be applicable. The second semiconductor structure S2 may further include a cell interconnection line 185 as a cell interconnection structure, and may further include a second bonding via 195, a second bonding metal layer 198, and a second bonding insulating layer 199 as a bonding structure. The second semiconductor structure S2 may further include a passivation layer 106 covering the upper surface of the plate layer 101.

[0098] The cell interconnection line 185 may be connected to the short pillar 180. However, in some implementations, the number of layers and arrangement of the plugs and interconnection lines included in the cell interconnection structure may vary. The cell interconnection line 185 may be formed of a conductive material and may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).

[0099] The second bonding via 195 and the second bonding metal layer 198 may be disposed below the uppermost cell interconnection line 185. The second bonding via 195 may connect the cell interconnection line 185 to the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 may be bonded and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 195 and the second bonding metal layer 198 may include a conductive material such as copper (Cu). The second bonding insulating layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0100] The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other through bonding between the first bonding metal layer 298 and the second bonding metal layer 198 and bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding between the first bonding metal layer 298 and the second bonding metal layer 198 may be, for example, copper (Cu) to copper (Cu) bonding, and the bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199 may be, for example, dielectric to dielectric bonding, such as SiCN to SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other through a hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0101] The passivation layer 106 may be disposed on the upper surface of the plate layer 101 and may protect the semiconductor device 100f. The passivation layer 106 may include an insulating material such as at least one of silicon oxide, silicon nitride, and silicon carbide. The substrate insulating layer 121 may be relatively widely disposed in the second region R2 to cover the upper end of the contact plug 170. However, in some implementations, the arrangement form of the substrate insulating layer 121 may vary within a range that electrically isolates the contact plug 170 from the plate layer 101.

[0102] In some implementations, the second semiconductor structure S2 may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see Figure 2A In the first channel layer 140 (see Figure 4B ) is exposed through the upper end, and the first channel structure CH can be directly connected to the plate layer 101. However, in some implementations, the electrical connection form between the first channel structure CH and the common source line can be changed, and the first channel structure and the source structure can have the same Figure 2A The structure is the same as the structure in the implementation method.

[0103] Fig. 9 is a cross-sectional view illustrating a semiconductor device according to some implementations.

[0104] Fig. 10A and Fig. 10B are respectively along Fig. 9 Schematic diagrams taken along lines IV-IV′ and V-V′ in FIG. 1 illustrate cross-sectional views of a semiconductor device according to some implementations.

[0105] refer to Figures 9 to 10B The semiconductor device 300 includes a stacked structure GS, a vertical structure 370, and a gap-filling insulating layer 350. The stacked structure GS is located on a substrate 301 and has a step region GP. The vertical structure 370 penetrates a portion of the stacked structure GS or extends vertically between the step regions GP. The gap-filling insulating layer 350 fills the gaps between the step regions GP. The semiconductor device 300 includes a first insulating layer 352 covering the stacked structure GS, a second insulating layer 354 covering the side surface of the vertical structure 370, a third insulating layer 356 located on the stacked structure GS, and a surface insulating layer 325 surrounding a portion of the side surface of the vertical structure 370.

[0106] The stacked structure GS includes alternately stacked first layers 320 and second layers 330. For example, the first layer 320 may be an insulating layer and the second layer 330 may be a conductive layer. The stacked structure GS may have a step region GP having a step structure on ends opposite to each other.

[0107] The vertical structure 370 may penetrate the gap-filling insulating layer 350 between the step region GP and the step region GP and extend downward. The vertical structure 370 may penetrate at least a portion of the substrate 301, but some implementations thereof are not limited thereto. When the vertical structure 370 includes a conductive material, the vertical structure 370 may be electrically connected to the second layer 330. In this case, the vertical structure 370 may have a horizontally extending form in the region connected to the second layer 330, but the connection form is not limited thereto. The side surface insulating layer 325 may be disposed between the second layer 330 and the vertical structure 370 that are not connected to the vertical structure 370. When the vertical structure 370 includes an insulating material, the vertical structure 370 may not be electrically connected to the stacked structure GS.

[0108] The gap-filling insulating layer 350 may be disposed at a substantially uniform thickness along the side surfaces of the stacked structure GS and the side surfaces of the second insulating layer 354 on the vertical structure 370. A portion of the upper surface of the gap-filling insulating layer 350 may be disposed at a height substantially the same as that of the upper ends of the vertical structures 370, and another portion of the upper surface of the gap-filling insulating layer 350 may be disposed at a height lower than that of the upper ends of the vertical structures 370, for example, may be disposed at a height substantially the same as that of the lower surface of the third insulating layer 356.

[0109] The gap-filling insulating layer 350 includes a void VD spaced apart from the stacked structure GS and the vertical structure 370. Fig. 9 As shown, the void VD may be spaced apart from the stacked structure GS and the vertical structure 370. The void VD may be spaced apart from the first layer 320 and the second layer 330. Fig. 10B As illustrated, the void VD may be disposed symmetrically about one of the vertical structures 370 and / or the center of the illustrated region.

[0110] Likewise, reference Figures 1 to 4B The description of the gap-filling insulating layer 150 and the first, second, and third unit insulating layers 152 , 154 , and 156 may be applied to the description of the gap-filling insulating layer 350 and the first, second, and third insulating layers 352 , 354 , and 356 , respectively.

[0111] Fig.11 is a cross-sectional view illustrating a semiconductor device according to some implementations. Fig.11 The graphic representation can be Fig. 10A The cross-sectional view corresponding to the illustration.

[0112] refer to Fig.11 ,and Fig. 10A Different from the implementation in FIG. 3 , the semiconductor device 300a may not include the step region GP. The vertical structure 370 may extend by penetrating the gap-filling insulating layer 350 instead of penetrating the second layer 330. Therefore, even when a region other than the step region is filled, the gap-filling insulating layer 350 including the void VD may be applied.

[0113] Fig.12 is a flow chart illustrating a method of fabricating a semiconductor device according to some implementations.

[0114] FIG. 13A to FIG. 13O is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some implementations. FIG. 13A to FIG. 13O The graphic representation can be Figure 2A The cross-sectional view corresponding to the illustration.

[0115] refer to Fig.13A , a circuit device 220 , a circuit interconnection structure, and a peripheral region insulating layer 290 included in a peripheral circuit region PERI may be formed on a substrate 201 .

[0116] First, a device isolation layer 210 may be formed in the substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The device isolation layer 210 may be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polysilicon or a metal silicide layer, but the implementation is not limited thereto. Thereafter, a spacer layer 224 and an impurity region 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In some implementations, the spacer layer 224 may include a plurality of layers. The impurity region 205 may be formed by performing an ion implantation process.

[0117] The circuit contact plug 270 of the circuit interconnection structure may be formed by partially forming the peripheral region insulating layer 290, removing a portion thereof by etching, and filling a conductive material therein. The circuit interconnection line 280 may be formed, for example, by depositing a conductive material and patterning the conductive material.

[0118] The peripheral region insulating layer 290 may include a plurality of insulating layers. The peripheral region insulating layer 290 may become a part of each process of forming a circuit interconnection structure. Thus, a peripheral circuit region PERI may be formed.

[0119] refer to Fig.12 and Fig. 13B A board layer 101 having a memory cell region CELL, a horizontal sacrificial layer 110, a second horizontal conductive layer 104, and a substrate insulating layer 121 may be formed on the peripheral circuit region PERI, and a mold structure PS may be formed by alternately stacking sacrificial insulating layers 118 and interlayer insulating layers 120 (S110).

[0120] The plate layer 101 may be formed on the peripheral region insulating layer 290. The plate layer 101 may be formed of, for example, polysilicon, and may be formed through a CVD process. The polysilicon included in the plate layer 101 may include impurities.

[0121] The first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 included in the horizontal sacrificial layer 110 may be alternately stacked on the board layer 101. A portion of the horizontal sacrificial layer 110 may be used in a subsequent process. Figure 2AThe first horizontal sacrificial layer 111 may be replaced by the first horizontal conductive layer 102 in the first region R2. The first horizontal sacrificial layer 111 may include a material different from that of the second horizontal sacrificial layer 112. For example, the first horizontal sacrificial layer 111 may be formed of the same material as that of the interlayer insulating layer 120, and the second horizontal sacrificial layer 112 may be formed of the same material as that of the subsequent sacrificial insulating layer 118. A portion of the horizontal sacrificial layer 110 may be removed in a partial region (e.g., the second region R2) by a patterning process.

[0122] The second horizontal conductive layer 104 may be formed on the horizontal sacrificial layer 110 , and may make contact with the board layer 101 in a region from which the horizontal sacrificial layer 110 is removed.

[0123] The substrate insulating layer 121 may be formed to include a contact plug 170 (see Figure 2A ) penetrates the board layer 101 in a partial area of ​​the area. The substrate insulating layer 121 may be formed by removing a portion of the board layer 101, the horizontal sacrificial layer 110, and the second horizontal conductive layer 104 and filling the insulating material. After filling the insulating material, a planarization process may be further performed using a chemical mechanical polishing (CMP) process. Therefore, the upper surface of the substrate insulating layer 121 may be substantially coplanar with the upper surface of the second horizontal conductive layer 104.

[0124] At least a portion of the sacrificial insulating layer 118 may be replaced by a gate electrode 130 (see Figure 2A ) is replaced. The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material having an etching selectivity relative to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some implementations, the interlayer insulating layer 120 may not have the same thickness. The thickness of the interlayer insulating layer 120 and the sacrificial insulating layer 118 and the number of films included therein may vary from the illustrated example.

[0125] refer to Fig.12 and Fig. 13C , a step region GP having the first and second stepped structures ST1 and ST2 in a step shape may be formed by partially removing the mold structure PS, and the first unit insulating layer 152 may be formed.

[0126] The step region GP may be formed by repeatedly performing a photolithography process and an etching process on the mold structure PS. The step region GP may be formed in the second region R2 and may be formed to include a region in which the upper sacrificial insulating layer 118 may extend shorter than the lower sacrificial insulating layer 118. In each step region GP, ​​a first step structure ST1 and a second step structure ST2 symmetrical to each other may be formed so that the upper surfaces and ends of the plurality of sacrificial insulating layers 118 may be exposed upward. However, in some implementations, the specific shape of the step region GP may be as shown in FIG. Figure 3A By further forming the sacrificial insulating layer 118 on the first and second stepped structures ST1 and ST2 of the step region GP, ​​the sacrificial insulating layer 118 disposed in the uppermost portion of each region may have a relatively large thickness.

[0127] The first unit insulating layer 152 may be formed by, for example, an ALD process, and may be conformally formed along the first and second stepped structures ST1 and ST2 .

[0128] refer to Fig.12 and Fig.13D , a gap-filling sacrificial layer 116 filling the step region GP may be formed ( S130 ), and a third unit insulating layer 156 may be formed.

[0129] The gap filling sacrificial layer 116 may be formed by being deposited to fill the step region GP and being planarized. The gap filling sacrificial layer 116 may be selected from a material for filling, for example, a step region GP having a depth of 1 μm or more (such as 10 μm or more) without voids and sharp corners. Similarly, as the gap filling sacrificial layer 116, a material that is etched at an appropriate etching rate during a subsequent low temperature etching process may be selected. The gap filling sacrificial layer 116 may include, for example, N-type doped polysilicon.

[0130] The third unit insulating layer 156 may be formed to cover an upper surface of the first unit insulating layer 152 on the mold structure PS, and may cover an upper surface of the gap-fill sacrificial layer 116 .

[0131] refer to Fig.12 and FIG. 13E to FIG. 13G , a vertical sacrificial layer 119 penetrating the gap-filling sacrificial layer 116 and the mold structure PS may be formed ( S140 ).

[0132] First, refer to Fig.13E , a through hole OH penetrating the gap-filling sacrificial layer 116 and the mold structure PS may be formed.

[0133] The through hole OH can be formed in Figure 2AThe through hole OH may be formed, for example, by a low temperature etching process. The through hole OH may further penetrate the third unit insulating layer 156, the first unit insulating layer 152, and the substrate insulating layer 121. The circuit interconnect line 280 may be exposed through the bottom surface of the through hole OH. Since the through hole OH is formed by penetrating the gap-filling sacrificial layer 116, which is advantageous for the low temperature etching process, the through hole OH may be formed to have a columnar hole shape without distortion and twisting.

[0134] refer to Fig.13F , a second unit insulating layer 154 may be formed around the through hole OH.

[0135] The second unit insulating layer 154 may be formed by oxidizing the gap-filling sacrificial layer 116 exposed through the through-holes OH. Therefore, the second unit insulating layer 154 may be formed only on the surface of the gap-filling sacrificial layer 116. For example, the gap-filling sacrificial layer 116 may be a silicon oxide layer.

[0136] refer to Figure 13G , a vertical sacrificial layer 119 may be formed by filling the through holes OH.

[0137] The vertical sacrificial layer 119 may include a material different from those of the gap-fill sacrificial layer 116, the second unit insulating layer 154, and the third unit insulating layer 156. The vertical sacrificial layer 119 may include, for example, a metal material or a carbon-based material. The vertical sacrificial layer 119 may be formed by filling the through hole OH with the aforementioned material and performing a planarization process.

[0138] refer to Fig.12 and Fig.13H , an opening OP may be formed in the third unit insulating layer 156 , and the gap-filling sacrificial layer 116 may be removed through the opening OP ( S150 ).

[0139] First, the openings OP may be formed by partially removing the third unit insulating layer 156 on the gap-filling sacrificial layer 116. The size and number of the openings OP are not limited to the examples illustrated in the drawings and may vary in some implementations.

[0140] The gap-fill sacrificial layer 116 may be removed selectively with respect to the first and second cell insulating layers 152 and 154 using, for example, a wet etching process.

[0141] refer to Fig.12 and Fig.13I , a gap-filling insulating layer 150 having a void VD may be formed in the region from which the gap-filling sacrificial layer 116 is removed ( S160 ).

[0142] The gap-filling insulating layer 150 may be substantially conformally formed along the first unit insulating layer 152 and the second unit insulating layer 154. For example, the gap-filling insulating layer 150 may be formed using an ALD process. A void VD may be formed in the gap-filling insulating layer 150 and may have a shape corresponding to that of the step region GP in at least some regions.

[0143] refer to Fig.13J , a first channel structure CH can be formed.

[0144] The first channel structure CH may be formed by removing the vertical sacrificial layer 119 from the first region R1 to form a lower channel hole and sequentially depositing at least a portion of a first gate dielectric layer 145 , a first channel layer 140 , a first channel filling insulating layer 147 , and a first channel pad 149 .

[0145] The first gate dielectric layer 145 may be formed to have a uniform thickness using an ALD or CVD process. In this process, the entirety or a portion of the first gate dielectric layer 145 may be formed, and a portion extending perpendicularly to the plate layer 101 along the first channel structure CH may be formed in this process. The first channel layer 140 may be formed on the first gate dielectric layer 145 in the lower channel hole. The first channel filling insulating layer 147 may be formed to fill the lower channel hole and may be an insulating material. The first channel pad 149 may be formed of a conductive material (e.g., polysilicon).

[0146] refer to Figure 13K , the vertical sacrificial layer 119 may be removed, the preliminary side surface insulating layer 125P and the vertical sacrificial layer 191 may be formed, and the sacrificial insulating layer 118 may be removed.

[0147] First, the vertical sacrificial layer 119 in the through hole OH may be removed from the second region R2, and the exposed sacrificial insulating layer 118 may be partially removed. A contact tunnel portion may be formed by removing the sacrificial insulating layer 118 to a predetermined length around the through hole OH. The contact tunnel portion may be formed to have a relatively short length in the uppermost sacrificial insulating layer 118 and a relatively long length in the lower sacrificial insulating layer 118.

[0148] Specifically, initially, on the contrary, the contact tunnel portion may be formed to have a relatively long length in the uppermost sacrificial insulating layer 118. This may be because the uppermost sacrificial insulating layer 118 may include an area having a relatively faster etching rate than the etching rate of the sacrificial insulating layer 118 below it. Thereafter, another sacrificial layer may be formed in the through hole OH and the contact tunnel portion. The sacrificial layer may be formed of a material having a lower etching rate than the etching rate of the sacrificial insulating layer 118. Thereafter, a portion of the sacrificial layer and the sacrificial insulating layer 118 may be removed. In this case, the sacrificial layer may remain in the uppermost portion, the sacrificial layer may be removed, and the sacrificial insulating layer 118 may be partially removed in the lower portion. Therefore, finally, the contact tunnel portion may be formed to have a relatively short length in the uppermost sacrificial insulating layer 118.

[0149] The preliminary side surface insulating layer 125P may be formed by depositing an insulating material in the through hole OH and the contact tunnel portion. The preliminary side surface insulating layer 125P may be formed on the sidewall of the through hole OH and may fill the contact tunnel portion. In the uppermost sacrificial insulating layer 118, the preliminary side surface insulating layer 125P may not completely fill the contact tunnel portion.

[0150] The vertical sacrificial layer 191 may fill the through hole OH and may fill the uppermost contact tunnel portion. The vertical sacrificial layer 191 may include a material different from that of the preliminary side surface insulating layer 125P, and may include, for example, polysilicon.

[0151] Thereafter, the first isolation region MS (see Figure 1 and Figure 2B ) is formed in a position of the first region R1 through the sacrificial insulating layer 118 and the interlayer insulating layer 120 and extending to the plate layer 101. Thereafter, by performing an etch-back process when the sacrificial spacer layer is formed in the opening, the horizontal sacrificial layer 110 can be selectively removed from the first region R1, and a portion of the exposed first gate dielectric layer 145 can be removed together. The first horizontal conductive layer 102 can be formed by depositing a conductive material in the region from which the horizontal sacrificial layer 110 is removed, and the sacrificial spacer layer can be removed from the opening. Through this process, the first horizontal conductive layer 102 can be formed in the first region R1.

[0152] Thereafter, the sacrificial insulating layer 118 may be removed selectively with respect to the interlayer insulating layer 120 , the second horizontal conductive layer 104 , and the preliminary side surface insulating layer 125P using, for example, wet etching.

[0153] refer to Figure 13L , which may form a portion of the gate electrode 130 .

[0154] In this process, a gate electrode 130 other than the first upper gate electrode 130U1 may be formed. The gate electrode 130 may be formed by depositing a conductive material in a region from which the sacrificial insulating layer 118 is removed. The conductive material may include a metal, polysilicon, or a metal silicide material. In some implementations, a portion of the first gate dielectric layer 145 may be formed first before forming the gate electrode 130.

[0155] After forming the gate electrode 130, a gate isolation insulating layer 105 may be formed in the opening formed to correspond to the first isolation region MS (see Figure 2B ).

[0156] refer to Figure 13M , a horizontal insulating layer 158 and a first upper gate electrode 130U1 may be formed, and a second channel structure SCH penetrating the first upper gate electrode 130U1 may be formed.

[0157] A horizontal insulating layer 158 may be formed on the first channel structure CH. Thereafter, an upper insulating layer 190 may be partially formed, and the first upper gate electrode 130U1 may be patterned and formed. The first upper gate electrode 130U1 may include a material different from that of the other gate electrodes 130, but some implementations thereof are not limited thereto. For example, the first upper gate electrode 130U1 may include polysilicon. Thereafter, an upper insulating layer 190 may be additionally formed.

[0158] In order to form the second channel structure SCH, first, an upper channel hole penetrating the first upper gate electrode 130U1 may be formed, and a second channel dielectric layer 165 and a sacrificial layer may be sequentially formed. Thereafter, a lower channel hole penetrating the second channel dielectric layer 165 and the sacrificial layer and extending to the horizontal insulating layer 158 may be formed on the bottom surface of the upper channel hole, and the first channel pad 149 may be exposed by partially removing the horizontal insulating layer 158 exposed by the lower channel hole. A connecting pad 161 may be formed in the region from which the horizontal insulating layer 158 is removed, the sacrificial layer may be removed, and a second channel layer 160, a second channel filling insulating layer 167, and a second channel pad 169 may be sequentially formed in each upper channel hole, thereby forming the second channel structure SCH. Each layer may be formed in the same manner as in the first channel structure CH. The second channel layer 160 may be connected to the connecting pad 161 in the lower portion.

[0159] refer to Fig.13N , an upper opening UP can be formed.

[0160] The upper opening UP may be formed to penetrate the upper insulating layer 190. Specifically, the upper opening UP may be formed at a position corresponding to the upper insulating layer 190. Figure 2AThe upper opening UP may penetrate the upper insulating layer 190 and the horizontal insulating layer 158 at a position corresponding to the contact plug 170 in the upper opening UP, and may be formed so that the preliminary contact insulating layer 125P and the vertical sacrificial layer 191 may be exposed. In some implementations, the depth of each upper opening UP may vary. For example, in some implementations, the lower end of the upper opening UP may be disposed below the third unit insulating layer 156.

[0161] refer to Fig.13O , the vertical sacrificial layer 191 may be removed from the through-hole OH and the contact plug 170 may be formed.

[0162] The vertical sacrificial layer 191 may be selectively removed relative to the interlayer insulating layer 120 and the gate electrode 130. After the vertical sacrificial layer 191 is removed, a portion of the exposed preliminary side surface insulating layer 125P may also be removed. In this case, the entirety of the preliminary side surface insulating layer 125P may be removed from the contact region 130P, and the preliminary side surface insulating layer 125P therebelow may remain and the side surface insulating layer 125 may be formed. In the contact region 130P, when the first gate dielectric layer 145 is exposed after the preliminary side surface insulating layer 125P is removed, the first gate dielectric layer 145 may also be removed so that the side surface of the gate electrode 130 may be exposed.

[0163] The contact plug 170 may be formed by depositing a conductive material in the through hole OH. The contact plug 170 may be formed to have a horizontal extension portion 170H extending horizontally from the contact region 130P (see Figure 3B ), and thus, the contact plug 170 may be physically and electrically connected to the gate electrode 130.

[0164] After that, refer to Figure 2A The semiconductor device 100 may be manufactured by forming a short pillar 180 connected to the contact plug 170 and the upper end of the first channel structure CH.

[0165] Fig.14 is a diagram illustrating a data storage system including a semiconductor device according to some implementations.

[0166] refer to Fig.14 , the data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid state drive (SSD), a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0167] The semiconductor device 1100 may be implemented as a nonvolatile memory device, such as, for example, a Figures 1 to 11 The NAND flash memory device described in the aforementioned example embodiments. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S located on the first structure 1100F. In some implementations, the first structure 1100F may be disposed on one side of the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure including the following items: a bit line BL; a common source line CSL; a word line WL disposed between the bit line BL and the common source line CSL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR.

[0168] In the second structure 1100S, each memory cell string CSTR includes lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In some implementations, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0169] In some implementations, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be configured as a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0170] In some implementations, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series to each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation to erase data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0171] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnect 1125 extending from the first structure 110F to the second structure 1100S.

[0172] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0173] The controller 1200 includes a processor 1210 , a NAND controller 1220 , and a host interface (I / F) 1230 . In some implementations, the data storage system 1000 includes a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0174] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 includes a controller interface (I / F) 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be sent. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command from an external host is received through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0175] Fig.15 is a perspective view illustrating a data storage system including a semiconductor device according to some implementations.

[0176] refer to Fig.15In some implementations, the data storage system 2000 includes a mainboard 2001, a controller 2002 mounted on the mainboard 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnection pattern 2005 formed on the mainboard 2001.

[0177] The mainboard 2001 includes a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some implementations, the data storage system 2000 may communicate with the external host according to one of the interfaces among the universal serial bus (USB), the peripheral component interconnect (PCI-Express), the serial advanced technology attachment (SATA), and the universal flash memory (UFS) M-Phy. In some implementations, the data storage system 2000 may operate by power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0178] The controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operating speed of the data storage system 2000 .

[0179] The DRAM 2004 may be configured as a buffer memory for alleviating the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0180] The semiconductor package 2003 includes a first semiconductor package 2003a and a second semiconductor package 2003b that are spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b includes a package substrate 2100, a semiconductor chip 2200 located on the package substrate 2100, an adhesive layer 2300 respectively disposed on the lower surface of the semiconductor chip 2200, a connection structure 2400 that electrically connects the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0181] The package substrate 2100 may be configured as a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 includes an input / output pad 2210. The input / output pad 2210 may correspond to Fig.14 Each semiconductor chip 2200 includes a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include a reference Figures 1 to 11 The semiconductor devices are described in the foregoing example embodiments.

[0182] In some implementations, the connection structure 2400 may be configured as a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some implementations, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through-hole electrode (TSV) instead of the connection structure 2400 of the bonding wire method.

[0183] In some implementations, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some implementations, the controller 2002 and the semiconductor chip 2200 may be mounted on a built-in layer substrate different from the mainboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through interconnections formed on the built-in layer substrate.

[0184] Fig.16 is a cross-sectional view illustrating a semiconductor package according to some implementations. Fig.16 The diagram can correspond to Fig.15Some implementations of the semiconductor package 2003 taken along line VI-VI'.

[0185] refer to Fig.16 In the semiconductor package 2003, the package substrate 2100 may be implemented as a printed circuit substrate. The package substrate 2100 includes a package substrate main body 2120, a package upper pad 2130 (see FIG. 213 ) disposed on the upper surface of the package substrate main body 2120, and a package upper pad 2130 (see FIG. 214 ). Fig.15 ), a lower pad 2125 disposed on or exposed through the lower surface of the package substrate main body portion 2120, and an internal interconnect 2135 electrically connecting the upper pad 2130 to the lower pad 2125 in the package substrate main body portion 2120. Fig.15 As illustrated, the lower pad 2125 may be connected to the interconnection pattern 2005 of the main board 2001 of the data storage system 2000 through the conductive connection portion 2800 .

[0186] Each semiconductor chip 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region having a peripheral interconnect 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 located on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see Fig.14 ) of the contact plug 3235. As shown in reference Figures 1 to 11 In the aforementioned example embodiments, described in each semiconductor chip 2200 , the gap-filling insulating layer 150 filling the step region GP of the gate electrode 130 in each semiconductor chip 2200 includes therein the void VD spaced apart from the contact plug 170 and the stack structure GS.

[0187] Each semiconductor chip 2200 includes a through interconnect 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through interconnect 3245 may be disposed outside the gate stack structure 3210, and may be further disposed to penetrate the gate stack structure 3210. Each semiconductor chip 2200 may also include an input / output pad 2210 electrically connected to the peripheral interconnect 3110 of the first structure 3100 (see Fig.15 ).

[0188] According to the aforementioned implementation, by optimizing the material of the upper selection gate electrode, the arrangement of the gate barrier layer, and the structure of the second channel structure penetrating the upper selection gate electrode, a semiconductor device with improved electrical characteristics and reliability and a data storage system including the semiconductor device can be provided.

[0189] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of what can be claimed. Certain features described in separate implementations in the present disclosure can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. In addition, although these features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the combination can be removed from the combination in some cases, and the combination can be directed to a sub-combination or a change in the sub-combination.

[0190] While various implementations have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first semiconductor structure, the first semiconductor structure comprising a substrate, a plurality of circuit devices located on the substrate, and a plurality of circuit interconnection lines located on the plurality of circuit devices; as well as a second semiconductor structure, the second semiconductor structure being located on the first semiconductor structure, Wherein, the second semiconductor structure comprises: Lamellar; a plurality of gate electrodes, the plurality of gate electrodes being located on the plate layer and spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer, wherein the plurality of gate electrodes extend different lengths in a second direction perpendicular to the first direction, and wherein the plurality of gate electrodes form a plurality of stepped regions; a gap-filling insulating layer, the gap-filling insulating layer filling regions between the plurality of gate electrodes spaced apart from each other in the second direction in the plurality of step regions; a plurality of channel structures extending through at least a portion of the plurality of gate electrodes, wherein the plurality of channel structures extend in the first direction; and a plurality of contact plugs extending through the gap-filling insulating layer and the plurality of gate electrodes in the plurality of step regions, wherein the plurality of contact plugs extend in the first direction, wherein the gap-filling insulating layer extends along a plurality of side surfaces of the plurality of gate electrodes and a plurality of side surfaces of the plurality of contact plugs, and The gap-filling insulating layer includes a plurality of gaps spaced apart from the plurality of contact plugs and the plurality of gate electrodes.

2. The semiconductor device according to claim 1, wherein The plurality of gaps are disposed between the plurality of contact plugs, and wherein the plurality of gaps are also disposed between the plurality of contact plugs and a stack structure of the plurality of gate electrodes.

3. The semiconductor device according to claim 1, wherein At least one of the plurality of voids includes a region having a shape corresponding to a shape of the plurality of stepped regions.

4. The semiconductor device according to claim 1, wherein: The plurality of voids have symmetrical shapes at opposite sides of at least one contact plug among the plurality of contact plugs in a third direction perpendicular to the first direction and the second direction.

5. The semiconductor device according to claim 1, wherein The gap-filling insulating layer surrounds the plurality of voids, and wherein the gap-filling insulating layer has a substantially constant thickness.

6. The semiconductor device according to claim 1, wherein The second semiconductor structure further includes: a plurality of interlayer insulating layers, the plurality of interlayer insulating layers and the plurality of gate electrodes being alternately stacked, wherein the plurality of interlayer insulating layers form a stacked structure; and A first unit insulating layer covers the plurality of side surfaces of the plurality of gate electrodes and the plurality of side surfaces of the plurality of interlayer insulating layers, wherein the first unit insulating layer contacts the gap-filling insulating layer in the plurality of step regions.

7. The semiconductor device according to claim 1, wherein The second semiconductor structure further includes a plurality of second unit insulating layers, each of the second unit insulating layers covering a portion of a corresponding side surface of the plurality of side surfaces of the plurality of contact plugs.

8. The semiconductor device according to claim 7, wherein: The plurality of second unit insulating layers include a plurality of inner side surfaces contacting the plurality of contact plugs, and include a plurality of outer side surfaces contacting the gap-fill insulating layer.

9. The semiconductor device according to claim 1, in, The second semiconductor structure further includes a third unit insulating layer, the third unit insulating layer being located on a portion of the gap-filling insulating layer and the stacked structure of the plurality of gate electrodes, and The third unit insulating layer has a plurality of openings filled with the gap-filling insulating layer.

10. The semiconductor device according to claim 1, in, Each of the plurality of stepped regions includes a first stepped structure and a second stepped structure, wherein the height of the first step structure decreases in the second direction, wherein the height of the second step structure increases in the second direction, and The plurality of contact plugs extend through at least the first step structure.

11. The semiconductor device according to claim 1, in, The plurality of gate electrodes form a first stack structure and a second stack structure, wherein the first stacking structure and the second stacking structure each form a stepped region, wherein the first stacking structure and the second stacking structure are stacked in the first direction, and The gap-filling insulating layer includes a first gap-filling insulating layer located on the step region of the first stacking structure and a second gap-filling insulating layer located on the step region of the second stacking structure.

12. The semiconductor device according to claim 1, in, The second semiconductor structure further includes a plurality of isolation regions extending through at least a portion of the plurality of gate electrodes and extending in the second direction, and The stacked structure of the plurality of gate electrodes includes a plurality of wall regions, and the plurality of wall regions are located between the plurality of isolation regions and the plurality of step regions in a third direction perpendicular to the first direction and the second direction.

13. A semiconductor device, comprising: Lamellar; a plurality of conductive layers, the plurality of conductive layers being located on the board layer and spaced apart from each other in a first direction perpendicular to an upper surface of the board layer, wherein the plurality of conductive layers extend different lengths in a second direction perpendicular to the first direction, and wherein the plurality of conductive layers form a stepped region; a gap-filling insulating layer, the gap-filling insulating layer being located on the step region; and a plurality of vertical structures extending through the gap-fill insulating layer and the plurality of conductive layers in the stepped region, wherein the plurality of vertical structures extend in the first direction, and wherein the gap-filling insulating layer includes a plurality of gaps arranged in a third direction perpendicular to the first direction and the second direction, and Wherein, the plurality of gaps are arranged symmetrically with respect to at least one of the following: at least one vertical structure of the plurality of vertical structures, or The center of the stepped area.

14. The semiconductor device according to claim 13, in, The gap-filling insulating layer extends along a plurality of side surfaces of the plurality of vertical structures, and Wherein, the plurality of gaps are spaced apart from the plurality of vertical structures.

15. The semiconductor device according to claim 13, in, The gap-filling insulating layer extends along the step region, and Wherein, the plurality of gaps are spaced apart from the plurality of conductive layers.

16. The semiconductor device according to claim 13, wherein: The plurality of gaps are disposed between the plurality of vertical structures, and wherein the plurality of gaps are also disposed between the stacked structure of the plurality of conductive layers and the plurality of vertical structures.

17. The semiconductor device according to claim 13, further comprising: A plurality of oxide layers are disposed between the gap-filling insulating layer and the plurality of vertical structures.

18. The semiconductor device according to claim 13, in, The upper ends of the vertical structures are located at a first height, and A portion of the upper surface of the gap-filling insulating layer is located at a second height lower than the first height.

19. A data storage system, the data storage system comprising: A semiconductor storage device, comprising: a first semiconductor structure, the first semiconductor structure comprising a plurality of circuit devices; a second semiconductor structure, the second semiconductor structure being located on a surface of the first semiconductor structure; and an input / output pad electrically connected to the plurality of circuit devices; and a controller electrically connected to the semiconductor memory device through the input / output pad, wherein the controller is configured to control the semiconductor memory device, Wherein, the second semiconductor structure comprises: Lamellar; a plurality of gate electrodes located on the plate layer and spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer, wherein the plurality of gate electrodes extend to different lengths in a second direction perpendicular to the first direction, and wherein the plurality of gate electrodes form a stepped region; a gap-filling insulating layer, the gap-filling insulating layer being located on the step region; and a plurality of contact plugs extending through the gap-filling insulating layer and the stepped region, wherein the plurality of contact plugs extend in the first direction, and The gap-filling insulating layer includes a plurality of gaps spaced apart from the plurality of contact plugs and the plurality of gate electrodes.

20. The data storage system according to claim 19, wherein: The plurality of voids are symmetrically disposed at opposite sides of at least one contact plug among the plurality of contact plugs in a third direction perpendicular to the first direction and the second direction.

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