Semiconductor rectification device and manufacturing method thereof

Abstract

The invention relates to a semiconductor rectification device and a manufacturing method thereof. The semiconductor rectification device includes an epitaxial layer having a top surface and a bottom surface; the first groove extends from the top surface to the bottom surface and comprises a first side wall and a second side wall which are opposite to each other, and a first bottom surface connected with the two side walls; the second groove is adjacent to the first groove and comprises a third side wall and a fourth side wall which are opposite to each other, and a second bottom surface connected with the two side walls; the first doped region extends from the top surface to the bottom surface and is adjacent to the first side wall of the first groove and at least part of the first bottom surface; the second doped region is adjacent to and separated from the first doped region, extends from the top surface to the bottom surface, and is adjacent to the third side wall, the fourth side wall and the second bottom surface of the second groove; the gate structure is arranged on the top surface between the first groove and the second groove, and the bottom surface of the gate structure is adjacent to the first doped region and the second doped region; and a contact metal layer.

Description

Technical Field

[0001] The present invention relates to a structure of a semiconductor rectifier device and a method for manufacturing the same, and more particularly, to a structure of a semiconductor rectifier device formed on silicon carbide and a method for manufacturing the same. Background Art

[0002] As is known, semiconductor materials with wide band gaps (e.g. band gap energy values ​​Eg greater than 1.1 eV), low on-resistance (RON), high thermal conductivity, high operating frequencies and high charge carrier saturation velocities are very suitable for the production of electronic components, such as diodes or transistors, in particular for power supply applications. A material having the above characteristics and designed for the manufacture of electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g. 3C-SiC, 4H-SiC, 6H-SiC), is superior to silicon in terms of the properties listed above.

[0003] Electronic devices on silicon carbide substrates have many advantages over similar devices on silicon substrates, such as low on-state output resistance, low leakage current, high operating temperature, and high operating frequency. Semiconductor structures based on silicon carbide substrates require high-temperature (e.g., 1700°C or above) annealing processes for activation, but polysilicon and common gate materials cannot withstand such high-temperature annealing processes, resulting in difficulties in process integration and increased total process costs. Summary of the invention

[0004] An embodiment of the present disclosure relates to a semiconductor rectifying device. The semiconductor rectifier device includes: an epitaxial layer having a top surface and a bottom surface opposite to each other; a first groove extending from the top surface to the bottom surface and including a first sidewall and a second sidewall opposite to each other, and a first bottom surface connecting the first sidewall and the second sidewall; a second groove extending from the top surface to the bottom surface and adjacent to the first groove, the second groove including a third sidewall and a fourth sidewall opposite to each other, and a second bottom surface connecting the third sidewall and the fourth sidewall; a first doped region extending from the top surface to the bottom surface and adjacent to the second sidewall and at least a portion of the first bottom surface of the first groove; a second doped region adjacent to the first doped region and separated from each other, extending from the top surface to the bottom surface and adjacent to the third sidewall, the fourth sidewall and the second bottom surface of the second groove; a gate structure disposed on the top surface between the first groove and the second groove, and the bottom surface of the gate structure adjacent to the first doped region and the second doped region; and a contact metal layer disposed on the top surface of the epitaxial layer along the first groove, the gate structure and the second groove.

[0005] The embodiments of the present disclosure relate to a method for manufacturing a semiconductor rectifier device. The method comprises: forming a patterned layer on a silicon carbide layer; etching the silicon carbide layer with the patterned layer as a mask to form a first groove and a second groove adjacent to the first groove; ion implanting the silicon carbide layer with the patterned layer as a mask; thermally annealing the silicon carbide layer; and after the thermal annealing, forming a gate structure on the silicon carbide layer between the first groove and the second groove, wherein the gate structure has a first sidewall and a second sidewall opposite to each other, the first sidewall and a sidewall of the first groove are continuous sidewalls, and the second sidewall and a sidewall of the second groove are continuous sidewalls. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of several embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that various structures may not be drawn to scale. In fact, the dimensions of various structures may be arbitrarily enlarged or reduced for clarity of discussion.

[0007] Figure 1 , 2 , 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 show one or more stages in a method for manufacturing a semiconductor rectifier device according to some embodiments of the present invention;

[0008] Fig.15 , 16 Shown is a top view of a semiconductor rectifier device according to various embodiments of the present invention;

[0009] Fig.17 , 18 , 19, 20, 21, 22, 23 show one or more stages in a method for manufacturing a semiconductor rectifier device according to some embodiments of the present invention;

[0010] Fig.24 , 25 , 26, 27, 28, 29, and 30 show one or more stages in a method for manufacturing a semiconductor rectifier device according to certain embodiments of the present case.

[0011] The same or similar components are marked with the same reference numerals in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be restrictive. In the present disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] The following is a detailed discussion of embodiments of the present disclosure. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0014] The present disclosure provides a structure of a semiconductor rectifier device and a manufacturing method thereof. Compared with a general manufacturing method of a semiconductor rectifier device, the manufacturing method of the present disclosure includes an activation process before forming a polysilicon material or a dielectric material, so as to well integrate the rectifier device on silicon carbide. Furthermore, the manufacturing method of the present disclosure further includes a self-alignment step of a gate structure, which can reduce the damage to the substrate that may be caused by the patterning process, and at the same time reduce the use of photomasks to reduce the total process cost.

[0015] Figures 1 to 14 Shown are one or more stages in a method of manufacturing a semiconductor rectifier device 1 according to some embodiments of the present invention. At least some of these drawings have been simplified to facilitate a better understanding of aspects of the present disclosure.

[0016] Reference Figure 1, the manufacturing method of the semiconductor rectifier device 1 includes performing epitaxial growth on the surface 11A of the semiconductor material layer 12 to form a silicon carbide layer 12, and forming a doped region 21 in the silicon carbide layer 12. The semiconductor material layer 11 has a relative surface 11A and a surface 11B. In some embodiments, the surface 11A and the surface 11B can be horizontal planes. For convenience of explanation, the direction orthogonal to the surface 11A and the surface 11B is defined as a vertical direction, and the direction orthogonal to the vertical direction is defined as a horizontal direction. In some embodiments, the surface 11A is the top surface of the semiconductor material layer 11, and the surface 11B is the bottom surface of the semiconductor material layer 11. In some embodiments, the surface 11A is the top surface of the silicon wafer. The material of the semiconductor material layer 11 can be polycrystalline silicon or single crystal silicon. The semiconductor material layer 11 may include a doped region. For example, the semiconductor material layer 11 includes a p-type doped region and an n-type doped region (which can be configured as a p-type transistor. The N-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The P-type doped region is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. The N-type or P-type doped region can be formed by performing an ion implantation process, a diffusion process, and / or other suitable doping processes. The semiconductor material layer 11 has a first-type doped region extending from the surface 11A to the surface 11B and covering the entire surface 11A. For ease of explanation, the first type is described below using the N-type as an example, but the present disclosure is not limited thereto, and the N-type (first type) or P-type (second type) semiconductor material layer 11 can be adjusted according to the conductivity type of the semiconductor rectifier device 1.

[0017] The silicon carbide layer 12 has the same conductivity type as the semiconductor material layer 11, that is, the first type doping. In some embodiments, ions with N-type electrical properties are introduced into the epitaxial growth to form an N-type silicon carbide layer 12, without the need for additional ion implantation. Therefore, the ions with N-type electrical properties can be distributed throughout the silicon carbide layer 12 to form a doped region 25 located throughout the silicon carbide layer 12. The silicon carbide layer 12 may have a surface 12A and a surface 12B opposite to the surface 12A. In some embodiments, the surface 12A and the surface 12B may be horizontal planes. In some embodiments, the surface 12A is the top surface of the silicon carbide layer 12, and the surface 12B is the bottom surface of the silicon carbide layer 12. In some embodiments, the surface 12B of the silicon carbide layer 12 contacts the surface 11A of the semiconductor material layer 11.

[0018] Next, ion implantation is performed on the surface 12A of the silicon carbide layer 12 to form a doping region 21 having a second type of doping. In some embodiments, the doping region 21 is a doping region as a circuit terminal, and is also referred to as a terminal doping region. In some embodiments, the doping region 21 has the function of a guard ring. In some embodiments, the doping region 21 is annular in shape from a top view (not shown in the figure). The method for forming the doping region 21 may be to form an oxide layer on the surface 12A of the silicon carbide layer 12, and then form a patterned photomask on the oxide layer. The oxide layer is patterned using a patterned photomask, and after removing the photomask, ion implantation is performed on the surface 12A of the silicon carbide layer 12 using the patterned oxide layer as a mask. The patterned oxide layer will be removed after the ion implantation step. The above-mentioned method for forming the doping region 21 is an example description provided according to some embodiments of the present disclosure, but the present disclosure is not limited thereto. In addition, since the doping region 21 offsets the conductivity of the doping region 25, in terms of electrical properties, the coverage of the doping region 25 is defined as the portion of the silicon carbide layer 12 outside the doping region 21.

[0019] Reference Figure 2 , the manufacturing method of the semiconductor rectifier device 1 includes forming a patterned layer 51 on the surface 12A of the semiconductor material silicon carbide layer 12, exposing part of the silicon carbide layer 12 and covering part of the doped region 21. In some embodiments, the patterned layer 51 exposes part of the doped region 21 and part of the silicon carbide layer 12 connected to the doped region 21. In some embodiments, the patterned layer 51 has an opening 511 and an opening 512 that exposes part of the silicon carbide layer 12. The patterned layer 51 can be a material layer suitable for a mask for a subsequent etching process, such as a photomask, a hardening layer, a dielectric layer (such as an oxide layer or a nitride layer). In some embodiments, the patterned layer 51 includes an oxide (such as silicon oxide). In some embodiments, an oxide layer is formed to cover the surface 12A of the silicon carbide 12, a patterned photomask is formed on the oxide layer, and a portion of the oxide layer is removed using the patterned photomask, and then the photomask is removed to form a patterned layer 51 that exposes part of the silicon carbide layer 12.

[0020] Reference Figure 3 The manufacturing method of the semiconductor rectifier device 1 includes etching the silicon carbide layer 12 with the patterned layer 51 as a mask to form a plurality of grooves (such as Figure 3The grooves 41 and 42 shown in the figure are adjacent to each other and extend from the surface 12A of the silicon carbide layer 12 to the surface 12B. Since they are formed by the same etching step, the multiple grooves have approximately the same depth. In some embodiments, the bottom surfaces of the multiple grooves are approximately located at the same horizontal plane 12D. In some embodiments, the depth D41 of the groove 41 is approximately the same as the depth D42 of the groove 42. In some embodiments, the depth D41 of the groove 41 or the depth D42 of the groove 42 is between 4000 and 5000 angstroms. In some embodiments, the bottom surface 41B of the groove 41 and the bottom surface 42D of the groove 41 have approximately the same horizontal height at the horizontal plane 12. In some embodiments, the bottom surface 41B of the groove 41 and the bottom surface 42D of the groove 41 are located at the same horizontal plane 12. In some embodiments, the depth of the multiple grooves 41 and 42 is less than the depth of the doped region 21. Since the patterned layer 51 exposes a portion of the doped region 21, and the depth of the groove 41 is less than the depth of the doped region 21, the doped region 21 will be adjacent to the sidewall 41D of the groove 41 and a portion of the bottom surface 41B. In addition, since multiple grooves (including grooves 41 and 42) are formed using the patterned layer 51 as a mask, the patterned layer 51 corresponds to multiple openings of the multiple grooves. The sidewalls 41C and 41D of the groove 41 are aligned with the sidewalls of the corresponding first opening 511 of the patterned layer 51, and the sidewalls 42C and 42D of the groove 42 are aligned with the sidewalls of the corresponding second opening 512 of the patterned layer 51, wherein the sidewalls 41C and 41D are respectively connected to the bottom surface 41B and are opposite to each other, and the sidewalls 42C and 42D are respectively connected to the bottom surface 42B and are opposite to each other. In some embodiments, the first opening 511 of the patterned layer 51 overlaps with a portion of the doped region 21 along the vertical direction, such as Figure 3 shown.

[0021] Reference Figure 4 The manufacturing method of the semiconductor rectifier device 1 includes ion implanting the silicon carbide layer 12 with the patterned layer 51 as a mask to form a plurality of doped regions 22, wherein the plurality of doped regions 22 have the same conductivity type as the doped region 21. Similar to the above description, since the doped region 22 offsets the conductivity of the doped region 25, in terms of electrical properties, the coverage of the doped region 25 is defined as the portion of the silicon carbide layer 12 outside the doped regions 21 and 22.

[0022] The plurality of doped regions 22 include a doped region 221 and a doped region 222. In some embodiments, the doped region 221 extends from the surface 12A to the surface 12B and is adjacent to the sidewall 41C and a portion of the bottom surface 41B of the groove 41. In some embodiments, the doped region 221 extends toward the inside of the silicon carbide layer 12 along the sidewall 41C and a portion of the bottom surface 41B of the groove 41. In order to allow each of the plurality of doped regions 22 to diffuse laterally along the corresponding groove sidewall, Figure 4The steps shown include at least one oblique angle ion implantation. In some embodiments, Figure 4 The steps shown include multiple ion implantations, at least one of which is an oblique angle ion implantation. In some embodiments, Figure 4 The steps shown include multiple oblique angle ion implantations, and different oblique angle ion implantations can be set at different angles to achieve the desired lateral diffusion range. In some embodiments, the depth of the doped region 21 from the surface 12A to the surface 12B is greater than or equal to the depth of the doped region 22 from the surface 12A to the surface 12B.

[0023] Since the patterned layer 51 exposes a portion of the doped region 21, the doped region 221 contacts the doped region 21. In some embodiments, Figure 4 The ion implantation step will implant ions into the exposed doping region 21, such as Figure 4 The region 211 marked with a dotted box represents the region in the doping region 21 that is implanted with secondary ions, so the region 211 will have a higher doping concentration. The multiple doping regions 22 serve as the body doping region of the semiconductor rectifier device 1, while the doping region 21 serves as the terminal doping region. The region 211 will be covered by a dielectric material in subsequent steps and will not function as a body doping region, but as a terminal doping region. Therefore, for the convenience of explanation, the region 211 is defined as a part of the doping region 21, and the boundary between the region 211 and the doping region 221 is equivalent to the boundary between the doping region 21 and the doping region 221. In some embodiments, the region 211 has a higher doping concentration than the doping region 221. In some embodiments, the region 211 has a higher doping concentration than other parts of the doping region 21. In some embodiments, the doping region 22 has a different doping concentration from the doping region 21. In some embodiments, the doping concentration of the doping region 21 is between 1*10 17 To 1*10 18 Per cubic centimeter (cm -3 ). In some embodiments, the doping concentration of the doping region 22 is between 1*10 16 To 1*10 17 cm -3 between.

[0024] The doped region 222 is adjacent to and separated from the doped region 221. In some embodiments, the doped region 222 extends from the surface 12A to the surface 12B and is adjacent to the opposite sidewalls 42C, 42D and the bottom surface 42B of the groove 42. In some embodiments, the doped region 222 extends toward the inside of the silicon carbide layer 12 along the sidewalls 42C, 42D and the bottom surface 42B of the groove 41. The doped region 222 and the doped region 221 are formed by the same ion implantation step, and thus have approximately the same depth and doping concentration as the doped region 221.

[0025] Reference Figure 5, the manufacturing method of the semiconductor rectifier device 1 includes forming a carbon-containing layer 52 to cover the silicon carbide layer 12, and then performing high-temperature annealing on the silicon carbide layer 12. In some embodiments, the carbon-containing layer 52 covers the entire silicon carbide layer 12. In some embodiments, the carbon-containing layer 52 conformally covers the silicon carbide layer 12. Since the silicon carbide layer 12 will be subsequently subjected to high-temperature annealing to activate the ions in the doping regions 21 and 22, the carbon-containing layer 52 can prevent silicon from precipitating at high temperatures. After the carbon-containing layer 52 is formed, the silicon carbide layer 12 is subjected to high-temperature annealing. In some embodiments, the temperature of the high-temperature annealing step is between 1400 and 2500 degrees (℃). In some embodiments, the time for performing the high-temperature annealing step is between 20 and 40 minutes. The carbon-containing layer 52 is removed after the high-temperature annealing step.

[0026] Reference Figure 6 , the manufacturing method of the semiconductor rectifier device 1 includes forming a dielectric layer 13 to cover the doped region 21 after the high temperature annealing step. To ensure that the dielectric layer 13 covers the entire doped region 21, the dielectric layer 13 will further cover the portion of the doped region 221 adjacent to the doped region 21. The method for forming the dielectric layer 13 can refer to the method for forming the aforementioned patterned layer 51, and will not be repeated here. In some embodiments, the dielectric layer 13 covers the sidewall 41D of the groove 41 and a portion of the bottom surface 41B. In some embodiments, the dielectric layer 13 includes an oxide (e.g., silicon oxide).

[0027] Reference Figure 7 The manufacturing method of the semiconductor rectifier device 1 includes forming a dielectric layer 14 to fill the remaining grooves 41 and 42 after the dielectric layer 13 is formed. In some embodiments, a deposition process is performed to form a dielectric material to cover the entire silicon carbide layer 12, and then the dielectric material is dry-etched to remove a portion of the dielectric material above the surface 12A to form the dielectric layer 14. In some embodiments, the dielectric material has an etching selectivity ratio with the silicon carbide layer 12, so the dry etching step stops at the surface 12A of the silicon carbide layer 12.

[0028] The top surface 14A of the dielectric layer 14 is flush or coplanar with the surface 12A of the silicon carbide layer 12. The dielectric layer 14 may include a plurality of portions filling the plurality of grooves. In some embodiments, the dielectric layer 14 includes a portion of the dielectric layer 141 located in the groove 41, and a portion of the dielectric layer 142 located in the groove 42. In some embodiments, the top surface 141A of the portion of the dielectric layer 141 is flush or coplanar with the surface 12A of the silicon carbide layer 12. In some embodiments, the top surface 142A of the portion of the dielectric layer 142 is flush or coplanar with the surface 12A of the silicon carbide layer 12. In some embodiments, the top surface 142A of the portion of the dielectric layer 142 is at approximately the same level as the top surface 142A of the portion of the dielectric layer 142. Furthermore, in order to have an etching selectivity between the dielectric layer 13 and the dielectric layer 14 in a subsequent etching process, the dielectric layer 14 has a dielectric material different from that of the dielectric layer 13. In some embodiments, the dielectric layer 14 includes nitride (eg, silicon nitride).

[0029] Reference Figure 8, the manufacturing method of the semiconductor rectifier device 1 includes removing part of the silicon carbide layer 12 so that the top surface of the exposed part of the silicon carbide layer 12 is lower than the top surface 14A of the dielectric layer 14. In some embodiments, the silicon carbide layer 12 is dry-etched to remove the part of the silicon carbide layer 12 not covered by the dielectric layers 13 and 14. The silicon carbide layer 12 after the dry etching step has an exposed surface 12C, and the level of the surface 12C is lower than the level of the surface 12A and higher than the level of the bottom surface of the plurality of grooves (including 41 and 42). In some embodiments, the surface 12C can be a horizontal plane. In some embodiments, the top surface of the silicon carbide layer 12 after the dry etching step includes horizontal planes with different levels. In some embodiments, the top surface of the silicon carbide layer 12 after the dry etching step includes the surface 12A and the surface 12C, and the level of the surface 12A is higher than the level of the surface 12C. The dry etching step removes a predetermined thickness of the silicon carbide layer 12, and the predetermined thickness is less than the depth of the groove 41. Since a gate electrode structure will be formed on the surface 12C in a subsequent step, the thickness of the removed silicon carbide layer 12 will determine the thickness of the gate electrode structure, so the preset thickness can be adjusted according to the required thickness of the gate electrode structure. In some embodiments, the dry etching step can be a time-mode, and the dry etching step is performed at a preset time to control the thickness of the removed silicon carbide layer 12 to reach the preset thickness. In some embodiments, the preset thickness is between 1000 angstroms and 3000 angstroms. In other words, the vertical distance D12 between the surface 12C of the silicon carbide layer 12 and the top surface 14A (including the top surfaces 141A and 142A) of the dielectric layer 14 is between 1000 angstroms and 3000 angstroms. In some embodiments, the portion of the silicon carbide layer 12 covered by the dielectric layer 13 retains a portion of the surface 12A, and the vertical distance (equivalent to D12) between the surface 12C and the surface 12A is between 1000 angstroms and 3000 angstroms. In some embodiments, sidewalls 41C, 42C, 42D have approximately the same height. In some embodiments, the height of sidewall 41D is greater than the height of sidewalls 41C, 42C, or 42D.

[0030] It is worth noting that, since the gate structure will be formed on the surface 12C of the silicon carbide layer 12 in a subsequent step, a channel will be formed in the silicon carbide layer 12 adjacent to the surface 12C between the grooves 41 and 42 when the semiconductor rectifier device 1 is in operation, and the doped regions 221 and 222 extending laterally to the silicon carbide layer 12 below the gate structure will facilitate the flow of current. Figure 4 As shown, due to the coverage of the patterned layer 51, even if the oblique ion implantation is performed, the contact range of the doped regions 221, 222 to the surface 12A is very limited. Figure 8After the dry etching process, the range of the doped regions 221 and 222 contacting the surface 12C increases, which is beneficial to the flow of current and improves the efficiency of the semiconductor rectifier device 1. In some embodiments, after the dry etching step, the height of the side wall 41C is less than the height of the side wall 41D. In some embodiments, after the dry etching step, the doped region 221 is adjacent to the corner of the side wall 41C and the surface 12C. In some embodiments, after the dry etching step, the doped region 221 is adjacent to the side wall 41C and a portion of the surface 12C. Similarly, the heights of the side walls 42C and 42D of the groove 42 are approximately the same as the height of the side wall 41C. In addition, the positional relationship between the doped region 222 and the surface 12C is similar to the positional relationship between the doped region 221 and the side wall 41C, and will not be repeated here.

[0031] Reference Fig. 9 , the manufacturing method of the semiconductor rectifier device 1 includes forming a dielectric layer 15 on the exposed surface 12C of the silicon carbide layer 12. In some embodiments, the dielectric layer 15 includes an oxide (e.g., silicon oxide). In some embodiments, the silicon carbide layer 12 is subjected to a thermal oxidation step to form the dielectric layer 15. In some embodiments, the thickness of the dielectric layer 15 is between 50 angstroms and 200 angstroms. In some embodiments, the dielectric layer 15 serves as a gate dielectric layer of a gate structure formed later. In some embodiments, the dielectric layer 15 covers the entire exposed surface 12C of the silicon carbide layer 12. The dielectric layer 15 includes a plurality of portions, each extending between adjacent portions of the dielectric layer 14. For example, the dielectric layer 15 includes a portion of the dielectric layer 151 and a portion of the dielectric layer 152. In some embodiments, the portions of the dielectric layer 151 and 152 are separated from each other. In some embodiments, the portion of the dielectric layer 151 extends on the surface 12C between the grooves 41 and 42. In some embodiments, the portion of dielectric layer 151 is located between and contacts the portions of dielectric layers 141 and 142. In some embodiments, the portion of dielectric layer 152 extends on the surface 12C between the portion of dielectric layer 142 and another portion of another adjacent dielectric layer 14 (not shown).

[0032] Reference Fig.10 , the manufacturing method of the semiconductor rectifier device 1 includes forming a gate electrode layer 16 on the dielectric layer 15. In some embodiments, the gate electrode layer 16 includes polysilicon. In some embodiments, a deposition step is performed to form a gate electrode material covering the entire silicon carbide layer 12, and then an etching step is performed to remove the gate electrode material above the top surface 14A of the dielectric layer 14 to form the gate electrode layer 16. Similar to the dielectric layer 15, the gate electrode layer 16 also includes a plurality of parts, which are respectively formed on different parts of the dielectric layer 15. For example, the gate electrode layer 16 includes a gate electrode 161 on a portion of the dielectric layer 151, a gate electrode 162 adjacent to the gate electrode 161 on a portion of the dielectric layer 152, and the gate electrodes 161 and 162 are separated from each other.

[0033] Since the gate electrode layer 16 and the dielectric layer 14 have an etching selectivity, the etching step performed on the gate electrode material stops at the top surface 14A of the dielectric layer 14. Therefore, the top surface 16A of the gate electrode layer 16 and the top surface 14A of the dielectric layer 14 are located at approximately the same level. In some embodiments, the top surface 16A of the gate electrode layer 16 is flush with or coplanar with the top surface 14A of the dielectric layer 14. In other words, the top surface 161A of the gate electrode 161 is at the same level or coplanar with any one or more of the top surface 141A of the portion of the dielectric layer 141, the top surface 142A of the portion of the dielectric layer 142, and the top surface 162A of the gate electrode 162. Furthermore, since the surface 14A of the dielectric layer 14 is flush with or coplanar with the surface 12A of the silicon carbide layer 12, the top surface 16A of the gate electrode layer 16 is flush with or coplanar with the surface 12A of the silicon carbide layer 12. In other words, any one or more of top surface 161A of gate electrode 161 , top surface 162A of gate electrode 162 are located at the same level as surface 12A of silicon carbide layer 12 .

[0034] Reference Fig.11 , the manufacturing method of the semiconductor rectifier device 1 includes removing the dielectric layer 14. In some embodiments, wet etching is performed to remove the dielectric layer 14 in the grooves 41 and 42. The gate electrode 161 and a portion of the dielectric layer 151 together constitute the gate structure 171, and the gate electrode 162 and a portion of the dielectric layer 152 together constitute the gate structure 172. In some embodiments, the sidewall of the gate structure 171 adjacent to the sidewall 41C is in a straight line with the sidewall 41C from a cross-sectional view, and the sidewall of the gate structure 171 adjacent to the sidewall 42D is in a straight line with the sidewall 42D from a cross-sectional view. The gate structure 172 has a similar configuration to the gate structure 171, and no repeated description is given here.

[0035] Reference Fig.12, the manufacturing method of the semiconductor rectifier device 1 includes conformally forming a contact metal layer 31 on the silicon carbide layer 12 and the gate structure 17. The contact metal layer 31 may include a suitable metal material, such as titanium (Ti), nickel (Ni), molybdenum (Mo), titanium nitride (TiN), molybdenum nitride (MoN) or a combination thereof. In some embodiments, the contact metal layer 31 contacts the sidewall 41C and a portion of the bottom surface 41B of the groove 41, and contacts the sidewalls 42C, 42D and the bottom surface 42B of the groove 42. In addition, since the process of forming the contact metal layer 31 or thereafter may be a temperature step between 400 and 600°C, a metal silicide is formed between the contact metal layer 31 and the silicon carbide layer 12, and between the contact metal layer 31 and the gate electrode layer 16. The formation of the metal silicide can reduce the resistance between the contact metal layer 31 and the silicon carbide layer 12 or between the contact metal layer 31 and the gate electrode layer 16, which helps to improve the performance of the semiconductor rectifier device 1.

[0036] Reference Fig.13 , the manufacturing method of the semiconductor rectifier device 1 includes forming a first electrode layer 32 on the contact metal 31. The first electrode layer 32 may include a suitable metal material or alloy, such as titanium tungsten (TiW), aluminum silicon copper alloy (AlSiCu) or a combination thereof, which is not limited here. After forming the first electrode layer 32, the first electrode layer 32 and the contact metal 31 may be etched so that part of the gate structure 17 is electrically connected and part of the gate structure 17 is electrically isolated. Since the etching step is performed according to the required circuit design, the etching step is not shown in the figure, and those skilled in the art can adjust the etching step according to the above content of the present disclosure to form the required pattern of the first electrode layer 32 and the pattern of the contact metal 31.

[0037] Reference Fig.14 , the manufacturing method of the semiconductor rectifier device 1 includes forming a passivation layer 33 on the first electrode layer 32, and forming a second electrode layer 34 below the silicon carbide layer 12. In some embodiments, the passivation layer 33 can be formed by a deposition step and a patterning step. The first electrode layer 32 exposed by the passivation layer 33 is used to be electrically connected to the conductive plug in the subsequent process of forming a conductive plug (not shown in the figure). In some embodiments, the second electrode layer 34 has the same conductive material as the first electrode layer 32. The second electrode layer 34 and the first electrode layer 32 are located on opposite sides of the silicon carbide layer 12. In some embodiments, the second electrode layer 34 is formed on the surface 11B of the semiconductor material layer 11. In some embodiments, the second electrode layer 34 contacts the semiconductor material layer 11. In some embodiments, the semiconductor material layer 11 is ground or etched before the second electrode layer 34 is formed to reduce the thickness of the semiconductor material layer 11.

[0038] Fig.14 The arrows in the figure are used to indicate the direction of the current when the semiconductor rectifier device 1 is working. It can be understood that the larger the range of the doped region 221 in lateral contact with the surface 12C, the more conducive the current is to flow. Figure 4 The oblique ion implantation in the embodiment helps the doped region 22 to extend horizontally along the groove sidewalls (e.g., 41C, 42C, 42D). However, the patterned layer 51 will limit the horizontal extension range of the doped region 22 adjacent to the surface 12A. This problem can be solved by the aforementioned Figure 8 The doping region 221 at the bottom of the gate structure 171 can provide a function of an extended doping region (similar to a lightly doped drain extension (LDD) in a transistor), which can improve the operating speed of the semiconductor rectifier device 1.

[0039] The self-aligned gate process helps to reduce the use of photomasks, which not only avoids alignment problems but also reduces the overall process cost. However, the existing gate structure self-aligned process uses the gate structure as a mask to perform ion implantation on the substrate. Therefore, the annealing step for activating ions needs to be performed after the gate structure is formed, which makes the self-aligned gate unsuitable for silicon carbide materials. Figures 1 to 14 The high temperature annealing step of the present invention is performed before the step of forming the gate structure 17, so it can solve the problem of gate structure damage caused by excessively high annealing temperature in the prior art, and can be further applied to silicon carbide materials. The doping region 22 and the gate structure 17 can be defined by the patterned layer 51, without the need for an additional photomask, to achieve the effect of the self-aligned gate process of the prior art. In addition, since the doping region 22 is formed by an oblique angle ion implantation step, the present invention can achieve the effect of self-aligned extended doping region.

[0040] Fig.15 , 16 1 and 2 are top views of semiconductor rectifier devices 2 and 3 according to different embodiments of the present invention, showing different configurations that the gate structure 17 may have. Figure 2 , 3 The configuration of the gate structure 17 is for illustration only and is not intended to limit the present disclosure.

[0041] Reference Fig.15 In some embodiments, the gate structure 17 includes a plurality of groups, and the extension directions of the gate structures 17 of adjacent groups are perpendicular to each other. In some embodiments, the doped region 21 is annular and surrounds all the gate structures 17. In some embodiments, Fig.14 The gate structures 171 and 172 are connected to each other. In some embodiments, the gate structures 171 and 172 belong to two sides of the same gate structure, wherein the two sides are opposite to each other and parallel to each other. In some embodiments, Figures 1 to 14 is based on Fig.15In some embodiments, Figures 1 to 14 is based on Fig.15 In some embodiments, the doped region 25 is adjacent to the surface 12A and surrounds the doped region 221 from a top view.

[0042] Reference Fig.16 In some embodiments, the gate structures 17 are multiple adjacent and parallel gate structures 17. In some embodiments, the doped region 21 is annular and surrounds all gate structures 17. In some embodiments, the extension direction of the gate structure 17 is parallel to one side of the semiconductor rectifier device 3. Connected to each other. In some embodiments, Fig.14 The gate structures 171 and 172 are connected to each other. In some embodiments, the gate structures 171 and 172 belong to two sides of the same gate structure, wherein the two sides are opposite to each other and parallel to each other. In some embodiments, Figures 1 to 14 is based on Fig.15 In some embodiments, the doped region 25 is adjacent to the surface 12A and surrounds the doped region 221 from a top view.

[0043] According to the structure and process of the present disclosure described above, under the same purpose and concept, the steps in the above process can be adjusted or replaced in sequence to achieve the same or similar vertical power semiconductor device semiconductor rectifier device. Figures 17 to 23 FIG. 1 shows one or more stages in a method for manufacturing a semiconductor rectifier device 4 according to another embodiment of the present invention. At least some of the drawings have been simplified to facilitate a better understanding of the present disclosure. Figures 1 to 14 The processes shown are described in detail in detail, and the same or similar steps will not be described repeatedly.

[0044] Reference Figure 17 to Figure 18 , according to the above Figures 1 to 3 The steps to form a plurality of grooves are different in that Fig.18 In some embodiments, the plurality of grooves further include a groove 43 adjacent to the groove 42, the groove 43 and the groove 41 are located on opposite sides of the groove, and the groove 41 is formed in the doping region 21. In some embodiments, the patterned layer 51 further includes an opening 513 corresponding to the groove 43. In some embodiments, the patterned layer 51 further includes an opening 513 corresponding to the groove 43. In some embodiments, from the cross-sectional view, the opening 511 is located within the coverage of the projection of the doping region 21 along the vertical direction. In some embodiments, from the cross-sectional view, the sidewalls 41C, 41D and the bottom surface 41B of the groove 41 adjacent to the doping region 21.

[0045] Reference Fig.19 , according to the above Figure 4 The steps of forming a plurality of doping regions 22 are different in that: Fig.19 In the ion implantation step shown, since the groove 41 is formed within the coverage of the doped region 21 of the silicon carbide layer 12, the doped region 221 overlaps with the doped region 21. In other words, part of the doped region 21 adjacent to the sidewalls 41C, 41D and the bottom surface 41B of the groove 41 is simultaneously ion implanted in the step of forming the doped region 22. In some embodiments, the doped region 221 is formed in the doped region 21. In some embodiments, the doping concentration of the doped region 221 is higher than that of the doped region 21 or other doped regions 22 (such as doped regions 222 and 223). Fig.19 After the steps, you can follow the above Figure 5 A step of forming a carbon-containing layer is performed, a high temperature annealing step is performed after the carbon-containing layer is formed, and the carbon-containing layer is removed after the high temperature annealing step.

[0046] Reference Fig. 20 , according to the above Figure 7 The dielectric layer 14 is formed by the steps of Fig. 20 The dielectric layer 14 shown further includes a portion of the dielectric layer 143 located in the groove 43 , and opposite sidewalls and a bottom surface of the portion of the dielectric layer 141 are adjacent to the doped region 221 .

[0047] Reference Fig.21 , according to the above Figure 8 The step of removing the portion of the silicon carbide layer 12 adjacent to the surface 12A is different in that: Fig. 20 The silicon carbide layer 12 is not shown Figure 8 The silicon carbide layer 12 is covered by the dielectric layer 13, so the silicon carbide layer 12 does not have a surface 12A and a surface 12C located at different levels at the same time. In some embodiments, the etching process is performed on all surfaces 12A exposed to the dielectric layer 14. In other words, in some embodiments, the top surface of the silicon carbide layer 12 after the etching step (equivalent to the surface 12C) is lower than the top surface 14A of the dielectric layer 14.

[0048] Reference Fig. 22 , according to the above Figure 6 The dielectric layer 13 is formed by the steps of Fig. 20 The dielectric layer 13 is shown to be located on the surface 12C and does not cover the groove 41. In some embodiments, the dielectric layer 13 and a portion of the dielectric layer 141 are separated from each other.

[0049] Reference Fig.23 , according to the above Figures 9 to 14 The semiconductor rectifier device 4 is formed by the steps of Fig.23The gate structure 17 further includes gate structures 173 and 174. In some embodiments, the dielectric layer 15 further includes portions of dielectric layers 153 and 154, wherein the portion of dielectric layer 153 is located on a portion of the surface 12C adjacent to the groove 43 and on a side of the groove 43 opposite to the portion of dielectric layer 153, and the portion of dielectric layer 154 is located on the surface 12C between the groove 41 and the dielectric layer 13. In some embodiments, the gate electrode layer 16 further includes a gate electrode 163 located on the portion of the dielectric layer 153, and a gate electrode 164 located on the portion of the dielectric layer 154. In some embodiments, the gate structure 173 includes a portion of the dielectric layer 153 and the gate electrode 163, and the gate structure 174 includes a portion of the dielectric layer 154 and the gate electrode 164. The gate structure 174 is adjacent to the dielectric layer 13 and does not contribute to the operation and performance of the semiconductor rectifier device 4, and is therefore also referred to as a dummy gate.

[0050] According to the structure and process of the present disclosure described above, under the same purpose and concept, the steps in the above process can also be adjusted or replaced in sequence to achieve the same or similar semiconductor rectifier device. Figure 24 to Figure 30 FIG. 1 shows one or more stages in a method for manufacturing a semiconductor rectifier device 5 according to another embodiment of the present invention. At least some of the drawings have been simplified to facilitate a better understanding of the present disclosure. Figures 17 to 23 The processes shown are described in detail in detail, and the same or similar steps will not be described repeatedly.

[0051] Reference Fig.24 , according to the above Fig.18 The steps of forming a plurality of doping regions 22 are different in that Fig.24 In an embodiment, the ion implantation step is to vertically implant ions into the silicon carbide layer 12. In some embodiments, the ion implantation step includes vertical ion implantation. In some embodiments, the ion implantation step does not include oblique angle ion implantation. By adjusting the parameters of the ion implantation process, the multiple doped regions 22 formed can be adjusted to be separated from the surface 12A or adjacent to the surface 12A. In some embodiments, each doped region 22 (including 221, 222, 223) is separated from the surface 12A, and the vertical distance D13 between each doped region 22 (including 221, 222, 223) and the surface 12A is between 1000 and 2000 angstroms. In some embodiments, each doped region 22 (including 221, 222, 223) is adjacent to the surface 12A (similar to Fig.19 doped regions 221, 222, 223).

[0052] Reference Fig.25The manufacturing method of the semiconductor rectifier device 5 further includes forming sidewall spacers 54 on the sidewalls of the openings 511, 512, and 513 of the patterned layer 53. The formation of the sidewall spacers 54, for example, includes conformally depositing a dielectric material on the patterned layer 53 and the silicon carbide layer 12, and then performing an etching process on the dielectric material to remove the horizontal portion of the dielectric material.

[0053] Reference Fig.26 , according to the above Fig.18 (or Figure 3 ) to form a plurality of grooves (including 41, 42, 43), the difference being that: Fig.26 In some embodiments, the silicon carbide layer 12 is etched using the patterned layer 53 and the sidewall spacer 54 as a mask. In some embodiments, the widths of the grooves 41, 42, 43 are smaller than the widths of the openings 51, 52, 53, respectively. In some embodiments, the patterned layer 53 and the sidewall spacer 54 include the same dielectric material. In some embodiments, the patterned layer 53 and the sidewall spacer 54 can be removed simultaneously (or in a single etching step).

[0054] Reference Figure 27 to Figure 30 , according to the above Figure 20 to Figure 23 The semiconductor rectifier device 5 is formed by the steps of Fig.30 The step of forming the doped region 22 of the semiconductor rectifier device 5 does not include an oblique ion implantation, so the configuration of the doped region 22 of the semiconductor rectifier device 5 may be slightly different from the configuration of the doped region 22 of the semiconductor rectifier device 4. Furthermore, in some embodiments, since the doped region 22 of the semiconductor rectifier device 5 is separated from the surface 12A (e.g. Fig. 27 shown), so Fig.28 The preset thickness of the etching step will be controlled to be greater than or equal to Fig.24 The distance D13 is shown to ensure that the plurality of doped regions 221 , 222 , 223 (especially 222 , 223 ) contact the surface 12C.

[0055] The semiconductor rectifier device 4 and the semiconductor rectifier device 5 formed according to the above method have similar structures to the semiconductor rectifier device 1, and their advantages over the prior art are the same as those of the semiconductor rectifier device 1, which will not be described in detail here. Therefore, the semiconductor rectifier device provided by the present disclosure benefits from the material properties of silicon carbide, can reduce power consumption and improve switching efficiency, and the manufacturing method provided by the present disclosure can effectively integrate the self-alignment process on the silicon carbide material, avoid the damage to the gate structure caused by the high-temperature annealing process, and reduce the total process cost.

[0056] Spatially relative terms such as "under," "below," "lower," "above," "upper," "left," "right," and the like may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use or operating in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0057] As used herein, the terms "approximately", "substantially", "substantially" and "about" are used to describe and explain small changes. When used in conjunction with an event or situation, the term can refer to an instance where the event or situation occurs precisely and an instance where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1% or ±0.5% of a given value or range. The range can be expressed as one endpoint to another endpoint or between two endpoints herein. All ranges disclosed herein include endpoints unless otherwise specified. The term "substantially coplanar" can refer to a position difference of two surfaces positioned along the same plane within a few microns (μm), such as a position difference positioned along the same plane within 10 μm, within 5 μm, within 1 μm or within 0.5 μm. When a numerical value or characteristic is referred to as being "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the value.

[0058] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures to facilitate the implementation of the same or similar purposes and / or to achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor rectifier device, characterized in that: include: an epitaxial layer having a top surface and a bottom surface opposite to each other; A first groove extending from the top surface to the bottom surface and comprising a first side wall and a second side wall opposite to each other, and a first bottom surface connecting the first side wall and the second side wall; a second groove extending from the top surface to the bottom surface and adjacent to the first groove, the second groove comprising a third side wall and a fourth side wall opposite to each other, and a second bottom surface connecting the third side wall and the fourth side wall; a first doped region extending from the top surface toward the bottom surface and adjacent to the first sidewall of the first groove and at least a portion of the first bottom surface; a second doped region, adjacent to and separated from the first doped region, extending from the top surface to the bottom surface, and adjacent to the third sidewall, the fourth sidewall, and the second bottom surface of the second groove; as well as A gate structure is disposed on the top surface between the first groove and the second groove, and a bottom surface of the gate structure is adjacent to the first doped region and the second doped region; as well as A contact metal layer is disposed on the top surface of the epitaxial layer along the first groove, the gate structure and the second groove.

2. The semiconductor rectifier device according to claim 1, wherein the gate structure comprises a fifth sidewall and a sixth sidewall opposite to each other, wherein the fifth sidewall and the second sidewall of the first groove are in a straight line from a cross-sectional view, and the sixth sidewall of the gate structure and the third sidewall of the second groove are in a straight line from a cross-sectional view.

3. The semiconductor rectifier device according to claim 1, wherein the first side wall of the first groove is connected to the first portion of the top surface, and a portion of the top surface between the first groove and the second groove is the second portion of the top surface, and the first portion and the second portion are located at approximately the same horizontal height.

4. The semiconductor rectifier device according to claim 1, wherein the first side wall of the first groove is connected to a first portion of the top surface, a portion of the top surface between the first groove and the second groove is a second portion of the top surface, and a horizontal height of the first portion is higher than a horizontal height of the second portion.

5. The semiconductor rectifier device according to claim 1, further comprising: The third doping region extends from the top surface toward the bottom surface and overlaps with at least a portion of the first doping region, and a depth of the third doping region is greater than a depth of the first doping region. 6 . The semiconductor rectifier device according to claim 5 , wherein a portion of the third doping region close to the first doping region has a higher doping concentration.

7. The semiconductor rectifier device according to claim 1, wherein the contact metal layer contacts the second sidewall of the first groove, the bottom surface of the first groove, the third sidewall and the fourth sidewall of the second groove, and the bottom surface of the second groove. 8 . The semiconductor rectifier device according to claim 1 , wherein the first doped region further adjoins the first sidewall of the first groove.

9. The semiconductor rectifier device according to claim 1, wherein the first height of the first side wall of the first groove is greater than the second height of the second side wall, the third height of the third side wall of the second groove is approximately equal to and approximately the same as the fourth height of the fourth side wall, and the second height, the third height, and the fourth height are approximately the same.

10. A method for manufacturing a semiconductor rectifier device, characterized in that: include: forming a patterned layer on the silicon carbide layer; Using the patterned layer as a mask, etching the silicon carbide layer to form a first groove and a second groove adjacent to the first groove; Performing ion implantation on the silicon carbide layer using the patterned layer as a mask; thermally annealing the silicon carbide layer; as well as After the thermal annealing, a gate structure is formed on the silicon carbide layer between the first groove and the second groove, wherein the gate structure has a first sidewall and a second sidewall opposite to each other, the first sidewall and a side wall of the first groove are continuous sidewalls, and the second sidewall and a side wall of the second groove are continuous sidewalls.

11. The manufacturing method according to claim 10, further comprising: Before the thermal annealing, forming a carbon-containing layer covering the silicon carbide layer; as well as After the thermal annealing, the carbon-containing layer is removed.

12. The manufacturing method according to claim 10, further comprising: forming a first dielectric layer to fill the first groove and the second groove, wherein a top surface of the first dielectric layer is flush with a top surface of the silicon carbide layer; removing a portion of the silicon carbide layer adjacent to the top surface of the silicon carbide layer that is exposed to form a first surface that is lower than the top surface of the silicon carbide layer, wherein the first surface is higher than a bottom surface of the first groove; as well as The gate structure is formed on the first surface.

13. The manufacturing method according to claim 12, wherein forming the electrode structure on the first surface comprises: forming a second dielectric layer on the first surface; as well as A gate electrode layer is formed on the second dielectric layer, wherein a top surface of the gate layer is flush with the top surface of the first dielectric layer. 14 . The manufacturing method according to claim 12 , wherein a vertical distance between the first surface and the top surface of the silicon carbide layer is between 1500 and 2000 angstroms.

15. The manufacturing method according to claim 10, further comprising: Before forming the patterned layer, a terminal doping region is formed in the silicon carbide layer. 16 . The manufacturing method according to claim 15 , wherein the patterned layer exposes a portion of the terminal doping region, and the terminal doping region is adjacent to the first groove. 17 . The manufacturing method according to claim 15 , wherein the patterned layer comprises an opening for defining the first groove, and from a cross-sectional view, the opening overlaps a portion of the terminal doped region along a vertical direction. 18 . The manufacturing method according to claim 15 , wherein the patterned layer comprises an opening for defining the first groove, and from a cross-sectional view, the opening is located within a coverage range of a projection of the terminal doping region along a vertical direction.

19. The manufacturing method according to claim 15, further comprising: Before forming the electrode structure on the silicon carbide layer between the first groove and the second groove, a third dielectric layer is formed to cover the terminal doping region and a portion of the first groove adjacent to the terminal doping region.

20. The manufacturing method according to claim 10, further comprising: Conformally forming a contact metal layer on the silicon carbide layer and the electrode structure, wherein the contact metal layer contacts the sidewall and bottom surface of the first groove, and contacts the sidewall and bottom surface of the second groove; forming a first electrode layer on the contact metal layer; as well as A second electrode layer is formed below the silicon carbide layer, wherein the first electrode layer and the second electrode layer are located on opposite sides of the silicon carbide layer.

21. The manufacturing method according to claim 20, further comprising: providing a substrate; epitaxially growing the silicon carbide layer on the substrate; reducing the thickness of the substrate; as well as The second electrode layer is formed, wherein the second electrode layer contacts the substrate.

22. The manufacturing method according to claim 10, wherein a depth of the first groove or the second groove is between 4000 and 5000 angstroms.

23. The manufacturing method according to claim 10, wherein the ion implantation comprises oblique angle ion implantation.

24. The manufacturing method according to claim 10, further comprising: Before the ion implantation, sidewall spacers are formed on a plurality of sidewalls of the patterned layer. 25 . The manufacturing method according to claim 24 , wherein the ion implantation is performed on the silicon carbide layer using the patterned layer and the sidewall spacer as a mask.

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