Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure including a substrate having a device region and a dummy region and a method of manufacturing the same are provided. A first active region is disposed over the substrate in the device region, and a second active region is over the substrate in the dummy region. A first operational gate structure is over the first active region and a first non-operational gate structure is over the second active region. A first epitaxial region of n-type dopant adjacent the first operating gate structure; and the second epitaxial region of the n-type dopant is adjacent to the first non-operating gate structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs, and in order to achieve these advances, similar developments in IC processing and manufacturing are needed.

[0003] Such shrinkage also increases the complexity of processing and manufacturing ICs. For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FiNFETs) and multi-bridge channel (MBC) transistors (also referred to as full-all-around gate (GAA) devices) are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. MBC transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. For various performance considerations, planar transistors can also be implemented.

[0004] Semiconductor devices such as the transistors discussed above are active devices that are formed, in some instances, along with passive devices, on a device region of a substrate. The substrate also includes a dummy region that may not include functional devices. Although existing techniques for fabricating semiconductor structures that include device regions and dummy regions are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor structure, including: a substrate, including a device region and a dummy region; a first active region and a second active region, the first active region being located above the substrate in the device region, and the second active region being located above the substrate in the dummy region; a first operating gate structure being located above the first active region; a first non-operating gate structure being located above the second active region; a first epitaxial region of n-type dopants, adjacent to the first operating gate structure; and a second epitaxial region of n-type dopants, adjacent to the first non-operating gate structure.

[0006] Other embodiments of the present application provide a semiconductor structure, including: a substrate, including a device region and a dummy region; a plurality of n-type epitaxial (NEPI) regions, located in the dummy region, wherein the plurality of n-type epitaxial regions include an active region extending in a first direction, a plurality of gate structures extending in a second direction, and an n-type doped epitaxial region; and a plurality of n-type epitaxial regions, located in the device region, wherein the plurality of n-type epitaxial regions include an active region extending in the first direction, a plurality of gate structures extending in the second direction, and an n-type doped epitaxial region.

[0007] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: providing a substrate having a dummy region and a device region; forming a first active region in the dummy region, and forming a second active region in the device region; forming a gate structure above the substrate, wherein a first plurality of gate structures extend above the first active region in the dummy region, and a second plurality of gate structures extend above the second active region in the device region; providing a first masking element having a first opening group above the dummy region and the device region; when providing the first masking element, growing a first plurality of epitaxial regions having a first dopant type in the dummy region and the device region; providing a second masking element having a second opening group above the dummy region and the device region; and when providing the second masking element, growing a second plurality of epitaxial regions having a second dopant type in the dummy region and the device region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a flow chart of an exemplary method for designing a layout according to various aspects of an embodiment of the present disclosure.

[0010] Figure 2A and Figure 2B is a partial layout of an exemplary semiconductor structure according to various aspects of the embodiments of the present disclosure.

[0011] Figure 3A and Figure 3B The present invention shows various aspects of the embodiments of the present invention. Figure 2B An alternative embodiment of an enlarged portion of a layout.

[0012] Figure 4A According to various aspects of the embodiments of the present disclosure Figure 2B A partial view of the layout. Figure 4B , Figure 4C and Figure 4D According to various aspects of the embodiments of the present disclosure, Figure 2B An exemplary embodiment of a semiconductor structure of a layout.

[0013] Figure 5 is a top view of a layout of an embodiment of a semiconductor structure including a device region and a dummy region according to various aspects of the embodiments of the present disclosure.

[0014] Figures 6 to 11 1 are each top views of a layout of an embodiment of a dummy region of a semiconductor structure according to various aspects of an embodiment of the present disclosure.

[0015] Fig.12 is a flow chart of an exemplary method for fabricating a semiconductor structure according to various aspects of an embodiment of the present disclosure.

[0016] Fig.13 is used to implement Figure 1 A block diagram of a system of one or more aspects of an embodiment of the present disclosure of a method. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] In forming a semiconductor structure such as a semiconductor chip, an active semiconductor device such as a transistor is formed on a substrate. The transistor may be a planar transistor or a multi-gate transistor, such as a fin field effect transistor (FiNFET) or a full-all-around gate (GAA) transistor. The transistors are interconnected to form an integrated circuit (IC). The transistors fabricated on the substrate may be a p-type transistor or a PMOS transistor (e.g., including a p-type source / drain component) or an n-type transistor or an NMOS transistor (e.g., an n-type source / drain component). PMOS and NMOS transistors are formed in a device region of the substrate. In particular, the semiconductor structure includes many oxide-defined (OD) or active device regions on which transistors are formed. The OD region defines an active region for each transistor; that is, a region forming the source / drain and channel of the transistor. The OD region is defined between isolation regions such as those provided by shallow trench isolation (STI) or field oxide (FOX) regions.

[0021] Semiconductor structures are formed starting with a design process. Computer-aided design / electronic design automation (CAD / EDA) tools allow semiconductor devices to be designed in this way. In some embodiments, the circuit design process starts with a specification that describes the desired functionality of a semiconductor structure (e.g., an integrated circuit) and may include various performance requirements. Then, during the logic design phase, one of several hardware description languages ​​(e.g., Verilog or VHDL at the register transfer logic (RTL) level of abstraction) is used to describe the logic implementation of the semiconductor structure. EDA software tools can use libraries to synthesize the abstract logic into a technology-dependent netlist. The outputs may also describe the behavior of the circuits on the chip, as well as the interconnections to the inputs and outputs.

[0022] After the logical design phase, the design enters the physical design phase. Physical design creates a semiconductor structure design (e.g., a chip design). Physical design includes various steps, including floorplanning, placement and routing, layout and schematic comparison (LVS), and design rule checking (DRC) determination. After the design of a semiconductor structure such as an integrated circuit chip is completed, a file (e.g., a graphic data system (GDS) file) including the layout of the semiconductor structure is generated. The information is then provided (e.g., tape-out) to a manufacturing facility. Masks are then manufactured that define the layers of the layout and are used to manufacture the semiconductor structure itself. The disclosed embodiments include features that may be present in the layout during the design process.

[0023] A consideration in the design phase, and in particular in the physical design phase, is uniformity across the chip. Physical variations are introduced across the structure according to certain semiconductor manufacturing processes designed for manufacturing chips. Physical variations may cause electrical performance and reliability issues. And therefore, a dummy region is provided in a semiconductor structure (e.g., a chip) including an active region (e.g., including active semiconductor devices such as transistors discussed above). The dummy region may include components (e.g., transistor components) similar to the active region that do not provide electrical functions (e.g., not interconnected) to the semiconductor structure. The dummy region may mitigate any loading effects during patterning, etching, polishing, deposition, and / or other manufacturing processes. The present disclosure provides semiconductor structures, systems, and methods that define dummy regions. The present disclosure provides a design of a dummy region that can be formed on a substrate together with an active region.

[0024] In semiconductor structure design, a standard cell is a box of transistors that is repeated according to a set of design rules across a design layout. Standard cells can be used for different functions. For example, a standard cell can be a static random access memory (SRAM) cell or a logic cell for logic operations. A standard cell may include one or more p-type transistors and one or more n-type transistors. In some embodiments, a cell that is a pseudo-cell may also be formed. The disclosed embodiments include a pseudo-region layout that may be provided as a cell for implementation into a semiconductor structure, as discussed below.

[0025] Figure 1 A method 100 is shown that can be implemented to form a semiconductor structure layout. In an embodiment, the semiconductor structure is a chip, and in particular an integrated circuit (IC) chip. The method 100 is merely exemplary and is not intended to limit the disclosed embodiments to those explicitly shown therein. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For reasons of simplicity, not all steps are described in detail herein.

[0026] In a first block 102, in a design process such as the physical design process discussed above, device regions are identified on a layout for a semiconductor structure. The device regions may include active devices of n-type transistors and p-type transistors. The transistors may be planar devices, FiNFET devices, GAA devices, nanosheet devices, and / or suitable transistor configurations.

[0027] Method 100 and frame 102 can be used to define the layout of semiconductor devices including but not limited to active and passive devices. Examples of active devices include: transistors, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), FiNFETs, GAA devices, nanosheet transistors (including those shown below), planar MOS transistors including those with protruding source / drains, etc. Other active devices include diodes. Examples of passive components include but are not limited to capacitors, inductors, fuses, resistors, etc. The layout may include interconnect components that couple one or more of the active and passive devices together and to the input / output terminals of the semiconductor structure. Components (e.g., gate structures) of semiconductor devices may be operational (e.g., contributing to the function of the device).

[0028] In block 104 of method 100, a dummy region of the substrate for the semiconductor structure is defined. Block 104 may be performed simultaneously with block 102. The dummy region may include a device (e.g., an IC chip) that does not provide electrical functionality to the semiconductor structure. In other words, components of the dummy region (e.g., a gate structure) may be non-operational. The dummy region may include structures implemented using substantially the same manufacturing processes as those of the device region. The dummy region may be an adjacent device region.

[0029] In block 106, method 100 continues with defining components within the dummy region of block 104. In some embodiments, the dummy region includes, for example, transistor components that are substantially the same as those components that form the transistors of the device region (e.g., OD region, gate structure, source / drain region). In some further embodiments, the transistor components of the dummy region are not connected (e.g., lack contacts) such that they are not interconnected to each other and / or to input / output (I / O) of a semiconductor structure (e.g., an IC chip).

[0030] In particular, in some embodiments, block 106 includes: defining certain sub-regions of the dummy region including dummy components substantially similar to n-type transistor components and certain sub-regions of the dummy region including dummy components substantially similar to p-type transistors. For example, in some embodiments, one or more sub-regions are provided, which provide dummy components substantially similar to n-type transistors such as n-type epitaxial (NEPI) regions. The sub-regions including these n-type transistor components (e.g., NEPI) can be referred to as NEPI regions. The NEPI region can provide a source / drain region of a functional n-type transistor. The NEPI region in the manufacture of the chip is usually defined by a masking element, which provides an opening in the dummy region and an opening in the device region, wherein the opening in the device region allows the formation of a source / drain component of an n-type transistor. The n-type epitaxial region is formed on the OD or active region exposed by the opening. In an embodiment, the NEPI region provides an n-type epitaxial region in the dummy region, which is substantially similar to the source / drain region of the n-type transistor of the device region, and is formed simultaneously with the source / drain region of the n-type transistor of the device region.

[0031] In addition, in frame 106, in some embodiments, one or more sub-regions are also provided, which provide dummy components of p-type transistors substantially similar to p-type epitaxial (PEPI) regions. The sub-regions including these p-type transistor components (e.g., PEPI) can be referred to as PEPI regions. The PEPI region in the manufacture of the chip is generally defined by a masking element, which provides an opening in the dummy region and an opening in the device region, wherein the opening in the device region allows the formation of source / drain components of the p-type transistor. The p-type epitaxial region is formed on the active region or OD region exposed by the opening. In an embodiment, the PEPI region provides a p-type epitaxial region in the dummy region, which is substantially similar to the source / drain region of the p-type transistor of the device region, and is formed simultaneously with the source / drain region of the p-type transistor of the device region.

[0032] The configuration of the layout pattern of the dummy region, including the location and number of NEPI regions and PEPI regions, is selectively determined based on the components of the active region of block 102. For example, in some embodiments, the number of NEPI regions in the dummy region is the same as the number of PEPI regions in the device region. In some embodiments, the number of PEPI regions in the dummy region is the same as the number of NEPI regions in the device region. The layout pattern may be any of the patterns discussed herein, including the following discussed. Figures 5 to 11 Those.

[0033] Then, block 108 continues with further processing. The further processing may include additional design processes, such as design rule checking, tape-out of the layout, fabrication of a photomask based on the layout, and fabrication of a semiconductor structure based on the photomask. The fabricated semiconductor structure may include a dummy region having multiple NEPI regions and, in some embodiments, multiple NEPI regions and PEPI regions.

[0034] refer to Figure 2A , a segment of a plan view of a semiconductor structure 200 is shown. The plan view includes a chip boundary region 202. The area between the edge of the chip 200 and the chip boundary region 202 may provide a keep-out zone, which may not include any active or passive component semiconductor devices. A plurality of sub-regions 204 are formed on the semiconductor chip. The sub-regions 204 may be similar to each other. In an embodiment, the individual sub-regions 204 may be patterned to include components that are different from each other. In an embodiment, the sub-regions 204 are formed by the same pattern. For reference purposes, in an embodiment, the dotted lines illustrate the stepping field of the lithography process. In some embodiments, the stepper distance may be half the length of the sub-region 204 in the x-direction. In an embodiment, the sub-regions define an area of ​​approximately 18 μm by 18 μm in the manufactured device.

[0035] The sub-region 204 may include a device region 204A and a dummy region 204B. Figure 2B . The device region 204A may be defined as discussed above with reference to block 102 of method 100. The dummy region 204B may be defined as discussed above with reference to block 104 of method 100. Each of the device region 204A and the dummy region 204B includes a plurality of ODs or active regions on which semiconductor devices such as transistors are formed. For example, gate structures and source / drain features are formed on the OD regions.

[0036] Device region 204A may include a functional n-type transistor (e.g., including an OD region for an n-type transistor) and a functional p-type transistor (e.g., including an OD region for a p-type transistor). Pseudo region 204B may include dummy OD regions corresponding to those formed in device region 204A. In the illustrated embodiment, dummy region 204B is approximately the same in shape and size as device region 204A. However, other configurations are also possible. In some embodiments, the components in device region 204A and dummy region 204B are implemented using substantially the same manufacturing process and have substantially the same internal structure.

[0037] Each of the sub-region 204 and the device region 204A and the dummy region 204B is not limited to the quadrilateral top view shown, and for example, a polygonal structure including a triangular, pentagonal and octagonal structure and a circular structure including an elliptical structure may be adopted without departing from the technical concept of the embodiment of the present disclosure. In an embodiment, all OD regions (dummy and device) may be larger than at least 10% of the structure (e.g., chip) 200.

[0038] When fabricated as a semiconductor structure 200, a semiconductor substrate 201 is provided. In an embodiment, the substrate 201 includes silicon. Optionally or additionally, the substrate 201 includes: another element semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Optionally, the substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using isolation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0039] Figure 3A and Figure 3B A layout diagram of a portion of a semiconductor structure 200 is shown. The layout may be constructed using Figure 1 Method 100 and / or Fig.13 The system 1300 is used to generate and store. Generally, in the disclosed embodiments, a layout or a plan view also illustrates a semiconductor structure corresponding to the layout, because at the end of the manufacturing process, the layout will be manufactured into a semiconductor structure.

[0040] Figure 3A and Figure 3B 2. Exemplary sub-regions 204' and 204' of the layout of the semiconductor structure are shown, respectively. Sub-region 204' includes device region 204A' and dummy region 204B', which is substantially similar to that described above with reference to FIG. Figure 2A and Figure 2B As discussed above. Device region 204A' includes a first plurality of NEPI regions 304 and a second plurality of PEPI regions 302. NEPI region 304 provides an area in which components of an n-type transistor are formed, such as an OD component, a gate structure, and an n-type doped source / drain of an n-type transistor. NEPI region 304 is also referred to as a unit. PEPI region 302 provides an area in which components of a p-type transistor are formed, such as an OD component, a gate structure, and a p-type source / drain of a p-type transistor. PEPI region 302 is also referred to as a unit. In the embodiment shown, a three-by-two (row-by-column) arrangement of PEPI region 302 and a two-by-two (row-by-column) arrangement of NEPI region 304 are shown in device region 204A'. Other embodiments are also possible. In some embodiments, the arrangement of PEPI region and NEPI region is dynamically adjusted so that the ratio of PEPI region to NEPI region is adjusted to achieve desired device functions and performance.

[0041] NEPI region 304 includes n-type epitaxial material and is defined by the edge of the n-type epitaxial material. PEPI region 302 includes p-type epitaxial material and is defined by the edge of the p-type epitaxial material. In some embodiments of the manufacture of the semiconductor structure, during the manufacture of structure 200, PEPI region 302 is defined by a first masking element. That is, when the masking element covers the remainder of the structure, an opening is provided in the masking element-PEPI region 302-, and a p-type epitaxial structure is manufactured on the exposed OD region. And in some embodiments, during the manufacture of structure 200, NEPI region 304 is defined by another masking element. That is, when the masking element covers the remainder of the structure, an opening is provided in the masking element-NEPI region 304-, and an n-type epitaxial structure is manufactured on the exposed OD region.

[0042] The pseudo region 204B' includes a first plurality of NEPI regions 304 and a second plurality of PEPI regions 302. The NEPI regions 304 may be substantially similar to those in the device region 204A'. That is, the NEPI regions 304 in the pseudo region 204B' provide regions substantially similar to the NEPI regions 304 configuration of the source / drain of the transistor including the device region 204A'. The PEPI regions 302 provide p-type regions. The PEPI regions 302 of the pseudo region 204B' may be substantially similar to the PEPI regions 302 of the device region 204A'. That is, the PEPI regions 302 of the pseudo region 204B' provide p-type regions substantially similar to the PEPI regions 302 configuration of the source / drain of the transistor providing the device region 204A'. In the embodiment as shown, a three-by-two (row-by-column) arrangement of the NEPI regions 304 and a two-by-two (row-by-column) arrangement of the PEPI regions 302 are provided in the pseudo region 204B'.

[0043] In the illustrated embodiment, the configuration of the NEPI regions and PEPI regions from the device region 204A' to the dummy region 204B' is reversed or swapped. In an embodiment, the number of NEPI regions 304 in the device region 204A' may be equal to the number of PEPI regions 302 in the dummy region 204B'. In an embodiment, the number of PEPI regions 302 in the device region 204A' may be equal to the number of NEPI regions 304 in the dummy region 204B'.

[0044] Now go to Figure 3B In the embodiment of the present invention, the sub-region 204" includes a device region 204A" and a dummy region 204B". The device region 204A" includes a first plurality of NEPI regions 304 and a second plurality of PEPI regions 302. The NEPI regions 304 and the PEPI regions 302 may be substantially similar to those described in reference Figure 3A However, in Figure 3B In the embodiment shown in , a three-by-two (row-by-column) arrangement of NEPI regions 304 and a two-by-two (row-by-column) arrangement of PEPI regions 302 are provided in the device region 204A". And a three-by-two (row-by-column) arrangement of PEPI regions 302 and a two-by-two (row-by-column) arrangement of NEPI regions 304 are provided in the dummy region 204B". Figure 3BIn the illustrated embodiment, the configuration of the NEPI regions and PEPI regions from the device region 204A” to the pseudo region 204B” is reversed or swapped. In an embodiment, the number of NEPI regions 304 in the device region 204A” may be equal to the number of PEPI regions 302 in the pseudo region 204B”. In an embodiment, the number of PEPI regions 302 in the device region 204A” may be equal to the number of NEPI regions 304 in the pseudo region 204B”.

[0045] In some embodiments, selecting the number and configuration of NEPI regions 304 and / or PEPI regions 302 of dummy region 204B" and / or dummy region 204B' can be implemented as part of box 106 of method 100. That is, the dummy region 204B' / 204B" configuration can be dynamically adjusted based on the determined layout of active region 204A' / 204A". In some embodiments, the distribution of NEPI regions and PEPI regions in the dummy region allows for convergence of EPI critical dimension (CD) distribution between devices of a semiconductor structure (e.g., a chip). As discussed above, during the manufacture of a semiconductor substrate corresponding to the layout of sub-regions 204' and 204", the NEPI regions and PEPI regions can be defined by masking elements formed in a photolithography process. The aperture ratio of the masking element that provides the NEPI opening affects the NEPI CD. That is, a small aperture ratio (e.g., a lower number of NEPI regions) for the NEPI can provide a larger NEPI CD.

[0046] about FIG. 4A to FIG. 4D Provides references applicable to the above Figure 2A , Figure 2B , Figure 3A and Figure 3B Further description of the sub-regions 204, 204', 204" discussed. In particular, FIG. 4A to FIG. 4D An embodiment of a dummy region 204B of a sub-region 204 is shown. The dummy region 204B may be substantially similar to the above referenced Figure 2B , Figure 3A and Figure 3B Dummy region 204B discussed. In an implementation, transistors formed in dummy region 204B do not provide functionality to the structure being formed (eg, are not interconnected), whereas transistors formed in device region 204A are interconnected to form IC functionality of the structure (eg, chip).

[0047] Figure 4AA plan view of a portion of the dummy region 204B showing the first sub-region 302 and the second sub-region 304 is shown. The first sub-region 302 is a PEPI region. The second sub-region 304 is a NEPI region. The NEPI region is defined for n-type transistors (e.g., dummy n-type transistors). The PEPI region is defined for p-type transistors (e.g., dummy p-type transistors).

[0048] Figure 4B A top view of a dummy region 204B is shown showing a corresponding layout diagram of a first type of sub-region 302 and a second type of sub-region 304. In an embodiment, the first sub-region 302 is a PEPI region and the second sub-region 304 is a NEPI region. Between the sub-regions 302 and 304 may be isolation features, such as isolation features 402 and 412 discussed below.

[0049] like Figure 4B As shown in FIG. 1 , the plurality of gate structures 404 extend in the y-direction in the top view. In some embodiments, the gate structures 404 of the sub-region 304 are substantially collinear with the gate structures 404 of the sub-region 302. In an embodiment, the dielectric region 412 is interposed between the gate structures 404 of the sub-region 302 and the gate structures 404 of the sub-region 304 (see FIG. 1 ). Figure 4C ). The gate structure 404 extends over the corresponding OD region 406. Figure 4B In some embodiments shown in , the OD region 406 extends in the x-direction in the top view.

[0050] In an embodiment, such as Figure 4C and Figure 4D As shown in , OD region 406 is composed of fin elements. The fin element extends vertically from the top surface of the substrate (e.g., z direction) and provides a channel region accessible from multiple sides and the top surface. In the top view, the fin element can extend in the x direction substantially perpendicular to the gate structure 404. In other embodiments, OD region 406 includes a planar semiconductor substrate region. In other embodiments, OD region 406 includes a plurality of nanowires or nanosheets providing a channel region. In an embodiment, OD region 406 is silicon. However, other semiconductor materials including those discussed below with respect to the substrate may be additionally or alternatively implemented.

[0051] Between OD regions 406 are isolation components 402. These isolation regions may also be referred to as shallow trench isolation (STI) components. In some embodiments, isolation components 402 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. Isolation components 402 may include multilayer components. Exemplary deposition processes include low pressure CVD (LPCVD), CVD, plasma enhanced CVD (PECVD), PVD, atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, or other suitable deposition techniques or combinations thereof.

[0052] Between the gate structures 404, an epitaxial region is formed over the OD region 406. The epitaxial region is substantially similar to those of the NEPI region 304 and the PEPI region 302 discussed above, including that the epitaxial region corresponds to the source / drain features of the transistor. Figure 4D As shown in , epitaxial layers 410 and 408 are formed over the OD region 406. In an embodiment, the epitaxial component 408 is a p-type dopant material; and the epitaxial component 410 is an n-type dopant material. Suitable epitaxial processes for forming the p-type epitaxial component 408 include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the components of the OD region 406. When the p-type epitaxial region 408 is formed in the PEPI region 304, the NEPI region 302 may be masked. In various embodiments, the p-type epitaxial component 408 may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe (SiGeB), or other suitable materials. The p-type epitaxial component 408 can be in-situ doped by introducing a doping species including a p-type dopant during the epitaxial process, such as boron or BF2 and / or other suitable dopants including combinations thereof. In some embodiments, an implantation process can be performed to dope the p-type epitaxial component 408. The p-type epitaxial component 408 is configured substantially similar to the source / drain components of the p-type transistor in the device region 204A, but is not connected.

[0053] After forming the p-type epitaxial component 408, the patterned pattern film covering the NEPI region 304 can be removed. Another patterned pattern film (not explicitly shown) can then be formed to cover the PEPI region 302. A suitable epitaxial process for forming the n-type dopant epitaxial component 410 can be similar to the epitaxial process for forming the p-type epitaxial component 408. In various embodiments, the n-type epitaxial component 410 may include silicon, GaAs, GaAsP, SiP, or other suitable materials. The n-type epitaxial component 410 can be in-situ doped during the epitaxial process by introducing a doping substance including an n-type dopant, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. In some embodiments, an implantation process can be performed to dope the n-type epitaxial component 410. The n-type epitaxial component 410 is configured substantially similar to the source / drain components of the n-type transistor in the device region 204A, but is not connected.

[0054] Isolation region 412 is between epitaxial components 408 and 410 ( Figure 4D ) and the gate structure 404 ( Figure 4C ). In an embodiment, the isolation region 412 may include a contact etch stop layer (CESL) and / or an interlayer dielectric (ILD) layer. The CESL may include silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art, and may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer may be deposited by a PECVD process or other suitable deposition techniques.

[0055] The gate structure 404 includes a gate dielectric layer 404A and a gate electrode 404B. In an exemplary process, the gate dielectric layer 404A is first formed, and the gate electrode 404B is deposited over the gate dielectric layer. In an embodiment, the gate structure 404 is a polysilicon gate that provides the electrode 404B of polysilicon. In some embodiments, the gate dielectric layer 404A can be silicon oxide.

[0056] In some other embodiments, the gate structure 404 may be a high-k metal gate structure formed using a dummy gate structure (e.g., the polycrystalline gate discussed above) that is subsequently replaced by a replacement gate process. In some embodiments, the gate dielectric layer 404A may include an interfacial layer and a high-k dielectric layer. The high-k gate dielectric (as used and described herein) includes a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermal silicon oxide (~3.9). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be deposited using chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. The high-K dielectric layer may include hafnium oxide, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, zirconium oxide, yttrium oxide, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba, Sr)TiO3 (BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials. The high-K dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate electrode 404B of the gate structure 404 may include a single layer or optionally a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. In various embodiments, the gate electrode 404B may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. The gate electrode 404B may include an n-type work function metal layer or a p-type work function metal layer corresponding to the function of the device. The n-type work function metal layer may include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or a combination thereof. The p-type functional metal layer may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WCN, other p-type work function materials, or a combination thereof.

[0057] In some embodiments, contacts are formed to one or more of the gate electrode or source / drain features.

[0058] Reference now Figure 5 , shows the configuration of the layout of the semiconductor structure 500 . Figure 5 The semiconductor structure 500 may be as described above with reference to Figure 2A and Figure 2B A portion of a semiconductor structure such as chip 200 is depicted. Figure 55 is a first device region 502 and a second device region 504. A dummy region 506 is between the first device region 502 and the second device region 504. The first device region 502 and the second device region 504 may be substantially similar to the device region 204A discussed above. The first device region 502 and the second device region 504 include a plurality of functional semiconductor devices, such as n-type and p-type transistors. Each device region 502, 504 includes a plurality of NEPI regions or n-type transistor cells 304 and a plurality of PEPI regions or p-type transistor cells 302. The NEPI region 304 and the PEPI region 302 may be substantially similar to as discussed. A plurality of gate structures 404 extend in the y direction, and the OD region 406 extends in the x direction. As discussed above, the OD region 406 may be a planar substrate region, a fin element, a nanowire or a nanosheet, and / or other channel configurations. The epitaxial component 410 provides a source / drain component in the NEPI region 304; the epitaxial component 408 provides a source / drain component in the PEPI region 302. The isolation structure 402 / 412 is interposed between the PEPI region 302 and the NEPI region 304 and / or between portions of the OD region 406 .

[0059] like Figure 5 As shown in FIG. 5 , each of the device regions 502 and 504 includes an equal number of NEPI regions 304 and PEPI regions 302. And each of the device regions 502 and 504 has an array of NEPI regions 304 and PEPI regions 302, wherein the array has alternating NEPI regions 304 and PEPI regions 302.

[0060] The dummy region 506 between the first device region 502 and the second device region 504 also includes a plurality of NEPI regions or cells 304 and a plurality of PEPI regions or cells 302. The dummy region 506 can be substantially similar to the dummy region 204B discussed above. The dummy region 506 does not include functional semiconductor devices such as n-type and p-type transistors, but rather includes components that are substantially similar to transistor configurations that are not connected. The NEPI regions 304 and the PEPI regions 302 can be substantially similar to those discussed above with respect to FIG. 4A to FIG. 4DAs discussed above. Multiple gate structures 404 extend in the y-direction, and OD region 406 extends in the x-direction. As discussed above, OD region 406 can be a planar substrate region, a fin element, a nanowire or nanosheet, and / or other channel configuration. Epitaxial component 408 provides an epitaxial component in PEPI region 302; epitaxial component 410 provides an epitaxial component in NEPI region 304. Isolation structure 402 / 412 is between PEPI region 302 and NEPI region 304 and / or between portions of OD region 406. Although OD region 406, gate structure 404, and epitaxial component 408 / 410 are substantially similar to those transistor components of device regions 502, 504, the components do not form active transistors in dummy region 506 because they are not connected to other transistors and / or I / O.

[0061] like Figure 5 As shown in the figure, the dummy region 506 includes an equal number of NEPI regions 304 and PEPI regions 302. And the dummy region 506 has an array of NEPI regions 304 and PEPI regions 302, wherein the NEPI regions 304 and the PEPI regions 302 alternate. In the embodiment as shown, the dummy region 506 has the same configuration as the device region 502 and / or 504.

[0062] In an embodiment of the layout, all OD regions are larger than about 10% of the semiconductor (eg, chip) area.

[0063] Figures 6 to 11 An exemplary layout diagram of a dummy region of a semiconductor structure is shown. The dummy region may be substantially similar to Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 4C and Figure 4D Area 204B and / or Figure 5 The layout of the dummy region includes a NEPI region 304 and a PEPI region 302. Each of the NEPI region 304 and the PEPI region 302 includes a plurality of gate structures 404 extending in the y direction and an OD region 406 over which the gate structures 404 extend. The NEPI region 304 includes an n-type epitaxial region, such as the one described above with respect to Figure 4D The epitaxial region 410 discussed above. The PEPI region 302 includes a p-type epitaxial region, such as Figure 4D The extension region 408 is discussed.

[0064] exist Figure 6, layout 600 shows a dummy region having a first plurality of PEPI regions 302 and a second plurality of NEPI regions 304. The first plurality of PEPI regions 302 is greater in number than the second plurality of NEPI regions 304. In an embodiment, the ratio of PEPI regions 302 to NEPI regions 304 is 2:1. In an embodiment, a device region adjacent to a dummy region of layout 600 may include a 2:1 ratio of NEPI regions 304 to PEPI regions 302, wherein the NEPI and PEPI configurations are swapped in array positions between the device region and the dummy region.

[0065] exist Figure 7 , layout 700 shows a dummy region having a first plurality of PEPI regions 304 and a second plurality of NEPI regions 302. The first plurality of NEPI regions 304 is greater in number than the first plurality of PEPI regions 302. In an embodiment, the ratio of NEPI regions 304 to PEPI regions 302 is 2:1. In an embodiment, a device region adjacent to a dummy region of layout 700 may include a 1:2 ratio of NEPI regions 304 to PEPI regions 302, wherein the NEPI and PEPI configurations are swapped in array positions between the device region and the dummy region.

[0066] exist Figure 8 , layout 800 shows a dummy region having a first plurality of PEPI regions 302 and a second plurality of NEPI regions 304. The first plurality of PEPI regions 302 is equal in number to the second plurality of NEPI regions 304. In an embodiment, the ratio of PEPI regions 302 to NEPI regions 304 is 1:1. In an embodiment, layout 800 includes alternating PEPI regions 302 and NEPI regions 304 along rows and columns of the array. In an embodiment, a device region adjacent to a dummy region of layout 800 may include a 1:1 ratio of NEPI regions 304 to PEPI regions 302, wherein the NEPI and PEPI configurations are swapped in array positions between the device region and the dummy region.

[0067] exist Fig. 9, layout 900 shows a dummy region having a first plurality of PEPI regions 302 and a second plurality of NEPI regions 304. The first plurality of PEPI regions 302 is equal in number to the second plurality of NEPI regions 304. In an embodiment, the ratio of PEPI regions 302 to NEPI regions 304 is 1:1. In an embodiment, layout 900 includes two PEPI regions 302 and two subsequent NEPI regions 304 along a column. In an embodiment, layout 900 includes a PEPI region 302 and a subsequent NEPI region 304 along a row. In an embodiment, a device region adjacent to a dummy region of layout 900 may include a 1:1 ratio of NEPI regions 304 to PEPI regions 302, wherein the NEPI and PEPI configurations are swapped in array positions between the device region and the dummy region.

[0068] exist Fig.10 1 , layout 1000 shows a dummy region with multiple NEPI regions 304. In an embodiment, layout 1000 does not include PEPI region 302. In an embodiment, a device region adjacent to a dummy region of layout 1000 may include NEPI region 304 and PEPI region 302, such as, for example, Figure 3A and Figure 3B as shown in .

[0069] exist Fig.11 1 , layout 1100 shows a dummy region having a first plurality of PEPI regions 302 and a second plurality of NEPI regions 304. In an embodiment, the ratio of NEPI regions 304 to PEPI regions 302 is greater than 2:1. In an embodiment, the ratio of NEPI regions 304 to PEPI regions 302 is between approximately 2:1 and 1:2. In a further embodiment, the ratio of NEPI regions 304 to PEPI regions 302 is 2:1. In a further embodiment, the ratio of NEPI regions 304 to PEPI regions 302 is 1:2. In an embodiment, layout 1100 has a non-uniform configuration. In an embodiment, a device region adjacent to a dummy region of layout 1000 may include NEPI regions 304 and PEPI regions 302, such as, for example, Figure 3A and Figure 3B as shown in .

[0070] In some embodiments, the dummy region includes approximately 50% region of the first dopant type and approximately 50% region of the second dopant type (eg, 50% PEPI and 50% NEPI).

[0071] Fig.12A method 1200 is shown that can be implemented to form a semiconductor structure. In an embodiment, the semiconductor structure is a chip, and in particular an integrated circuit (IC) chip. The method 1200 can be implemented after a layout for the semiconductor structure has been determined as discussed above, including the steps of: Figure 1 Method 1200 is merely exemplary and is not intended to limit the disclosed embodiments to those expressly shown herein. Additional steps may be provided before, during, and after method 1200, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For simplicity, not all steps are described in detail herein.

[0072] In a first block 1202, an active region or OD region is formed on a substrate. The active region or OD region is formed on a device region of the substrate and a dummy region of the substrate. The device region may include active devices such as n-type transistors and p-type transistors that are interconnected to form a semiconductor device. The dummy region may include components corresponding to those in the device region, but does not provide electrical functionality to the semiconductor device.

[0073] In an embodiment, the active OD region is a planar portion of a semiconductor substrate. In an embodiment, the active OD region is a fin element extending above the substrate, such as Figure 4C and Figure 4D 406 of the OD region. In an embodiment, the active OD region includes nanowires, nanorods, or nanosheets, all of which are collectively referred to as nanostructures. The nanostructures can be used to form the channel region of a full gate (GAA) device. Isolation components such as shallow trench isolation (STI) or field oxide (FOX) are formed between the active OD regions. The isolation components can be substantially similar to the isolation components 402 discussed above.

[0074] The method 1200 then proceeds to block 1204, where a gate structure is formed over the active OD region. The gate structure may include a gate stack substantially similar to the gate structure 404 discussed above. In some embodiments, the gate structure includes a gate dielectric and an electrode. The gate structure formed in block 1204 may be a dummy gate structure that is removed in a later process step to form a trench, within which a functional gate is formed. In such an example, the gate stack as formed in block 1204 may be a polysilicon gate.

[0075] The method 1200 then proceeds to blocks 1206 and 1208, where source / drain features are formed. The source / drain features may be epitaxial regions, such as those described above with reference to FIG. Figure 4C and Figure 4D Epitaxial regions 408 and 410 are discussed.

[0076] In an embodiment, a first masking layer is formed on the substrate, wherein the first masking layer includes a plurality of openings defining a region of a first doping type (e.g., p-type). The openings are aligned with regions of the active OD region in the device region and dummy region of the substrate where source / drain features of the first dopant type are to be grown. In an embodiment, the plurality of openings of the masking layer may be substantially similar to the PEPI region 302 discussed above.

[0077] While maintaining the first masking element, a CVD deposition technique (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes are performed to form an epitaxial region of a first dopant type. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the components of the active OD region of block 1202. In various embodiments, the p-type epitaxial component may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe (SiGeB), or other suitable materials. The p-type epitaxial component may be in-situ doped during the epitaxial process by introducing a doping substance including a p-type dopant, such as boron or BF2 and / or other suitable dopants including combinations thereof. In some embodiments, an implantation process may be performed to dope the p-type epitaxial component.

[0078] The method then proceeds to block 1208, where after removing the first masking element of block 1206, a second masking element is formed on the substrate, where the second masking layer includes a plurality of openings defining a region of a second doping type (e.g., n-type). The openings are aligned with regions of the active OD regions in the device region and dummy region of the substrate where source / drain features of the second dopant type are to be grown. In an embodiment, the plurality of openings may be substantially similar to the NEPI region 304 discussed above.

[0079] While maintaining the second masking element, a CVD deposition technique (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes are performed to form an epitaxial region of the first dopant type. The epitaxial growth process can use gaseous and / or liquid precursors that interact with the components of the active OD region of block 1202.

[0080] A suitable epitaxial process for forming the second type epitaxial component can be similar to the epitaxial process for forming the first type epitaxial source / drain component. In various embodiments, n-type epitaxial components can be formed including Si, GaAs, GaAsP, SiP or other suitable materials. The n-type epitaxial component can be in-situ doped during the epitaxial process by introducing a doping substance including an n-type dopant, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. In some embodiments, an implantation process can be performed to dope the n-type epitaxial component.

[0081] Then, block 1208 continues to other semiconductor manufacturing processes. In some embodiments, a dielectric material such as the insulating region 412 is formed over the substrate. The gate structure of block 1204 can be removed and replaced with a high-k dielectric gate oxide and a metal gate electrode gate stack. Various other components including MLI (such as contacts, metal lines, and intervening vias) are formed.

[0082] Fig.13 According to some embodiments, a method for implementing a reference Figures 1 to 12 1 is a block diagram of a hardware system 1300 of an embodiment of the method and arrangement described. The system 1300 includes at least one processor 1302, a network interface 1304, an input and output (I / O) device 1306, a storage 1308, a memory 1312, and a bus 1310. The bus 1310 couples the network interface 1304, the I / O device 1306, the storage 1308, and the memory 1312 to the processor 1302.

[0083] In some embodiments, the memory 1312 includes a random access memory (RAM) and / or other volatile memory devices and / or a read-only memory (ROM) and / or other non-volatile memory devices. The memory 1312 includes a kernel and a user space, and is configured to store program instructions to be executed by the processor 1302 and data accessed by the program instructions.

[0084] In some embodiments, network interface 1304 is configured to access program instructions and data accessed by program instructions stored remotely over a network. I / O devices 1306 include input devices and output devices configured to enable a user to interact with system 1300. Input devices include, for example, keyboards, mice, etc. Output devices include, for example, displays, printers, etc. Storage device 1308 is configured to store program instructions and data accessed by program instructions. Storage device 1308 includes, for example, magnetic disks and optical disks.

[0085] In some embodiments, when executing program instructions, processor 1302 is configured to implement method 100 and / or provide the layout described above. In some embodiments, program instructions are stored in a non-transitory computer-readable recording medium, such as one or more optical disks, hard disks, and non-volatile memory devices. In some embodiments, a file containing the layout described above is stored in a non-transitory computer-readable storage medium.

[0086] Based on the above description, it can be seen that the embodiments of the present disclosure provide advantages over conventional methods and semiconductor structures. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and no particular advantages are required for all embodiments. For example, the embodiments of the present disclosure provide systems, structures, layouts, and methods that allow a chip to have improved critical dimensions of n-type epitaxial regions (e.g., n-type source / drain) in terms of CD values ​​and / or uniformity (CDU). The NEPI region of the dummy region of the semiconductor structure may be selected and arranged (e.g., adjusted) based on the active area design to provide improved CD and CDU.

[0087] The disclosed embodiments provide many different embodiments. The present invention discloses a semiconductor structure, a semiconductor structure design, a method for designing a semiconductor structure layout, and a method for manufacturing the same. In one exemplary aspect, the disclosed embodiments relate to a semiconductor structure including a substrate having a device region and a dummy region. A first active region is disposed above the substrate in the device region, and a second active region is disposed above the substrate in the dummy region. A first operating gate structure is disposed above the first active region, and a first non-operating gate structure is disposed above the second active region. A first epitaxial region of an n-type dopant is adjacent to the first operating gate structure; and a second epitaxial region of an n-type dopant is adjacent to the first non-operating gate structure.

[0088] In an embodiment, the first active region is a first fin element, and the second active region is a second fin element. In an embodiment, the first active region is a first plurality of nanostructures, and the second active region is a second plurality of nanostructures. In some embodiments, the structure may further include: a third active region and a fourth active region, the third active region being located above the substrate in the device region, and the fourth active region being located above the substrate in the dummy region; a second operating gate structure being located above the third active region; a second non-operating gate structure being located above the fourth active region; a third epitaxial region of p-type dopants, adjacent to the second operating gate structure; and a fourth epitaxial region of n-type dopants, adjacent to the second non-operating gate structure.

[0089] In an embodiment of the structure, a first cell array is included in the device region and a second cell array is included in the dummy region. And the first active region forms a first cell of the first cell array and the second active region forms a first cell of the second cell array. In an embodiment, the second epitaxial region is formed on the second active region. The first active region may be formed by a nanosheet.

[0090] In another broader embodiment, a semiconductor structure includes: a substrate including a device region and a dummy region; and a plurality of NEPI regions located in the dummy region. The plurality of NEPI regions include an active region extending in a first direction, a plurality of gate structures extending in a second direction, and an n-type doped epitaxial region. The plurality of NEPI regions are located in the device region. The plurality of NEPI regions include an active region extending in a first direction, a plurality of gate structures extending in a second direction, and an n-type doped epitaxial region.

[0091] In a further embodiment, the pseudo region also includes a plurality of PEPI regions. In an embodiment, in the pseudo region, the total number of a plurality of NEPI regions is greater than the total number of a plurality of PEPI regions. In an embodiment, a plurality of NEPI regions are configured in the first column of the region array, and the first column includes a first NEPI region, a second adjacent NEPI region, and a first adjacent PEPI region. In another embodiment, the pseudo region includes a plurality of NEPI regions and a plurality of PEPI regions arranged alternately. In some embodiments, the pseudo region includes an array of a plurality of NEPI regions and a plurality of PEPI regions, wherein the first NEPI region of a plurality of NEPI regions, the second NEPI region of a plurality of NEPI regions, and the first PEPI region of a plurality of PEPI regions are sequentially included in the first column of the array. In an embodiment, the active region includes another array of a plurality of NEPI regions and a plurality of PEPI regions. The first column of another array may sequentially include the second PEPI region of a plurality of PEPI regions, the third PEPI region of a plurality of PEPI regions, and the second NEPI region of a plurality of NEPI regions. In a further embodiment, the first NEPI region of the pseudo region and the second PEPI region of the active region are aligned in the same row. In an embodiment, the isolation region is located between the second PEPI region and the third PEPI region.

[0092] In another broader embodiment, the method includes: providing a substrate having a dummy region and a device region; forming a first active region in the dummy region and forming a second active region in the device region; and forming a gate structure over the substrate. A first plurality of gate structures extend over the first active region in the dummy region, and a second plurality of gate structures extend over the second active region in the device region. The method also includes: providing a first masking element having a first opening group over the dummy region and the device region; and while providing the first masking element, growing a first plurality of epitaxial regions having a first dopant type in the dummy region and the device region. Providing a second masking element having a second opening group over the dummy region and the device region. And while providing the second masking element, growing a second plurality of epitaxial regions having a second dopant type in the dummy region and the device region.

[0093] In a further embodiment of the method, after growing the first plurality of epitaxial regions and the second plurality of epitaxial regions, replacing the gate structure with a gate stack of a high-k gate dielectric and a metal gate electrode. In an embodiment, the first active region is formed by forming a fin element in the dummy region, and forming the second active region includes forming the fin element in the device region. In an embodiment, the method also includes: determining an opening of the first masking element in the dummy region based on an opening of the first masking element in the device region.

[0094] Some embodiments of the present application provide a semiconductor structure, including: a substrate, including a device region and a dummy region; a first active region and a second active region, the first active region being located above the substrate in the device region, and the second active region being located above the substrate in the dummy region; a first operating gate structure being located above the first active region; a first non-operating gate structure being located above the second active region; a first epitaxial region of n-type dopants, adjacent to the first operating gate structure; and a second epitaxial region of n-type dopants, adjacent to the first non-operating gate structure.

[0095] In some embodiments, the first active region is a first fin element, and the second active region is a second fin element. In some embodiments, the first active region is a first plurality of nanostructures, and the second active region is a second plurality of nanostructures. In some embodiments, the semiconductor structure further comprises: a third active region and a fourth active region, the third active region being located above the substrate in the device region, and the fourth active region being located above the substrate in the dummy region; a second operating gate structure being located above the third active region; a second non-operating gate structure being located above the fourth active region; a third epitaxial region of p-type dopants, adjacent to the second operating gate structure; and a fourth epitaxial region of n-type dopants, adjacent to the second non-operating gate structure. In some embodiments, a first cell array is included in the device region, and a second cell array is included in the dummy region, wherein the first active region forms a first cell of the first cell array, and the second active region forms a first cell of the second cell array. In some embodiments, the second epitaxial region is formed on the second active region. In some embodiments, the first active region is a nanosheet.

[0096] Other embodiments of the present application provide a semiconductor structure, including: a substrate, including a device region and a dummy region; a plurality of n-type epitaxial (NEPI) regions, located in the dummy region, wherein the plurality of n-type epitaxial regions include an active region extending in a first direction, a plurality of gate structures extending in a second direction, and an n-type doped epitaxial region; and a plurality of n-type epitaxial regions, located in the device region, wherein the plurality of n-type epitaxial regions include an active region extending in the first direction, a plurality of gate structures extending in the second direction, and an n-type doped epitaxial region.

[0097] In some embodiments, the dummy region further comprises a plurality of p-type epitaxial (PEPI) regions. In some embodiments, in the dummy region, the total number of the plurality of n-type epitaxial regions is greater than the total number of the plurality of p-type epitaxial regions. In some embodiments, the plurality of n-type epitaxial regions are configured in a first column of a region array, wherein the first column comprises a first n-type epitaxial region, a next adjacent second n-type epitaxial region, and a next adjacent first p-type epitaxial region. In some embodiments, the dummy region comprises the plurality of n-type epitaxial regions and the plurality of p-type epitaxial regions arranged alternately. In some embodiments, the dummy region comprises an array of the plurality of n-type epitaxial regions and the plurality of p-type epitaxial regions, wherein the first n-type epitaxial region of the plurality of n-type epitaxial regions, the second n-type epitaxial region of the plurality of n-type epitaxial regions, and the first p-type epitaxial region of the plurality of p-type epitaxial regions are sequentially included in the first column of the array. In some embodiments, the active region includes another array of the plurality of n-type epitaxial regions and the plurality of p-type epitaxial regions, wherein a second p-type epitaxial region of the plurality of p-type epitaxial regions, a third p-type epitaxial region of the plurality of p-type epitaxial regions, and a second n-type epitaxial region of the plurality of n-type epitaxial regions are sequentially included in a first column of the another array. In some embodiments, the first n-type epitaxial region of the dummy region and the second p-type epitaxial region of the active region are aligned in the same row. In some embodiments, an isolation region is located between the second p-type epitaxial region and the third p-type epitaxial region.

[0098] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: providing a substrate having a dummy region and a device region; forming a first active region in the dummy region, and forming a second active region in the device region; forming a gate structure above the substrate, wherein a first plurality of gate structures extend above the first active region in the dummy region, and a second plurality of gate structures extend above the second active region in the device region; providing a first masking element having a first opening group above the dummy region and the device region; when providing the first masking element, growing a first plurality of epitaxial regions having a first dopant type in the dummy region and the device region; providing a second masking element having a second opening group above the dummy region and the device region; and when providing the second masking element, growing a second plurality of epitaxial regions having a second dopant type in the dummy region and the device region.

[0099] In some embodiments, the method further comprises: replacing the gate structure with a gate stack of a high-k gate dielectric and a metal gate electrode after growing the first plurality of epitaxial regions and the second plurality of epitaxial regions. In some embodiments, forming the first active region comprises forming a fin element in the dummy region, and forming the second active region comprises forming a fin element in the device region. In some embodiments, the method further comprises: determining an opening of the first masking element in the dummy region based on the opening of the first masking element in the device region.

[0100] The features of several embodiments are summarized above. Those skilled in the art will appreciate that they can easily use the disclosed embodiments as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosed embodiments, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the disclosed embodiments.

Claims

1. A semiconductor structure comprising: a substrate, including a device region and a dummy region; a first active region and a second active region, the first active region being located above the substrate in the device region and the second active region being located above the substrate in the dummy region; a first operating gate structure located above the first active region; a first non-operational gate structure located above the second active region; a first epitaxial region of n-type dopant adjacent to the first operating gate structure; and A second epitaxial region of n-type dopant is adjacent to the first non-operating gate structure.

2. The semiconductor structure according to claim 1, wherein: The first active region is a first fin element, and the second active region is a second fin element.

3. The semiconductor structure according to claim 1, wherein: The first active region is a first plurality of nanostructures and the second active region is a second plurality of nanostructures.

4. The semiconductor structure according to claim 1, further comprising: a third active region and a fourth active region, the third active region being located above the substrate in the device region, and the fourth active region being located above the substrate in the dummy region; a second operating gate structure located above the third active region; a second non-operational gate structure located above the fourth active region; a third epitaxial region of p-type dopant adjacent to the second operating gate structure; and A fourth epitaxial region of n-type dopant is adjacent to the second non-operating gate structure.

5. The semiconductor structure according to claim 1, wherein: A first cell array is included in the device region, and a second cell array is included in the dummy region, wherein the first active region forms a first cell of the first cell array, and the second active region forms a first cell of the second cell array.

6. The semiconductor structure according to claim 1, wherein: The second epitaxial region is formed on the second active region.

7. The semiconductor structure according to claim 1, wherein: The first active region is a nanosheet.

8. A semiconductor structure comprising: a substrate, including a device region and a dummy region; a plurality of n-type epitaxial (NEPI) regions located in the dummy region, wherein the plurality of n-type epitaxial regions include an active region extending in a first direction, a plurality of gate structures extending in a second direction, and an n-type doped epitaxial region; and A plurality of n-type epitaxial regions are located in the device region, wherein the plurality of n-type epitaxial regions include an active region extending in the first direction, a plurality of gate structures extending in the second direction, and an n-type doped epitaxial region.

9. The semiconductor structure according to claim 8, wherein: The dummy region further includes a plurality of p-type epitaxial (PEPI) regions.

10. A method for manufacturing a semiconductor structure, comprising: providing a substrate having a dummy region and a device region; forming a first active region in the dummy region and forming a second active region in the device region; forming gate structures over the substrate, wherein a first plurality of gate structures extend over the first active region in the dummy region and a second plurality of gate structures extend over the second active region in the device region; providing a first masking element having a first set of openings over the dummy region and the device region; while providing the first masking element, growing a first plurality of epitaxial regions having a first dopant type in the dummy region and the device region; providing a second masking element having a second set of openings over the dummy region and the device region; and While the second masking element is provided, a second plurality of epitaxial regions having a second dopant type are grown in the dummy region and the device region.

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